hw/omap_mmc.c

   1 /*
   2  * OMAP on-chip MMC/SD host emulation.
   3  *
   4  * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20 #include "hw.h"
  21 #include "omap.h"
  22 #include "sd.h"
  23
  24 struct omap_mmc_s {
  25     qemu_irq irq;
  26     qemu_irq *dma;
  27     qemu_irq coverswitch;
  28     omap_clk clk;
  29     SDState *card;
  30     uint16_t last_cmd;
  31     uint16_t sdio;
  32     uint16_t rsp[8];
  33     uint32_t arg;
  34     int lines;
  35     int dw;
  36     int mode;
  37     int enable;
  38     int be;
  39     int rev;
  40     uint16_t status;
  41     uint16_t mask;
  42     uint8_t cto;
  43     uint16_t dto;
  44     int clkdiv;
  45     uint16_t fifo[32];
  46     int fifo_start;
  47     int fifo_len;
  48     uint16_t blen;
  49     uint16_t blen_counter;
  50     uint16_t nblk;
  51     uint16_t nblk_counter;
  52     int tx_dma;
  53     int rx_dma;
  54     int af_level;
  55     int ae_level;
  56
  57     int ddir;
  58     int transfer;
  59
  60     int cdet_wakeup;
  61     int cdet_enable;
  62     int cdet_state;
  63     qemu_irq cdet;
  64 };
  65
  66 static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
  67 {
  68     qemu_set_irq(s->irq, !!(s->status & s->mask));
  69 }
  70
  71 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
  72 {
  73     if (!host->transfer && !host->fifo_len) {
  74         host->status &= 0xf3ff;
  75         return;
  76     }
  77
  78     if (host->fifo_len > host->af_level && host->ddir) {
  79         if (host->rx_dma) {
  80             host->status &= 0xfbff;
  81             qemu_irq_raise(host->dma[1]);
  82         } else
  83             host->status |= 0x0400;
  84     } else {
  85         host->status &= 0xfbff;
  86         qemu_irq_lower(host->dma[1]);
  87     }
  88
  89     if (host->fifo_len < host->ae_level && !host->ddir) {
  90         if (host->tx_dma) {
  91             host->status &= 0xf7ff;
  92             qemu_irq_raise(host->dma[0]);
  93         } else
  94             host->status |= 0x0800;
  95     } else {
  96         qemu_irq_lower(host->dma[0]);
  97         host->status &= 0xf7ff;
  98     }
  99 }
 100
 101 typedef enum {
 102     sd_nore = 0,        /* no response */
 103     sd_r1,              /* normal response command */
 104     sd_r2,              /* CID, CSD registers */
 105     sd_r3,              /* OCR register */
 106     sd_r6 = 6,          /* Published RCA response */
 107     sd_r1b = -1,
 108 } sd_rsp_type_t;
 109
 110 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
 111                 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
 112 {
 113     uint32_t rspstatus, mask;
 114     int rsplen, timeout;
 115     struct sd_request_s request;
 116     uint8_t response[16];
 117
 118     if (init && cmd == 0) {
 119         host->status |= 0x0001;
 120         return;
 121     }
 122
 123     if (resptype == sd_r1 && busy)
 124         resptype = sd_r1b;
 125
 126     if (type == sd_adtc) {
 127         host->fifo_start = 0;
 128         host->fifo_len = 0;
 129         host->transfer = 1;
 130         host->ddir = dir;
 131     } else
 132         host->transfer = 0;
 133     timeout = 0;
 134     mask = 0;
 135     rspstatus = 0;
 136
 137     request.cmd = cmd;
 138     request.arg = host->arg;
 139     request.crc = 0; /* FIXME */
 140
 141     rsplen = sd_do_command(host->card, &request, response);
 142
 143     /* TODO: validate CRCs */
 144     switch (resptype) {
 145     case sd_nore:
 146         rsplen = 0;
 147         break;
 148
 149     case sd_r1:
 150     case sd_r1b:
 151         if (rsplen < 4) {
 152             timeout = 1;
 153             break;
 154         }
 155         rsplen = 4;
 156
 157         mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
 158                 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
 159                 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
 160                 CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
 161                 CID_CSD_OVERWRITE;
 162         if (host->sdio & (1 << 13))
 163             mask |= AKE_SEQ_ERROR;
 164         rspstatus = (response[0] << 24) | (response[1] << 16) |
 165                 (response[2] << 8) | (response[3] << 0);
 166         break;
 167
 168     case sd_r2:
 169         if (rsplen < 16) {
 170             timeout = 1;
 171             break;
 172         }
 173         rsplen = 16;
 174         break;
 175
 176     case sd_r3:
 177         if (rsplen < 4) {
 178             timeout = 1;
 179             break;
 180         }
 181         rsplen = 4;
 182
 183         rspstatus = (response[0] << 24) | (response[1] << 16) |
 184                 (response[2] << 8) | (response[3] << 0);
 185         if (rspstatus & 0x80000000)
 186             host->status &= 0xe000;
 187         else
 188             host->status |= 0x1000;
 189         break;
 190
 191     case sd_r6:
 192         if (rsplen < 4) {
 193             timeout = 1;
 194             break;
 195         }
 196         rsplen = 4;
 197
 198         mask = 0xe000 | AKE_SEQ_ERROR;
 199         rspstatus = (response[2] << 8) | (response[3] << 0);
 200     }
 201
 202     if (rspstatus & mask)
 203         host->status |= 0x4000;
 204     else
 205         host->status &= 0xb000;
 206
 207     if (rsplen)
 208         for (rsplen = 0; rsplen < 8; rsplen ++)
 209             host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
 210                     (response[(rsplen << 1) | 0] << 8);
 211
 212     if (timeout)
 213         host->status |= 0x0080;
 214     else if (cmd == 12)
 215         host->status |= 0x0005; /* Makes it more real */
 216     else
 217         host->status |= 0x0001;
 218 }
 219
 220 static void omap_mmc_transfer(struct omap_mmc_s *host)
 221 {
 222     uint8_t value;
 223
 224     if (!host->transfer)
 225         return;
 226
 227     while (1) {
 228         if (host->ddir) {
 229             if (host->fifo_len > host->af_level)
 230                 break;
 231
 232             value = sd_read_data(host->card);
 233             host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
 234             if (-- host->blen_counter) {
 235                 value = sd_read_data(host->card);
 236                 host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
 237                         value << 8;
 238                 host->blen_counter --;
 239             }
 240
 241             host->fifo_len ++;
 242         } else {
 243             if (!host->fifo_len)
 244                 break;
 245
 246             value = host->fifo[host->fifo_start] & 0xff;
 247             sd_write_data(host->card, value);
 248             if (-- host->blen_counter) {
 249                 value = host->fifo[host->fifo_start] >> 8;
 250                 sd_write_data(host->card, value);
 251                 host->blen_counter --;
 252             }
 253
 254             host->fifo_start ++;
 255             host->fifo_len --;
 256             host->fifo_start &= 31;
 257         }
 258
 259         if (host->blen_counter == 0) {
 260             host->nblk_counter --;
 261             host->blen_counter = host->blen;
 262
 263             if (host->nblk_counter == 0) {
 264                 host->nblk_counter = host->nblk;
 265                 host->transfer = 0;
 266                 host->status |= 0x0008;
 267                 break;
 268             }
 269         }
 270     }
 271 }
 272
 273 static void omap_mmc_update(void *opaque)
 274 {
 275     struct omap_mmc_s *s = opaque;
 276     omap_mmc_transfer(s);
 277     omap_mmc_fifolevel_update(s);
 278     omap_mmc_interrupts_update(s);
 279 }
 280
 281 void omap_mmc_reset(struct omap_mmc_s *host)
 282 {
 283     host->last_cmd = 0;
 284     memset(host->rsp, 0, sizeof(host->rsp));
 285     host->arg = 0;
 286     host->dw = 0;
 287     host->mode = 0;
 288     host->enable = 0;
 289     host->status = 0;
 290     host->mask = 0;
 291     host->cto = 0;
 292     host->dto = 0;
 293     host->fifo_len = 0;
 294     host->blen = 0;
 295     host->blen_counter = 0;
 296     host->nblk = 0;
 297     host->nblk_counter = 0;
 298     host->tx_dma = 0;
 299     host->rx_dma = 0;
 300     host->ae_level = 0x00;
 301     host->af_level = 0x1f;
 302     host->transfer = 0;
 303     host->cdet_wakeup = 0;
 304     host->cdet_enable = 0;
 305     qemu_set_irq(host->coverswitch, host->cdet_state);
 306     host->clkdiv = 0;
 307 }
 308
 309 static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
 310 {
 311     uint16_t i;
 312     struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
 313     offset &= OMAP_MPUI_REG_MASK;
 314
 315     switch (offset) {
 316     case 0x00:  /* MMC_CMD */
 317         return s->last_cmd;
 318
 319     case 0x04:  /* MMC_ARGL */
 320         return s->arg & 0x0000ffff;
 321
 322     case 0x08:  /* MMC_ARGH */
 323         return s->arg >> 16;
 324
 325     case 0x0c:  /* MMC_CON */
 326         return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) |
 327                 (s->be << 10) | s->clkdiv;
 328
 329     case 0x10:  /* MMC_STAT */
 330         return s->status;
 331
 332     case 0x14:  /* MMC_IE */
 333         return s->mask;
 334
 335     case 0x18:  /* MMC_CTO */
 336         return s->cto;
 337
 338     case 0x1c:  /* MMC_DTO */
 339         return s->dto;
 340
 341     case 0x20:  /* MMC_DATA */
 342         /* TODO: support 8-bit access */
 343         i = s->fifo[s->fifo_start];
 344         if (s->fifo_len == 0) {
 345             printf("MMC: FIFO underrun\n");
 346             return i;
 347         }
 348         s->fifo_start ++;
 349         s->fifo_len --;
 350         s->fifo_start &= 31;
 351         omap_mmc_transfer(s);
 352         omap_mmc_fifolevel_update(s);
 353         omap_mmc_interrupts_update(s);
 354         return i;
 355
 356     case 0x24:  /* MMC_BLEN */
 357         return s->blen_counter;
 358
 359     case 0x28:  /* MMC_NBLK */
 360         return s->nblk_counter;
 361
 362     case 0x2c:  /* MMC_BUF */
 363         return (s->rx_dma << 15) | (s->af_level << 8) |
 364             (s->tx_dma << 7) | s->ae_level;
 365
 366     case 0x30:  /* MMC_SPI */
 367         return 0x0000;
 368     case 0x34:  /* MMC_SDIO */
 369         return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
 370     case 0x38:  /* MMC_SYST */
 371         return 0x0000;
 372
 373     case 0x3c:  /* MMC_REV */
 374         return s->rev;
 375
 376     case 0x40:  /* MMC_RSP0 */
 377     case 0x44:  /* MMC_RSP1 */
 378     case 0x48:  /* MMC_RSP2 */
 379     case 0x4c:  /* MMC_RSP3 */
 380     case 0x50:  /* MMC_RSP4 */
 381     case 0x54:  /* MMC_RSP5 */
 382     case 0x58:  /* MMC_RSP6 */
 383     case 0x5c:  /* MMC_RSP7 */
 384         return s->rsp[(offset - 0x40) >> 2];
 385
 386     /* OMAP2-specific */
 387     case 0x60:  /* MMC_IOSR */
 388     case 0x64:  /* MMC_SYSC */
 389         return 0;
 390     case 0x68:  /* MMC_SYSS */
 391         return 1;                                               /* RSTD */
 392     }
 393
 394     OMAP_BAD_REG(offset);
 395     return 0;
 396 }
 397
 398 static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
 399                 uint32_t value)
 400 {
 401     int i;
 402     struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
 403     offset &= OMAP_MPUI_REG_MASK;
 404
 405     switch (offset) {
 406     case 0x00:  /* MMC_CMD */
 407         if (!s->enable)
 408             break;
 409
 410         s->last_cmd = value;
 411         for (i = 0; i < 8; i ++)
 412             s->rsp[i] = 0x0000;
 413         omap_mmc_command(s, value & 63, (value >> 15) & 1,
 414                 (sd_cmd_type_t) ((value >> 12) & 3),
 415                 (value >> 11) & 1,
 416                 (sd_rsp_type_t) ((value >> 8) & 7),
 417                 (value >> 7) & 1);
 418         omap_mmc_update(s);
 419         break;
 420
 421     case 0x04:  /* MMC_ARGL */
 422         s->arg &= 0xffff0000;
 423         s->arg |= 0x0000ffff & value;
 424         break;
 425
 426     case 0x08:  /* MMC_ARGH */
 427         s->arg &= 0x0000ffff;
 428         s->arg |= value << 16;
 429         break;
 430
 431     case 0x0c:  /* MMC_CON */
 432         s->dw = (value >> 15) & 1;
 433         s->mode = (value >> 12) & 3;
 434         s->enable = (value >> 11) & 1;
 435         s->be = (value >> 10) & 1;
 436         s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
 437         if (s->mode != 0)
 438             printf("SD mode %i unimplemented!\n", s->mode);
 439         if (s->be != 0)
 440             printf("SD FIFO byte sex unimplemented!\n");
 441         if (s->dw != 0 && s->lines < 4)
 442             printf("4-bit SD bus enabled\n");
 443         if (!s->enable)
 444             omap_mmc_reset(s);
 445         break;
 446
 447     case 0x10:  /* MMC_STAT */
 448         s->status &= ~value;
 449         omap_mmc_interrupts_update(s);
 450         break;
 451
 452     case 0x14:  /* MMC_IE */
 453         s->mask = value & 0x7fff;
 454         omap_mmc_interrupts_update(s);
 455         break;
 456
 457     case 0x18:  /* MMC_CTO */
 458         s->cto = value & 0xff;
 459         if (s->cto > 0xfd && s->rev <= 1)
 460             printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
 461         break;
 462
 463     case 0x1c:  /* MMC_DTO */
 464         s->dto = value & 0xffff;
 465         break;
 466
 467     case 0x20:  /* MMC_DATA */
 468         /* TODO: support 8-bit access */
 469         if (s->fifo_len == 32)
 470             break;
 471         s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
 472         s->fifo_len ++;
 473         omap_mmc_transfer(s);
 474         omap_mmc_fifolevel_update(s);
 475         omap_mmc_interrupts_update(s);
 476         break;
 477
 478     case 0x24:  /* MMC_BLEN */
 479         s->blen = (value & 0x07ff) + 1;
 480         s->blen_counter = s->blen;
 481         break;
 482
 483     case 0x28:  /* MMC_NBLK */
 484         s->nblk = (value & 0x07ff) + 1;
 485         s->nblk_counter = s->nblk;
 486         s->blen_counter = s->blen;
 487         break;
 488
 489     case 0x2c:  /* MMC_BUF */
 490         s->rx_dma = (value >> 15) & 1;
 491         s->af_level = (value >> 8) & 0x1f;
 492         s->tx_dma = (value >> 7) & 1;
 493         s->ae_level = value & 0x1f;
 494
 495         if (s->rx_dma)
 496             s->status &= 0xfbff;
 497         if (s->tx_dma)
 498             s->status &= 0xf7ff;
 499         omap_mmc_fifolevel_update(s);
 500         omap_mmc_interrupts_update(s);
 501         break;
 502
 503     /* SPI, SDIO and TEST modes unimplemented */
 504     case 0x30:  /* MMC_SPI (OMAP1 only) */
 505         break;
 506     case 0x34:  /* MMC_SDIO */
 507         s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
 508         s->cdet_wakeup = (value >> 9) & 1;
 509         s->cdet_enable = (value >> 2) & 1;
 510         break;
 511     case 0x38:  /* MMC_SYST */
 512         break;
 513
 514     case 0x3c:  /* MMC_REV */
 515     case 0x40:  /* MMC_RSP0 */
 516     case 0x44:  /* MMC_RSP1 */
 517     case 0x48:  /* MMC_RSP2 */
 518     case 0x4c:  /* MMC_RSP3 */
 519     case 0x50:  /* MMC_RSP4 */
 520     case 0x54:  /* MMC_RSP5 */
 521     case 0x58:  /* MMC_RSP6 */
 522     case 0x5c:  /* MMC_RSP7 */
 523         OMAP_RO_REG(offset);
 524         break;
 525
 526     /* OMAP2-specific */
 527     case 0x60:  /* MMC_IOSR */
 528         if (value & 0xf)
 529             printf("MMC: SDIO bits used!\n");
 530         break;
 531     case 0x64:  /* MMC_SYSC */
 532         if (value & (1 << 2))                                   /* SRTS */
 533             omap_mmc_reset(s);
 534         break;
 535     case 0x68:  /* MMC_SYSS */
 536         OMAP_RO_REG(offset);
 537         break;
 538
 539     default:
 540         OMAP_BAD_REG(offset);
 541     }
 542 }
 543
 544 static CPUReadMemoryFunc *omap_mmc_readfn[] = {
 545     omap_badwidth_read16,
 546     omap_mmc_read,
 547     omap_badwidth_read16,
 548 };
 549
 550 static CPUWriteMemoryFunc *omap_mmc_writefn[] = {
 551     omap_badwidth_write16,
 552     omap_mmc_write,
 553     omap_badwidth_write16,
 554 };
 555
 556 static void omap_mmc_cover_cb(void *opaque, int line, int level)
 557 {
 558     struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
 559
 560     if (!host->cdet_state && level) {
 561         host->status |= 0x0002;
 562         omap_mmc_interrupts_update(host);
 563         if (host->cdet_wakeup)
 564             /* TODO: Assert wake-up */;
 565     }
 566
 567     if (host->cdet_state != level) {
 568         qemu_set_irq(host->coverswitch, level);
 569         host->cdet_state = level;
 570     }
 571 }
 572
 573 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
 574                 BlockDriverState *bd,
 575                 qemu_irq irq, qemu_irq dma[], omap_clk clk)
 576 {
 577     int iomemtype;
 578     struct omap_mmc_s *s = (struct omap_mmc_s *)
 579             qemu_mallocz(sizeof(struct omap_mmc_s));
 580
 581     s->irq = irq;
 582     s->dma = dma;
 583     s->clk = clk;
 584     s->lines = 1;       /* TODO: needs to be settable per-board */
 585     s->rev = 1;
 586
 587     omap_mmc_reset(s);
 588
 589     iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
 590                     omap_mmc_writefn, s);
 591     cpu_register_physical_memory(base, 0x800, iomemtype);
 592
 593     /* Instantiate the storage */
 594     s->card = sd_init(bd, 0);
 595
 596     return s;
 597 }
 598
 599 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
 600                 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
 601                 omap_clk fclk, omap_clk iclk)
 602 {
 603     int iomemtype;
 604     struct omap_mmc_s *s = (struct omap_mmc_s *)
 605             qemu_mallocz(sizeof(struct omap_mmc_s));
 606
 607     s->irq = irq;
 608     s->dma = dma;
 609     s->clk = fclk;
 610     s->lines = 4;
 611     s->rev = 2;
 612
 613     omap_mmc_reset(s);
 614
 615     iomemtype = l4_register_io_memory(0, omap_mmc_readfn,
 616                     omap_mmc_writefn, s);
 617     omap_l4_attach(ta, 0, iomemtype);
 618
 619     /* Instantiate the storage */
 620     s->card = sd_init(bd, 0);
 621
 622     s->cdet = qemu_allocate_irqs(omap_mmc_cover_cb, s, 1)[0];
 623     sd_set_cb(s->card, 0, s->cdet);
 624
 625     return s;
 626 }
 627
 628 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
 629 {
 630     if (s->cdet) {
 631         sd_set_cb(s->card, ro, s->cdet);
 632         s->coverswitch = cover;
 633         qemu_set_irq(cover, s->cdet_state);
 634     } else
 635         sd_set_cb(s->card, ro, cover);
 636 }
 637
 638 void omap_mmc_enable(struct omap_mmc_s *s, int enable)
 639 {
 640     sd_enable(s->card, enable);
 641 }