cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #ifndef CPU_DEFS_H
  21 #define CPU_DEFS_H
  22
  23 #ifndef NEED_CPU_H
  24 #error cpu.h included from common code
  25 #endif
  26
  27 #include "config.h"
  28 #include <setjmp.h>
  29 #include <inttypes.h>
  30 #include <signal.h>
  31 #include "osdep.h"
  32 #include "sys-queue.h"
  33 #include "targphys.h"
  34
  35 #ifndef TARGET_LONG_BITS
  36 #error TARGET_LONG_BITS must be defined before including this header
  37 #endif
  38
  39 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
  40
  41 /* target_ulong is the type of a virtual address */
  42 #if TARGET_LONG_SIZE == 4
  43 typedef int32_t target_long;
  44 typedef uint32_t target_ulong;
  45 #define TARGET_FMT_lx "%08x"
  46 #define TARGET_FMT_ld "%d"
  47 #define TARGET_FMT_lu "%u"
  48 #elif TARGET_LONG_SIZE == 8
  49 typedef int64_t target_long;
  50 typedef uint64_t target_ulong;
  51 #define TARGET_FMT_lx "%016" PRIx64
  52 #define TARGET_FMT_ld "%" PRId64
  53 #define TARGET_FMT_lu "%" PRIu64
  54 #else
  55 #error TARGET_LONG_SIZE undefined
  56 #endif
  57
  58 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
  59
  60 #define EXCP_INTERRUPT  0x10000 /* async interruption */
  61 #define EXCP_HLT        0x10001 /* hlt instruction reached */
  62 #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
  63 #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
  64
  65 #define TB_JMP_CACHE_BITS 12
  66 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
  67
  68 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
  69    addresses on the same page.  The top bits are the same.  This allows
  70    TLB invalidation to quickly clear a subset of the hash table.  */
  71 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
  72 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
  73 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
  74 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
  75
  76 #define CPU_TLB_BITS 8
  77 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
  78
  79 #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
  80 #define CPU_TLB_ENTRY_BITS 4
  81 #else
  82 #define CPU_TLB_ENTRY_BITS 5
  83 #endif
  84
  85 typedef struct CPUTLBEntry {
  86     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
  87        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
  88                                     go directly to ram.
  89        bit 3                      : indicates that the entry is invalid
  90        bit 2..0                   : zero
  91     */
  92     target_ulong addr_read;
  93     target_ulong addr_write;
  94     target_ulong addr_code;
  95     /* Addend to virtual address to get physical address.  IO accesses
  96        use the corresponding iotlb value.  */
  97 #if TARGET_PHYS_ADDR_BITS == 64
  98     /* on i386 Linux make sure it is aligned */
  99     target_phys_addr_t addend __attribute__((aligned(8)));
 100 #else
 101     target_phys_addr_t addend;
 102 #endif
 103     /* padding to get a power of two size */
 104     uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
 105                   (sizeof(target_ulong) * 3 +
 106                    ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
 107                    sizeof(target_phys_addr_t))];
 108 } CPUTLBEntry;
 109
 110 #ifdef WORDS_BIGENDIAN
 111 typedef struct icount_decr_u16 {
 112     uint16_t high;
 113     uint16_t low;
 114 } icount_decr_u16;
 115 #else
 116 typedef struct icount_decr_u16 {
 117     uint16_t low;
 118     uint16_t high;
 119 } icount_decr_u16;
 120 #endif
 121
 122 struct kvm_run;
 123 struct KVMState;
 124
 125 typedef struct CPUBreakpoint {
 126     target_ulong pc;
 127     int flags; /* BP_* */
 128     TAILQ_ENTRY(CPUBreakpoint) entry;
 129 } CPUBreakpoint;
 130
 131 typedef struct CPUWatchpoint {
 132     target_ulong vaddr;
 133     target_ulong len_mask;
 134     int flags; /* BP_* */
 135     TAILQ_ENTRY(CPUWatchpoint) entry;
 136 } CPUWatchpoint;
 137
 138 #define CPU_TEMP_BUF_NLONGS 128
 139 #define CPU_COMMON                                                      \
 140     struct TranslationBlock *current_tb; /* currently executing TB  */  \
 141     /* soft mmu support */                                              \
 142     /* in order to avoid passing too many arguments to the MMIO         \
 143        helpers, we store some rarely used information in the CPU        \
 144        context) */                                                      \
 145     unsigned long mem_io_pc; /* host pc at which the memory was         \
 146                                 accessed */                             \
 147     target_ulong mem_io_vaddr; /* target virtual addr at which the      \
 148                                      memory was accessed */             \
 149     uint32_t halted; /* Nonzero if the CPU is in suspend state */       \
 150     uint32_t stop;   /* Stop request */                                 \
 151     uint32_t stopped; /* Artificially stopped */                        \
 152     uint32_t interrupt_request;                                         \
 153     volatile sig_atomic_t exit_request;                                 \
 154     /* The meaning of the MMU modes is defined in the target code. */   \
 155     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
 156     target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
 157     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
 158     /* buffer for temporaries in the code generator */                  \
 159     long temp_buf[CPU_TEMP_BUF_NLONGS];                                 \
 160                                                                         \
 161     int64_t icount_extra; /* Instructions until next timer event.  */   \
 162     /* Number of cycles left, with interrupt flag in high bit.          \
 163        This allows a single read-compare-cbranch-write sequence to test \
 164        for both decrementer underflow and exceptions.  */               \
 165     union {                                                             \
 166         uint32_t u32;                                                   \
 167         icount_decr_u16 u16;                                            \
 168     } icount_decr;                                                      \
 169     uint32_t can_do_io; /* nonzero if memory mapped IO is safe.  */     \
 170                                                                         \
 171     /* from this point: preserved by CPU reset */                       \
 172     /* ice debug support */                                             \
 173     TAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;            \
 174     int singlestep_enabled;                                             \
 175                                                                         \
 176     TAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;            \
 177     CPUWatchpoint *watchpoint_hit;                                      \
 178                                                                         \
 179     struct GDBRegisterState *gdb_regs;                                  \
 180                                                                         \
 181     /* Core interrupt code */                                           \
 182     jmp_buf jmp_env;                                                    \
 183     int exception_index;                                                \
 184                                                                         \
 185     CPUState *next_cpu; /* next CPU sharing TB cache */                 \
 186     int cpu_index; /* CPU index (informative) */                        \
 187     uint32_t host_tid; /* host thread ID */                             \
 188     int numa_node; /* NUMA node this cpu is belonging to  */            \
 189     int running; /* Nonzero if cpu is currently running(usermode).  */  \
 190     /* user data */                                                     \
 191     void *opaque;                                                       \
 192                                                                         \
 193     uint32_t created;                                                   \
 194     struct QemuThread *thread;                                          \
 195     struct QemuCond *halt_cond;                                         \
 196     const char *cpu_model_str;                                          \
 197     struct KVMState *kvm_state;                                         \
 198     struct kvm_run *kvm_run;                                            \
 199     int kvm_fd;
 200
 201 #endif