2 * QEMU VMware-SVGA "chipset".
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
33 #define HW_MOUSE_ACCEL
39 struct vmsvga_state_s
{
62 ram_addr_t vram_offset
;
65 target_phys_addr_t vram_base
;
82 struct __attribute__((__packed__
)) {
87 /* Add registers here when adding capabilities. */
92 #define REDRAW_FIFO_LEN 512
93 struct vmsvga_rect_s
{
95 } redraw_fifo
[REDRAW_FIFO_LEN
];
96 int redraw_fifo_first
, redraw_fifo_last
;
99 struct pci_vmsvga_state_s
{
101 struct vmsvga_state_s chip
;
104 #define SVGA_MAGIC 0x900000UL
105 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
106 #define SVGA_ID_0 SVGA_MAKE_ID(0)
107 #define SVGA_ID_1 SVGA_MAKE_ID(1)
108 #define SVGA_ID_2 SVGA_MAKE_ID(2)
110 #define SVGA_LEGACY_BASE_PORT 0x4560
111 #define SVGA_INDEX_PORT 0x0
112 #define SVGA_VALUE_PORT 0x1
113 #define SVGA_BIOS_PORT 0x2
115 #define SVGA_VERSION_2
117 #ifdef SVGA_VERSION_2
118 # define SVGA_ID SVGA_ID_2
119 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
120 # define SVGA_IO_MUL 1
121 # define SVGA_FIFO_SIZE 0x10000
122 # define SVGA_MEM_BASE 0xe0000000
123 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
125 # define SVGA_ID SVGA_ID_1
126 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
127 # define SVGA_IO_MUL 4
128 # define SVGA_FIFO_SIZE 0x10000
129 # define SVGA_MEM_BASE 0xe0000000
130 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
134 /* ID 0, 1 and 2 registers */
139 SVGA_REG_MAX_WIDTH
= 4,
140 SVGA_REG_MAX_HEIGHT
= 5,
142 SVGA_REG_BITS_PER_PIXEL
= 7, /* Current bpp in the guest */
143 SVGA_REG_PSEUDOCOLOR
= 8,
144 SVGA_REG_RED_MASK
= 9,
145 SVGA_REG_GREEN_MASK
= 10,
146 SVGA_REG_BLUE_MASK
= 11,
147 SVGA_REG_BYTES_PER_LINE
= 12,
148 SVGA_REG_FB_START
= 13,
149 SVGA_REG_FB_OFFSET
= 14,
150 SVGA_REG_VRAM_SIZE
= 15,
151 SVGA_REG_FB_SIZE
= 16,
153 /* ID 1 and 2 registers */
154 SVGA_REG_CAPABILITIES
= 17,
155 SVGA_REG_MEM_START
= 18, /* Memory for command FIFO */
156 SVGA_REG_MEM_SIZE
= 19,
157 SVGA_REG_CONFIG_DONE
= 20, /* Set when memory area configured */
158 SVGA_REG_SYNC
= 21, /* Write to force synchronization */
159 SVGA_REG_BUSY
= 22, /* Read to check if sync is done */
160 SVGA_REG_GUEST_ID
= 23, /* Set guest OS identifier */
161 SVGA_REG_CURSOR_ID
= 24, /* ID of cursor */
162 SVGA_REG_CURSOR_X
= 25, /* Set cursor X position */
163 SVGA_REG_CURSOR_Y
= 26, /* Set cursor Y position */
164 SVGA_REG_CURSOR_ON
= 27, /* Turn cursor on/off */
165 SVGA_REG_HOST_BITS_PER_PIXEL
= 28, /* Current bpp in the host */
166 SVGA_REG_SCRATCH_SIZE
= 29, /* Number of scratch registers */
167 SVGA_REG_MEM_REGS
= 30, /* Number of FIFO registers */
168 SVGA_REG_NUM_DISPLAYS
= 31, /* Number of guest displays */
169 SVGA_REG_PITCHLOCK
= 32, /* Fixed pitch for all modes */
171 SVGA_PALETTE_BASE
= 1024, /* Base of SVGA color map */
172 SVGA_PALETTE_END
= SVGA_PALETTE_BASE
+ 767,
173 SVGA_SCRATCH_BASE
= SVGA_PALETTE_BASE
+ 768,
176 #define SVGA_CAP_NONE 0
177 #define SVGA_CAP_RECT_FILL (1 << 0)
178 #define SVGA_CAP_RECT_COPY (1 << 1)
179 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
180 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
181 #define SVGA_CAP_RASTER_OP (1 << 4)
182 #define SVGA_CAP_CURSOR (1 << 5)
183 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
184 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
185 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
186 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
187 #define SVGA_CAP_GLYPH (1 << 10)
188 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
189 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
190 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
191 #define SVGA_CAP_3D (1 << 14)
192 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
193 #define SVGA_CAP_MULTIMON (1 << 16)
194 #define SVGA_CAP_PITCHLOCK (1 << 17)
197 * FIFO offsets (seen as an array of 32-bit words)
201 * The original defined FIFO offsets
204 SVGA_FIFO_MAX
, /* The distance from MIN to MAX must be at least 10K */
209 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
211 SVGA_FIFO_CAPABILITIES
= 4,
214 SVGA_FIFO_3D_HWVERSION
,
218 #define SVGA_FIFO_CAP_NONE 0
219 #define SVGA_FIFO_CAP_FENCE (1 << 0)
220 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
221 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
223 #define SVGA_FIFO_FLAG_NONE 0
224 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
226 /* These values can probably be changed arbitrarily. */
227 #define SVGA_SCRATCH_SIZE 0x8000
228 #define SVGA_MAX_WIDTH 2360
229 #define SVGA_MAX_HEIGHT 1770
232 # define GUEST_OS_BASE 0x5001
233 static const char *vmsvga_guest_id
[] = {
234 [0x00 ... 0x15] = "an unknown OS",
236 [0x01] = "Windows 3.1",
237 [0x02] = "Windows 95",
238 [0x03] = "Windows 98",
239 [0x04] = "Windows ME",
240 [0x05] = "Windows NT",
241 [0x06] = "Windows 2000",
246 [0x15] = "Windows 2003",
251 SVGA_CMD_INVALID_CMD
= 0,
253 SVGA_CMD_RECT_FILL
= 2,
254 SVGA_CMD_RECT_COPY
= 3,
255 SVGA_CMD_DEFINE_BITMAP
= 4,
256 SVGA_CMD_DEFINE_BITMAP_SCANLINE
= 5,
257 SVGA_CMD_DEFINE_PIXMAP
= 6,
258 SVGA_CMD_DEFINE_PIXMAP_SCANLINE
= 7,
259 SVGA_CMD_RECT_BITMAP_FILL
= 8,
260 SVGA_CMD_RECT_PIXMAP_FILL
= 9,
261 SVGA_CMD_RECT_BITMAP_COPY
= 10,
262 SVGA_CMD_RECT_PIXMAP_COPY
= 11,
263 SVGA_CMD_FREE_OBJECT
= 12,
264 SVGA_CMD_RECT_ROP_FILL
= 13,
265 SVGA_CMD_RECT_ROP_COPY
= 14,
266 SVGA_CMD_RECT_ROP_BITMAP_FILL
= 15,
267 SVGA_CMD_RECT_ROP_PIXMAP_FILL
= 16,
268 SVGA_CMD_RECT_ROP_BITMAP_COPY
= 17,
269 SVGA_CMD_RECT_ROP_PIXMAP_COPY
= 18,
270 SVGA_CMD_DEFINE_CURSOR
= 19,
271 SVGA_CMD_DISPLAY_CURSOR
= 20,
272 SVGA_CMD_MOVE_CURSOR
= 21,
273 SVGA_CMD_DEFINE_ALPHA_CURSOR
= 22,
274 SVGA_CMD_DRAW_GLYPH
= 23,
275 SVGA_CMD_DRAW_GLYPH_CLIPPED
= 24,
276 SVGA_CMD_UPDATE_VERBOSE
= 25,
277 SVGA_CMD_SURFACE_FILL
= 26,
278 SVGA_CMD_SURFACE_COPY
= 27,
279 SVGA_CMD_SURFACE_ALPHA_BLEND
= 28,
280 SVGA_CMD_FRONT_ROP_FILL
= 29,
284 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
286 SVGA_CURSOR_ON_HIDE
= 0,
287 SVGA_CURSOR_ON_SHOW
= 1,
288 SVGA_CURSOR_ON_REMOVE_FROM_FB
= 2,
289 SVGA_CURSOR_ON_RESTORE_TO_FB
= 3,
292 static inline void vmsvga_update_rect(struct vmsvga_state_s
*s
,
293 int x
, int y
, int w
, int h
)
303 if (x
+ w
> s
->width
) {
304 fprintf(stderr
, "%s: update width too large x: %d, w: %d\n",
306 x
= MIN(x
, s
->width
);
310 if (y
+ h
> s
->height
) {
311 fprintf(stderr
, "%s: update height too large y: %d, h: %d\n",
313 y
= MIN(y
, s
->height
);
318 bypl
= s
->bypp
* s
->width
;
320 start
= s
->bypp
* x
+ bypl
* y
;
321 src
= s
->vram
+ start
;
322 dst
= s
->ds
->data
+ start
;
324 for (; line
> 0; line
--, src
+= bypl
, dst
+= bypl
)
325 memcpy(dst
, src
, width
);
328 dpy_update(s
->ds
, x
, y
, w
, h
);
331 static inline void vmsvga_update_screen(struct vmsvga_state_s
*s
)
334 memcpy(s
->ds
->data
, s
->vram
, s
->bypp
* s
->width
* s
->height
);
337 dpy_update(s
->ds
, 0, 0, s
->width
, s
->height
);
341 # define vmsvga_update_rect_delayed vmsvga_update_rect
343 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s
*s
,
344 int x
, int y
, int w
, int h
)
346 struct vmsvga_rect_s
*rect
= &s
->redraw_fifo
[s
->redraw_fifo_last
++];
347 s
->redraw_fifo_last
&= REDRAW_FIFO_LEN
- 1;
355 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s
*s
)
357 struct vmsvga_rect_s
*rect
;
358 if (s
->invalidated
) {
359 s
->redraw_fifo_first
= s
->redraw_fifo_last
;
362 /* Overlapping region updates can be optimised out here - if someone
363 * knows a smart algorithm to do that, please share. */
364 while (s
->redraw_fifo_first
!= s
->redraw_fifo_last
) {
365 rect
= &s
->redraw_fifo
[s
->redraw_fifo_first
++];
366 s
->redraw_fifo_first
&= REDRAW_FIFO_LEN
- 1;
367 vmsvga_update_rect(s
, rect
->x
, rect
->y
, rect
->w
, rect
->h
);
372 static inline void vmsvga_copy_rect(struct vmsvga_state_s
*s
,
373 int x0
, int y0
, int x1
, int y1
, int w
, int h
)
376 uint8_t *vram
= s
->ds
->data
;
378 uint8_t *vram
= s
->vram
;
380 int bypl
= s
->bypp
* s
->width
;
381 int width
= s
->bypp
* w
;
387 s
->ds
->dpy_copy(s
->ds
, x0
, y0
, x1
, y1
, w
, h
);
392 ptr
[0] = vram
+ s
->bypp
* x0
+ bypl
* (y0
+ h
- 1);
393 ptr
[1] = vram
+ s
->bypp
* x1
+ bypl
* (y1
+ h
- 1);
394 for (; line
> 0; line
--, ptr
[0] -= bypl
, ptr
[1] -= bypl
)
395 memmove(ptr
[1], ptr
[0], width
);
397 ptr
[0] = vram
+ s
->bypp
* x0
+ bypl
* y0
;
398 ptr
[1] = vram
+ s
->bypp
* x1
+ bypl
* y1
;
399 for (; line
> 0; line
--, ptr
[0] += bypl
, ptr
[1] += bypl
)
400 memmove(ptr
[1], ptr
[0], width
);
404 vmsvga_update_rect_delayed(s
, x1
, y1
, w
, h
);
409 static inline void vmsvga_fill_rect(struct vmsvga_state_s
*s
,
410 uint32_t c
, int x
, int y
, int w
, int h
)
413 uint8_t *vram
= s
->ds
->data
;
415 uint8_t *vram
= s
->vram
;
418 int bypl
= bypp
* s
->width
;
419 int width
= bypp
* w
;
422 uint8_t *fst
= vram
+ bypp
* x
+ bypl
* y
;
429 s
->ds
->dpy_fill(s
->ds
, x
, y
, w
, h
, c
);
441 for (column
= width
; column
> 0; column
--) {
442 *(dst
++) = *(src
++);
443 if (src
- col
== bypp
)
447 for (; line
> 0; line
--) {
449 memcpy(dst
, fst
, width
);
454 vmsvga_update_rect_delayed(s
, x
, y
, w
, h
);
458 struct vmsvga_cursor_definition_s
{
466 uint32_t image
[1024];
469 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
470 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
472 #ifdef HW_MOUSE_ACCEL
473 static inline void vmsvga_cursor_define(struct vmsvga_state_s
*s
,
474 struct vmsvga_cursor_definition_s
*c
)
477 for (i
= SVGA_BITMAP_SIZE(c
->width
, c
->height
) - 1; i
>= 0; i
--)
478 c
->mask
[i
] = ~c
->mask
[i
];
480 if (s
->ds
->cursor_define
)
481 s
->ds
->cursor_define(c
->width
, c
->height
, c
->bpp
, c
->hot_x
, c
->hot_y
,
482 (uint8_t *) c
->image
, (uint8_t *) c
->mask
);
486 static inline int vmsvga_fifo_empty(struct vmsvga_state_s
*s
)
488 if (!s
->config
|| !s
->enable
)
490 return (s
->cmd
->next_cmd
== s
->cmd
->stop
);
493 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s
*s
)
495 uint32_t cmd
= s
->fifo
[s
->cmd
->stop
>> 2];
497 if (s
->cmd
->stop
>= s
->cmd
->max
)
498 s
->cmd
->stop
= s
->cmd
->min
;
502 static void vmsvga_fifo_run(struct vmsvga_state_s
*s
)
504 uint32_t cmd
, colour
;
506 int x
, y
, dx
, dy
, width
, height
;
507 struct vmsvga_cursor_definition_s cursor
;
508 while (!vmsvga_fifo_empty(s
))
509 switch (cmd
= vmsvga_fifo_read(s
)) {
510 case SVGA_CMD_UPDATE
:
511 case SVGA_CMD_UPDATE_VERBOSE
:
512 x
= vmsvga_fifo_read(s
);
513 y
= vmsvga_fifo_read(s
);
514 width
= vmsvga_fifo_read(s
);
515 height
= vmsvga_fifo_read(s
);
516 vmsvga_update_rect_delayed(s
, x
, y
, width
, height
);
519 case SVGA_CMD_RECT_FILL
:
520 colour
= vmsvga_fifo_read(s
);
521 x
= vmsvga_fifo_read(s
);
522 y
= vmsvga_fifo_read(s
);
523 width
= vmsvga_fifo_read(s
);
524 height
= vmsvga_fifo_read(s
);
526 vmsvga_fill_rect(s
, colour
, x
, y
, width
, height
);
532 case SVGA_CMD_RECT_COPY
:
533 x
= vmsvga_fifo_read(s
);
534 y
= vmsvga_fifo_read(s
);
535 dx
= vmsvga_fifo_read(s
);
536 dy
= vmsvga_fifo_read(s
);
537 width
= vmsvga_fifo_read(s
);
538 height
= vmsvga_fifo_read(s
);
540 vmsvga_copy_rect(s
, x
, y
, dx
, dy
, width
, height
);
546 case SVGA_CMD_DEFINE_CURSOR
:
547 cursor
.id
= vmsvga_fifo_read(s
);
548 cursor
.hot_x
= vmsvga_fifo_read(s
);
549 cursor
.hot_y
= vmsvga_fifo_read(s
);
550 cursor
.width
= x
= vmsvga_fifo_read(s
);
551 cursor
.height
= y
= vmsvga_fifo_read(s
);
553 cursor
.bpp
= vmsvga_fifo_read(s
);
554 for (args
= 0; args
< SVGA_BITMAP_SIZE(x
, y
); args
++)
555 cursor
.mask
[args
] = vmsvga_fifo_read(s
);
556 for (args
= 0; args
< SVGA_PIXMAP_SIZE(x
, y
, cursor
.bpp
); args
++)
557 cursor
.image
[args
] = vmsvga_fifo_read(s
);
558 #ifdef HW_MOUSE_ACCEL
559 vmsvga_cursor_define(s
, &cursor
);
567 * Other commands that we at least know the number of arguments
568 * for so we can avoid FIFO desync if driver uses them illegally.
570 case SVGA_CMD_DEFINE_ALPHA_CURSOR
:
574 x
= vmsvga_fifo_read(s
);
575 y
= vmsvga_fifo_read(s
);
578 case SVGA_CMD_RECT_ROP_FILL
:
581 case SVGA_CMD_RECT_ROP_COPY
:
584 case SVGA_CMD_DRAW_GLYPH_CLIPPED
:
587 args
= 7 + (vmsvga_fifo_read(s
) >> 2);
589 case SVGA_CMD_SURFACE_ALPHA_BLEND
:
594 * Other commands that are not listed as depending on any
595 * CAPABILITIES bits, but are not described in the README either.
597 case SVGA_CMD_SURFACE_FILL
:
598 case SVGA_CMD_SURFACE_COPY
:
599 case SVGA_CMD_FRONT_ROP_FILL
:
601 case SVGA_CMD_INVALID_CMD
:
608 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
616 static uint32_t vmsvga_index_read(void *opaque
, uint32_t address
)
618 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
622 static void vmsvga_index_write(void *opaque
, uint32_t address
, uint32_t index
)
624 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
628 static uint32_t vmsvga_value_read(void *opaque
, uint32_t address
)
631 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
636 case SVGA_REG_ENABLE
:
642 case SVGA_REG_HEIGHT
:
645 case SVGA_REG_MAX_WIDTH
:
646 return SVGA_MAX_WIDTH
;
648 case SVGA_REG_MAX_HEIGHT
:
649 return SVGA_MAX_HEIGHT
;
654 case SVGA_REG_BITS_PER_PIXEL
:
655 return (s
->depth
+ 7) & ~7;
657 case SVGA_REG_PSEUDOCOLOR
:
660 case SVGA_REG_RED_MASK
:
662 case SVGA_REG_GREEN_MASK
:
664 case SVGA_REG_BLUE_MASK
:
667 case SVGA_REG_BYTES_PER_LINE
:
668 return ((s
->depth
+ 7) >> 3) * s
->new_width
;
670 case SVGA_REG_FB_START
:
673 case SVGA_REG_FB_OFFSET
:
676 case SVGA_REG_VRAM_SIZE
:
677 return s
->vram_size
- SVGA_FIFO_SIZE
;
679 case SVGA_REG_FB_SIZE
:
682 case SVGA_REG_CAPABILITIES
:
683 caps
= SVGA_CAP_NONE
;
685 caps
|= SVGA_CAP_RECT_COPY
;
688 caps
|= SVGA_CAP_RECT_FILL
;
690 #ifdef HW_MOUSE_ACCEL
691 if (s
->ds
->mouse_set
)
692 caps
|= SVGA_CAP_CURSOR
| SVGA_CAP_CURSOR_BYPASS_2
|
693 SVGA_CAP_CURSOR_BYPASS
;
697 case SVGA_REG_MEM_START
:
698 return s
->vram_base
+ s
->vram_size
- SVGA_FIFO_SIZE
;
700 case SVGA_REG_MEM_SIZE
:
701 return SVGA_FIFO_SIZE
;
703 case SVGA_REG_CONFIG_DONE
:
710 case SVGA_REG_GUEST_ID
:
713 case SVGA_REG_CURSOR_ID
:
716 case SVGA_REG_CURSOR_X
:
719 case SVGA_REG_CURSOR_Y
:
722 case SVGA_REG_CURSOR_ON
:
725 case SVGA_REG_HOST_BITS_PER_PIXEL
:
726 return (s
->depth
+ 7) & ~7;
728 case SVGA_REG_SCRATCH_SIZE
:
729 return s
->scratch_size
;
731 case SVGA_REG_MEM_REGS
:
732 case SVGA_REG_NUM_DISPLAYS
:
733 case SVGA_REG_PITCHLOCK
:
734 case SVGA_PALETTE_BASE
... SVGA_PALETTE_END
:
738 if (s
->index
>= SVGA_SCRATCH_BASE
&&
739 s
->index
< SVGA_SCRATCH_BASE
+ s
->scratch_size
)
740 return s
->scratch
[s
->index
- SVGA_SCRATCH_BASE
];
741 printf("%s: Bad register %02x\n", __FUNCTION__
, s
->index
);
747 static void vmsvga_value_write(void *opaque
, uint32_t address
, uint32_t value
)
749 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
752 if (value
== SVGA_ID_2
|| value
== SVGA_ID_1
|| value
== SVGA_ID_0
)
756 case SVGA_REG_ENABLE
:
758 s
->config
&= !!value
;
763 s
->invalidate(opaque
);
766 s
->fb_size
= ((s
->depth
+ 7) >> 3) * s
->new_width
* s
->new_height
;
770 s
->new_width
= value
;
774 case SVGA_REG_HEIGHT
:
775 s
->new_height
= value
;
780 case SVGA_REG_BITS_PER_PIXEL
:
781 if (value
!= s
->depth
) {
782 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__
, value
);
787 case SVGA_REG_CONFIG_DONE
:
789 s
->fifo
= (uint32_t *) &s
->vram
[s
->vram_size
- SVGA_FIFO_SIZE
];
790 /* Check range and alignment. */
791 if ((s
->cmd
->min
| s
->cmd
->max
|
792 s
->cmd
->next_cmd
| s
->cmd
->stop
) & 3)
794 if (s
->cmd
->min
< (uint8_t *) s
->cmd
->fifo
- (uint8_t *) s
->fifo
)
796 if (s
->cmd
->max
> SVGA_FIFO_SIZE
)
798 if (s
->cmd
->max
< s
->cmd
->min
+ 10 * 1024)
806 vmsvga_fifo_run(s
); /* Or should we just wait for update_display? */
809 case SVGA_REG_GUEST_ID
:
812 if (value
>= GUEST_OS_BASE
&& value
< GUEST_OS_BASE
+
813 sizeof(vmsvga_guest_id
) / sizeof(*vmsvga_guest_id
))
814 printf("%s: guest runs %s.\n", __FUNCTION__
,
815 vmsvga_guest_id
[value
- GUEST_OS_BASE
]);
819 case SVGA_REG_CURSOR_ID
:
820 s
->cursor
.id
= value
;
823 case SVGA_REG_CURSOR_X
:
827 case SVGA_REG_CURSOR_Y
:
831 case SVGA_REG_CURSOR_ON
:
832 s
->cursor
.on
|= (value
== SVGA_CURSOR_ON_SHOW
);
833 s
->cursor
.on
&= (value
!= SVGA_CURSOR_ON_HIDE
);
834 #ifdef HW_MOUSE_ACCEL
835 if (s
->ds
->mouse_set
&& value
<= SVGA_CURSOR_ON_SHOW
)
836 s
->ds
->mouse_set(s
->cursor
.x
, s
->cursor
.y
, s
->cursor
.on
);
840 case SVGA_REG_MEM_REGS
:
841 case SVGA_REG_NUM_DISPLAYS
:
842 case SVGA_REG_PITCHLOCK
:
843 case SVGA_PALETTE_BASE
... SVGA_PALETTE_END
:
847 if (s
->index
>= SVGA_SCRATCH_BASE
&&
848 s
->index
< SVGA_SCRATCH_BASE
+ s
->scratch_size
) {
849 s
->scratch
[s
->index
- SVGA_SCRATCH_BASE
] = value
;
852 printf("%s: Bad register %02x\n", __FUNCTION__
, s
->index
);
856 static uint32_t vmsvga_bios_read(void *opaque
, uint32_t address
)
858 printf("%s: what are we supposed to return?\n", __FUNCTION__
);
862 static void vmsvga_bios_write(void *opaque
, uint32_t address
, uint32_t data
)
864 printf("%s: what are we supposed to do with (%08x)?\n",
868 static inline void vmsvga_size(struct vmsvga_state_s
*s
)
870 if (s
->new_width
!= s
->width
|| s
->new_height
!= s
->height
) {
871 s
->width
= s
->new_width
;
872 s
->height
= s
->new_height
;
873 qemu_console_resize(s
->console
, s
->width
, s
->height
);
878 static void vmsvga_update_display(void *opaque
)
880 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
891 vmsvga_update_rect_flush(s
);
894 * Is it more efficient to look at vram VGA-dirty bits or wait
895 * for the driver to issue SVGA_CMD_UPDATE?
897 if (s
->invalidated
) {
899 vmsvga_update_screen(s
);
903 static void vmsvga_reset(struct vmsvga_state_s
*s
)
911 s
->depth
= s
->ds
->depth
? s
->ds
->depth
: 24;
912 s
->bypp
= (s
->depth
+ 7) >> 3;
914 s
->redraw_fifo_first
= 0;
915 s
->redraw_fifo_last
= 0;
918 s
->wred
= 0x00000007;
919 s
->wgreen
= 0x00000038;
920 s
->wblue
= 0x000000c0;
923 s
->wred
= 0x0000001f;
924 s
->wgreen
= 0x000003e0;
925 s
->wblue
= 0x00007c00;
928 s
->wred
= 0x0000001f;
929 s
->wgreen
= 0x000007e0;
930 s
->wblue
= 0x0000f800;
933 s
->wred
= 0x00ff0000;
934 s
->wgreen
= 0x0000ff00;
935 s
->wblue
= 0x000000ff;
938 s
->wred
= 0x00ff0000;
939 s
->wgreen
= 0x0000ff00;
940 s
->wblue
= 0x000000ff;
946 static void vmsvga_invalidate_display(void *opaque
)
948 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
951 s
->invalidate(opaque
);
959 /* save the vga display in a PPM image even if no display is
961 static void vmsvga_screen_dump(void *opaque
, const char *filename
)
963 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
966 s
->screen_dump(opaque
, filename
);
971 if (s
->depth
== 32) {
972 ppm_save(filename
, s
->vram
, s
->width
, s
->height
, s
->ds
->linesize
);
976 static void vmsvga_text_update(void *opaque
, console_ch_t
*chardata
)
978 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
981 s
->text_update(opaque
, chardata
);
985 static uint32_t vmsvga_vram_readb(void *opaque
, target_phys_addr_t addr
)
987 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
988 addr
-= s
->vram_base
;
989 if (addr
< s
->fb_size
)
990 return *(uint8_t *) (s
->ds
->data
+ addr
);
992 return *(uint8_t *) (s
->vram
+ addr
);
995 static uint32_t vmsvga_vram_readw(void *opaque
, target_phys_addr_t addr
)
997 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
998 addr
-= s
->vram_base
;
999 if (addr
< s
->fb_size
)
1000 return *(uint16_t *) (s
->ds
->data
+ addr
);
1002 return *(uint16_t *) (s
->vram
+ addr
);
1005 static uint32_t vmsvga_vram_readl(void *opaque
, target_phys_addr_t addr
)
1007 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1008 addr
-= s
->vram_base
;
1009 if (addr
< s
->fb_size
)
1010 return *(uint32_t *) (s
->ds
->data
+ addr
);
1012 return *(uint32_t *) (s
->vram
+ addr
);
1015 static void vmsvga_vram_writeb(void *opaque
, target_phys_addr_t addr
,
1018 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1019 addr
-= s
->vram_base
;
1020 if (addr
< s
->fb_size
)
1021 *(uint8_t *) (s
->ds
->data
+ addr
) = value
;
1023 *(uint8_t *) (s
->vram
+ addr
) = value
;
1026 static void vmsvga_vram_writew(void *opaque
, target_phys_addr_t addr
,
1029 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1030 addr
-= s
->vram_base
;
1031 if (addr
< s
->fb_size
)
1032 *(uint16_t *) (s
->ds
->data
+ addr
) = value
;
1034 *(uint16_t *) (s
->vram
+ addr
) = value
;
1037 static void vmsvga_vram_writel(void *opaque
, target_phys_addr_t addr
,
1040 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1041 addr
-= s
->vram_base
;
1042 if (addr
< s
->fb_size
)
1043 *(uint32_t *) (s
->ds
->data
+ addr
) = value
;
1045 *(uint32_t *) (s
->vram
+ addr
) = value
;
1048 static CPUReadMemoryFunc
*vmsvga_vram_read
[] = {
1054 static CPUWriteMemoryFunc
*vmsvga_vram_write
[] = {
1061 static void vmsvga_save(struct vmsvga_state_s
*s
, QEMUFile
*f
)
1063 qemu_put_be32(f
, s
->depth
);
1064 qemu_put_be32(f
, s
->enable
);
1065 qemu_put_be32(f
, s
->config
);
1066 qemu_put_be32(f
, s
->cursor
.id
);
1067 qemu_put_be32(f
, s
->cursor
.x
);
1068 qemu_put_be32(f
, s
->cursor
.y
);
1069 qemu_put_be32(f
, s
->cursor
.on
);
1070 qemu_put_be32(f
, s
->index
);
1071 qemu_put_buffer(f
, (uint8_t *) s
->scratch
, s
->scratch_size
* 4);
1072 qemu_put_be32(f
, s
->new_width
);
1073 qemu_put_be32(f
, s
->new_height
);
1074 qemu_put_be32s(f
, &s
->guest
);
1075 qemu_put_be32s(f
, &s
->svgaid
);
1076 qemu_put_be32(f
, s
->syncing
);
1077 qemu_put_be32(f
, s
->fb_size
);
1080 static int vmsvga_load(struct vmsvga_state_s
*s
, QEMUFile
*f
)
1083 depth
=qemu_get_be32(f
);
1084 s
->enable
=qemu_get_be32(f
);
1085 s
->config
=qemu_get_be32(f
);
1086 s
->cursor
.id
=qemu_get_be32(f
);
1087 s
->cursor
.x
=qemu_get_be32(f
);
1088 s
->cursor
.y
=qemu_get_be32(f
);
1089 s
->cursor
.on
=qemu_get_be32(f
);
1090 s
->index
=qemu_get_be32(f
);
1091 qemu_get_buffer(f
, (uint8_t *) s
->scratch
, s
->scratch_size
* 4);
1092 s
->new_width
=qemu_get_be32(f
);
1093 s
->new_height
=qemu_get_be32(f
);
1094 qemu_get_be32s(f
, &s
->guest
);
1095 qemu_get_be32s(f
, &s
->svgaid
);
1096 s
->syncing
=qemu_get_be32(f
);
1097 s
->fb_size
=qemu_get_be32(f
);
1099 if (s
->enable
&& depth
!= s
->depth
) {
1100 printf("%s: need colour depth of %i bits to resume operation.\n",
1101 __FUNCTION__
, depth
);
1107 s
->fifo
= (uint32_t *) &s
->vram
[s
->vram_size
- SVGA_FIFO_SIZE
];
1112 static void vmsvga_init(struct vmsvga_state_s
*s
, DisplayState
*ds
,
1113 uint8_t *vga_ram_base
, unsigned long vga_ram_offset
,
1117 s
->vram
= vga_ram_base
;
1118 s
->vram_size
= vga_ram_size
;
1119 s
->vram_offset
= vga_ram_offset
;
1121 s
->scratch_size
= SVGA_SCRATCH_SIZE
;
1122 s
->scratch
= (uint32_t *) qemu_malloc(s
->scratch_size
* 4);
1126 s
->console
= graphic_console_init(ds
, vmsvga_update_display
,
1127 vmsvga_invalidate_display
,
1129 vmsvga_text_update
, s
);
1132 vga_common_init((VGAState
*) s
, ds
,
1133 vga_ram_base
, vga_ram_offset
, vga_ram_size
);
1134 vga_init((VGAState
*) s
);
1138 static void pci_vmsvga_save(QEMUFile
*f
, void *opaque
)
1140 struct pci_vmsvga_state_s
*s
= (struct pci_vmsvga_state_s
*) opaque
;
1141 pci_device_save(&s
->card
, f
);
1142 vmsvga_save(&s
->chip
, f
);
1145 static int pci_vmsvga_load(QEMUFile
*f
, void *opaque
, int version_id
)
1147 struct pci_vmsvga_state_s
*s
= (struct pci_vmsvga_state_s
*) opaque
;
1150 ret
= pci_device_load(&s
->card
, f
);
1154 ret
= vmsvga_load(&s
->chip
, f
);
1161 static void pci_vmsvga_map_ioport(PCIDevice
*pci_dev
, int region_num
,
1162 uint32_t addr
, uint32_t size
, int type
)
1164 struct pci_vmsvga_state_s
*d
= (struct pci_vmsvga_state_s
*) pci_dev
;
1165 struct vmsvga_state_s
*s
= &d
->chip
;
1167 register_ioport_read(addr
+ SVGA_IO_MUL
* SVGA_INDEX_PORT
,
1168 1, 4, vmsvga_index_read
, s
);
1169 register_ioport_write(addr
+ SVGA_IO_MUL
* SVGA_INDEX_PORT
,
1170 1, 4, vmsvga_index_write
, s
);
1171 register_ioport_read(addr
+ SVGA_IO_MUL
* SVGA_VALUE_PORT
,
1172 1, 4, vmsvga_value_read
, s
);
1173 register_ioport_write(addr
+ SVGA_IO_MUL
* SVGA_VALUE_PORT
,
1174 1, 4, vmsvga_value_write
, s
);
1175 register_ioport_read(addr
+ SVGA_IO_MUL
* SVGA_BIOS_PORT
,
1176 1, 4, vmsvga_bios_read
, s
);
1177 register_ioport_write(addr
+ SVGA_IO_MUL
* SVGA_BIOS_PORT
,
1178 1, 4, vmsvga_bios_write
, s
);
1181 static void pci_vmsvga_map_mem(PCIDevice
*pci_dev
, int region_num
,
1182 uint32_t addr
, uint32_t size
, int type
)
1184 struct pci_vmsvga_state_s
*d
= (struct pci_vmsvga_state_s
*) pci_dev
;
1185 struct vmsvga_state_s
*s
= &d
->chip
;
1188 s
->vram_base
= addr
;
1190 iomemtype
= cpu_register_io_memory(0, vmsvga_vram_read
,
1191 vmsvga_vram_write
, s
);
1193 iomemtype
= s
->vram_offset
| IO_MEM_RAM
;
1195 cpu_register_physical_memory(s
->vram_base
, s
->vram_size
,
1199 #define PCI_VENDOR_ID_VMWARE 0x15ad
1200 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
1201 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
1202 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
1203 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
1204 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
1205 #define PCI_CLASS_BASE_DISPLAY 0x03
1206 #define PCI_CLASS_SUB_VGA 0x00
1207 #define PCI_CLASS_HEADERTYPE_00h 0x00
1209 void pci_vmsvga_init(PCIBus
*bus
, DisplayState
*ds
, uint8_t *vga_ram_base
,
1210 unsigned long vga_ram_offset
, int vga_ram_size
)
1212 struct pci_vmsvga_state_s
*s
;
1214 /* Setup PCI configuration */
1215 s
= (struct pci_vmsvga_state_s
*)
1216 pci_register_device(bus
, "QEMUware SVGA",
1217 sizeof(struct pci_vmsvga_state_s
), -1, 0, 0);
1218 s
->card
.config
[PCI_VENDOR_ID
] = PCI_VENDOR_ID_VMWARE
& 0xff;
1219 s
->card
.config
[PCI_VENDOR_ID
+ 1] = PCI_VENDOR_ID_VMWARE
>> 8;
1220 s
->card
.config
[PCI_DEVICE_ID
] = SVGA_PCI_DEVICE_ID
& 0xff;
1221 s
->card
.config
[PCI_DEVICE_ID
+ 1] = SVGA_PCI_DEVICE_ID
>> 8;
1222 s
->card
.config
[PCI_COMMAND
] = 0x07; /* I/O + Memory */
1223 s
->card
.config
[PCI_CLASS_DEVICE
] = PCI_CLASS_SUB_VGA
;
1224 s
->card
.config
[0x0b] = PCI_CLASS_BASE_DISPLAY
;
1225 s
->card
.config
[0x0c] = 0x08; /* Cache line size */
1226 s
->card
.config
[0x0d] = 0x40; /* Latency timer */
1227 s
->card
.config
[0x0e] = PCI_CLASS_HEADERTYPE_00h
;
1228 s
->card
.config
[0x10] = ((SVGA_IO_BASE
>> 0) & 0xff) | 1;
1229 s
->card
.config
[0x11] = (SVGA_IO_BASE
>> 8) & 0xff;
1230 s
->card
.config
[0x12] = (SVGA_IO_BASE
>> 16) & 0xff;
1231 s
->card
.config
[0x13] = (SVGA_IO_BASE
>> 24) & 0xff;
1232 s
->card
.config
[0x18] = (SVGA_MEM_BASE
>> 0) & 0xff;
1233 s
->card
.config
[0x19] = (SVGA_MEM_BASE
>> 8) & 0xff;
1234 s
->card
.config
[0x1a] = (SVGA_MEM_BASE
>> 16) & 0xff;
1235 s
->card
.config
[0x1b] = (SVGA_MEM_BASE
>> 24) & 0xff;
1236 s
->card
.config
[0x2c] = PCI_VENDOR_ID_VMWARE
& 0xff;
1237 s
->card
.config
[0x2d] = PCI_VENDOR_ID_VMWARE
>> 8;
1238 s
->card
.config
[0x2e] = SVGA_PCI_DEVICE_ID
& 0xff;
1239 s
->card
.config
[0x2f] = SVGA_PCI_DEVICE_ID
>> 8;
1240 s
->card
.config
[0x3c] = 0xff; /* End */
1242 pci_register_io_region(&s
->card
, 0, 0x10,
1243 PCI_ADDRESS_SPACE_IO
, pci_vmsvga_map_ioport
);
1244 pci_register_io_region(&s
->card
, 1, vga_ram_size
,
1245 PCI_ADDRESS_SPACE_MEM_PREFETCH
, pci_vmsvga_map_mem
);
1247 vmsvga_init(&s
->chip
, ds
, vga_ram_base
, vga_ram_offset
, vga_ram_size
);
1249 register_savevm("vmware_vga", 0, 0, pci_vmsvga_save
, pci_vmsvga_load
, s
);