Handle SEJ notifications
[qemu-kvm/fedora.git] / cpu-defs.h
blob6387a2fb436e5a1eae14a5480d3f22162ed2776b
1 /*
2 * common defines for all CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef CPU_DEFS_H
21 #define CPU_DEFS_H
23 #ifndef NEED_CPU_H
24 #error cpu.h included from common code
25 #endif
27 #include "config.h"
28 #include <setjmp.h>
29 #include <inttypes.h>
30 #include "osdep.h"
32 #ifndef TARGET_LONG_BITS
33 #error TARGET_LONG_BITS must be defined before including this header
34 #endif
36 #ifndef TARGET_PHYS_ADDR_BITS
37 #if TARGET_LONG_BITS >= HOST_LONG_BITS
38 #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
39 #else
40 #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
41 #endif
42 #endif
44 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
46 /* target_ulong is the type of a virtual address */
47 #if TARGET_LONG_SIZE == 4
48 typedef int32_t target_long;
49 typedef uint32_t target_ulong;
50 #define TARGET_FMT_lx "%08x"
51 #define TARGET_FMT_ld "%d"
52 #define TARGET_FMT_lu "%u"
53 #elif TARGET_LONG_SIZE == 8
54 typedef int64_t target_long;
55 typedef uint64_t target_ulong;
56 #define TARGET_FMT_lx "%016" PRIx64
57 #define TARGET_FMT_ld "%" PRId64
58 #define TARGET_FMT_lu "%" PRIu64
59 #else
60 #error TARGET_LONG_SIZE undefined
61 #endif
63 /* target_phys_addr_t is the type of a physical address (its size can
64 be different from 'target_ulong'). We have sizeof(target_phys_addr)
65 = max(sizeof(unsigned long),
66 sizeof(size_of_target_physical_address)) because we must pass a
67 host pointer to memory operations in some cases */
69 #if TARGET_PHYS_ADDR_BITS == 32
70 typedef uint32_t target_phys_addr_t;
71 #define TARGET_FMT_plx "%08x"
72 #elif TARGET_PHYS_ADDR_BITS == 64
73 typedef uint64_t target_phys_addr_t;
74 #define TARGET_FMT_plx "%016" PRIx64
75 #else
76 #error TARGET_PHYS_ADDR_BITS undefined
77 #endif
79 /* address in the RAM (different from a physical address) */
80 typedef unsigned long ram_addr_t;
82 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
84 #define EXCP_INTERRUPT 0x10000 /* async interruption */
85 #define EXCP_HLT 0x10001 /* hlt instruction reached */
86 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
87 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
88 #define MAX_BREAKPOINTS 32
89 #define MAX_WATCHPOINTS 32
91 #define TB_JMP_CACHE_BITS 12
92 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
94 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
95 addresses on the same page. The top bits are the same. This allows
96 TLB invalidation to quickly clear a subset of the hash table. */
97 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
98 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
99 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
100 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
102 #define CPU_TLB_BITS 8
103 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
105 #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
106 #define CPU_TLB_ENTRY_BITS 4
107 #else
108 #define CPU_TLB_ENTRY_BITS 5
109 #endif
111 typedef struct CPUTLBEntry {
112 /* bit 31 to TARGET_PAGE_BITS : virtual address
113 bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
114 zone number
115 bit 3 : indicates that the entry is invalid
116 bit 2..0 : zero
118 target_ulong addr_read;
119 target_ulong addr_write;
120 target_ulong addr_code;
121 /* addend to virtual address to get physical address */
122 #if TARGET_PHYS_ADDR_BITS == 64
123 /* on i386 Linux make sure it is aligned */
124 target_phys_addr_t addend __attribute__((aligned(8)));
125 #else
126 target_phys_addr_t addend;
127 #endif
128 /* padding to get a power of two size */
129 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
130 (sizeof(target_ulong) * 3 +
131 ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
132 sizeof(target_phys_addr_t))];
133 } CPUTLBEntry;
135 #define CPU_COMMON \
136 struct TranslationBlock *current_tb; /* currently executing TB */ \
137 /* soft mmu support */ \
138 /* in order to avoid passing too many arguments to the memory \
139 write helpers, we store some rarely used information in the CPU \
140 context) */ \
141 unsigned long mem_write_pc; /* host pc at which the memory was \
142 written */ \
143 target_ulong mem_write_vaddr; /* target virtual addr at which the \
144 memory was written */ \
145 /* The meaning of the MMU modes is defined in the target code. */ \
146 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
147 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
148 long temp_buf[128]; /* buffer for temporaries in the code generator */ \
150 /* from this point: preserved by CPU reset */ \
151 /* ice debug support */ \
152 target_ulong breakpoints[MAX_BREAKPOINTS]; \
153 int nb_breakpoints; \
154 int singlestep_enabled; \
156 struct { \
157 target_ulong vaddr; \
158 target_phys_addr_t addend; \
159 } watchpoint[MAX_WATCHPOINTS]; \
160 int nb_watchpoints; \
161 int watchpoint_hit; \
163 void *next_cpu; /* next CPU sharing TB cache */ \
164 int cpu_index; /* CPU index (informative) */ \
165 int thread_id; \
166 /* user data */ \
167 void *opaque; \
169 const char *cpu_model_str;
171 #endif