hw/ipf.c

   1 /*
   2  * Itanium Platforma Emulator derived from QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Copyright (c) 2007 Intel
   7  * Ported for IA64 Platform Zhang Xiantao <xiantao.zhang@intel.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "hw.h"
  29 #include "pc.h"
  30 #include "fdc.h"
  31 #include "pci.h"
  32 #include "block.h"
  33 #include "sysemu.h"
  34 #include "audio/audio.h"
  35 #include "net.h"
  36 #include "smbus.h"
  37 #include "boards.h"
  38 #include "firmware.h"
  39 #include "ia64intrin.h"
  40 #include <unistd.h>
  41
  42 #include "qemu-kvm.h"
  43
  44 #define FW_FILENAME "Flash.fd"
  45
  46 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  47 #define ACPI_DATA_SIZE       0x10000
  48
  49 #define MAX_IDE_BUS 2
  50
  51 static fdctrl_t *floppy_controller;
  52 static RTCState *rtc_state;
  53 static PCIDevice *i440fx_state;
  54
  55 static uint32_t ipf_to_legacy_io(target_phys_addr_t addr)
  56 {
  57         return (uint32_t)(((addr&0x3ffffff) >> 12 << 2)|((addr) & 0x3));
  58 }
  59
  60 static void ipf_legacy_io_writeb(void *opaque, target_phys_addr_t addr,
  61                                  uint32_t val) {
  62         uint32_t port = ipf_to_legacy_io(addr);
  63         cpu_outb(0, port, val);
  64 }
  65
  66 static void ipf_legacy_io_writew(void *opaque, target_phys_addr_t addr,
  67                                  uint32_t val) {
  68         uint32_t port = ipf_to_legacy_io(addr);
  69
  70         cpu_outw(0, port, val);
  71 }
  72
  73 static void ipf_legacy_io_writel(void *opaque, target_phys_addr_t addr,
  74                                  uint32_t val) {
  75         uint32_t port = ipf_to_legacy_io(addr);
  76
  77         cpu_outl(0, port, val);
  78 }
  79
  80 static uint32_t ipf_legacy_io_readb(void *opaque, target_phys_addr_t addr)
  81 {
  82         uint32_t port = ipf_to_legacy_io(addr);
  83
  84         return cpu_inb(0, port);
  85 }
  86
  87 static uint32_t ipf_legacy_io_readw(void *opaque, target_phys_addr_t addr)
  88 {
  89         uint32_t port = ipf_to_legacy_io(addr);
  90
  91         return cpu_inw(0, port);
  92 }
  93
  94 static uint32_t ipf_legacy_io_readl(void *opaque, target_phys_addr_t addr)
  95 {
  96         uint32_t port = ipf_to_legacy_io(addr);
  97
  98         return cpu_inl(0, port);
  99 }
 100
 101 static CPUReadMemoryFunc *ipf_legacy_io_read[3] = {
 102     ipf_legacy_io_readb,
 103     ipf_legacy_io_readw,
 104     ipf_legacy_io_readl,
 105 };
 106
 107 static CPUWriteMemoryFunc *ipf_legacy_io_write[3] = {
 108     ipf_legacy_io_writeb,
 109     ipf_legacy_io_writew,
 110     ipf_legacy_io_writel,
 111 };
 112
 113 static void pic_irq_request(void *opaque, int irq, int level)
 114 {
 115         fprintf(stderr,"pic_irq_request called!\n");
 116 }
 117
 118 /* PC cmos mappings */
 119
 120 #define REG_EQUIPMENT_BYTE          0x14
 121
 122 static int cmos_get_fd_drive_type(int fd0)
 123 {
 124     int val;
 125
 126     switch (fd0) {
 127     case 0:
 128         /* 1.44 Mb 3"5 drive */
 129         val = 4;
 130         break;
 131     case 1:
 132         /* 2.88 Mb 3"5 drive */
 133         val = 5;
 134         break;
 135     case 2:
 136         /* 1.2 Mb 5"5 drive */
 137         val = 2;
 138         break;
 139     default:
 140         val = 0;
 141         break;
 142     }
 143     return val;
 144 }
 145
 146 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 147 {
 148     RTCState *s = rtc_state;
 149     int cylinders, heads, sectors;
 150     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 151     rtc_set_memory(s, type_ofs, 47);
 152     rtc_set_memory(s, info_ofs, cylinders);
 153     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 154     rtc_set_memory(s, info_ofs + 2, heads);
 155     rtc_set_memory(s, info_ofs + 3, 0xff);
 156     rtc_set_memory(s, info_ofs + 4, 0xff);
 157     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 158     rtc_set_memory(s, info_ofs + 6, cylinders);
 159     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 160     rtc_set_memory(s, info_ofs + 8, sectors);
 161 }
 162
 163 /* convert boot_device letter to something recognizable by the bios */
 164 static int boot_device2nibble(char boot_device)
 165 {
 166     switch(boot_device) {
 167     case 'a':
 168     case 'b':
 169         return 0x01; /* floppy boot */
 170     case 'c':
 171         return 0x02; /* hard drive boot */
 172     case 'd':
 173         return 0x03; /* CD-ROM boot */
 174     case 'n':
 175         return 0x04; /* Network boot */
 176     }
 177     return 0;
 178 }
 179
 180 /* hd_table must contain 4 block drivers */
 181 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 182                       const char *boot_device, BlockDriverState **hd_table,
 183                       int smp_cpus)
 184 {
 185     RTCState *s = rtc_state;
 186     int nbds, bds[3] = { 0, };
 187     int val;
 188     int fd0, fd1, nb;
 189     int i;
 190
 191     /* various important CMOS locations needed by PC/Bochs bios */
 192
 193     /* memory size */
 194     val = 640; /* base memory in K */
 195     rtc_set_memory(s, 0x15, val);
 196     rtc_set_memory(s, 0x16, val >> 8);
 197
 198     val = (ram_size / 1024) - 1024;
 199     if (val > 65535)
 200         val = 65535;
 201     rtc_set_memory(s, 0x17, val);
 202     rtc_set_memory(s, 0x18, val >> 8);
 203     rtc_set_memory(s, 0x30, val);
 204     rtc_set_memory(s, 0x31, val >> 8);
 205
 206     if (above_4g_mem_size) {
 207         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 208         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 209         rtc_set_memory(s, 0x5d, above_4g_mem_size >> 32);
 210     }
 211     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 212
 213     if (ram_size > (16 * 1024 * 1024))
 214         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 215     else
 216         val = 0;
 217     if (val > 65535)
 218         val = 65535;
 219     rtc_set_memory(s, 0x34, val);
 220     rtc_set_memory(s, 0x35, val >> 8);
 221
 222     /* set boot devices, and disable floppy signature check if requested */
 223 #define PC_MAX_BOOT_DEVICES 3
 224     nbds = strlen(boot_device);
 225     if (nbds > PC_MAX_BOOT_DEVICES) {
 226         fprintf(stderr, "Too many boot devices for PC\n");
 227         exit(1);
 228     }
 229     for (i = 0; i < nbds; i++) {
 230         bds[i] = boot_device2nibble(boot_device[i]);
 231         if (bds[i] == 0) {
 232             fprintf(stderr, "Invalid boot device for PC: '%c'\n",
 233                     boot_device[i]);
 234             exit(1);
 235         }
 236     }
 237     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 238     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
 239
 240     /* floppy type */
 241
 242     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 243     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 244
 245     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 246     rtc_set_memory(s, 0x10, val);
 247
 248     val = 0;
 249     nb = 0;
 250     if (fd0 < 3)
 251         nb++;
 252     if (fd1 < 3)
 253         nb++;
 254     switch (nb) {
 255     case 0:
 256         break;
 257     case 1:
 258         val |= 0x01; /* 1 drive, ready for boot */
 259         break;
 260     case 2:
 261         val |= 0x41; /* 2 drives, ready for boot */
 262         break;
 263     }
 264     val |= 0x02; /* FPU is there */
 265     val |= 0x04; /* PS/2 mouse installed */
 266     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 267
 268     /* hard drives */
 269
 270     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 271     if (hd_table[0])
 272         cmos_init_hd(0x19, 0x1b, hd_table[0]);
 273     if (hd_table[1])
 274         cmos_init_hd(0x1a, 0x24, hd_table[1]);
 275
 276     val = 0;
 277     for (i = 0; i < 4; i++) {
 278         if (hd_table[i]) {
 279             int cylinders, heads, sectors, translation;
 280             /* NOTE: bdrv_get_geometry_hint() returns the physical
 281                 geometry.  It is always such that: 1 <= sects <= 63, 1
 282                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 283                 geometry can be different if a translation is done. */
 284             translation = bdrv_get_translation_hint(hd_table[i]);
 285             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 286                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 287                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 288                     /* No translation. */
 289                     translation = 0;
 290                 } else {
 291                     /* LBA translation. */
 292                     translation = 1;
 293                 }
 294             } else {
 295                 translation--;
 296             }
 297             val |= translation << (i * 2);
 298         }
 299     }
 300     rtc_set_memory(s, 0x39, val);
 301 }
 302
 303 static void main_cpu_reset(void *opaque)
 304 {
 305     CPUState *env = opaque;
 306     cpu_reset(env);
 307 }
 308
 309 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 310 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 311 static const int ide_irq[2] = { 14, 15 };
 312
 313 #define NE2000_NB_MAX 6
 314
 315 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
 316 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 317
 318 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 319 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 320
 321 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 322 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 323
 324 #ifdef HAS_AUDIO
 325 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 326 {
 327     struct soundhw *c;
 328     int audio_enabled = 0;
 329
 330     for (c = soundhw; !audio_enabled && c->name; ++c) {
 331         audio_enabled = c->enabled;
 332     }
 333
 334     if (audio_enabled) {
 335         AudioState *s;
 336
 337         s = AUD_init ();
 338         if (s) {
 339             for (c = soundhw; c->name; ++c) {
 340                 if (c->enabled) {
 341                     if (c->isa) {
 342                         c->init.init_isa (s, pic);
 343                     }
 344                     else {
 345                         if (pci_bus) {
 346                             c->init.init_pci (pci_bus, s);
 347                         }
 348                     }
 349                 }
 350             }
 351         }
 352     }
 353 }
 354 #endif
 355
 356 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 357 {
 358     static int nb_ne2k = 0;
 359
 360     if (nb_ne2k == NE2000_NB_MAX)
 361         return;
 362     isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
 363     nb_ne2k++;
 364 }
 365
 366 /* Itanium hardware initialisation */
 367 static void ipf_init1(ram_addr_t ram_size, int vga_ram_size,
 368                      const char *boot_device, DisplayState *ds,
 369                      const char *kernel_filename, const char *kernel_cmdline,
 370                      const char *initrd_filename,
 371                      int pci_enabled, const char *cpu_model)
 372 {
 373     char buf[1024];
 374     int i;
 375     ram_addr_t ram_addr, vga_ram_addr;
 376     ram_addr_t above_4g_mem_size = 0;
 377     PCIBus *pci_bus;
 378     int piix3_devfn = -1;
 379     CPUState *env;
 380     NICInfo *nd;
 381     qemu_irq *cpu_irq;
 382     qemu_irq *i8259;
 383     int page_size;
 384     int index;
 385     unsigned long ipf_legacy_io_base, ipf_legacy_io_mem;
 386     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 387     BlockDriverState *fd[MAX_FD];
 388
 389     page_size = getpagesize();
 390     if (page_size != TARGET_PAGE_SIZE) {
 391         fprintf(stderr,"Error! Host page size != qemu target page size,"
 392                         " you may need to change TARGET_PAGE_BITS in qemu!"
 393                         "host page size:0x%x\n", page_size);
 394                 exit(-1);
 395     };
 396
 397     if (ram_size >= 0xc0000000 ) {
 398         above_4g_mem_size = ram_size - 0xc0000000;
 399         ram_size = 0xc0000000;
 400     }
 401
 402     /* init CPUs */
 403     if (cpu_model == NULL) {
 404         cpu_model = "IA64";
 405     }
 406
 407     for(i = 0; i < smp_cpus; i++) {
 408         env = cpu_init(cpu_model);
 409         if (!env) {
 410             fprintf(stderr, "Unable to find CPU definition\n");
 411             exit(1);
 412         }
 413         if (i != 0)
 414             env->hflags |= HF_HALTED_MASK;
 415         register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
 416         qemu_register_reset(main_cpu_reset, env);
 417     }
 418
 419         /* allocate RAM */
 420 #ifdef KVM_CAP_USER_MEMORY
 421         if (kvm_enabled() && kvm_qemu_check_extension(KVM_CAP_USER_MEMORY)) {
 422                 ram_addr = qemu_ram_alloc(0xa0000);
 423                 cpu_register_physical_memory(0, 0xa0000, ram_addr);
 424                 kvm_cpu_register_physical_memory(0, 0xa0000, ram_addr);
 425
 426                 ram_addr = qemu_ram_alloc(0x20000); // Workaround 0xa0000-0xc0000
 427
 428                 ram_addr = qemu_ram_alloc(0x40000);
 429                 cpu_register_physical_memory(0xc0000, 0x40000, ram_addr);
 430                 kvm_cpu_register_physical_memory(0xc0000, 0x40000, ram_addr);
 431
 432                 ram_addr = qemu_ram_alloc(ram_size - 0x100000);
 433                 cpu_register_physical_memory(0x100000, ram_size - 0x100000, ram_addr);
 434                 kvm_cpu_register_physical_memory(0x100000, ram_size - 0x100000,
 435                                 ram_addr);
 436         } else
 437 #endif
 438     {
 439         ram_addr = qemu_ram_alloc(ram_size);
 440         cpu_register_physical_memory(0, ram_size, ram_addr);
 441     }
 442     /* allocate VGA RAM */
 443     vga_ram_addr = qemu_ram_alloc(vga_ram_size);
 444
 445         /* above 4giga memory allocation */
 446         if (above_4g_mem_size > 0) {
 447                 ram_addr = qemu_ram_alloc(above_4g_mem_size);
 448                 cpu_register_physical_memory(0x100000000, above_4g_mem_size, ram_addr);
 449         if (kvm_enabled())
 450                 kvm_cpu_register_physical_memory(0x100000000, above_4g_mem_size,
 451                                         ram_addr);
 452         }
 453
 454         /*Load firware to its proper position.*/
 455         if (kvm_enabled()) {
 456                 int r;
 457                 unsigned long  image_size;
 458                 char *image = NULL;
 459                 char *fw_image_start;
 460                 ram_addr_t fw_offset = qemu_ram_alloc(GFW_SIZE);
 461                 char *fw_start = phys_ram_base + fw_offset;
 462
 463                 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, FW_FILENAME);
 464                 image = read_image(buf, &image_size );
 465                 if (NULL == image || !image_size) {
 466                         fprintf(stderr, "Error when reading Guest Firmware!\n");
 467                         fprintf(stderr, "Please check Guest firmware at %s\n", buf);
 468                         exit(1);
 469                 }
 470                 fw_image_start = fw_start + GFW_SIZE - image_size;
 471
 472 #ifdef KVM_CAP_USER_MEMORY
 473                 r = kvm_qemu_check_extension(KVM_CAP_USER_MEMORY);
 474                 if (r) {
 475                         cpu_register_physical_memory(GFW_START, GFW_SIZE, fw_offset);
 476                         kvm_cpu_register_physical_memory(GFW_START,GFW_SIZE, fw_offset);
 477                         memcpy(fw_image_start, image, image_size);
 478                 }
 479                 else
 480 #endif
 481                 {
 482                         fw_start = kvm_create_phys_mem(kvm_context, (uint32_t)(-image_size),
 483                                         image_size, 0, 1);
 484                         if (!fw_start)
 485                                 exit(1);
 486                         fw_image_start = fw_start + GFW_SIZE - image_size;
 487                         memcpy(fw_image_start, image, image_size);
 488                 }
 489                 free(image);
 490                 flush_icache_range((unsigned long)fw_image_start,
 491                         (unsigned long)fw_image_start + image_size);
 492                 kvm_ia64_build_hob(ram_size + above_4g_mem_size, smp_cpus, fw_start);
 493         }
 494
 495     /*Register legacy io address space, size:64M*/
 496     ipf_legacy_io_base = 0xE0000000;
 497     ipf_legacy_io_mem = cpu_register_io_memory(0, ipf_legacy_io_read,
 498                                                 ipf_legacy_io_write, NULL);
 499     cpu_register_physical_memory(ipf_legacy_io_base, 64*1024*1024, ipf_legacy_io_mem);
 500
 501     cpu_irq = qemu_allocate_irqs(pic_irq_request, first_cpu, 1);
 502     i8259 = i8259_init(cpu_irq[0]);
 503
 504     if (pci_enabled) {
 505         pci_bus = i440fx_init(&i440fx_state, i8259);
 506         piix3_devfn = piix3_init(pci_bus, -1);
 507     } else {
 508         pci_bus = NULL;
 509     }
 510
 511     if (cirrus_vga_enabled) {
 512         if (pci_enabled) {
 513             pci_cirrus_vga_init(pci_bus,
 514                                 ds, phys_ram_base + vga_ram_addr,
 515                                 vga_ram_addr, vga_ram_size);
 516         } else {
 517             isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr,
 518                                 vga_ram_addr, vga_ram_size);
 519         }
 520     } else {
 521         if (pci_enabled) {
 522             pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
 523                          vga_ram_addr, vga_ram_size, 0, 0);
 524         } else {
 525             isa_vga_init(ds, phys_ram_base + vga_ram_addr,
 526                          vga_ram_addr, vga_ram_size);
 527         }
 528     }
 529
 530     rtc_state = rtc_init(0x70, i8259[8]);
 531
 532     if (pci_enabled) {
 533         pic_set_alt_irq_func(isa_pic, NULL, NULL);
 534     }
 535
 536     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 537         if (serial_hds[i]) {
 538             serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
 539         }
 540     }
 541
 542     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 543         if (parallel_hds[i]) {
 544             parallel_init(parallel_io[i], i8259[parallel_irq[i]],
 545                           parallel_hds[i]);
 546         }
 547     }
 548
 549     for(i = 0; i < nb_nics; i++) {
 550         nd = &nd_table[i];
 551         if (!nd->model) {
 552             if (pci_enabled) {
 553                 nd->model = "ne2k_pci";
 554             } else {
 555                 nd->model = "ne2k_isa";
 556             }
 557         }
 558         if (strcmp(nd->model, "ne2k_isa") == 0) {
 559             pc_init_ne2k_isa(nd, i8259);
 560         } else if (pci_enabled) {
 561             if (strcmp(nd->model, "?") == 0)
 562                 fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
 563             if (!pci_nic_init(pci_bus, nd, -1))
 564                 exit(1);
 565         } else if (strcmp(nd->model, "?") == 0) {
 566             fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
 567             exit(1);
 568         } else {
 569             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 570             exit(1);
 571         }
 572     }
 573
 574 #undef USE_HYPERCALL  //Disable it now, need to implement later!
 575 #ifdef USE_HYPERCALL
 576     pci_hypercall_init(pci_bus);
 577 #endif
 578
 579     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 580         fprintf(stderr, "qemu: too many IDE bus\n");
 581         exit(1);
 582     }
 583
 584     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 585         index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 586         if (index != -1)
 587             hd[i] = drives_table[index].bdrv;
 588         else
 589             hd[i] = NULL;
 590     }
 591
 592     if (pci_enabled) {
 593         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
 594     } else {
 595         for(i = 0; i < MAX_IDE_BUS; i++) {
 596             isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 597                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
 598         }
 599     }
 600
 601     i8042_init(i8259[1], i8259[12], 0x60);
 602     DMA_init(0);
 603 #ifdef HAS_AUDIO
 604     audio_init(pci_enabled ? pci_bus : NULL, i8259);
 605 #endif
 606
 607     for(i = 0; i < MAX_FD; i++) {
 608         index = drive_get_index(IF_FLOPPY, 0, i);
 609         if (index != -1)
 610             fd[i] = drives_table[index].bdrv;
 611         else
 612             fd[i] = NULL;
 613     }
 614     floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
 615
 616     cmos_init(ram_size, above_4g_mem_size, boot_device, hd, smp_cpus);
 617
 618     if (pci_enabled && usb_enabled) {
 619         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
 620     }
 621
 622     if (pci_enabled && acpi_enabled) {
 623         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
 624         i2c_bus *smbus;
 625
 626         /* TODO: Populate SPD eeprom data.  */
 627         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
 628         for (i = 0; i < 8; i++) {
 629             smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
 630         }
 631     }
 632
 633     if (i440fx_state) {
 634         i440fx_init_memory_mappings(i440fx_state);
 635     }
 636
 637     if (pci_enabled) {
 638         int max_bus;
 639         int bus, unit;
 640         void *scsi;
 641
 642         max_bus = drive_get_max_bus(IF_SCSI);
 643
 644         for (bus = 0; bus <= max_bus; bus++) {
 645             scsi = lsi_scsi_init(pci_bus, -1);
 646             for (unit = 0; unit < LSI_MAX_DEVS; unit++) {
 647                 index = drive_get_index(IF_SCSI, bus, unit);
 648                 if (index == -1)
 649                     continue;
 650                 lsi_scsi_attach(scsi, drives_table[index].bdrv, unit);
 651             }
 652         }
 653     }
 654 }
 655
 656 static void ipf_init_pci(ram_addr_t ram_size, int vga_ram_size,
 657                         const char *boot_device, DisplayState *ds,
 658                         const char *kernel_filename,
 659                         const char *kernel_cmdline,
 660                         const char *initrd_filename,
 661                         const char *cpu_model)
 662 {
 663     ipf_init1(ram_size, vga_ram_size, boot_device, ds,
 664              kernel_filename, kernel_cmdline,
 665              initrd_filename, 1, cpu_model);
 666 }
 667
 668 QEMUMachine ipf_machine = {
 669     "itanium",
 670     "Itanium Platform",
 671     ipf_init_pci,
 672 };