hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "qemu-timer.h"
  23
  24 #include "qemu-kvm.h"
  25
  26 //#define DEBUG_APIC
  27 //#define DEBUG_IOAPIC
  28
  29 /* APIC Local Vector Table */
  30 #define APIC_LVT_TIMER   0
  31 #define APIC_LVT_THERMAL 1
  32 #define APIC_LVT_PERFORM 2
  33 #define APIC_LVT_LINT0   3
  34 #define APIC_LVT_LINT1   4
  35 #define APIC_LVT_ERROR   5
  36 #define APIC_LVT_NB      6
  37
  38 /* APIC delivery modes */
  39 #define APIC_DM_FIXED   0
  40 #define APIC_DM_LOWPRI  1
  41 #define APIC_DM_SMI     2
  42 #define APIC_DM_NMI     4
  43 #define APIC_DM_INIT    5
  44 #define APIC_DM_SIPI    6
  45 #define APIC_DM_EXTINT  7
  46
  47 /* APIC destination mode */
  48 #define APIC_DESTMODE_FLAT      0xf
  49 #define APIC_DESTMODE_CLUSTER   1
  50
  51 #define APIC_TRIGGER_EDGE  0
  52 #define APIC_TRIGGER_LEVEL 1
  53
  54 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  55 #define APIC_LVT_MASKED                 (1<<16)
  56 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  57 #define APIC_LVT_REMOTE_IRR             (1<<14)
  58 #define APIC_INPUT_POLARITY             (1<<13)
  59 #define APIC_SEND_PENDING               (1<<12)
  60
  61 /* FIXME: it's now hard coded to be equal with KVM_IOAPIC_NUM_PINS */
  62 #define IOAPIC_NUM_PINS                 0x18
  63 #define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
  64
  65 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  66
  67 #define APIC_SV_ENABLE (1 << 8)
  68
  69 #define MAX_APICS 255
  70 #define MAX_APIC_WORDS 8
  71
  72 typedef struct APICState {
  73     CPUState *cpu_env;
  74     uint32_t apicbase;
  75     uint8_t id;
  76     uint8_t arb_id;
  77     uint8_t tpr;
  78     uint32_t spurious_vec;
  79     uint8_t log_dest;
  80     uint8_t dest_mode;
  81     uint32_t isr[8];  /* in service register */
  82     uint32_t tmr[8];  /* trigger mode register */
  83     uint32_t irr[8]; /* interrupt request register */
  84     uint32_t lvt[APIC_LVT_NB];
  85     uint32_t esr; /* error register */
  86     uint32_t icr[2];
  87
  88     uint32_t divide_conf;
  89     int count_shift;
  90     uint32_t initial_count;
  91     int64_t initial_count_load_time, next_time;
  92     QEMUTimer *timer;
  93 } APICState;
  94
  95 struct IOAPICState {
  96     uint8_t id;
  97     uint8_t ioregsel;
  98     uint64_t base_address;
  99
 100     uint32_t irr;
 101     uint64_t ioredtbl[IOAPIC_NUM_PINS];
 102 };
 103
 104 static int apic_io_memory;
 105 static APICState *local_apics[MAX_APICS + 1];
 106 static int last_apic_id = 0;
 107
 108 static void apic_init_ipi(APICState *s);
 109 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 110 static void apic_update_irq(APICState *s);
 111
 112 /* Find first bit starting from msb. Return 0 if value = 0 */
 113 static int fls_bit(uint32_t value)
 114 {
 115     unsigned int ret = 0;
 116
 117 #if defined(HOST_I386)
 118     __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
 119     return ret;
 120 #else
 121     if (value > 0xffff)
 122         value >>= 16, ret = 16;
 123     if (value > 0xff)
 124         value >>= 8, ret += 8;
 125     if (value > 0xf)
 126         value >>= 4, ret += 4;
 127     if (value > 0x3)
 128         value >>= 2, ret += 2;
 129     return ret + (value >> 1);
 130 #endif
 131 }
 132
 133 /* Find first bit starting from lsb. Return 0 if value = 0 */
 134 static int ffs_bit(uint32_t value)
 135 {
 136     unsigned int ret = 0;
 137
 138 #if defined(HOST_I386)
 139     __asm__ __volatile__ ("bsf %1, %0\n" : "+r" (ret) : "rm" (value));
 140     return ret;
 141 #else
 142     if (!value)
 143         return 0;
 144     if (!(value & 0xffff))
 145         value >>= 16, ret = 16;
 146     if (!(value & 0xff))
 147         value >>= 8, ret += 8;
 148     if (!(value & 0xf))
 149         value >>= 4, ret += 4;
 150     if (!(value & 0x3))
 151         value >>= 2, ret += 2;
 152     if (!(value & 0x1))
 153         ret++;
 154     return ret;
 155 #endif
 156 }
 157
 158 static inline void set_bit(uint32_t *tab, int index)
 159 {
 160     int i, mask;
 161     i = index >> 5;
 162     mask = 1 << (index & 0x1f);
 163     tab[i] |= mask;
 164 }
 165
 166 static inline void reset_bit(uint32_t *tab, int index)
 167 {
 168     int i, mask;
 169     i = index >> 5;
 170     mask = 1 << (index & 0x1f);
 171     tab[i] &= ~mask;
 172 }
 173
 174 #define foreach_apic(apic, deliver_bitmask, code) \
 175 {\
 176     int __i, __j, __mask;\
 177     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 178         __mask = deliver_bitmask[__i];\
 179         if (__mask) {\
 180             for(__j = 0; __j < 32; __j++) {\
 181                 if (__mask & (1 << __j)) {\
 182                     apic = local_apics[__i * 32 + __j];\
 183                     if (apic) {\
 184                         code;\
 185                     }\
 186                 }\
 187             }\
 188         }\
 189     }\
 190 }
 191
 192 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 193                              uint8_t delivery_mode,
 194                              uint8_t vector_num, uint8_t polarity,
 195                              uint8_t trigger_mode)
 196 {
 197     APICState *apic_iter;
 198
 199     switch (delivery_mode) {
 200         case APIC_DM_LOWPRI:
 201             /* XXX: search for focus processor, arbitration */
 202             {
 203                 int i, d;
 204                 d = -1;
 205                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 206                     if (deliver_bitmask[i]) {
 207                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 208                         break;
 209                     }
 210                 }
 211                 if (d >= 0) {
 212                     apic_iter = local_apics[d];
 213                     if (apic_iter) {
 214                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 215                     }
 216                 }
 217             }
 218             return;
 219
 220         case APIC_DM_FIXED:
 221             break;
 222
 223         case APIC_DM_SMI:
 224         case APIC_DM_NMI:
 225             break;
 226
 227         case APIC_DM_INIT:
 228             /* normal INIT IPI sent to processors */
 229             foreach_apic(apic_iter, deliver_bitmask,
 230                          apic_init_ipi(apic_iter) );
 231             return;
 232
 233         case APIC_DM_EXTINT:
 234             /* handled in I/O APIC code */
 235             break;
 236
 237         default:
 238             return;
 239     }
 240
 241     foreach_apic(apic_iter, deliver_bitmask,
 242                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 243 }
 244
 245 void cpu_set_apic_base(CPUState *env, uint64_t val)
 246 {
 247     APICState *s = env->apic_state;
 248 #ifdef DEBUG_APIC
 249     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 250 #endif
 251     s->apicbase = (val & 0xfffff000) |
 252         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 253     /* if disabled, cannot be enabled again */
 254     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 255         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 256         env->cpuid_features &= ~CPUID_APIC;
 257         s->spurious_vec &= ~APIC_SV_ENABLE;
 258     }
 259 }
 260
 261 uint64_t cpu_get_apic_base(CPUState *env)
 262 {
 263     APICState *s = env->apic_state;
 264 #ifdef DEBUG_APIC
 265     printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
 266 #endif
 267     return s->apicbase;
 268 }
 269
 270 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 271 {
 272     APICState *s = env->apic_state;
 273     s->tpr = (val & 0x0f) << 4;
 274     apic_update_irq(s);
 275 }
 276
 277 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 278 {
 279     APICState *s = env->apic_state;
 280     return s->tpr >> 4;
 281 }
 282
 283 /* return -1 if no bit is set */
 284 static int get_highest_priority_int(uint32_t *tab)
 285 {
 286     int i;
 287     for(i = 7; i >= 0; i--) {
 288         if (tab[i] != 0) {
 289             return i * 32 + fls_bit(tab[i]);
 290         }
 291     }
 292     return -1;
 293 }
 294
 295 static int apic_get_ppr(APICState *s)
 296 {
 297     int tpr, isrv, ppr;
 298
 299     tpr = (s->tpr >> 4);
 300     isrv = get_highest_priority_int(s->isr);
 301     if (isrv < 0)
 302         isrv = 0;
 303     isrv >>= 4;
 304     if (tpr >= isrv)
 305         ppr = s->tpr;
 306     else
 307         ppr = isrv << 4;
 308     return ppr;
 309 }
 310
 311 static int apic_get_arb_pri(APICState *s)
 312 {
 313     /* XXX: arbitration */
 314     return 0;
 315 }
 316
 317 /* signal the CPU if an irq is pending */
 318 static void apic_update_irq(APICState *s)
 319 {
 320     int irrv, ppr;
 321     if (!(s->spurious_vec & APIC_SV_ENABLE))
 322         return;
 323     irrv = get_highest_priority_int(s->irr);
 324     if (irrv < 0)
 325         return;
 326     ppr = apic_get_ppr(s);
 327     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 328         return;
 329     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 330 }
 331
 332 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 333 {
 334     set_bit(s->irr, vector_num);
 335     if (trigger_mode)
 336         set_bit(s->tmr, vector_num);
 337     else
 338         reset_bit(s->tmr, vector_num);
 339     apic_update_irq(s);
 340 }
 341
 342 static void apic_eoi(APICState *s)
 343 {
 344     int isrv;
 345     isrv = get_highest_priority_int(s->isr);
 346     if (isrv < 0)
 347         return;
 348     reset_bit(s->isr, isrv);
 349     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 350             set the remote IRR bit for level triggered interrupts. */
 351     apic_update_irq(s);
 352 }
 353
 354 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 355                                       uint8_t dest, uint8_t dest_mode)
 356 {
 357     APICState *apic_iter;
 358     int i;
 359
 360     if (dest_mode == 0) {
 361         if (dest == 0xff) {
 362             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 363         } else {
 364             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 365             set_bit(deliver_bitmask, dest);
 366         }
 367     } else {
 368         /* XXX: cluster mode */
 369         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 370         for(i = 0; i < MAX_APICS; i++) {
 371             apic_iter = local_apics[i];
 372             if (apic_iter) {
 373                 if (apic_iter->dest_mode == 0xf) {
 374                     if (dest & apic_iter->log_dest)
 375                         set_bit(deliver_bitmask, i);
 376                 } else if (apic_iter->dest_mode == 0x0) {
 377                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 378                         (dest & apic_iter->log_dest & 0x0f)) {
 379                         set_bit(deliver_bitmask, i);
 380                     }
 381                 }
 382             }
 383         }
 384     }
 385 }
 386
 387
 388 static void apic_init_ipi(APICState *s)
 389 {
 390     int i;
 391
 392     s->tpr = 0;
 393     s->spurious_vec = 0xff;
 394     s->log_dest = 0;
 395     s->dest_mode = 0xf;
 396     memset(s->isr, 0, sizeof(s->isr));
 397     memset(s->tmr, 0, sizeof(s->tmr));
 398     memset(s->irr, 0, sizeof(s->irr));
 399     for(i = 0; i < APIC_LVT_NB; i++)
 400         s->lvt[i] = 1 << 16; /* mask LVT */
 401     s->esr = 0;
 402     memset(s->icr, 0, sizeof(s->icr));
 403     s->divide_conf = 0;
 404     s->count_shift = 0;
 405     s->initial_count = 0;
 406     s->initial_count_load_time = 0;
 407     s->next_time = 0;
 408
 409     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 410         if (s->cpu_env)
 411             kvm_apic_init(s->cpu_env);
 412 }
 413
 414 /* send a SIPI message to the CPU to start it */
 415 static void apic_startup(APICState *s, int vector_num)
 416 {
 417     CPUState *env = s->cpu_env;
 418     if (!(env->hflags & HF_HALTED_MASK))
 419         return;
 420     env->eip = 0;
 421     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
 422                            0xffff, 0);
 423     env->hflags &= ~HF_HALTED_MASK;
 424     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 425         kvm_update_after_sipi(env);
 426 }
 427
 428 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 429                          uint8_t delivery_mode, uint8_t vector_num,
 430                          uint8_t polarity, uint8_t trigger_mode)
 431 {
 432     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 433     int dest_shorthand = (s->icr[0] >> 18) & 3;
 434     APICState *apic_iter;
 435
 436     switch (dest_shorthand) {
 437     case 0:
 438         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 439         break;
 440     case 1:
 441         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 442         set_bit(deliver_bitmask, s->id);
 443         break;
 444     case 2:
 445         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 446         break;
 447     case 3:
 448         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 449         reset_bit(deliver_bitmask, s->id);
 450         break;
 451     }
 452
 453     switch (delivery_mode) {
 454         case APIC_DM_INIT:
 455             {
 456                 int trig_mode = (s->icr[0] >> 15) & 1;
 457                 int level = (s->icr[0] >> 14) & 1;
 458                 if (level == 0 && trig_mode == 1) {
 459                     foreach_apic(apic_iter, deliver_bitmask,
 460                                  apic_iter->arb_id = apic_iter->id );
 461                     return;
 462                 }
 463             }
 464             break;
 465
 466         case APIC_DM_SIPI:
 467             foreach_apic(apic_iter, deliver_bitmask,
 468                          apic_startup(apic_iter, vector_num) );
 469             return;
 470     }
 471
 472     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 473                      trigger_mode);
 474 }
 475
 476 int apic_get_interrupt(CPUState *env)
 477 {
 478     APICState *s = env->apic_state;
 479     int intno;
 480
 481     /* if the APIC is installed or enabled, we let the 8259 handle the
 482        IRQs */
 483     if (!s)
 484         return -1;
 485     if (!(s->spurious_vec & APIC_SV_ENABLE))
 486         return -1;
 487
 488     /* XXX: spurious IRQ handling */
 489     intno = get_highest_priority_int(s->irr);
 490     if (intno < 0)
 491         return -1;
 492     if (s->tpr && intno <= s->tpr)
 493         return s->spurious_vec & 0xff;
 494     reset_bit(s->irr, intno);
 495     set_bit(s->isr, intno);
 496     apic_update_irq(s);
 497     return intno;
 498 }
 499
 500 int apic_accept_pic_intr(CPUState *env)
 501 {
 502     APICState *s = env->apic_state;
 503     uint32_t lvt0;
 504
 505     if (!s)
 506         return -1;
 507
 508     lvt0 = s->lvt[APIC_LVT_LINT0];
 509
 510     if (s->id == 0 &&
 511         ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 512          ((lvt0 & APIC_LVT_MASKED) == 0 &&
 513           ((lvt0 >> 8) & 0x7) == APIC_DM_EXTINT)))
 514         return 1;
 515
 516     return 0;
 517 }
 518
 519 static uint32_t apic_get_current_count(APICState *s)
 520 {
 521     int64_t d;
 522     uint32_t val;
 523     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 524         s->count_shift;
 525     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 526         /* periodic */
 527         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 528     } else {
 529         if (d >= s->initial_count)
 530             val = 0;
 531         else
 532             val = s->initial_count - d;
 533     }
 534     return val;
 535 }
 536
 537 static void apic_timer_update(APICState *s, int64_t current_time)
 538 {
 539     int64_t next_time, d;
 540
 541     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 542         d = (current_time - s->initial_count_load_time) >>
 543             s->count_shift;
 544         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 545             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 546         } else {
 547             if (d >= s->initial_count)
 548                 goto no_timer;
 549             d = (uint64_t)s->initial_count + 1;
 550         }
 551         next_time = s->initial_count_load_time + (d << s->count_shift);
 552         qemu_mod_timer(s->timer, next_time);
 553         s->next_time = next_time;
 554     } else {
 555     no_timer:
 556         qemu_del_timer(s->timer);
 557     }
 558 }
 559
 560 static void apic_timer(void *opaque)
 561 {
 562     APICState *s = opaque;
 563
 564     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 565         apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
 566     }
 567     apic_timer_update(s, s->next_time);
 568 }
 569
 570 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 571 {
 572     return 0;
 573 }
 574
 575 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 576 {
 577     return 0;
 578 }
 579
 580 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 581 {
 582 }
 583
 584 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 585 {
 586 }
 587
 588 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 589 {
 590     CPUState *env;
 591     APICState *s;
 592     uint32_t val;
 593     int index;
 594
 595     env = cpu_single_env;
 596     if (!env)
 597         return 0;
 598     s = env->apic_state;
 599
 600     index = (addr >> 4) & 0xff;
 601     switch(index) {
 602     case 0x02: /* id */
 603         val = s->id << 24;
 604         break;
 605     case 0x03: /* version */
 606         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 607         break;
 608     case 0x08:
 609         val = s->tpr;
 610         break;
 611     case 0x09:
 612         val = apic_get_arb_pri(s);
 613         break;
 614     case 0x0a:
 615         /* ppr */
 616         val = apic_get_ppr(s);
 617         break;
 618     case 0x0b:
 619         break;
 620     case 0x0d:
 621         val = s->log_dest << 24;
 622         break;
 623     case 0x0e:
 624         val = s->dest_mode << 28;
 625         break;
 626     case 0x0f:
 627         val = s->spurious_vec;
 628         break;
 629     case 0x10 ... 0x17:
 630         val = s->isr[index & 7];
 631         break;
 632     case 0x18 ... 0x1f:
 633         val = s->tmr[index & 7];
 634         break;
 635     case 0x20 ... 0x27:
 636         val = s->irr[index & 7];
 637         break;
 638     case 0x28:
 639         val = s->esr;
 640         break;
 641     case 0x30:
 642     case 0x31:
 643         val = s->icr[index & 1];
 644         break;
 645     case 0x32 ... 0x37:
 646         val = s->lvt[index - 0x32];
 647         break;
 648     case 0x38:
 649         val = s->initial_count;
 650         break;
 651     case 0x39:
 652         val = apic_get_current_count(s);
 653         break;
 654     case 0x3e:
 655         val = s->divide_conf;
 656         break;
 657     default:
 658         s->esr |= ESR_ILLEGAL_ADDRESS;
 659         val = 0;
 660         break;
 661     }
 662 #ifdef DEBUG_APIC
 663     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 664 #endif
 665     return val;
 666 }
 667
 668 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 669 {
 670     CPUState *env;
 671     APICState *s;
 672     int index;
 673
 674     env = cpu_single_env;
 675     if (!env)
 676         return;
 677     s = env->apic_state;
 678
 679 #ifdef DEBUG_APIC
 680     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 681 #endif
 682
 683     index = (addr >> 4) & 0xff;
 684     switch(index) {
 685     case 0x02:
 686         s->id = (val >> 24);
 687         break;
 688     case 0x03:
 689         break;
 690     case 0x08:
 691         s->tpr = val;
 692         apic_update_irq(s);
 693         break;
 694     case 0x09:
 695     case 0x0a:
 696         break;
 697     case 0x0b: /* EOI */
 698         apic_eoi(s);
 699         break;
 700     case 0x0d:
 701         s->log_dest = val >> 24;
 702         break;
 703     case 0x0e:
 704         s->dest_mode = val >> 28;
 705         break;
 706     case 0x0f:
 707         s->spurious_vec = val & 0x1ff;
 708         apic_update_irq(s);
 709         break;
 710     case 0x10 ... 0x17:
 711     case 0x18 ... 0x1f:
 712     case 0x20 ... 0x27:
 713     case 0x28:
 714         break;
 715     case 0x30:
 716         s->icr[0] = val;
 717         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 718                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 719                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 720         break;
 721     case 0x31:
 722         s->icr[1] = val;
 723         break;
 724     case 0x32 ... 0x37:
 725         {
 726             int n = index - 0x32;
 727             s->lvt[n] = val;
 728             if (n == APIC_LVT_TIMER)
 729                 apic_timer_update(s, qemu_get_clock(vm_clock));
 730         }
 731         break;
 732     case 0x38:
 733         s->initial_count = val;
 734         s->initial_count_load_time = qemu_get_clock(vm_clock);
 735         apic_timer_update(s, s->initial_count_load_time);
 736         break;
 737     case 0x39:
 738         break;
 739     case 0x3e:
 740         {
 741             int v;
 742             s->divide_conf = val & 0xb;
 743             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 744             s->count_shift = (v + 1) & 7;
 745         }
 746         break;
 747     default:
 748         s->esr |= ESR_ILLEGAL_ADDRESS;
 749         break;
 750     }
 751 }
 752
 753 #ifdef KVM_CAP_IRQCHIP
 754
 755 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 756 {
 757     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 758 }
 759
 760 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 761                                  int reg_id, uint32_t val)
 762 {
 763     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 764 }
 765
 766 static void kvm_kernel_lapic_save_to_user(APICState *s)
 767 {
 768     struct kvm_lapic_state apic;
 769     struct kvm_lapic_state *kapic = &apic;
 770     int i, v;
 771
 772     kvm_get_lapic(kvm_context, s->cpu_env->cpu_index, kapic);
 773
 774     s->id = kapic_reg(kapic, 0x2);
 775     s->tpr = kapic_reg(kapic, 0x8);
 776     s->arb_id = kapic_reg(kapic, 0x9);
 777     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 778     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 779     s->spurious_vec = kapic_reg(kapic, 0xf);
 780     for (i = 0; i < 8; i++) {
 781         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 782         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 783         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 784     }
 785     s->esr = kapic_reg(kapic, 0x28);
 786     s->icr[0] = kapic_reg(kapic, 0x30);
 787     s->icr[1] = kapic_reg(kapic, 0x31);
 788     for (i = 0; i < APIC_LVT_NB; i++)
 789         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 790     s->initial_count = kapic_reg(kapic, 0x38);
 791     s->divide_conf = kapic_reg(kapic, 0x3e);
 792
 793     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 794     s->count_shift = (v + 1) & 7;
 795
 796     s->initial_count_load_time = qemu_get_clock(vm_clock);
 797     apic_timer_update(s, s->initial_count_load_time);
 798 }
 799
 800 static void kvm_kernel_lapic_load_from_user(APICState *s)
 801 {
 802     struct kvm_lapic_state apic;
 803     struct kvm_lapic_state *klapic = &apic;
 804     int i;
 805
 806     memset(klapic, 0, sizeof apic);
 807     kapic_set_reg(klapic, 0x2, s->id);
 808     kapic_set_reg(klapic, 0x8, s->tpr);
 809     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 810     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 811     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 812     for (i = 0; i < 8; i++) {
 813         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 814         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 815         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 816     }
 817     kapic_set_reg(klapic, 0x28, s->esr);
 818     kapic_set_reg(klapic, 0x30, s->icr[0]);
 819     kapic_set_reg(klapic, 0x31, s->icr[1]);
 820     for (i = 0; i < APIC_LVT_NB; i++)
 821         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 822     kapic_set_reg(klapic, 0x38, s->initial_count);
 823     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 824
 825     kvm_set_lapic(kvm_context, s->cpu_env->cpu_index, klapic);
 826 }
 827
 828 #endif
 829
 830 static void apic_save(QEMUFile *f, void *opaque)
 831 {
 832     APICState *s = opaque;
 833     int i;
 834
 835 #ifdef KVM_CAP_IRQCHIP
 836     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 837         kvm_kernel_lapic_save_to_user(s);
 838     }
 839 #endif
 840
 841     qemu_put_be32s(f, &s->apicbase);
 842     qemu_put_8s(f, &s->id);
 843     qemu_put_8s(f, &s->arb_id);
 844     qemu_put_8s(f, &s->tpr);
 845     qemu_put_be32s(f, &s->spurious_vec);
 846     qemu_put_8s(f, &s->log_dest);
 847     qemu_put_8s(f, &s->dest_mode);
 848     for (i = 0; i < 8; i++) {
 849         qemu_put_be32s(f, &s->isr[i]);
 850         qemu_put_be32s(f, &s->tmr[i]);
 851         qemu_put_be32s(f, &s->irr[i]);
 852     }
 853     for (i = 0; i < APIC_LVT_NB; i++) {
 854         qemu_put_be32s(f, &s->lvt[i]);
 855     }
 856     qemu_put_be32s(f, &s->esr);
 857     qemu_put_be32s(f, &s->icr[0]);
 858     qemu_put_be32s(f, &s->icr[1]);
 859     qemu_put_be32s(f, &s->divide_conf);
 860     qemu_put_be32(f, s->count_shift);
 861     qemu_put_be32s(f, &s->initial_count);
 862     qemu_put_be64(f, s->initial_count_load_time);
 863     qemu_put_be64(f, s->next_time);
 864
 865     qemu_put_timer(f, s->timer);
 866 }
 867
 868 static int apic_load(QEMUFile *f, void *opaque, int version_id)
 869 {
 870     APICState *s = opaque;
 871     int i;
 872
 873     if (version_id > 2)
 874         return -EINVAL;
 875
 876     /* XXX: what if the base changes? (registered memory regions) */
 877     qemu_get_be32s(f, &s->apicbase);
 878     qemu_get_8s(f, &s->id);
 879     qemu_get_8s(f, &s->arb_id);
 880     qemu_get_8s(f, &s->tpr);
 881     qemu_get_be32s(f, &s->spurious_vec);
 882     qemu_get_8s(f, &s->log_dest);
 883     qemu_get_8s(f, &s->dest_mode);
 884     for (i = 0; i < 8; i++) {
 885         qemu_get_be32s(f, &s->isr[i]);
 886         qemu_get_be32s(f, &s->tmr[i]);
 887         qemu_get_be32s(f, &s->irr[i]);
 888     }
 889     for (i = 0; i < APIC_LVT_NB; i++) {
 890         qemu_get_be32s(f, &s->lvt[i]);
 891     }
 892     qemu_get_be32s(f, &s->esr);
 893     qemu_get_be32s(f, &s->icr[0]);
 894     qemu_get_be32s(f, &s->icr[1]);
 895     qemu_get_be32s(f, &s->divide_conf);
 896     s->count_shift=qemu_get_be32(f);
 897     qemu_get_be32s(f, &s->initial_count);
 898     s->initial_count_load_time=qemu_get_be64(f);
 899     s->next_time=qemu_get_be64(f);
 900
 901     if (version_id >= 2)
 902         qemu_get_timer(f, s->timer);
 903
 904 #ifdef KVM_CAP_IRQCHIP
 905     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 906         kvm_kernel_lapic_load_from_user(s);
 907     }
 908 #endif
 909
 910     return 0;
 911 }
 912
 913 static void apic_reset(void *opaque)
 914 {
 915     APICState *s = opaque;
 916     apic_init_ipi(s);
 917
 918     /*
 919      * LINT0 delivery mode is set to ExtInt at initialization time
 920      * typically by BIOS, so PIC interrupt can be delivered to the
 921      * processor when local APIC is enabled.
 922      */
 923     s->lvt[APIC_LVT_LINT0] = 0x700;
 924 #ifdef KVM_CAP_IRQCHIP
 925     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 926         kvm_kernel_lapic_load_from_user(s);
 927     }
 928 #endif
 929 }
 930
 931 static CPUReadMemoryFunc *apic_mem_read[3] = {
 932     apic_mem_readb,
 933     apic_mem_readw,
 934     apic_mem_readl,
 935 };
 936
 937 static CPUWriteMemoryFunc *apic_mem_write[3] = {
 938     apic_mem_writeb,
 939     apic_mem_writew,
 940     apic_mem_writel,
 941 };
 942
 943 int apic_init(CPUState *env)
 944 {
 945     APICState *s;
 946
 947     if (last_apic_id >= MAX_APICS)
 948         return -1;
 949     s = qemu_mallocz(sizeof(APICState));
 950     if (!s)
 951         return -1;
 952     env->apic_state = s;
 953     apic_init_ipi(s);
 954     s->id = last_apic_id++;
 955     env->cpuid_apic_id = s->id;
 956     s->cpu_env = env;
 957     s->apicbase = 0xfee00000 |
 958         (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
 959
 960     /*
 961      * LINT0 delivery mode is set to ExtInt at initialization time
 962      * typically by BIOS, so PIC interrupt can be delivered to the
 963      * processor when local APIC is enabled.
 964      */
 965     s->lvt[APIC_LVT_LINT0] = 0x700;
 966
 967     /* XXX: mapping more APICs at the same memory location */
 968     if (apic_io_memory == 0) {
 969         /* NOTE: the APIC is directly connected to the CPU - it is not
 970            on the global memory bus. */
 971         apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
 972                                                 apic_mem_write, NULL);
 973         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
 974                                      apic_io_memory);
 975     }
 976     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
 977
 978     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
 979     qemu_register_reset(apic_reset, s);
 980
 981     local_apics[s->id] = s;
 982     return 0;
 983 }
 984
 985 static void ioapic_service(IOAPICState *s)
 986 {
 987     uint8_t i;
 988     uint8_t trig_mode;
 989     uint8_t vector;
 990     uint8_t delivery_mode;
 991     uint32_t mask;
 992     uint64_t entry;
 993     uint8_t dest;
 994     uint8_t dest_mode;
 995     uint8_t polarity;
 996     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 997
 998     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 999         mask = 1 << i;
1000         if (s->irr & mask) {
1001             entry = s->ioredtbl[i];
1002             if (!(entry & APIC_LVT_MASKED)) {
1003                 trig_mode = ((entry >> 15) & 1);
1004                 dest = entry >> 56;
1005                 dest_mode = (entry >> 11) & 1;
1006                 delivery_mode = (entry >> 8) & 7;
1007                 polarity = (entry >> 13) & 1;
1008                 if (trig_mode == APIC_TRIGGER_EDGE)
1009                     s->irr &= ~mask;
1010                 if (delivery_mode == APIC_DM_EXTINT)
1011                     vector = pic_read_irq(isa_pic);
1012                 else
1013                     vector = entry & 0xff;
1014
1015                 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
1016                 apic_bus_deliver(deliver_bitmask, delivery_mode,
1017                                  vector, polarity, trig_mode);
1018             }
1019         }
1020     }
1021 }
1022
1023 void ioapic_set_irq(void *opaque, int vector, int level)
1024 {
1025     IOAPICState *s = opaque;
1026
1027     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1028         uint32_t mask = 1 << vector;
1029         uint64_t entry = s->ioredtbl[vector];
1030
1031         if ((entry >> 15) & 1) {
1032             /* level triggered */
1033             if (level) {
1034                 s->irr |= mask;
1035                 ioapic_service(s);
1036             } else {
1037                 s->irr &= ~mask;
1038             }
1039         } else {
1040             /* edge triggered */
1041             if (level) {
1042                 s->irr |= mask;
1043                 ioapic_service(s);
1044             }
1045         }
1046     }
1047 }
1048
1049 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1050 {
1051     IOAPICState *s = opaque;
1052     int index;
1053     uint32_t val = 0;
1054
1055     addr &= 0xff;
1056     if (addr == 0x00) {
1057         val = s->ioregsel;
1058     } else if (addr == 0x10) {
1059         switch (s->ioregsel) {
1060             case 0x00:
1061                 val = s->id << 24;
1062                 break;
1063             case 0x01:
1064                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1065                 break;
1066             case 0x02:
1067                 val = 0;
1068                 break;
1069             default:
1070                 index = (s->ioregsel - 0x10) >> 1;
1071                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1072                     if (s->ioregsel & 1)
1073                         val = s->ioredtbl[index] >> 32;
1074                     else
1075                         val = s->ioredtbl[index] & 0xffffffff;
1076                 }
1077         }
1078 #ifdef DEBUG_IOAPIC
1079         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
1080 #endif
1081     }
1082     return val;
1083 }
1084
1085 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1086 {
1087     IOAPICState *s = opaque;
1088     int index;
1089
1090     addr &= 0xff;
1091     if (addr == 0x00)  {
1092         s->ioregsel = val;
1093         return;
1094     } else if (addr == 0x10) {
1095 #ifdef DEBUG_IOAPIC
1096         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
1097 #endif
1098         switch (s->ioregsel) {
1099             case 0x00:
1100                 s->id = (val >> 24) & 0xff;
1101                 return;
1102             case 0x01:
1103             case 0x02:
1104                 return;
1105             default:
1106                 index = (s->ioregsel - 0x10) >> 1;
1107                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1108                     if (s->ioregsel & 1) {
1109                         s->ioredtbl[index] &= 0xffffffff;
1110                         s->ioredtbl[index] |= (uint64_t)val << 32;
1111                     } else {
1112                         s->ioredtbl[index] &= ~0xffffffffULL;
1113                         s->ioredtbl[index] |= val;
1114                     }
1115                     ioapic_service(s);
1116                 }
1117         }
1118     }
1119 }
1120
1121 static void kvm_kernel_ioapic_save_to_user(IOAPICState *s)
1122 {
1123 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
1124     struct kvm_irqchip chip;
1125     struct kvm_ioapic_state *kioapic;
1126     int i;
1127
1128     chip.chip_id = KVM_IRQCHIP_IOAPIC;
1129     kvm_get_irqchip(kvm_context, &chip);
1130     kioapic = &chip.chip.ioapic;
1131
1132     s->id = kioapic->id;
1133     s->ioregsel = kioapic->ioregsel;
1134     s->base_address = kioapic->base_address;
1135     s->irr = kioapic->irr;
1136     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1137         s->ioredtbl[i] = kioapic->redirtbl[i].bits;
1138     }
1139 #endif
1140 }
1141
1142 static void kvm_kernel_ioapic_load_from_user(IOAPICState *s)
1143 {
1144 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
1145     struct kvm_irqchip chip;
1146     struct kvm_ioapic_state *kioapic;
1147     int i;
1148
1149     chip.chip_id = KVM_IRQCHIP_IOAPIC;
1150     kioapic = &chip.chip.ioapic;
1151
1152     kioapic->id = s->id;
1153     kioapic->ioregsel = s->ioregsel;
1154     kioapic->base_address = s->base_address;
1155     kioapic->irr = s->irr;
1156     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1157         kioapic->redirtbl[i].bits = s->ioredtbl[i];
1158     }
1159
1160     kvm_set_irqchip(kvm_context, &chip);
1161 #endif
1162 }
1163
1164 static void ioapic_save(QEMUFile *f, void *opaque)
1165 {
1166     IOAPICState *s = opaque;
1167     int i;
1168
1169     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1170         kvm_kernel_ioapic_save_to_user(s);
1171     }
1172
1173     qemu_put_8s(f, &s->id);
1174     qemu_put_8s(f, &s->ioregsel);
1175     qemu_put_be64s(f, &s->base_address);
1176     qemu_put_be32s(f, &s->irr);
1177     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1178         qemu_put_be64s(f, &s->ioredtbl[i]);
1179     }
1180 }
1181
1182 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1183 {
1184     IOAPICState *s = opaque;
1185     int i;
1186
1187     if (version_id < 1 || version_id > 2)
1188         return -EINVAL;
1189
1190     qemu_get_8s(f, &s->id);
1191     qemu_get_8s(f, &s->ioregsel);
1192     if (version_id == 2) {
1193       /* for version 2, we get this data off of the wire */
1194       qemu_get_be64s(f, &s->base_address);
1195       qemu_get_be32s(f, &s->irr);
1196     }
1197     else {
1198       /* in case we are doing version 1, we just set these to sane values */
1199       s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
1200       s->irr = 0;
1201     }
1202     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1203         qemu_get_be64s(f, &s->ioredtbl[i]);
1204     }
1205
1206     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1207         kvm_kernel_ioapic_load_from_user(s);
1208     }
1209
1210     return 0;
1211 }
1212
1213 static void ioapic_reset(void *opaque)
1214 {
1215     IOAPICState *s = opaque;
1216     int i;
1217
1218     memset(s, 0, sizeof(*s));
1219     for(i = 0; i < IOAPIC_NUM_PINS; i++)
1220         s->ioredtbl[i] = 1 << 16; /* mask LVT */
1221 }
1222
1223 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1224     ioapic_mem_readl,
1225     ioapic_mem_readl,
1226     ioapic_mem_readl,
1227 };
1228
1229 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1230     ioapic_mem_writel,
1231     ioapic_mem_writel,
1232     ioapic_mem_writel,
1233 };
1234
1235 IOAPICState *ioapic_init(void)
1236 {
1237     IOAPICState *s;
1238     int io_memory;
1239
1240     s = qemu_mallocz(sizeof(IOAPICState));
1241     if (!s)
1242         return NULL;
1243     ioapic_reset(s);
1244     s->id = last_apic_id++;
1245
1246     io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1247                                        ioapic_mem_write, s);
1248     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1249
1250     register_savevm("ioapic", 0, 2, ioapic_save, ioapic_load, s);
1251     qemu_register_reset(ioapic_reset, s);
1252
1253     return s;
1254 }