2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
33 #include "qemu-common.h"
39 //#define MIPS_DEBUG_DISAS
40 //#define MIPS_DEBUG_SIGN_EXTENSIONS
42 /* MIPS major opcodes */
43 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
46 /* indirect opcode tables */
47 OPC_SPECIAL
= (0x00 << 26),
48 OPC_REGIMM
= (0x01 << 26),
49 OPC_CP0
= (0x10 << 26),
50 OPC_CP1
= (0x11 << 26),
51 OPC_CP2
= (0x12 << 26),
52 OPC_CP3
= (0x13 << 26),
53 OPC_SPECIAL2
= (0x1C << 26),
54 OPC_SPECIAL3
= (0x1F << 26),
55 /* arithmetic with immediate */
56 OPC_ADDI
= (0x08 << 26),
57 OPC_ADDIU
= (0x09 << 26),
58 OPC_SLTI
= (0x0A << 26),
59 OPC_SLTIU
= (0x0B << 26),
60 /* logic with immediate */
61 OPC_ANDI
= (0x0C << 26),
62 OPC_ORI
= (0x0D << 26),
63 OPC_XORI
= (0x0E << 26),
64 OPC_LUI
= (0x0F << 26),
65 /* arithmetic with immediate */
66 OPC_DADDI
= (0x18 << 26),
67 OPC_DADDIU
= (0x19 << 26),
68 /* Jump and branches */
70 OPC_JAL
= (0x03 << 26),
71 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
72 OPC_BEQL
= (0x14 << 26),
73 OPC_BNE
= (0x05 << 26),
74 OPC_BNEL
= (0x15 << 26),
75 OPC_BLEZ
= (0x06 << 26),
76 OPC_BLEZL
= (0x16 << 26),
77 OPC_BGTZ
= (0x07 << 26),
78 OPC_BGTZL
= (0x17 << 26),
79 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
81 OPC_LDL
= (0x1A << 26),
82 OPC_LDR
= (0x1B << 26),
83 OPC_LB
= (0x20 << 26),
84 OPC_LH
= (0x21 << 26),
85 OPC_LWL
= (0x22 << 26),
86 OPC_LW
= (0x23 << 26),
87 OPC_LBU
= (0x24 << 26),
88 OPC_LHU
= (0x25 << 26),
89 OPC_LWR
= (0x26 << 26),
90 OPC_LWU
= (0x27 << 26),
91 OPC_SB
= (0x28 << 26),
92 OPC_SH
= (0x29 << 26),
93 OPC_SWL
= (0x2A << 26),
94 OPC_SW
= (0x2B << 26),
95 OPC_SDL
= (0x2C << 26),
96 OPC_SDR
= (0x2D << 26),
97 OPC_SWR
= (0x2E << 26),
98 OPC_LL
= (0x30 << 26),
99 OPC_LLD
= (0x34 << 26),
100 OPC_LD
= (0x37 << 26),
101 OPC_SC
= (0x38 << 26),
102 OPC_SCD
= (0x3C << 26),
103 OPC_SD
= (0x3F << 26),
104 /* Floating point load/store */
105 OPC_LWC1
= (0x31 << 26),
106 OPC_LWC2
= (0x32 << 26),
107 OPC_LDC1
= (0x35 << 26),
108 OPC_LDC2
= (0x36 << 26),
109 OPC_SWC1
= (0x39 << 26),
110 OPC_SWC2
= (0x3A << 26),
111 OPC_SDC1
= (0x3D << 26),
112 OPC_SDC2
= (0x3E << 26),
113 /* MDMX ASE specific */
114 OPC_MDMX
= (0x1E << 26),
115 /* Cache and prefetch */
116 OPC_CACHE
= (0x2F << 26),
117 OPC_PREF
= (0x33 << 26),
118 /* Reserved major opcode */
119 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
122 /* MIPS special opcodes */
123 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
127 OPC_SLL
= 0x00 | OPC_SPECIAL
,
128 /* NOP is SLL r0, r0, 0 */
129 /* SSNOP is SLL r0, r0, 1 */
130 /* EHB is SLL r0, r0, 3 */
131 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
132 OPC_SRA
= 0x03 | OPC_SPECIAL
,
133 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
134 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
135 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
136 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
137 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
138 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
139 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
140 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
141 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
142 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
143 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
144 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
145 /* Multiplication / division */
146 OPC_MULT
= 0x18 | OPC_SPECIAL
,
147 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
148 OPC_DIV
= 0x1A | OPC_SPECIAL
,
149 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
150 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
151 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
152 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
153 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
154 /* 2 registers arithmetic / logic */
155 OPC_ADD
= 0x20 | OPC_SPECIAL
,
156 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
157 OPC_SUB
= 0x22 | OPC_SPECIAL
,
158 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
159 OPC_AND
= 0x24 | OPC_SPECIAL
,
160 OPC_OR
= 0x25 | OPC_SPECIAL
,
161 OPC_XOR
= 0x26 | OPC_SPECIAL
,
162 OPC_NOR
= 0x27 | OPC_SPECIAL
,
163 OPC_SLT
= 0x2A | OPC_SPECIAL
,
164 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
165 OPC_DADD
= 0x2C | OPC_SPECIAL
,
166 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
167 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
168 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
170 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
171 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
173 OPC_TGE
= 0x30 | OPC_SPECIAL
,
174 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
175 OPC_TLT
= 0x32 | OPC_SPECIAL
,
176 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
177 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
178 OPC_TNE
= 0x36 | OPC_SPECIAL
,
179 /* HI / LO registers load & stores */
180 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
181 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
182 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
183 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
184 /* Conditional moves */
185 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
186 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
188 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
191 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
192 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
193 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
194 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
195 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
197 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
198 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
199 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
200 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
201 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
202 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
203 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
206 /* Multiplication variants of the vr54xx. */
207 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
210 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
211 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
212 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
213 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
214 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
215 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
216 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
217 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
218 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
219 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
220 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
221 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
222 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
223 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
226 /* REGIMM (rt field) opcodes */
227 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
230 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
231 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
232 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
233 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
234 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
235 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
236 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
237 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
238 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
239 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
240 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
241 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
242 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
243 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
244 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
247 /* Special2 opcodes */
248 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
251 /* Multiply & xxx operations */
252 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
253 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
254 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
255 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
256 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
258 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
259 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
260 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
261 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
263 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
266 /* Special3 opcodes */
267 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
270 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
271 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
272 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
273 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
274 OPC_INS
= 0x04 | OPC_SPECIAL3
,
275 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
276 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
277 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
278 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
279 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
280 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
281 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
282 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
286 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
289 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
290 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
291 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
295 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
298 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
299 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
302 /* Coprocessor 0 (rs field) */
303 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
306 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
307 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
308 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
309 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
310 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
311 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
312 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
313 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
314 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
315 OPC_C0
= (0x10 << 21) | OPC_CP0
,
316 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
317 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
321 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
324 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
325 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
326 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
327 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
328 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
329 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
332 /* Coprocessor 0 (with rs == C0) */
333 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
336 OPC_TLBR
= 0x01 | OPC_C0
,
337 OPC_TLBWI
= 0x02 | OPC_C0
,
338 OPC_TLBWR
= 0x06 | OPC_C0
,
339 OPC_TLBP
= 0x08 | OPC_C0
,
340 OPC_RFE
= 0x10 | OPC_C0
,
341 OPC_ERET
= 0x18 | OPC_C0
,
342 OPC_DERET
= 0x1F | OPC_C0
,
343 OPC_WAIT
= 0x20 | OPC_C0
,
346 /* Coprocessor 1 (rs field) */
347 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
350 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
351 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
352 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
353 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
354 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
355 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
356 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
357 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
358 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
359 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
360 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
361 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
362 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
363 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
364 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
365 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
366 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
367 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
370 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
371 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
374 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
375 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
376 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
377 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
381 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
382 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
386 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
387 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
390 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
393 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
394 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
395 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
396 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
397 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
398 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
399 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
400 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
401 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
404 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
407 OPC_LWXC1
= 0x00 | OPC_CP3
,
408 OPC_LDXC1
= 0x01 | OPC_CP3
,
409 OPC_LUXC1
= 0x05 | OPC_CP3
,
410 OPC_SWXC1
= 0x08 | OPC_CP3
,
411 OPC_SDXC1
= 0x09 | OPC_CP3
,
412 OPC_SUXC1
= 0x0D | OPC_CP3
,
413 OPC_PREFX
= 0x0F | OPC_CP3
,
414 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
415 OPC_MADD_S
= 0x20 | OPC_CP3
,
416 OPC_MADD_D
= 0x21 | OPC_CP3
,
417 OPC_MADD_PS
= 0x26 | OPC_CP3
,
418 OPC_MSUB_S
= 0x28 | OPC_CP3
,
419 OPC_MSUB_D
= 0x29 | OPC_CP3
,
420 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
421 OPC_NMADD_S
= 0x30 | OPC_CP3
,
422 OPC_NMADD_D
= 0x31 | OPC_CP3
,
423 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
424 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
425 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
426 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
429 /* global register indices */
430 static TCGv_ptr cpu_env
;
431 static TCGv cpu_gpr
[32], cpu_PC
;
432 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
], cpu_ACX
[MIPS_DSP_ACC
];
433 static TCGv cpu_dspctrl
, btarget
, bcond
;
434 static TCGv_i32 hflags
;
435 static TCGv_i32 fpu_fcr0
, fpu_fcr31
;
437 #include "gen-icount.h"
439 #define gen_helper_0i(name, arg) do { \
440 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
441 gen_helper_##name(helper_tmp); \
442 tcg_temp_free_i32(helper_tmp); \
445 #define gen_helper_1i(name, arg1, arg2) do { \
446 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
447 gen_helper_##name(arg1, helper_tmp); \
448 tcg_temp_free_i32(helper_tmp); \
451 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
452 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
453 gen_helper_##name(arg1, arg2, helper_tmp); \
454 tcg_temp_free_i32(helper_tmp); \
457 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
458 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
459 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
460 tcg_temp_free_i32(helper_tmp); \
463 typedef struct DisasContext
{
464 struct TranslationBlock
*tb
;
465 target_ulong pc
, saved_pc
;
467 /* Routine used to access memory */
469 uint32_t hflags
, saved_hflags
;
471 target_ulong btarget
;
475 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
476 * exception condition */
477 BS_STOP
= 1, /* We want to stop translation for any reason */
478 BS_BRANCH
= 2, /* We reached a branch condition */
479 BS_EXCP
= 3, /* We reached an exception condition */
482 static const char *regnames
[] =
483 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
484 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
485 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
486 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
488 static const char *regnames_HI
[] =
489 { "HI0", "HI1", "HI2", "HI3", };
491 static const char *regnames_LO
[] =
492 { "LO0", "LO1", "LO2", "LO3", };
494 static const char *regnames_ACX
[] =
495 { "ACX0", "ACX1", "ACX2", "ACX3", };
497 static const char *fregnames
[] =
498 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
499 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
500 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
501 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
503 #ifdef MIPS_DEBUG_DISAS
504 #define MIPS_DEBUG(fmt, ...) \
505 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
506 TARGET_FMT_lx ": %08x " fmt "\n", \
507 ctx->pc, ctx->opcode , ## __VA_ARGS__)
508 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
510 #define MIPS_DEBUG(fmt, ...) do { } while(0)
511 #define LOG_DISAS(...) do { } while (0)
514 #define MIPS_INVAL(op) \
516 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
517 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
520 /* General purpose registers moves. */
521 static inline void gen_load_gpr (TCGv t
, int reg
)
524 tcg_gen_movi_tl(t
, 0);
526 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
529 static inline void gen_store_gpr (TCGv t
, int reg
)
532 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
535 /* Moves to/from ACX register. */
536 static inline void gen_load_ACX (TCGv t
, int reg
)
538 tcg_gen_mov_tl(t
, cpu_ACX
[reg
]);
541 static inline void gen_store_ACX (TCGv t
, int reg
)
543 tcg_gen_mov_tl(cpu_ACX
[reg
], t
);
546 /* Moves to/from shadow registers. */
547 static inline void gen_load_srsgpr (int from
, int to
)
549 TCGv t0
= tcg_temp_new();
552 tcg_gen_movi_tl(t0
, 0);
554 TCGv_i32 t2
= tcg_temp_new_i32();
555 TCGv_ptr addr
= tcg_temp_new_ptr();
557 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
558 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
559 tcg_gen_andi_i32(t2
, t2
, 0xf);
560 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
561 tcg_gen_ext_i32_ptr(addr
, t2
);
562 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
564 tcg_gen_ld_tl(t0
, addr
, sizeof(target_ulong
) * from
);
565 tcg_temp_free_ptr(addr
);
566 tcg_temp_free_i32(t2
);
568 gen_store_gpr(t0
, to
);
572 static inline void gen_store_srsgpr (int from
, int to
)
575 TCGv t0
= tcg_temp_new();
576 TCGv_i32 t2
= tcg_temp_new_i32();
577 TCGv_ptr addr
= tcg_temp_new_ptr();
579 gen_load_gpr(t0
, from
);
580 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
581 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
582 tcg_gen_andi_i32(t2
, t2
, 0xf);
583 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
584 tcg_gen_ext_i32_ptr(addr
, t2
);
585 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
587 tcg_gen_st_tl(t0
, addr
, sizeof(target_ulong
) * to
);
588 tcg_temp_free_ptr(addr
);
589 tcg_temp_free_i32(t2
);
594 /* Floating point register moves. */
595 static inline void gen_load_fpr32 (TCGv_i32 t
, int reg
)
597 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
600 static inline void gen_store_fpr32 (TCGv_i32 t
, int reg
)
602 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
605 static inline void gen_load_fpr32h (TCGv_i32 t
, int reg
)
607 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
610 static inline void gen_store_fpr32h (TCGv_i32 t
, int reg
)
612 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
615 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
617 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
618 tcg_gen_ld_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
620 TCGv_i32 t0
= tcg_temp_new_i32();
621 TCGv_i32 t1
= tcg_temp_new_i32();
622 gen_load_fpr32(t0
, reg
& ~1);
623 gen_load_fpr32(t1
, reg
| 1);
624 tcg_gen_concat_i32_i64(t
, t0
, t1
);
625 tcg_temp_free_i32(t0
);
626 tcg_temp_free_i32(t1
);
630 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
632 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
633 tcg_gen_st_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
635 TCGv_i64 t0
= tcg_temp_new_i64();
636 TCGv_i32 t1
= tcg_temp_new_i32();
637 tcg_gen_trunc_i64_i32(t1
, t
);
638 gen_store_fpr32(t1
, reg
& ~1);
639 tcg_gen_shri_i64(t0
, t
, 32);
640 tcg_gen_trunc_i64_i32(t1
, t0
);
641 gen_store_fpr32(t1
, reg
| 1);
642 tcg_temp_free_i32(t1
);
643 tcg_temp_free_i64(t0
);
647 static inline int get_fp_bit (int cc
)
655 #define FOP_CONDS(type, fmt, bits) \
656 static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \
657 TCGv_i##bits b, int cc) \
660 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\
661 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\
662 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\
663 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\
664 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\
665 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\
666 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\
667 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\
668 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\
669 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\
670 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\
671 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\
672 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\
673 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\
674 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\
675 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\
681 FOP_CONDS(abs
, d
, 64)
683 FOP_CONDS(abs
, s
, 32)
685 FOP_CONDS(abs
, ps
, 64)
689 #define OP_COND(name, cond) \
690 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, TCGv t1) \
692 int l1 = gen_new_label(); \
693 int l2 = gen_new_label(); \
695 tcg_gen_brcond_tl(cond, t0, t1, l1); \
696 tcg_gen_movi_tl(ret, 0); \
699 tcg_gen_movi_tl(ret, 1); \
702 OP_COND(eq
, TCG_COND_EQ
);
703 OP_COND(ne
, TCG_COND_NE
);
704 OP_COND(ge
, TCG_COND_GE
);
705 OP_COND(geu
, TCG_COND_GEU
);
706 OP_COND(lt
, TCG_COND_LT
);
707 OP_COND(ltu
, TCG_COND_LTU
);
710 #define OP_CONDI(name, cond) \
711 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, target_ulong val) \
713 int l1 = gen_new_label(); \
714 int l2 = gen_new_label(); \
716 tcg_gen_brcondi_tl(cond, t0, val, l1); \
717 tcg_gen_movi_tl(ret, 0); \
720 tcg_gen_movi_tl(ret, 1); \
723 OP_CONDI(lti
, TCG_COND_LT
);
724 OP_CONDI(ltiu
, TCG_COND_LTU
);
727 #define OP_CONDZ(name, cond) \
728 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0) \
730 int l1 = gen_new_label(); \
731 int l2 = gen_new_label(); \
733 tcg_gen_brcondi_tl(cond, t0, 0, l1); \
734 tcg_gen_movi_tl(ret, 0); \
737 tcg_gen_movi_tl(ret, 1); \
740 OP_CONDZ(gez
, TCG_COND_GE
);
741 OP_CONDZ(gtz
, TCG_COND_GT
);
742 OP_CONDZ(lez
, TCG_COND_LE
);
743 OP_CONDZ(ltz
, TCG_COND_LT
);
746 static inline void gen_save_pc(target_ulong pc
)
748 tcg_gen_movi_tl(cpu_PC
, pc
);
751 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
753 LOG_DISAS("hflags %08x saved %08x\n", ctx
->hflags
, ctx
->saved_hflags
);
754 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
755 gen_save_pc(ctx
->pc
);
756 ctx
->saved_pc
= ctx
->pc
;
758 if (ctx
->hflags
!= ctx
->saved_hflags
) {
759 tcg_gen_movi_i32(hflags
, ctx
->hflags
);
760 ctx
->saved_hflags
= ctx
->hflags
;
761 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
767 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
773 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
775 ctx
->saved_hflags
= ctx
->hflags
;
776 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
782 ctx
->btarget
= env
->btarget
;
788 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
790 TCGv_i32 texcp
= tcg_const_i32(excp
);
791 TCGv_i32 terr
= tcg_const_i32(err
);
792 save_cpu_state(ctx
, 1);
793 gen_helper_raise_exception_err(texcp
, terr
);
794 tcg_temp_free_i32(terr
);
795 tcg_temp_free_i32(texcp
);
799 generate_exception (DisasContext
*ctx
, int excp
)
801 save_cpu_state(ctx
, 1);
802 gen_helper_0i(raise_exception
, excp
);
805 /* Addresses computation */
806 static inline void gen_op_addr_add (DisasContext
*ctx
, TCGv t0
, TCGv t1
)
808 tcg_gen_add_tl(t0
, t0
, t1
);
810 #if defined(TARGET_MIPS64)
811 /* For compatibility with 32-bit code, data reference in user mode
812 with Status_UX = 0 should be casted to 32-bit and sign extended.
813 See the MIPS64 PRA manual, section 4.10. */
814 if (((ctx
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
815 !(ctx
->hflags
& MIPS_HFLAG_UX
)) {
816 tcg_gen_ext32s_i64(t0
, t0
);
821 static inline void check_cp0_enabled(DisasContext
*ctx
)
823 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
824 generate_exception_err(ctx
, EXCP_CpU
, 1);
827 static inline void check_cp1_enabled(DisasContext
*ctx
)
829 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
830 generate_exception_err(ctx
, EXCP_CpU
, 1);
833 /* Verify that the processor is running with COP1X instructions enabled.
834 This is associated with the nabla symbol in the MIPS32 and MIPS64
837 static inline void check_cop1x(DisasContext
*ctx
)
839 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
840 generate_exception(ctx
, EXCP_RI
);
843 /* Verify that the processor is running with 64-bit floating-point
844 operations enabled. */
846 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
848 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
849 generate_exception(ctx
, EXCP_RI
);
853 * Verify if floating point register is valid; an operation is not defined
854 * if bit 0 of any register specification is set and the FR bit in the
855 * Status register equals zero, since the register numbers specify an
856 * even-odd pair of adjacent coprocessor general registers. When the FR bit
857 * in the Status register equals one, both even and odd register numbers
858 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
860 * Multiple 64 bit wide registers can be checked by calling
861 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
863 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
865 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
866 generate_exception(ctx
, EXCP_RI
);
869 /* This code generates a "reserved instruction" exception if the
870 CPU does not support the instruction set corresponding to flags. */
871 static inline void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
873 if (unlikely(!(env
->insn_flags
& flags
)))
874 generate_exception(ctx
, EXCP_RI
);
877 /* This code generates a "reserved instruction" exception if 64-bit
878 instructions are not enabled. */
879 static inline void check_mips_64(DisasContext
*ctx
)
881 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
882 generate_exception(ctx
, EXCP_RI
);
885 /* load/store instructions. */
886 #define OP_LD(insn,fname) \
887 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
889 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
896 #if defined(TARGET_MIPS64)
902 #define OP_ST(insn,fname) \
903 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
905 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
910 #if defined(TARGET_MIPS64)
915 #define OP_LD_ATOMIC(insn,fname) \
916 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
918 TCGv t0 = tcg_temp_new(); \
919 tcg_gen_mov_tl(t0, arg1); \
920 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
921 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
922 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
925 OP_LD_ATOMIC(ll
,ld32s
);
926 #if defined(TARGET_MIPS64)
927 OP_LD_ATOMIC(lld
,ld64
);
931 #ifdef CONFIG_USER_ONLY
932 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
933 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
935 TCGv t0 = tcg_temp_new(); \
936 int l1 = gen_new_label(); \
937 int l2 = gen_new_label(); \
939 tcg_gen_andi_tl(t0, arg2, almask); \
940 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
941 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
942 generate_exception(ctx, EXCP_AdES); \
944 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
945 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
946 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
947 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
948 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
949 gen_helper_0i(raise_exception, EXCP_SC); \
951 tcg_gen_movi_tl(t0, 0); \
952 gen_store_gpr(t0, rt); \
956 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
957 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
959 TCGv t0 = tcg_temp_new(); \
960 TCGv t1 = tcg_temp_new(); \
961 int l1 = gen_new_label(); \
962 int l2 = gen_new_label(); \
963 int l3 = gen_new_label(); \
965 tcg_gen_andi_tl(t0, arg2, almask); \
966 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
967 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
968 generate_exception(ctx, EXCP_AdES); \
970 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
971 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
972 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, llval)); \
973 tcg_gen_qemu_##ldname(t1, arg2, ctx->mem_idx); \
974 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l2); \
976 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
977 tcg_gen_movi_tl(t0, 1); \
978 gen_store_gpr(t0, rt); \
981 tcg_gen_movi_tl(t0, 0); \
982 gen_store_gpr(t0, rt); \
988 OP_ST_ATOMIC(sc
,st32
,ld32s
,0x3);
989 #if defined(TARGET_MIPS64)
990 OP_ST_ATOMIC(scd
,st64
,ld64
,0x7);
995 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
996 int base
, int16_t offset
)
998 const char *opn
= "ldst";
999 TCGv t0
= tcg_temp_new();
1000 TCGv t1
= tcg_temp_new();
1003 tcg_gen_movi_tl(t0
, offset
);
1004 } else if (offset
== 0) {
1005 gen_load_gpr(t0
, base
);
1007 tcg_gen_movi_tl(t0
, offset
);
1008 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
]);
1010 /* Don't do NOP if destination is zero: we must perform the actual
1013 #if defined(TARGET_MIPS64)
1015 save_cpu_state(ctx
, 0);
1016 op_ldst_lwu(t0
, t0
, ctx
);
1017 gen_store_gpr(t0
, rt
);
1021 save_cpu_state(ctx
, 0);
1022 op_ldst_ld(t0
, t0
, ctx
);
1023 gen_store_gpr(t0
, rt
);
1027 save_cpu_state(ctx
, 0);
1028 op_ldst_lld(t0
, t0
, ctx
);
1029 gen_store_gpr(t0
, rt
);
1033 save_cpu_state(ctx
, 0);
1034 gen_load_gpr(t1
, rt
);
1035 op_ldst_sd(t1
, t0
, ctx
);
1039 save_cpu_state(ctx
, 1);
1040 gen_load_gpr(t1
, rt
);
1041 gen_helper_3i(ldl
, t1
, t1
, t0
, ctx
->mem_idx
);
1042 gen_store_gpr(t1
, rt
);
1046 save_cpu_state(ctx
, 1);
1047 gen_load_gpr(t1
, rt
);
1048 gen_helper_2i(sdl
, t1
, t0
, ctx
->mem_idx
);
1052 save_cpu_state(ctx
, 1);
1053 gen_load_gpr(t1
, rt
);
1054 gen_helper_3i(ldr
, t1
, t1
, t0
, ctx
->mem_idx
);
1055 gen_store_gpr(t1
, rt
);
1059 save_cpu_state(ctx
, 1);
1060 gen_load_gpr(t1
, rt
);
1061 gen_helper_2i(sdr
, t1
, t0
, ctx
->mem_idx
);
1066 save_cpu_state(ctx
, 0);
1067 op_ldst_lw(t0
, t0
, ctx
);
1068 gen_store_gpr(t0
, rt
);
1072 save_cpu_state(ctx
, 0);
1073 gen_load_gpr(t1
, rt
);
1074 op_ldst_sw(t1
, t0
, ctx
);
1078 save_cpu_state(ctx
, 0);
1079 op_ldst_lh(t0
, t0
, ctx
);
1080 gen_store_gpr(t0
, rt
);
1084 save_cpu_state(ctx
, 0);
1085 gen_load_gpr(t1
, rt
);
1086 op_ldst_sh(t1
, t0
, ctx
);
1090 save_cpu_state(ctx
, 0);
1091 op_ldst_lhu(t0
, t0
, ctx
);
1092 gen_store_gpr(t0
, rt
);
1096 save_cpu_state(ctx
, 0);
1097 op_ldst_lb(t0
, t0
, ctx
);
1098 gen_store_gpr(t0
, rt
);
1102 save_cpu_state(ctx
, 0);
1103 gen_load_gpr(t1
, rt
);
1104 op_ldst_sb(t1
, t0
, ctx
);
1108 save_cpu_state(ctx
, 0);
1109 op_ldst_lbu(t0
, t0
, ctx
);
1110 gen_store_gpr(t0
, rt
);
1114 save_cpu_state(ctx
, 1);
1115 gen_load_gpr(t1
, rt
);
1116 gen_helper_3i(lwl
, t1
, t1
, t0
, ctx
->mem_idx
);
1117 gen_store_gpr(t1
, rt
);
1121 save_cpu_state(ctx
, 1);
1122 gen_load_gpr(t1
, rt
);
1123 gen_helper_2i(swl
, t1
, t0
, ctx
->mem_idx
);
1127 save_cpu_state(ctx
, 1);
1128 gen_load_gpr(t1
, rt
);
1129 gen_helper_3i(lwr
, t1
, t1
, t0
, ctx
->mem_idx
);
1130 gen_store_gpr(t1
, rt
);
1134 save_cpu_state(ctx
, 1);
1135 gen_load_gpr(t1
, rt
);
1136 gen_helper_2i(swr
, t1
, t0
, ctx
->mem_idx
);
1140 save_cpu_state(ctx
, 0);
1141 op_ldst_ll(t0
, t0
, ctx
);
1142 gen_store_gpr(t0
, rt
);
1146 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1151 /* Store conditional */
1152 static void gen_st_cond (DisasContext
*ctx
, uint32_t opc
, int rt
,
1153 int base
, int16_t offset
)
1155 const char *opn
= "st_cond";
1158 t0
= tcg_temp_local_new();
1161 tcg_gen_movi_tl(t0
, offset
);
1162 } else if (offset
== 0) {
1163 gen_load_gpr(t0
, base
);
1165 tcg_gen_movi_tl(t0
, offset
);
1166 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
]);
1168 /* Don't do NOP if destination is zero: we must perform the actual
1171 t1
= tcg_temp_local_new();
1172 gen_load_gpr(t1
, rt
);
1174 #if defined(TARGET_MIPS64)
1176 save_cpu_state(ctx
, 0);
1177 op_ldst_scd(t1
, t0
, rt
, ctx
);
1182 save_cpu_state(ctx
, 0);
1183 op_ldst_sc(t1
, t0
, rt
, ctx
);
1187 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1192 /* Load and store */
1193 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1194 int base
, int16_t offset
)
1196 const char *opn
= "flt_ldst";
1197 TCGv t0
= tcg_temp_new();
1200 tcg_gen_movi_tl(t0
, offset
);
1201 } else if (offset
== 0) {
1202 gen_load_gpr(t0
, base
);
1204 tcg_gen_movi_tl(t0
, offset
);
1205 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
]);
1207 /* Don't do NOP if destination is zero: we must perform the actual
1212 TCGv_i32 fp0
= tcg_temp_new_i32();
1214 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
1215 tcg_gen_trunc_tl_i32(fp0
, t0
);
1216 gen_store_fpr32(fp0
, ft
);
1217 tcg_temp_free_i32(fp0
);
1223 TCGv_i32 fp0
= tcg_temp_new_i32();
1224 TCGv t1
= tcg_temp_new();
1226 gen_load_fpr32(fp0
, ft
);
1227 tcg_gen_extu_i32_tl(t1
, fp0
);
1228 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
1230 tcg_temp_free_i32(fp0
);
1236 TCGv_i64 fp0
= tcg_temp_new_i64();
1238 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
1239 gen_store_fpr64(ctx
, fp0
, ft
);
1240 tcg_temp_free_i64(fp0
);
1246 TCGv_i64 fp0
= tcg_temp_new_i64();
1248 gen_load_fpr64(ctx
, fp0
, ft
);
1249 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
1250 tcg_temp_free_i64(fp0
);
1256 generate_exception(ctx
, EXCP_RI
);
1259 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1264 /* Arithmetic with immediate operand */
1265 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1266 int rt
, int rs
, int16_t imm
)
1268 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1269 const char *opn
= "imm arith";
1271 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1272 /* If no destination, treat it as a NOP.
1273 For addi, we must generate the overflow exception when needed. */
1280 TCGv t0
= tcg_temp_local_new();
1281 TCGv t1
= tcg_temp_new();
1282 TCGv t2
= tcg_temp_new();
1283 int l1
= gen_new_label();
1285 gen_load_gpr(t1
, rs
);
1286 tcg_gen_addi_tl(t0
, t1
, uimm
);
1287 tcg_gen_ext32s_tl(t0
, t0
);
1289 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1290 tcg_gen_xori_tl(t2
, t0
, uimm
);
1291 tcg_gen_and_tl(t1
, t1
, t2
);
1293 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1295 /* operands of same sign, result different sign */
1296 generate_exception(ctx
, EXCP_OVERFLOW
);
1298 tcg_gen_ext32s_tl(t0
, t0
);
1299 gen_store_gpr(t0
, rt
);
1306 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1307 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
1309 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1313 #if defined(TARGET_MIPS64)
1316 TCGv t0
= tcg_temp_local_new();
1317 TCGv t1
= tcg_temp_new();
1318 TCGv t2
= tcg_temp_new();
1319 int l1
= gen_new_label();
1321 gen_load_gpr(t1
, rs
);
1322 tcg_gen_addi_tl(t0
, t1
, uimm
);
1324 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1325 tcg_gen_xori_tl(t2
, t0
, uimm
);
1326 tcg_gen_and_tl(t1
, t1
, t2
);
1328 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1330 /* operands of same sign, result different sign */
1331 generate_exception(ctx
, EXCP_OVERFLOW
);
1333 gen_store_gpr(t0
, rt
);
1340 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1342 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1348 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1351 /* Logic with immediate operand */
1352 static void gen_logic_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1355 const char *opn
= "imm logic";
1358 /* If no destination, treat it as a NOP. */
1362 uimm
= (uint16_t)imm
;
1365 if (likely(rs
!= 0))
1366 tcg_gen_andi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1368 tcg_gen_movi_tl(cpu_gpr
[rt
], 0);
1373 tcg_gen_ori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1375 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1379 if (likely(rs
!= 0))
1380 tcg_gen_xori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1382 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1386 tcg_gen_movi_tl(cpu_gpr
[rt
], imm
<< 16);
1390 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1393 /* Set on less than with immediate operand */
1394 static void gen_slt_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1396 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1397 const char *opn
= "imm arith";
1401 /* If no destination, treat it as a NOP. */
1405 t0
= tcg_temp_new();
1406 gen_load_gpr(t0
, rs
);
1409 gen_op_lti(cpu_gpr
[rt
], t0
, uimm
);
1413 gen_op_ltiu(cpu_gpr
[rt
], t0
, uimm
);
1417 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1421 /* Shifts with immediate operand */
1422 static void gen_shift_imm(CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1423 int rt
, int rs
, int16_t imm
)
1425 target_ulong uimm
= ((uint16_t)imm
) & 0x1f;
1426 const char *opn
= "imm shift";
1430 /* If no destination, treat it as a NOP. */
1435 t0
= tcg_temp_new();
1436 gen_load_gpr(t0
, rs
);
1439 tcg_gen_shli_tl(t0
, t0
, uimm
);
1440 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1444 tcg_gen_ext32s_tl(t0
, t0
);
1445 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1449 switch ((ctx
->opcode
>> 21) & 0x1f) {
1452 tcg_gen_ext32u_tl(t0
, t0
);
1453 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1455 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1460 /* rotr is decoded as srl on non-R2 CPUs */
1461 if (env
->insn_flags
& ISA_MIPS32R2
) {
1463 TCGv_i32 t1
= tcg_temp_new_i32();
1465 tcg_gen_trunc_tl_i32(t1
, t0
);
1466 tcg_gen_rotri_i32(t1
, t1
, uimm
);
1467 tcg_gen_ext_i32_tl(cpu_gpr
[rt
], t1
);
1468 tcg_temp_free_i32(t1
);
1473 tcg_gen_ext32u_tl(t0
, t0
);
1474 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1476 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1482 MIPS_INVAL("invalid srl flag");
1483 generate_exception(ctx
, EXCP_RI
);
1487 #if defined(TARGET_MIPS64)
1489 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
);
1493 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1497 switch ((ctx
->opcode
>> 21) & 0x1f) {
1499 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1503 /* drotr is decoded as dsrl on non-R2 CPUs */
1504 if (env
->insn_flags
& ISA_MIPS32R2
) {
1506 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
);
1510 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1515 MIPS_INVAL("invalid dsrl flag");
1516 generate_exception(ctx
, EXCP_RI
);
1521 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1525 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1529 switch ((ctx
->opcode
>> 21) & 0x1f) {
1531 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1535 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1536 if (env
->insn_flags
& ISA_MIPS32R2
) {
1537 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1540 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1545 MIPS_INVAL("invalid dsrl32 flag");
1546 generate_exception(ctx
, EXCP_RI
);
1552 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1557 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1558 int rd
, int rs
, int rt
)
1560 const char *opn
= "arith";
1562 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1563 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1564 /* If no destination, treat it as a NOP.
1565 For add & sub, we must generate the overflow exception when needed. */
1573 TCGv t0
= tcg_temp_local_new();
1574 TCGv t1
= tcg_temp_new();
1575 TCGv t2
= tcg_temp_new();
1576 int l1
= gen_new_label();
1578 gen_load_gpr(t1
, rs
);
1579 gen_load_gpr(t2
, rt
);
1580 tcg_gen_add_tl(t0
, t1
, t2
);
1581 tcg_gen_ext32s_tl(t0
, t0
);
1582 tcg_gen_xor_tl(t1
, t1
, t2
);
1583 tcg_gen_not_tl(t1
, t1
);
1584 tcg_gen_xor_tl(t2
, t0
, t2
);
1585 tcg_gen_and_tl(t1
, t1
, t2
);
1587 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1589 /* operands of same sign, result different sign */
1590 generate_exception(ctx
, EXCP_OVERFLOW
);
1592 gen_store_gpr(t0
, rd
);
1598 if (rs
!= 0 && rt
!= 0) {
1599 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1600 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1601 } else if (rs
== 0 && rt
!= 0) {
1602 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1603 } else if (rs
!= 0 && rt
== 0) {
1604 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1606 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1612 TCGv t0
= tcg_temp_local_new();
1613 TCGv t1
= tcg_temp_new();
1614 TCGv t2
= tcg_temp_new();
1615 int l1
= gen_new_label();
1617 gen_load_gpr(t1
, rs
);
1618 gen_load_gpr(t2
, rt
);
1619 tcg_gen_sub_tl(t0
, t1
, t2
);
1620 tcg_gen_ext32s_tl(t0
, t0
);
1621 tcg_gen_xor_tl(t2
, t1
, t2
);
1622 tcg_gen_xor_tl(t1
, t0
, t1
);
1623 tcg_gen_and_tl(t1
, t1
, t2
);
1625 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1627 /* operands of different sign, first operand and result different sign */
1628 generate_exception(ctx
, EXCP_OVERFLOW
);
1630 gen_store_gpr(t0
, rd
);
1636 if (rs
!= 0 && rt
!= 0) {
1637 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1638 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1639 } else if (rs
== 0 && rt
!= 0) {
1640 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1641 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1642 } else if (rs
!= 0 && rt
== 0) {
1643 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1645 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1649 #if defined(TARGET_MIPS64)
1652 TCGv t0
= tcg_temp_local_new();
1653 TCGv t1
= tcg_temp_new();
1654 TCGv t2
= tcg_temp_new();
1655 int l1
= gen_new_label();
1657 gen_load_gpr(t1
, rs
);
1658 gen_load_gpr(t2
, rt
);
1659 tcg_gen_add_tl(t0
, t1
, t2
);
1660 tcg_gen_xor_tl(t1
, t1
, t2
);
1661 tcg_gen_not_tl(t1
, t1
);
1662 tcg_gen_xor_tl(t2
, t0
, t2
);
1663 tcg_gen_and_tl(t1
, t1
, t2
);
1665 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1667 /* operands of same sign, result different sign */
1668 generate_exception(ctx
, EXCP_OVERFLOW
);
1670 gen_store_gpr(t0
, rd
);
1676 if (rs
!= 0 && rt
!= 0) {
1677 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1678 } else if (rs
== 0 && rt
!= 0) {
1679 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1680 } else if (rs
!= 0 && rt
== 0) {
1681 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1683 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1689 TCGv t0
= tcg_temp_local_new();
1690 TCGv t1
= tcg_temp_new();
1691 TCGv t2
= tcg_temp_new();
1692 int l1
= gen_new_label();
1694 gen_load_gpr(t1
, rs
);
1695 gen_load_gpr(t2
, rt
);
1696 tcg_gen_sub_tl(t0
, t1
, t2
);
1697 tcg_gen_xor_tl(t2
, t1
, t2
);
1698 tcg_gen_xor_tl(t1
, t0
, t1
);
1699 tcg_gen_and_tl(t1
, t1
, t2
);
1701 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1703 /* operands of different sign, first operand and result different sign */
1704 generate_exception(ctx
, EXCP_OVERFLOW
);
1706 gen_store_gpr(t0
, rd
);
1712 if (rs
!= 0 && rt
!= 0) {
1713 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1714 } else if (rs
== 0 && rt
!= 0) {
1715 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1716 } else if (rs
!= 0 && rt
== 0) {
1717 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1719 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1725 if (likely(rs
!= 0 && rt
!= 0)) {
1726 tcg_gen_mul_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1727 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1729 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1734 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1737 /* Conditional move */
1738 static void gen_cond_move (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1740 const char *opn
= "cond move";
1744 /* If no destination, treat it as a NOP.
1745 For add & sub, we must generate the overflow exception when needed. */
1750 l1
= gen_new_label();
1753 if (likely(rt
!= 0))
1754 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rt
], 0, l1
);
1760 if (likely(rt
!= 0))
1761 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rt
], 0, l1
);
1766 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1768 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1771 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1775 static void gen_logic (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1777 const char *opn
= "logic";
1780 /* If no destination, treat it as a NOP. */
1787 if (likely(rs
!= 0 && rt
!= 0)) {
1788 tcg_gen_and_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1790 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1795 if (rs
!= 0 && rt
!= 0) {
1796 tcg_gen_nor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1797 } else if (rs
== 0 && rt
!= 0) {
1798 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1799 } else if (rs
!= 0 && rt
== 0) {
1800 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1802 tcg_gen_movi_tl(cpu_gpr
[rd
], ~((target_ulong
)0));
1807 if (likely(rs
!= 0 && rt
!= 0)) {
1808 tcg_gen_or_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1809 } else if (rs
== 0 && rt
!= 0) {
1810 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1811 } else if (rs
!= 0 && rt
== 0) {
1812 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1814 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1819 if (likely(rs
!= 0 && rt
!= 0)) {
1820 tcg_gen_xor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1821 } else if (rs
== 0 && rt
!= 0) {
1822 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1823 } else if (rs
!= 0 && rt
== 0) {
1824 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1826 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1831 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1834 /* Set on lower than */
1835 static void gen_slt (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1837 const char *opn
= "slt";
1841 /* If no destination, treat it as a NOP. */
1846 t0
= tcg_temp_new();
1847 t1
= tcg_temp_new();
1848 gen_load_gpr(t0
, rs
);
1849 gen_load_gpr(t1
, rt
);
1852 gen_op_lt(cpu_gpr
[rd
], t0
, t1
);
1856 gen_op_ltu(cpu_gpr
[rd
], t0
, t1
);
1860 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1866 static void gen_shift (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1867 int rd
, int rs
, int rt
)
1869 const char *opn
= "shifts";
1873 /* If no destination, treat it as a NOP.
1874 For add & sub, we must generate the overflow exception when needed. */
1879 t0
= tcg_temp_new();
1880 t1
= tcg_temp_new();
1881 gen_load_gpr(t0
, rs
);
1882 gen_load_gpr(t1
, rt
);
1885 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1886 tcg_gen_shl_tl(t0
, t1
, t0
);
1887 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1891 tcg_gen_ext32s_tl(t1
, t1
);
1892 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1893 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1897 switch ((ctx
->opcode
>> 6) & 0x1f) {
1899 tcg_gen_ext32u_tl(t1
, t1
);
1900 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1901 tcg_gen_shr_tl(t0
, t1
, t0
);
1902 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1906 /* rotrv is decoded as srlv on non-R2 CPUs */
1907 if (env
->insn_flags
& ISA_MIPS32R2
) {
1908 TCGv_i32 t2
= tcg_temp_new_i32();
1909 TCGv_i32 t3
= tcg_temp_new_i32();
1911 tcg_gen_trunc_tl_i32(t2
, t0
);
1912 tcg_gen_trunc_tl_i32(t3
, t1
);
1913 tcg_gen_andi_i32(t2
, t2
, 0x1f);
1914 tcg_gen_rotr_i32(t2
, t3
, t2
);
1915 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
1916 tcg_temp_free_i32(t2
);
1917 tcg_temp_free_i32(t3
);
1920 tcg_gen_ext32u_tl(t1
, t1
);
1921 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1922 tcg_gen_shr_tl(t0
, t1
, t0
);
1923 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1928 MIPS_INVAL("invalid srlv flag");
1929 generate_exception(ctx
, EXCP_RI
);
1933 #if defined(TARGET_MIPS64)
1935 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1936 tcg_gen_shl_tl(cpu_gpr
[rd
], t1
, t0
);
1940 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1941 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1945 switch ((ctx
->opcode
>> 6) & 0x1f) {
1947 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1948 tcg_gen_shr_tl(cpu_gpr
[rd
], t1
, t0
);
1952 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1953 if (env
->insn_flags
& ISA_MIPS32R2
) {
1954 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1955 tcg_gen_rotr_tl(cpu_gpr
[rd
], t1
, t0
);
1958 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1959 tcg_gen_shr_tl(t0
, t1
, t0
);
1964 MIPS_INVAL("invalid dsrlv flag");
1965 generate_exception(ctx
, EXCP_RI
);
1971 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1976 /* Arithmetic on HI/LO registers */
1977 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1979 const char *opn
= "hilo";
1981 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1988 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_HI
[0]);
1992 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_LO
[0]);
1997 tcg_gen_mov_tl(cpu_HI
[0], cpu_gpr
[reg
]);
1999 tcg_gen_movi_tl(cpu_HI
[0], 0);
2004 tcg_gen_mov_tl(cpu_LO
[0], cpu_gpr
[reg
]);
2006 tcg_gen_movi_tl(cpu_LO
[0], 0);
2010 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
2013 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
2016 const char *opn
= "mul/div";
2022 #if defined(TARGET_MIPS64)
2026 t0
= tcg_temp_local_new();
2027 t1
= tcg_temp_local_new();
2030 t0
= tcg_temp_new();
2031 t1
= tcg_temp_new();
2035 gen_load_gpr(t0
, rs
);
2036 gen_load_gpr(t1
, rt
);
2040 int l1
= gen_new_label();
2041 int l2
= gen_new_label();
2043 tcg_gen_ext32s_tl(t0
, t0
);
2044 tcg_gen_ext32s_tl(t1
, t1
);
2045 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2046 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
2047 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
2049 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2050 tcg_gen_movi_tl(cpu_HI
[0], 0);
2053 tcg_gen_div_tl(cpu_LO
[0], t0
, t1
);
2054 tcg_gen_rem_tl(cpu_HI
[0], t0
, t1
);
2055 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
2056 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
2063 int l1
= gen_new_label();
2065 tcg_gen_ext32u_tl(t0
, t0
);
2066 tcg_gen_ext32u_tl(t1
, t1
);
2067 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2068 tcg_gen_divu_tl(cpu_LO
[0], t0
, t1
);
2069 tcg_gen_remu_tl(cpu_HI
[0], t0
, t1
);
2070 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
2071 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
2078 TCGv_i64 t2
= tcg_temp_new_i64();
2079 TCGv_i64 t3
= tcg_temp_new_i64();
2081 tcg_gen_ext_tl_i64(t2
, t0
);
2082 tcg_gen_ext_tl_i64(t3
, t1
);
2083 tcg_gen_mul_i64(t2
, t2
, t3
);
2084 tcg_temp_free_i64(t3
);
2085 tcg_gen_trunc_i64_tl(t0
, t2
);
2086 tcg_gen_shri_i64(t2
, t2
, 32);
2087 tcg_gen_trunc_i64_tl(t1
, t2
);
2088 tcg_temp_free_i64(t2
);
2089 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2090 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2096 TCGv_i64 t2
= tcg_temp_new_i64();
2097 TCGv_i64 t3
= tcg_temp_new_i64();
2099 tcg_gen_ext32u_tl(t0
, t0
);
2100 tcg_gen_ext32u_tl(t1
, t1
);
2101 tcg_gen_extu_tl_i64(t2
, t0
);
2102 tcg_gen_extu_tl_i64(t3
, t1
);
2103 tcg_gen_mul_i64(t2
, t2
, t3
);
2104 tcg_temp_free_i64(t3
);
2105 tcg_gen_trunc_i64_tl(t0
, t2
);
2106 tcg_gen_shri_i64(t2
, t2
, 32);
2107 tcg_gen_trunc_i64_tl(t1
, t2
);
2108 tcg_temp_free_i64(t2
);
2109 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2110 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2114 #if defined(TARGET_MIPS64)
2117 int l1
= gen_new_label();
2118 int l2
= gen_new_label();
2120 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2121 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
2122 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
2123 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2124 tcg_gen_movi_tl(cpu_HI
[0], 0);
2127 tcg_gen_div_i64(cpu_LO
[0], t0
, t1
);
2128 tcg_gen_rem_i64(cpu_HI
[0], t0
, t1
);
2135 int l1
= gen_new_label();
2137 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2138 tcg_gen_divu_i64(cpu_LO
[0], t0
, t1
);
2139 tcg_gen_remu_i64(cpu_HI
[0], t0
, t1
);
2145 gen_helper_dmult(t0
, t1
);
2149 gen_helper_dmultu(t0
, t1
);
2155 TCGv_i64 t2
= tcg_temp_new_i64();
2156 TCGv_i64 t3
= tcg_temp_new_i64();
2158 tcg_gen_ext_tl_i64(t2
, t0
);
2159 tcg_gen_ext_tl_i64(t3
, t1
);
2160 tcg_gen_mul_i64(t2
, t2
, t3
);
2161 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2162 tcg_gen_add_i64(t2
, t2
, t3
);
2163 tcg_temp_free_i64(t3
);
2164 tcg_gen_trunc_i64_tl(t0
, t2
);
2165 tcg_gen_shri_i64(t2
, t2
, 32);
2166 tcg_gen_trunc_i64_tl(t1
, t2
);
2167 tcg_temp_free_i64(t2
);
2168 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2169 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2175 TCGv_i64 t2
= tcg_temp_new_i64();
2176 TCGv_i64 t3
= tcg_temp_new_i64();
2178 tcg_gen_ext32u_tl(t0
, t0
);
2179 tcg_gen_ext32u_tl(t1
, t1
);
2180 tcg_gen_extu_tl_i64(t2
, t0
);
2181 tcg_gen_extu_tl_i64(t3
, t1
);
2182 tcg_gen_mul_i64(t2
, t2
, t3
);
2183 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2184 tcg_gen_add_i64(t2
, t2
, t3
);
2185 tcg_temp_free_i64(t3
);
2186 tcg_gen_trunc_i64_tl(t0
, t2
);
2187 tcg_gen_shri_i64(t2
, t2
, 32);
2188 tcg_gen_trunc_i64_tl(t1
, t2
);
2189 tcg_temp_free_i64(t2
);
2190 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2191 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2197 TCGv_i64 t2
= tcg_temp_new_i64();
2198 TCGv_i64 t3
= tcg_temp_new_i64();
2200 tcg_gen_ext_tl_i64(t2
, t0
);
2201 tcg_gen_ext_tl_i64(t3
, t1
);
2202 tcg_gen_mul_i64(t2
, t2
, t3
);
2203 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2204 tcg_gen_sub_i64(t2
, t3
, t2
);
2205 tcg_temp_free_i64(t3
);
2206 tcg_gen_trunc_i64_tl(t0
, t2
);
2207 tcg_gen_shri_i64(t2
, t2
, 32);
2208 tcg_gen_trunc_i64_tl(t1
, t2
);
2209 tcg_temp_free_i64(t2
);
2210 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2211 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2217 TCGv_i64 t2
= tcg_temp_new_i64();
2218 TCGv_i64 t3
= tcg_temp_new_i64();
2220 tcg_gen_ext32u_tl(t0
, t0
);
2221 tcg_gen_ext32u_tl(t1
, t1
);
2222 tcg_gen_extu_tl_i64(t2
, t0
);
2223 tcg_gen_extu_tl_i64(t3
, t1
);
2224 tcg_gen_mul_i64(t2
, t2
, t3
);
2225 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2226 tcg_gen_sub_i64(t2
, t3
, t2
);
2227 tcg_temp_free_i64(t3
);
2228 tcg_gen_trunc_i64_tl(t0
, t2
);
2229 tcg_gen_shri_i64(t2
, t2
, 32);
2230 tcg_gen_trunc_i64_tl(t1
, t2
);
2231 tcg_temp_free_i64(t2
);
2232 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2233 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2239 generate_exception(ctx
, EXCP_RI
);
2242 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2248 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2249 int rd
, int rs
, int rt
)
2251 const char *opn
= "mul vr54xx";
2252 TCGv t0
= tcg_temp_new();
2253 TCGv t1
= tcg_temp_new();
2255 gen_load_gpr(t0
, rs
);
2256 gen_load_gpr(t1
, rt
);
2259 case OPC_VR54XX_MULS
:
2260 gen_helper_muls(t0
, t0
, t1
);
2263 case OPC_VR54XX_MULSU
:
2264 gen_helper_mulsu(t0
, t0
, t1
);
2267 case OPC_VR54XX_MACC
:
2268 gen_helper_macc(t0
, t0
, t1
);
2271 case OPC_VR54XX_MACCU
:
2272 gen_helper_maccu(t0
, t0
, t1
);
2275 case OPC_VR54XX_MSAC
:
2276 gen_helper_msac(t0
, t0
, t1
);
2279 case OPC_VR54XX_MSACU
:
2280 gen_helper_msacu(t0
, t0
, t1
);
2283 case OPC_VR54XX_MULHI
:
2284 gen_helper_mulhi(t0
, t0
, t1
);
2287 case OPC_VR54XX_MULHIU
:
2288 gen_helper_mulhiu(t0
, t0
, t1
);
2291 case OPC_VR54XX_MULSHI
:
2292 gen_helper_mulshi(t0
, t0
, t1
);
2295 case OPC_VR54XX_MULSHIU
:
2296 gen_helper_mulshiu(t0
, t0
, t1
);
2299 case OPC_VR54XX_MACCHI
:
2300 gen_helper_macchi(t0
, t0
, t1
);
2303 case OPC_VR54XX_MACCHIU
:
2304 gen_helper_macchiu(t0
, t0
, t1
);
2307 case OPC_VR54XX_MSACHI
:
2308 gen_helper_msachi(t0
, t0
, t1
);
2311 case OPC_VR54XX_MSACHIU
:
2312 gen_helper_msachiu(t0
, t0
, t1
);
2316 MIPS_INVAL("mul vr54xx");
2317 generate_exception(ctx
, EXCP_RI
);
2320 gen_store_gpr(t0
, rd
);
2321 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2328 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2331 const char *opn
= "CLx";
2339 t0
= tcg_temp_new();
2340 gen_load_gpr(t0
, rs
);
2343 gen_helper_clo(cpu_gpr
[rd
], t0
);
2347 gen_helper_clz(cpu_gpr
[rd
], t0
);
2350 #if defined(TARGET_MIPS64)
2352 gen_helper_dclo(cpu_gpr
[rd
], t0
);
2356 gen_helper_dclz(cpu_gpr
[rd
], t0
);
2361 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2366 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2367 int rs
, int rt
, int16_t imm
)
2370 TCGv t0
= tcg_temp_new();
2371 TCGv t1
= tcg_temp_new();
2374 /* Load needed operands */
2382 /* Compare two registers */
2384 gen_load_gpr(t0
, rs
);
2385 gen_load_gpr(t1
, rt
);
2395 /* Compare register to immediate */
2396 if (rs
!= 0 || imm
!= 0) {
2397 gen_load_gpr(t0
, rs
);
2398 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2405 case OPC_TEQ
: /* rs == rs */
2406 case OPC_TEQI
: /* r0 == 0 */
2407 case OPC_TGE
: /* rs >= rs */
2408 case OPC_TGEI
: /* r0 >= 0 */
2409 case OPC_TGEU
: /* rs >= rs unsigned */
2410 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2412 generate_exception(ctx
, EXCP_TRAP
);
2414 case OPC_TLT
: /* rs < rs */
2415 case OPC_TLTI
: /* r0 < 0 */
2416 case OPC_TLTU
: /* rs < rs unsigned */
2417 case OPC_TLTIU
: /* r0 < 0 unsigned */
2418 case OPC_TNE
: /* rs != rs */
2419 case OPC_TNEI
: /* r0 != 0 */
2420 /* Never trap: treat as NOP. */
2424 int l1
= gen_new_label();
2429 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, t1
, l1
);
2433 tcg_gen_brcond_tl(TCG_COND_LT
, t0
, t1
, l1
);
2437 tcg_gen_brcond_tl(TCG_COND_LTU
, t0
, t1
, l1
);
2441 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
2445 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
2449 tcg_gen_brcond_tl(TCG_COND_EQ
, t0
, t1
, l1
);
2452 generate_exception(ctx
, EXCP_TRAP
);
2459 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2461 TranslationBlock
*tb
;
2463 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
2466 tcg_gen_exit_tb((long)tb
+ n
);
2473 /* Branches (before delay slot) */
2474 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2475 int rs
, int rt
, int32_t offset
)
2477 target_ulong btgt
= -1;
2479 int bcond_compute
= 0;
2480 TCGv t0
= tcg_temp_new();
2481 TCGv t1
= tcg_temp_new();
2483 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2484 #ifdef MIPS_DEBUG_DISAS
2485 LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n", ctx
->pc
);
2487 generate_exception(ctx
, EXCP_RI
);
2491 /* Load needed operands */
2497 /* Compare two registers */
2499 gen_load_gpr(t0
, rs
);
2500 gen_load_gpr(t1
, rt
);
2503 btgt
= ctx
->pc
+ 4 + offset
;
2517 /* Compare to zero */
2519 gen_load_gpr(t0
, rs
);
2522 btgt
= ctx
->pc
+ 4 + offset
;
2526 /* Jump to immediate */
2527 btgt
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
2531 /* Jump to register */
2532 if (offset
!= 0 && offset
!= 16) {
2533 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2534 others are reserved. */
2535 MIPS_INVAL("jump hint");
2536 generate_exception(ctx
, EXCP_RI
);
2539 gen_load_gpr(btarget
, rs
);
2542 MIPS_INVAL("branch/jump");
2543 generate_exception(ctx
, EXCP_RI
);
2546 if (bcond_compute
== 0) {
2547 /* No condition to be computed */
2549 case OPC_BEQ
: /* rx == rx */
2550 case OPC_BEQL
: /* rx == rx likely */
2551 case OPC_BGEZ
: /* 0 >= 0 */
2552 case OPC_BGEZL
: /* 0 >= 0 likely */
2553 case OPC_BLEZ
: /* 0 <= 0 */
2554 case OPC_BLEZL
: /* 0 <= 0 likely */
2556 ctx
->hflags
|= MIPS_HFLAG_B
;
2557 MIPS_DEBUG("balways");
2559 case OPC_BGEZAL
: /* 0 >= 0 */
2560 case OPC_BGEZALL
: /* 0 >= 0 likely */
2561 /* Always take and link */
2563 ctx
->hflags
|= MIPS_HFLAG_B
;
2564 MIPS_DEBUG("balways and link");
2566 case OPC_BNE
: /* rx != rx */
2567 case OPC_BGTZ
: /* 0 > 0 */
2568 case OPC_BLTZ
: /* 0 < 0 */
2570 MIPS_DEBUG("bnever (NOP)");
2572 case OPC_BLTZAL
: /* 0 < 0 */
2573 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2574 MIPS_DEBUG("bnever and link");
2576 case OPC_BLTZALL
: /* 0 < 0 likely */
2577 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2578 /* Skip the instruction in the delay slot */
2579 MIPS_DEBUG("bnever, link and skip");
2582 case OPC_BNEL
: /* rx != rx likely */
2583 case OPC_BGTZL
: /* 0 > 0 likely */
2584 case OPC_BLTZL
: /* 0 < 0 likely */
2585 /* Skip the instruction in the delay slot */
2586 MIPS_DEBUG("bnever and skip");
2590 ctx
->hflags
|= MIPS_HFLAG_B
;
2591 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2595 ctx
->hflags
|= MIPS_HFLAG_B
;
2596 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2599 ctx
->hflags
|= MIPS_HFLAG_BR
;
2600 MIPS_DEBUG("jr %s", regnames
[rs
]);
2604 ctx
->hflags
|= MIPS_HFLAG_BR
;
2605 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2608 MIPS_INVAL("branch/jump");
2609 generate_exception(ctx
, EXCP_RI
);
2615 gen_op_eq(bcond
, t0
, t1
);
2616 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2617 regnames
[rs
], regnames
[rt
], btgt
);
2620 gen_op_eq(bcond
, t0
, t1
);
2621 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2622 regnames
[rs
], regnames
[rt
], btgt
);
2625 gen_op_ne(bcond
, t0
, t1
);
2626 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2627 regnames
[rs
], regnames
[rt
], btgt
);
2630 gen_op_ne(bcond
, t0
, t1
);
2631 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2632 regnames
[rs
], regnames
[rt
], btgt
);
2635 gen_op_gez(bcond
, t0
);
2636 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2639 gen_op_gez(bcond
, t0
);
2640 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2643 gen_op_gez(bcond
, t0
);
2644 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2648 gen_op_gez(bcond
, t0
);
2650 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2653 gen_op_gtz(bcond
, t0
);
2654 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2657 gen_op_gtz(bcond
, t0
);
2658 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2661 gen_op_lez(bcond
, t0
);
2662 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2665 gen_op_lez(bcond
, t0
);
2666 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2669 gen_op_ltz(bcond
, t0
);
2670 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2673 gen_op_ltz(bcond
, t0
);
2674 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2677 gen_op_ltz(bcond
, t0
);
2679 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2681 ctx
->hflags
|= MIPS_HFLAG_BC
;
2684 gen_op_ltz(bcond
, t0
);
2686 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2688 ctx
->hflags
|= MIPS_HFLAG_BL
;
2691 MIPS_INVAL("conditional branch/jump");
2692 generate_exception(ctx
, EXCP_RI
);
2696 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2697 blink
, ctx
->hflags
, btgt
);
2699 ctx
->btarget
= btgt
;
2701 tcg_gen_movi_tl(cpu_gpr
[blink
], ctx
->pc
+ 8);
2709 /* special3 bitfield operations */
2710 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2711 int rs
, int lsb
, int msb
)
2713 TCGv t0
= tcg_temp_new();
2714 TCGv t1
= tcg_temp_new();
2717 gen_load_gpr(t1
, rs
);
2722 tcg_gen_shri_tl(t0
, t1
, lsb
);
2724 tcg_gen_andi_tl(t0
, t0
, (1 << (msb
+ 1)) - 1);
2726 tcg_gen_ext32s_tl(t0
, t0
);
2729 #if defined(TARGET_MIPS64)
2731 tcg_gen_shri_tl(t0
, t1
, lsb
);
2733 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1 + 32)) - 1);
2737 tcg_gen_shri_tl(t0
, t1
, lsb
+ 32);
2738 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2741 tcg_gen_shri_tl(t0
, t1
, lsb
);
2742 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2748 mask
= ((msb
- lsb
+ 1 < 32) ? ((1 << (msb
- lsb
+ 1)) - 1) : ~0) << lsb
;
2749 gen_load_gpr(t0
, rt
);
2750 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2751 tcg_gen_shli_tl(t1
, t1
, lsb
);
2752 tcg_gen_andi_tl(t1
, t1
, mask
);
2753 tcg_gen_or_tl(t0
, t0
, t1
);
2754 tcg_gen_ext32s_tl(t0
, t0
);
2756 #if defined(TARGET_MIPS64)
2760 mask
= ((msb
- lsb
+ 1 + 32 < 64) ? ((1ULL << (msb
- lsb
+ 1 + 32)) - 1) : ~0ULL) << lsb
;
2761 gen_load_gpr(t0
, rt
);
2762 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2763 tcg_gen_shli_tl(t1
, t1
, lsb
);
2764 tcg_gen_andi_tl(t1
, t1
, mask
);
2765 tcg_gen_or_tl(t0
, t0
, t1
);
2770 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2771 gen_load_gpr(t0
, rt
);
2772 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2773 tcg_gen_shli_tl(t1
, t1
, lsb
+ 32);
2774 tcg_gen_andi_tl(t1
, t1
, mask
);
2775 tcg_gen_or_tl(t0
, t0
, t1
);
2780 gen_load_gpr(t0
, rt
);
2781 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2782 gen_load_gpr(t0
, rt
);
2783 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2784 tcg_gen_shli_tl(t1
, t1
, lsb
);
2785 tcg_gen_andi_tl(t1
, t1
, mask
);
2786 tcg_gen_or_tl(t0
, t0
, t1
);
2791 MIPS_INVAL("bitops");
2792 generate_exception(ctx
, EXCP_RI
);
2797 gen_store_gpr(t0
, rt
);
2802 static void gen_bshfl (DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
2807 /* If no destination, treat it as a NOP. */
2812 t0
= tcg_temp_new();
2813 gen_load_gpr(t0
, rt
);
2817 TCGv t1
= tcg_temp_new();
2819 tcg_gen_shri_tl(t1
, t0
, 8);
2820 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF);
2821 tcg_gen_shli_tl(t0
, t0
, 8);
2822 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF);
2823 tcg_gen_or_tl(t0
, t0
, t1
);
2825 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
2829 tcg_gen_ext8s_tl(cpu_gpr
[rd
], t0
);
2832 tcg_gen_ext16s_tl(cpu_gpr
[rd
], t0
);
2834 #if defined(TARGET_MIPS64)
2837 TCGv t1
= tcg_temp_new();
2839 tcg_gen_shri_tl(t1
, t0
, 8);
2840 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF00FF00FFULL
);
2841 tcg_gen_shli_tl(t0
, t0
, 8);
2842 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF00FF00FFULL
);
2843 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2849 TCGv t1
= tcg_temp_new();
2851 tcg_gen_shri_tl(t1
, t0
, 16);
2852 tcg_gen_andi_tl(t1
, t1
, 0x0000FFFF0000FFFFULL
);
2853 tcg_gen_shli_tl(t0
, t0
, 16);
2854 tcg_gen_andi_tl(t0
, t0
, ~0x0000FFFF0000FFFFULL
);
2855 tcg_gen_or_tl(t0
, t0
, t1
);
2856 tcg_gen_shri_tl(t1
, t0
, 32);
2857 tcg_gen_shli_tl(t0
, t0
, 32);
2858 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2864 MIPS_INVAL("bsfhl");
2865 generate_exception(ctx
, EXCP_RI
);
2872 #ifndef CONFIG_USER_ONLY
2873 /* CP0 (MMU and control) */
2874 static inline void gen_mfc0_load32 (TCGv arg
, target_ulong off
)
2876 TCGv_i32 t0
= tcg_temp_new_i32();
2878 tcg_gen_ld_i32(t0
, cpu_env
, off
);
2879 tcg_gen_ext_i32_tl(arg
, t0
);
2880 tcg_temp_free_i32(t0
);
2883 static inline void gen_mfc0_load64 (TCGv arg
, target_ulong off
)
2885 tcg_gen_ld_tl(arg
, cpu_env
, off
);
2886 tcg_gen_ext32s_tl(arg
, arg
);
2889 static inline void gen_mtc0_store32 (TCGv arg
, target_ulong off
)
2891 TCGv_i32 t0
= tcg_temp_new_i32();
2893 tcg_gen_trunc_tl_i32(t0
, arg
);
2894 tcg_gen_st_i32(t0
, cpu_env
, off
);
2895 tcg_temp_free_i32(t0
);
2898 static inline void gen_mtc0_store64 (TCGv arg
, target_ulong off
)
2900 tcg_gen_ext32s_tl(arg
, arg
);
2901 tcg_gen_st_tl(arg
, cpu_env
, off
);
2904 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
2906 const char *rn
= "invalid";
2909 check_insn(env
, ctx
, ISA_MIPS32
);
2915 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
2919 check_insn(env
, ctx
, ASE_MT
);
2920 gen_helper_mfc0_mvpcontrol(arg
);
2924 check_insn(env
, ctx
, ASE_MT
);
2925 gen_helper_mfc0_mvpconf0(arg
);
2929 check_insn(env
, ctx
, ASE_MT
);
2930 gen_helper_mfc0_mvpconf1(arg
);
2940 gen_helper_mfc0_random(arg
);
2944 check_insn(env
, ctx
, ASE_MT
);
2945 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
2949 check_insn(env
, ctx
, ASE_MT
);
2950 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
2954 check_insn(env
, ctx
, ASE_MT
);
2955 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
2959 check_insn(env
, ctx
, ASE_MT
);
2960 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_YQMask
));
2964 check_insn(env
, ctx
, ASE_MT
);
2965 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
2969 check_insn(env
, ctx
, ASE_MT
);
2970 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
2971 rn
= "VPEScheFBack";
2974 check_insn(env
, ctx
, ASE_MT
);
2975 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
2985 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
2986 tcg_gen_ext32s_tl(arg
, arg
);
2990 check_insn(env
, ctx
, ASE_MT
);
2991 gen_helper_mfc0_tcstatus(arg
);
2995 check_insn(env
, ctx
, ASE_MT
);
2996 gen_helper_mfc0_tcbind(arg
);
3000 check_insn(env
, ctx
, ASE_MT
);
3001 gen_helper_mfc0_tcrestart(arg
);
3005 check_insn(env
, ctx
, ASE_MT
);
3006 gen_helper_mfc0_tchalt(arg
);
3010 check_insn(env
, ctx
, ASE_MT
);
3011 gen_helper_mfc0_tccontext(arg
);
3015 check_insn(env
, ctx
, ASE_MT
);
3016 gen_helper_mfc0_tcschedule(arg
);
3020 check_insn(env
, ctx
, ASE_MT
);
3021 gen_helper_mfc0_tcschefback(arg
);
3031 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
3032 tcg_gen_ext32s_tl(arg
, arg
);
3042 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
3043 tcg_gen_ext32s_tl(arg
, arg
);
3047 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
3048 rn
= "ContextConfig";
3057 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
3061 check_insn(env
, ctx
, ISA_MIPS32R2
);
3062 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
3072 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
3076 check_insn(env
, ctx
, ISA_MIPS32R2
);
3077 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
3081 check_insn(env
, ctx
, ISA_MIPS32R2
);
3082 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
3086 check_insn(env
, ctx
, ISA_MIPS32R2
);
3087 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
3091 check_insn(env
, ctx
, ISA_MIPS32R2
);
3092 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
3096 check_insn(env
, ctx
, ISA_MIPS32R2
);
3097 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
3107 check_insn(env
, ctx
, ISA_MIPS32R2
);
3108 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
3118 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
3119 tcg_gen_ext32s_tl(arg
, arg
);
3129 /* Mark as an IO operation because we read the time. */
3132 gen_helper_mfc0_count(arg
);
3135 ctx
->bstate
= BS_STOP
;
3139 /* 6,7 are implementation dependent */
3147 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
3148 tcg_gen_ext32s_tl(arg
, arg
);
3158 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
3161 /* 6,7 are implementation dependent */
3169 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
3173 check_insn(env
, ctx
, ISA_MIPS32R2
);
3174 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
3178 check_insn(env
, ctx
, ISA_MIPS32R2
);
3179 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
3183 check_insn(env
, ctx
, ISA_MIPS32R2
);
3184 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3194 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
3204 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
3205 tcg_gen_ext32s_tl(arg
, arg
);
3215 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
3219 check_insn(env
, ctx
, ISA_MIPS32R2
);
3220 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
3230 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
3234 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
3238 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
3242 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
3245 /* 4,5 are reserved */
3246 /* 6,7 are implementation dependent */
3248 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
3252 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
3262 gen_helper_mfc0_lladdr(arg
);
3272 gen_helper_1i(mfc0_watchlo
, arg
, sel
);
3282 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
3292 #if defined(TARGET_MIPS64)
3293 check_insn(env
, ctx
, ISA_MIPS3
);
3294 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3295 tcg_gen_ext32s_tl(arg
, arg
);
3304 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3307 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
3315 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3316 rn
= "'Diagnostic"; /* implementation dependent */
3321 gen_helper_mfc0_debug(arg
); /* EJTAG support */
3325 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
3326 rn
= "TraceControl";
3329 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
3330 rn
= "TraceControl2";
3333 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
3334 rn
= "UserTraceData";
3337 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
3348 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3349 tcg_gen_ext32s_tl(arg
, arg
);
3359 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
3360 rn
= "Performance0";
3363 // gen_helper_mfc0_performance1(arg);
3364 rn
= "Performance1";
3367 // gen_helper_mfc0_performance2(arg);
3368 rn
= "Performance2";
3371 // gen_helper_mfc0_performance3(arg);
3372 rn
= "Performance3";
3375 // gen_helper_mfc0_performance4(arg);
3376 rn
= "Performance4";
3379 // gen_helper_mfc0_performance5(arg);
3380 rn
= "Performance5";
3383 // gen_helper_mfc0_performance6(arg);
3384 rn
= "Performance6";
3387 // gen_helper_mfc0_performance7(arg);
3388 rn
= "Performance7";
3395 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3401 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3414 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
3421 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
3434 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
3441 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
3451 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3452 tcg_gen_ext32s_tl(arg
, arg
);
3463 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
3473 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3477 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3478 generate_exception(ctx
, EXCP_RI
);
3481 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
3483 const char *rn
= "invalid";
3486 check_insn(env
, ctx
, ISA_MIPS32
);
3495 gen_helper_mtc0_index(arg
);
3499 check_insn(env
, ctx
, ASE_MT
);
3500 gen_helper_mtc0_mvpcontrol(arg
);
3504 check_insn(env
, ctx
, ASE_MT
);
3509 check_insn(env
, ctx
, ASE_MT
);
3524 check_insn(env
, ctx
, ASE_MT
);
3525 gen_helper_mtc0_vpecontrol(arg
);
3529 check_insn(env
, ctx
, ASE_MT
);
3530 gen_helper_mtc0_vpeconf0(arg
);
3534 check_insn(env
, ctx
, ASE_MT
);
3535 gen_helper_mtc0_vpeconf1(arg
);
3539 check_insn(env
, ctx
, ASE_MT
);
3540 gen_helper_mtc0_yqmask(arg
);
3544 check_insn(env
, ctx
, ASE_MT
);
3545 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
3549 check_insn(env
, ctx
, ASE_MT
);
3550 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
3551 rn
= "VPEScheFBack";
3554 check_insn(env
, ctx
, ASE_MT
);
3555 gen_helper_mtc0_vpeopt(arg
);
3565 gen_helper_mtc0_entrylo0(arg
);
3569 check_insn(env
, ctx
, ASE_MT
);
3570 gen_helper_mtc0_tcstatus(arg
);
3574 check_insn(env
, ctx
, ASE_MT
);
3575 gen_helper_mtc0_tcbind(arg
);
3579 check_insn(env
, ctx
, ASE_MT
);
3580 gen_helper_mtc0_tcrestart(arg
);
3584 check_insn(env
, ctx
, ASE_MT
);
3585 gen_helper_mtc0_tchalt(arg
);
3589 check_insn(env
, ctx
, ASE_MT
);
3590 gen_helper_mtc0_tccontext(arg
);
3594 check_insn(env
, ctx
, ASE_MT
);
3595 gen_helper_mtc0_tcschedule(arg
);
3599 check_insn(env
, ctx
, ASE_MT
);
3600 gen_helper_mtc0_tcschefback(arg
);
3610 gen_helper_mtc0_entrylo1(arg
);
3620 gen_helper_mtc0_context(arg
);
3624 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
3625 rn
= "ContextConfig";
3634 gen_helper_mtc0_pagemask(arg
);
3638 check_insn(env
, ctx
, ISA_MIPS32R2
);
3639 gen_helper_mtc0_pagegrain(arg
);
3649 gen_helper_mtc0_wired(arg
);
3653 check_insn(env
, ctx
, ISA_MIPS32R2
);
3654 gen_helper_mtc0_srsconf0(arg
);
3658 check_insn(env
, ctx
, ISA_MIPS32R2
);
3659 gen_helper_mtc0_srsconf1(arg
);
3663 check_insn(env
, ctx
, ISA_MIPS32R2
);
3664 gen_helper_mtc0_srsconf2(arg
);
3668 check_insn(env
, ctx
, ISA_MIPS32R2
);
3669 gen_helper_mtc0_srsconf3(arg
);
3673 check_insn(env
, ctx
, ISA_MIPS32R2
);
3674 gen_helper_mtc0_srsconf4(arg
);
3684 check_insn(env
, ctx
, ISA_MIPS32R2
);
3685 gen_helper_mtc0_hwrena(arg
);
3699 gen_helper_mtc0_count(arg
);
3702 /* 6,7 are implementation dependent */
3710 gen_helper_mtc0_entryhi(arg
);
3720 gen_helper_mtc0_compare(arg
);
3723 /* 6,7 are implementation dependent */
3731 save_cpu_state(ctx
, 1);
3732 gen_helper_mtc0_status(arg
);
3733 /* BS_STOP isn't good enough here, hflags may have changed. */
3734 gen_save_pc(ctx
->pc
+ 4);
3735 ctx
->bstate
= BS_EXCP
;
3739 check_insn(env
, ctx
, ISA_MIPS32R2
);
3740 gen_helper_mtc0_intctl(arg
);
3741 /* Stop translation as we may have switched the execution mode */
3742 ctx
->bstate
= BS_STOP
;
3746 check_insn(env
, ctx
, ISA_MIPS32R2
);
3747 gen_helper_mtc0_srsctl(arg
);
3748 /* Stop translation as we may have switched the execution mode */
3749 ctx
->bstate
= BS_STOP
;
3753 check_insn(env
, ctx
, ISA_MIPS32R2
);
3754 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3755 /* Stop translation as we may have switched the execution mode */
3756 ctx
->bstate
= BS_STOP
;
3766 save_cpu_state(ctx
, 1);
3767 gen_helper_mtc0_cause(arg
);
3777 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_EPC
));
3791 check_insn(env
, ctx
, ISA_MIPS32R2
);
3792 gen_helper_mtc0_ebase(arg
);
3802 gen_helper_mtc0_config0(arg
);
3804 /* Stop translation as we may have switched the execution mode */
3805 ctx
->bstate
= BS_STOP
;
3808 /* ignored, read only */
3812 gen_helper_mtc0_config2(arg
);
3814 /* Stop translation as we may have switched the execution mode */
3815 ctx
->bstate
= BS_STOP
;
3818 /* ignored, read only */
3821 /* 4,5 are reserved */
3822 /* 6,7 are implementation dependent */
3832 rn
= "Invalid config selector";
3849 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
3859 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
3869 #if defined(TARGET_MIPS64)
3870 check_insn(env
, ctx
, ISA_MIPS3
);
3871 gen_helper_mtc0_xcontext(arg
);
3880 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3883 gen_helper_mtc0_framemask(arg
);
3892 rn
= "Diagnostic"; /* implementation dependent */
3897 gen_helper_mtc0_debug(arg
); /* EJTAG support */
3898 /* BS_STOP isn't good enough here, hflags may have changed. */
3899 gen_save_pc(ctx
->pc
+ 4);
3900 ctx
->bstate
= BS_EXCP
;
3904 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
3905 rn
= "TraceControl";
3906 /* Stop translation as we may have switched the execution mode */
3907 ctx
->bstate
= BS_STOP
;
3910 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
3911 rn
= "TraceControl2";
3912 /* Stop translation as we may have switched the execution mode */
3913 ctx
->bstate
= BS_STOP
;
3916 /* Stop translation as we may have switched the execution mode */
3917 ctx
->bstate
= BS_STOP
;
3918 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
3919 rn
= "UserTraceData";
3920 /* Stop translation as we may have switched the execution mode */
3921 ctx
->bstate
= BS_STOP
;
3924 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
3925 /* Stop translation as we may have switched the execution mode */
3926 ctx
->bstate
= BS_STOP
;
3937 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_DEPC
));
3947 gen_helper_mtc0_performance0(arg
);
3948 rn
= "Performance0";
3951 // gen_helper_mtc0_performance1(arg);
3952 rn
= "Performance1";
3955 // gen_helper_mtc0_performance2(arg);
3956 rn
= "Performance2";
3959 // gen_helper_mtc0_performance3(arg);
3960 rn
= "Performance3";
3963 // gen_helper_mtc0_performance4(arg);
3964 rn
= "Performance4";
3967 // gen_helper_mtc0_performance5(arg);
3968 rn
= "Performance5";
3971 // gen_helper_mtc0_performance6(arg);
3972 rn
= "Performance6";
3975 // gen_helper_mtc0_performance7(arg);
3976 rn
= "Performance7";
4002 gen_helper_mtc0_taglo(arg
);
4009 gen_helper_mtc0_datalo(arg
);
4022 gen_helper_mtc0_taghi(arg
);
4029 gen_helper_mtc0_datahi(arg
);
4040 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_ErrorEPC
));
4051 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4057 /* Stop translation as we may have switched the execution mode */
4058 ctx
->bstate
= BS_STOP
;
4063 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4064 /* For simplicity assume that all writes can cause interrupts. */
4067 ctx
->bstate
= BS_STOP
;
4072 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4073 generate_exception(ctx
, EXCP_RI
);
4076 #if defined(TARGET_MIPS64)
4077 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4079 const char *rn
= "invalid";
4082 check_insn(env
, ctx
, ISA_MIPS64
);
4088 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
4092 check_insn(env
, ctx
, ASE_MT
);
4093 gen_helper_mfc0_mvpcontrol(arg
);
4097 check_insn(env
, ctx
, ASE_MT
);
4098 gen_helper_mfc0_mvpconf0(arg
);
4102 check_insn(env
, ctx
, ASE_MT
);
4103 gen_helper_mfc0_mvpconf1(arg
);
4113 gen_helper_mfc0_random(arg
);
4117 check_insn(env
, ctx
, ASE_MT
);
4118 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
4122 check_insn(env
, ctx
, ASE_MT
);
4123 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
4127 check_insn(env
, ctx
, ASE_MT
);
4128 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
4132 check_insn(env
, ctx
, ASE_MT
);
4133 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
4137 check_insn(env
, ctx
, ASE_MT
);
4138 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4142 check_insn(env
, ctx
, ASE_MT
);
4143 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4144 rn
= "VPEScheFBack";
4147 check_insn(env
, ctx
, ASE_MT
);
4148 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
4158 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
4162 check_insn(env
, ctx
, ASE_MT
);
4163 gen_helper_mfc0_tcstatus(arg
);
4167 check_insn(env
, ctx
, ASE_MT
);
4168 gen_helper_mfc0_tcbind(arg
);
4172 check_insn(env
, ctx
, ASE_MT
);
4173 gen_helper_dmfc0_tcrestart(arg
);
4177 check_insn(env
, ctx
, ASE_MT
);
4178 gen_helper_dmfc0_tchalt(arg
);
4182 check_insn(env
, ctx
, ASE_MT
);
4183 gen_helper_dmfc0_tccontext(arg
);
4187 check_insn(env
, ctx
, ASE_MT
);
4188 gen_helper_dmfc0_tcschedule(arg
);
4192 check_insn(env
, ctx
, ASE_MT
);
4193 gen_helper_dmfc0_tcschefback(arg
);
4203 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
4213 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4217 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
4218 rn
= "ContextConfig";
4227 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
4231 check_insn(env
, ctx
, ISA_MIPS32R2
);
4232 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
4242 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
4246 check_insn(env
, ctx
, ISA_MIPS32R2
);
4247 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
4251 check_insn(env
, ctx
, ISA_MIPS32R2
);
4252 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
4256 check_insn(env
, ctx
, ISA_MIPS32R2
);
4257 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
4261 check_insn(env
, ctx
, ISA_MIPS32R2
);
4262 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
4266 check_insn(env
, ctx
, ISA_MIPS32R2
);
4267 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
4277 check_insn(env
, ctx
, ISA_MIPS32R2
);
4278 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
4288 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4298 /* Mark as an IO operation because we read the time. */
4301 gen_helper_mfc0_count(arg
);
4304 ctx
->bstate
= BS_STOP
;
4308 /* 6,7 are implementation dependent */
4316 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4326 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
4329 /* 6,7 are implementation dependent */
4337 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
4341 check_insn(env
, ctx
, ISA_MIPS32R2
);
4342 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
4346 check_insn(env
, ctx
, ISA_MIPS32R2
);
4347 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
4351 check_insn(env
, ctx
, ISA_MIPS32R2
);
4352 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4362 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
4372 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4382 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
4386 check_insn(env
, ctx
, ISA_MIPS32R2
);
4387 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
4397 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
4401 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
4405 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
4409 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
4412 /* 6,7 are implementation dependent */
4414 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
4418 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
4428 gen_helper_dmfc0_lladdr(arg
);
4438 gen_helper_1i(dmfc0_watchlo
, arg
, sel
);
4448 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
4458 check_insn(env
, ctx
, ISA_MIPS3
);
4459 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4467 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4470 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
4478 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4479 rn
= "'Diagnostic"; /* implementation dependent */
4484 gen_helper_mfc0_debug(arg
); /* EJTAG support */
4488 // gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
4489 rn
= "TraceControl";
4492 // gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
4493 rn
= "TraceControl2";
4496 // gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
4497 rn
= "UserTraceData";
4500 // gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
4511 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4521 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
4522 rn
= "Performance0";
4525 // gen_helper_dmfc0_performance1(arg);
4526 rn
= "Performance1";
4529 // gen_helper_dmfc0_performance2(arg);
4530 rn
= "Performance2";
4533 // gen_helper_dmfc0_performance3(arg);
4534 rn
= "Performance3";
4537 // gen_helper_dmfc0_performance4(arg);
4538 rn
= "Performance4";
4541 // gen_helper_dmfc0_performance5(arg);
4542 rn
= "Performance5";
4545 // gen_helper_dmfc0_performance6(arg);
4546 rn
= "Performance6";
4549 // gen_helper_dmfc0_performance7(arg);
4550 rn
= "Performance7";
4557 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4564 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4577 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
4584 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
4597 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
4604 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
4614 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4625 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4635 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4639 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4640 generate_exception(ctx
, EXCP_RI
);
4643 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4645 const char *rn
= "invalid";
4648 check_insn(env
, ctx
, ISA_MIPS64
);
4657 gen_helper_mtc0_index(arg
);
4661 check_insn(env
, ctx
, ASE_MT
);
4662 gen_helper_mtc0_mvpcontrol(arg
);
4666 check_insn(env
, ctx
, ASE_MT
);
4671 check_insn(env
, ctx
, ASE_MT
);
4686 check_insn(env
, ctx
, ASE_MT
);
4687 gen_helper_mtc0_vpecontrol(arg
);
4691 check_insn(env
, ctx
, ASE_MT
);
4692 gen_helper_mtc0_vpeconf0(arg
);
4696 check_insn(env
, ctx
, ASE_MT
);
4697 gen_helper_mtc0_vpeconf1(arg
);
4701 check_insn(env
, ctx
, ASE_MT
);
4702 gen_helper_mtc0_yqmask(arg
);
4706 check_insn(env
, ctx
, ASE_MT
);
4707 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4711 check_insn(env
, ctx
, ASE_MT
);
4712 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4713 rn
= "VPEScheFBack";
4716 check_insn(env
, ctx
, ASE_MT
);
4717 gen_helper_mtc0_vpeopt(arg
);
4727 gen_helper_mtc0_entrylo0(arg
);
4731 check_insn(env
, ctx
, ASE_MT
);
4732 gen_helper_mtc0_tcstatus(arg
);
4736 check_insn(env
, ctx
, ASE_MT
);
4737 gen_helper_mtc0_tcbind(arg
);
4741 check_insn(env
, ctx
, ASE_MT
);
4742 gen_helper_mtc0_tcrestart(arg
);
4746 check_insn(env
, ctx
, ASE_MT
);
4747 gen_helper_mtc0_tchalt(arg
);
4751 check_insn(env
, ctx
, ASE_MT
);
4752 gen_helper_mtc0_tccontext(arg
);
4756 check_insn(env
, ctx
, ASE_MT
);
4757 gen_helper_mtc0_tcschedule(arg
);
4761 check_insn(env
, ctx
, ASE_MT
);
4762 gen_helper_mtc0_tcschefback(arg
);
4772 gen_helper_mtc0_entrylo1(arg
);
4782 gen_helper_mtc0_context(arg
);
4786 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
4787 rn
= "ContextConfig";
4796 gen_helper_mtc0_pagemask(arg
);
4800 check_insn(env
, ctx
, ISA_MIPS32R2
);
4801 gen_helper_mtc0_pagegrain(arg
);
4811 gen_helper_mtc0_wired(arg
);
4815 check_insn(env
, ctx
, ISA_MIPS32R2
);
4816 gen_helper_mtc0_srsconf0(arg
);
4820 check_insn(env
, ctx
, ISA_MIPS32R2
);
4821 gen_helper_mtc0_srsconf1(arg
);
4825 check_insn(env
, ctx
, ISA_MIPS32R2
);
4826 gen_helper_mtc0_srsconf2(arg
);
4830 check_insn(env
, ctx
, ISA_MIPS32R2
);
4831 gen_helper_mtc0_srsconf3(arg
);
4835 check_insn(env
, ctx
, ISA_MIPS32R2
);
4836 gen_helper_mtc0_srsconf4(arg
);
4846 check_insn(env
, ctx
, ISA_MIPS32R2
);
4847 gen_helper_mtc0_hwrena(arg
);
4861 gen_helper_mtc0_count(arg
);
4864 /* 6,7 are implementation dependent */
4868 /* Stop translation as we may have switched the execution mode */
4869 ctx
->bstate
= BS_STOP
;
4874 gen_helper_mtc0_entryhi(arg
);
4884 gen_helper_mtc0_compare(arg
);
4887 /* 6,7 are implementation dependent */
4891 /* Stop translation as we may have switched the execution mode */
4892 ctx
->bstate
= BS_STOP
;
4897 save_cpu_state(ctx
, 1);
4898 gen_helper_mtc0_status(arg
);
4899 /* BS_STOP isn't good enough here, hflags may have changed. */
4900 gen_save_pc(ctx
->pc
+ 4);
4901 ctx
->bstate
= BS_EXCP
;
4905 check_insn(env
, ctx
, ISA_MIPS32R2
);
4906 gen_helper_mtc0_intctl(arg
);
4907 /* Stop translation as we may have switched the execution mode */
4908 ctx
->bstate
= BS_STOP
;
4912 check_insn(env
, ctx
, ISA_MIPS32R2
);
4913 gen_helper_mtc0_srsctl(arg
);
4914 /* Stop translation as we may have switched the execution mode */
4915 ctx
->bstate
= BS_STOP
;
4919 check_insn(env
, ctx
, ISA_MIPS32R2
);
4920 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4921 /* Stop translation as we may have switched the execution mode */
4922 ctx
->bstate
= BS_STOP
;
4932 save_cpu_state(ctx
, 1);
4933 gen_helper_mtc0_cause(arg
);
4943 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4957 check_insn(env
, ctx
, ISA_MIPS32R2
);
4958 gen_helper_mtc0_ebase(arg
);
4968 gen_helper_mtc0_config0(arg
);
4970 /* Stop translation as we may have switched the execution mode */
4971 ctx
->bstate
= BS_STOP
;
4974 /* ignored, read only */
4978 gen_helper_mtc0_config2(arg
);
4980 /* Stop translation as we may have switched the execution mode */
4981 ctx
->bstate
= BS_STOP
;
4987 /* 6,7 are implementation dependent */
4989 rn
= "Invalid config selector";
5006 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
5016 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
5026 check_insn(env
, ctx
, ISA_MIPS3
);
5027 gen_helper_mtc0_xcontext(arg
);
5035 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5038 gen_helper_mtc0_framemask(arg
);
5047 rn
= "Diagnostic"; /* implementation dependent */
5052 gen_helper_mtc0_debug(arg
); /* EJTAG support */
5053 /* BS_STOP isn't good enough here, hflags may have changed. */
5054 gen_save_pc(ctx
->pc
+ 4);
5055 ctx
->bstate
= BS_EXCP
;
5059 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
5060 /* Stop translation as we may have switched the execution mode */
5061 ctx
->bstate
= BS_STOP
;
5062 rn
= "TraceControl";
5065 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
5066 /* Stop translation as we may have switched the execution mode */
5067 ctx
->bstate
= BS_STOP
;
5068 rn
= "TraceControl2";
5071 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
5072 /* Stop translation as we may have switched the execution mode */
5073 ctx
->bstate
= BS_STOP
;
5074 rn
= "UserTraceData";
5077 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
5078 /* Stop translation as we may have switched the execution mode */
5079 ctx
->bstate
= BS_STOP
;
5090 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
5100 gen_helper_mtc0_performance0(arg
);
5101 rn
= "Performance0";
5104 // gen_helper_mtc0_performance1(arg);
5105 rn
= "Performance1";
5108 // gen_helper_mtc0_performance2(arg);
5109 rn
= "Performance2";
5112 // gen_helper_mtc0_performance3(arg);
5113 rn
= "Performance3";
5116 // gen_helper_mtc0_performance4(arg);
5117 rn
= "Performance4";
5120 // gen_helper_mtc0_performance5(arg);
5121 rn
= "Performance5";
5124 // gen_helper_mtc0_performance6(arg);
5125 rn
= "Performance6";
5128 // gen_helper_mtc0_performance7(arg);
5129 rn
= "Performance7";
5155 gen_helper_mtc0_taglo(arg
);
5162 gen_helper_mtc0_datalo(arg
);
5175 gen_helper_mtc0_taghi(arg
);
5182 gen_helper_mtc0_datahi(arg
);
5193 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
5204 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
5210 /* Stop translation as we may have switched the execution mode */
5211 ctx
->bstate
= BS_STOP
;
5216 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5217 /* For simplicity assume that all writes can cause interrupts. */
5220 ctx
->bstate
= BS_STOP
;
5225 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5226 generate_exception(ctx
, EXCP_RI
);
5228 #endif /* TARGET_MIPS64 */
5230 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5231 int u
, int sel
, int h
)
5233 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5234 TCGv t0
= tcg_temp_local_new();
5236 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5237 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5238 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5239 tcg_gen_movi_tl(t0
, -1);
5240 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5241 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5242 tcg_gen_movi_tl(t0
, -1);
5248 gen_helper_mftc0_tcstatus(t0
);
5251 gen_helper_mftc0_tcbind(t0
);
5254 gen_helper_mftc0_tcrestart(t0
);
5257 gen_helper_mftc0_tchalt(t0
);
5260 gen_helper_mftc0_tccontext(t0
);
5263 gen_helper_mftc0_tcschedule(t0
);
5266 gen_helper_mftc0_tcschefback(t0
);
5269 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5276 gen_helper_mftc0_entryhi(t0
);
5279 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5285 gen_helper_mftc0_status(t0
);
5288 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5294 gen_helper_mftc0_debug(t0
);
5297 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5302 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5304 } else switch (sel
) {
5305 /* GPR registers. */
5307 gen_helper_1i(mftgpr
, t0
, rt
);
5309 /* Auxiliary CPU registers */
5313 gen_helper_1i(mftlo
, t0
, 0);
5316 gen_helper_1i(mfthi
, t0
, 0);
5319 gen_helper_1i(mftacx
, t0
, 0);
5322 gen_helper_1i(mftlo
, t0
, 1);
5325 gen_helper_1i(mfthi
, t0
, 1);
5328 gen_helper_1i(mftacx
, t0
, 1);
5331 gen_helper_1i(mftlo
, t0
, 2);
5334 gen_helper_1i(mfthi
, t0
, 2);
5337 gen_helper_1i(mftacx
, t0
, 2);
5340 gen_helper_1i(mftlo
, t0
, 3);
5343 gen_helper_1i(mfthi
, t0
, 3);
5346 gen_helper_1i(mftacx
, t0
, 3);
5349 gen_helper_mftdsp(t0
);
5355 /* Floating point (COP1). */
5357 /* XXX: For now we support only a single FPU context. */
5359 TCGv_i32 fp0
= tcg_temp_new_i32();
5361 gen_load_fpr32(fp0
, rt
);
5362 tcg_gen_ext_i32_tl(t0
, fp0
);
5363 tcg_temp_free_i32(fp0
);
5365 TCGv_i32 fp0
= tcg_temp_new_i32();
5367 gen_load_fpr32h(fp0
, rt
);
5368 tcg_gen_ext_i32_tl(t0
, fp0
);
5369 tcg_temp_free_i32(fp0
);
5373 /* XXX: For now we support only a single FPU context. */
5374 gen_helper_1i(cfc1
, t0
, rt
);
5376 /* COP2: Not implemented. */
5383 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5384 gen_store_gpr(t0
, rd
);
5390 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5391 generate_exception(ctx
, EXCP_RI
);
5394 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5395 int u
, int sel
, int h
)
5397 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5398 TCGv t0
= tcg_temp_local_new();
5400 gen_load_gpr(t0
, rt
);
5401 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5402 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5403 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5405 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5406 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5413 gen_helper_mttc0_tcstatus(t0
);
5416 gen_helper_mttc0_tcbind(t0
);
5419 gen_helper_mttc0_tcrestart(t0
);
5422 gen_helper_mttc0_tchalt(t0
);
5425 gen_helper_mttc0_tccontext(t0
);
5428 gen_helper_mttc0_tcschedule(t0
);
5431 gen_helper_mttc0_tcschefback(t0
);
5434 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5441 gen_helper_mttc0_entryhi(t0
);
5444 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5450 gen_helper_mttc0_status(t0
);
5453 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5459 gen_helper_mttc0_debug(t0
);
5462 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5467 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5469 } else switch (sel
) {
5470 /* GPR registers. */
5472 gen_helper_1i(mttgpr
, t0
, rd
);
5474 /* Auxiliary CPU registers */
5478 gen_helper_1i(mttlo
, t0
, 0);
5481 gen_helper_1i(mtthi
, t0
, 0);
5484 gen_helper_1i(mttacx
, t0
, 0);
5487 gen_helper_1i(mttlo
, t0
, 1);
5490 gen_helper_1i(mtthi
, t0
, 1);
5493 gen_helper_1i(mttacx
, t0
, 1);
5496 gen_helper_1i(mttlo
, t0
, 2);
5499 gen_helper_1i(mtthi
, t0
, 2);
5502 gen_helper_1i(mttacx
, t0
, 2);
5505 gen_helper_1i(mttlo
, t0
, 3);
5508 gen_helper_1i(mtthi
, t0
, 3);
5511 gen_helper_1i(mttacx
, t0
, 3);
5514 gen_helper_mttdsp(t0
);
5520 /* Floating point (COP1). */
5522 /* XXX: For now we support only a single FPU context. */
5524 TCGv_i32 fp0
= tcg_temp_new_i32();
5526 tcg_gen_trunc_tl_i32(fp0
, t0
);
5527 gen_store_fpr32(fp0
, rd
);
5528 tcg_temp_free_i32(fp0
);
5530 TCGv_i32 fp0
= tcg_temp_new_i32();
5532 tcg_gen_trunc_tl_i32(fp0
, t0
);
5533 gen_store_fpr32h(fp0
, rd
);
5534 tcg_temp_free_i32(fp0
);
5538 /* XXX: For now we support only a single FPU context. */
5539 gen_helper_1i(ctc1
, t0
, rd
);
5541 /* COP2: Not implemented. */
5548 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5554 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5555 generate_exception(ctx
, EXCP_RI
);
5558 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5560 const char *opn
= "ldst";
5568 gen_mfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5573 TCGv t0
= tcg_temp_new();
5575 gen_load_gpr(t0
, rt
);
5576 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5581 #if defined(TARGET_MIPS64)
5583 check_insn(env
, ctx
, ISA_MIPS3
);
5588 gen_dmfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5592 check_insn(env
, ctx
, ISA_MIPS3
);
5594 TCGv t0
= tcg_temp_new();
5596 gen_load_gpr(t0
, rt
);
5597 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5604 check_insn(env
, ctx
, ASE_MT
);
5609 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5610 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5614 check_insn(env
, ctx
, ASE_MT
);
5615 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5616 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5621 if (!env
->tlb
->helper_tlbwi
)
5627 if (!env
->tlb
->helper_tlbwr
)
5633 if (!env
->tlb
->helper_tlbp
)
5639 if (!env
->tlb
->helper_tlbr
)
5645 check_insn(env
, ctx
, ISA_MIPS2
);
5647 ctx
->bstate
= BS_EXCP
;
5651 check_insn(env
, ctx
, ISA_MIPS32
);
5652 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5654 generate_exception(ctx
, EXCP_RI
);
5657 ctx
->bstate
= BS_EXCP
;
5662 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5663 /* If we get an exception, we want to restart at next instruction */
5665 save_cpu_state(ctx
, 1);
5668 ctx
->bstate
= BS_EXCP
;
5673 generate_exception(ctx
, EXCP_RI
);
5676 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5678 #endif /* !CONFIG_USER_ONLY */
5680 /* CP1 Branches (before delay slot) */
5681 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5682 int32_t cc
, int32_t offset
)
5684 target_ulong btarget
;
5685 const char *opn
= "cp1 cond branch";
5686 TCGv_i32 t0
= tcg_temp_new_i32();
5689 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5691 btarget
= ctx
->pc
+ 4 + offset
;
5695 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5696 tcg_gen_not_i32(t0
, t0
);
5697 tcg_gen_andi_i32(t0
, t0
, 1);
5698 tcg_gen_extu_i32_tl(bcond
, t0
);
5702 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5703 tcg_gen_not_i32(t0
, t0
);
5704 tcg_gen_andi_i32(t0
, t0
, 1);
5705 tcg_gen_extu_i32_tl(bcond
, t0
);
5709 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5710 tcg_gen_andi_i32(t0
, t0
, 1);
5711 tcg_gen_extu_i32_tl(bcond
, t0
);
5715 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5716 tcg_gen_andi_i32(t0
, t0
, 1);
5717 tcg_gen_extu_i32_tl(bcond
, t0
);
5720 ctx
->hflags
|= MIPS_HFLAG_BL
;
5724 TCGv_i32 t1
= tcg_temp_new_i32();
5725 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5726 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5727 tcg_gen_or_i32(t0
, t0
, t1
);
5728 tcg_temp_free_i32(t1
);
5729 tcg_gen_not_i32(t0
, t0
);
5730 tcg_gen_andi_i32(t0
, t0
, 1);
5731 tcg_gen_extu_i32_tl(bcond
, t0
);
5737 TCGv_i32 t1
= tcg_temp_new_i32();
5738 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5739 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5740 tcg_gen_or_i32(t0
, t0
, t1
);
5741 tcg_temp_free_i32(t1
);
5742 tcg_gen_andi_i32(t0
, t0
, 1);
5743 tcg_gen_extu_i32_tl(bcond
, t0
);
5749 TCGv_i32 t1
= tcg_temp_new_i32();
5750 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5751 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5752 tcg_gen_or_i32(t0
, t0
, t1
);
5753 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5754 tcg_gen_or_i32(t0
, t0
, t1
);
5755 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5756 tcg_gen_or_i32(t0
, t0
, t1
);
5757 tcg_temp_free_i32(t1
);
5758 tcg_gen_not_i32(t0
, t0
);
5759 tcg_gen_andi_i32(t0
, t0
, 1);
5760 tcg_gen_extu_i32_tl(bcond
, t0
);
5766 TCGv_i32 t1
= tcg_temp_new_i32();
5767 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5768 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5769 tcg_gen_or_i32(t0
, t0
, t1
);
5770 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5771 tcg_gen_or_i32(t0
, t0
, t1
);
5772 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5773 tcg_gen_or_i32(t0
, t0
, t1
);
5774 tcg_temp_free_i32(t1
);
5775 tcg_gen_andi_i32(t0
, t0
, 1);
5776 tcg_gen_extu_i32_tl(bcond
, t0
);
5780 ctx
->hflags
|= MIPS_HFLAG_BC
;
5784 generate_exception (ctx
, EXCP_RI
);
5787 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5788 ctx
->hflags
, btarget
);
5789 ctx
->btarget
= btarget
;
5792 tcg_temp_free_i32(t0
);
5795 /* Coprocessor 1 (FPU) */
5797 #define FOP(func, fmt) (((fmt) << 21) | (func))
5799 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5801 const char *opn
= "cp1 move";
5802 TCGv t0
= tcg_temp_new();
5807 TCGv_i32 fp0
= tcg_temp_new_i32();
5809 gen_load_fpr32(fp0
, fs
);
5810 tcg_gen_ext_i32_tl(t0
, fp0
);
5811 tcg_temp_free_i32(fp0
);
5813 gen_store_gpr(t0
, rt
);
5817 gen_load_gpr(t0
, rt
);
5819 TCGv_i32 fp0
= tcg_temp_new_i32();
5821 tcg_gen_trunc_tl_i32(fp0
, t0
);
5822 gen_store_fpr32(fp0
, fs
);
5823 tcg_temp_free_i32(fp0
);
5828 gen_helper_1i(cfc1
, t0
, fs
);
5829 gen_store_gpr(t0
, rt
);
5833 gen_load_gpr(t0
, rt
);
5834 gen_helper_1i(ctc1
, t0
, fs
);
5837 #if defined(TARGET_MIPS64)
5839 gen_load_fpr64(ctx
, t0
, fs
);
5840 gen_store_gpr(t0
, rt
);
5844 gen_load_gpr(t0
, rt
);
5845 gen_store_fpr64(ctx
, t0
, fs
);
5851 TCGv_i32 fp0
= tcg_temp_new_i32();
5853 gen_load_fpr32h(fp0
, fs
);
5854 tcg_gen_ext_i32_tl(t0
, fp0
);
5855 tcg_temp_free_i32(fp0
);
5857 gen_store_gpr(t0
, rt
);
5861 gen_load_gpr(t0
, rt
);
5863 TCGv_i32 fp0
= tcg_temp_new_i32();
5865 tcg_gen_trunc_tl_i32(fp0
, t0
);
5866 gen_store_fpr32h(fp0
, fs
);
5867 tcg_temp_free_i32(fp0
);
5873 generate_exception (ctx
, EXCP_RI
);
5876 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
5882 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
5898 l1
= gen_new_label();
5899 t0
= tcg_temp_new_i32();
5900 tcg_gen_andi_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5901 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5902 tcg_temp_free_i32(t0
);
5904 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5906 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
5911 static inline void gen_movcf_s (int fs
, int fd
, int cc
, int tf
)
5914 TCGv_i32 t0
= tcg_temp_new_i32();
5915 int l1
= gen_new_label();
5922 tcg_gen_andi_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5923 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5924 gen_load_fpr32(t0
, fs
);
5925 gen_store_fpr32(t0
, fd
);
5927 tcg_temp_free_i32(t0
);
5930 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
5933 TCGv_i32 t0
= tcg_temp_new_i32();
5935 int l1
= gen_new_label();
5942 tcg_gen_andi_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5943 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5944 tcg_temp_free_i32(t0
);
5945 fp0
= tcg_temp_new_i64();
5946 gen_load_fpr64(ctx
, fp0
, fs
);
5947 gen_store_fpr64(ctx
, fp0
, fd
);
5948 tcg_temp_free_i64(fp0
);
5952 static inline void gen_movcf_ps (int fs
, int fd
, int cc
, int tf
)
5955 TCGv_i32 t0
= tcg_temp_new_i32();
5956 int l1
= gen_new_label();
5957 int l2
= gen_new_label();
5964 tcg_gen_andi_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5965 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5966 gen_load_fpr32(t0
, fs
);
5967 gen_store_fpr32(t0
, fd
);
5970 tcg_gen_andi_i32(t0
, fpu_fcr31
, get_fp_bit(cc
+1));
5971 tcg_gen_brcondi_i32(cond
, t0
, 0, l2
);
5972 gen_load_fpr32h(t0
, fs
);
5973 gen_store_fpr32h(t0
, fd
);
5974 tcg_temp_free_i32(t0
);
5979 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
5980 int ft
, int fs
, int fd
, int cc
)
5982 const char *opn
= "farith";
5983 const char *condnames
[] = {
6001 const char *condnames_abs
[] = {
6019 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
6020 uint32_t func
= ctx
->opcode
& 0x3f;
6022 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
6025 TCGv_i32 fp0
= tcg_temp_new_i32();
6026 TCGv_i32 fp1
= tcg_temp_new_i32();
6028 gen_load_fpr32(fp0
, fs
);
6029 gen_load_fpr32(fp1
, ft
);
6030 gen_helper_float_add_s(fp0
, fp0
, fp1
);
6031 tcg_temp_free_i32(fp1
);
6032 gen_store_fpr32(fp0
, fd
);
6033 tcg_temp_free_i32(fp0
);
6040 TCGv_i32 fp0
= tcg_temp_new_i32();
6041 TCGv_i32 fp1
= tcg_temp_new_i32();
6043 gen_load_fpr32(fp0
, fs
);
6044 gen_load_fpr32(fp1
, ft
);
6045 gen_helper_float_sub_s(fp0
, fp0
, fp1
);
6046 tcg_temp_free_i32(fp1
);
6047 gen_store_fpr32(fp0
, fd
);
6048 tcg_temp_free_i32(fp0
);
6055 TCGv_i32 fp0
= tcg_temp_new_i32();
6056 TCGv_i32 fp1
= tcg_temp_new_i32();
6058 gen_load_fpr32(fp0
, fs
);
6059 gen_load_fpr32(fp1
, ft
);
6060 gen_helper_float_mul_s(fp0
, fp0
, fp1
);
6061 tcg_temp_free_i32(fp1
);
6062 gen_store_fpr32(fp0
, fd
);
6063 tcg_temp_free_i32(fp0
);
6070 TCGv_i32 fp0
= tcg_temp_new_i32();
6071 TCGv_i32 fp1
= tcg_temp_new_i32();
6073 gen_load_fpr32(fp0
, fs
);
6074 gen_load_fpr32(fp1
, ft
);
6075 gen_helper_float_div_s(fp0
, fp0
, fp1
);
6076 tcg_temp_free_i32(fp1
);
6077 gen_store_fpr32(fp0
, fd
);
6078 tcg_temp_free_i32(fp0
);
6085 TCGv_i32 fp0
= tcg_temp_new_i32();
6087 gen_load_fpr32(fp0
, fs
);
6088 gen_helper_float_sqrt_s(fp0
, fp0
);
6089 gen_store_fpr32(fp0
, fd
);
6090 tcg_temp_free_i32(fp0
);
6096 TCGv_i32 fp0
= tcg_temp_new_i32();
6098 gen_load_fpr32(fp0
, fs
);
6099 gen_helper_float_abs_s(fp0
, fp0
);
6100 gen_store_fpr32(fp0
, fd
);
6101 tcg_temp_free_i32(fp0
);
6107 TCGv_i32 fp0
= tcg_temp_new_i32();
6109 gen_load_fpr32(fp0
, fs
);
6110 gen_store_fpr32(fp0
, fd
);
6111 tcg_temp_free_i32(fp0
);
6117 TCGv_i32 fp0
= tcg_temp_new_i32();
6119 gen_load_fpr32(fp0
, fs
);
6120 gen_helper_float_chs_s(fp0
, fp0
);
6121 gen_store_fpr32(fp0
, fd
);
6122 tcg_temp_free_i32(fp0
);
6127 check_cp1_64bitmode(ctx
);
6129 TCGv_i32 fp32
= tcg_temp_new_i32();
6130 TCGv_i64 fp64
= tcg_temp_new_i64();
6132 gen_load_fpr32(fp32
, fs
);
6133 gen_helper_float_roundl_s(fp64
, fp32
);
6134 tcg_temp_free_i32(fp32
);
6135 gen_store_fpr64(ctx
, fp64
, fd
);
6136 tcg_temp_free_i64(fp64
);
6141 check_cp1_64bitmode(ctx
);
6143 TCGv_i32 fp32
= tcg_temp_new_i32();
6144 TCGv_i64 fp64
= tcg_temp_new_i64();
6146 gen_load_fpr32(fp32
, fs
);
6147 gen_helper_float_truncl_s(fp64
, fp32
);
6148 tcg_temp_free_i32(fp32
);
6149 gen_store_fpr64(ctx
, fp64
, fd
);
6150 tcg_temp_free_i64(fp64
);
6155 check_cp1_64bitmode(ctx
);
6157 TCGv_i32 fp32
= tcg_temp_new_i32();
6158 TCGv_i64 fp64
= tcg_temp_new_i64();
6160 gen_load_fpr32(fp32
, fs
);
6161 gen_helper_float_ceill_s(fp64
, fp32
);
6162 tcg_temp_free_i32(fp32
);
6163 gen_store_fpr64(ctx
, fp64
, fd
);
6164 tcg_temp_free_i64(fp64
);
6169 check_cp1_64bitmode(ctx
);
6171 TCGv_i32 fp32
= tcg_temp_new_i32();
6172 TCGv_i64 fp64
= tcg_temp_new_i64();
6174 gen_load_fpr32(fp32
, fs
);
6175 gen_helper_float_floorl_s(fp64
, fp32
);
6176 tcg_temp_free_i32(fp32
);
6177 gen_store_fpr64(ctx
, fp64
, fd
);
6178 tcg_temp_free_i64(fp64
);
6184 TCGv_i32 fp0
= tcg_temp_new_i32();
6186 gen_load_fpr32(fp0
, fs
);
6187 gen_helper_float_roundw_s(fp0
, fp0
);
6188 gen_store_fpr32(fp0
, fd
);
6189 tcg_temp_free_i32(fp0
);
6195 TCGv_i32 fp0
= tcg_temp_new_i32();
6197 gen_load_fpr32(fp0
, fs
);
6198 gen_helper_float_truncw_s(fp0
, fp0
);
6199 gen_store_fpr32(fp0
, fd
);
6200 tcg_temp_free_i32(fp0
);
6206 TCGv_i32 fp0
= tcg_temp_new_i32();
6208 gen_load_fpr32(fp0
, fs
);
6209 gen_helper_float_ceilw_s(fp0
, fp0
);
6210 gen_store_fpr32(fp0
, fd
);
6211 tcg_temp_free_i32(fp0
);
6217 TCGv_i32 fp0
= tcg_temp_new_i32();
6219 gen_load_fpr32(fp0
, fs
);
6220 gen_helper_float_floorw_s(fp0
, fp0
);
6221 gen_store_fpr32(fp0
, fd
);
6222 tcg_temp_free_i32(fp0
);
6227 gen_movcf_s(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6232 int l1
= gen_new_label();
6236 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6238 fp0
= tcg_temp_new_i32();
6239 gen_load_fpr32(fp0
, fs
);
6240 gen_store_fpr32(fp0
, fd
);
6241 tcg_temp_free_i32(fp0
);
6248 int l1
= gen_new_label();
6252 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6253 fp0
= tcg_temp_new_i32();
6254 gen_load_fpr32(fp0
, fs
);
6255 gen_store_fpr32(fp0
, fd
);
6256 tcg_temp_free_i32(fp0
);
6265 TCGv_i32 fp0
= tcg_temp_new_i32();
6267 gen_load_fpr32(fp0
, fs
);
6268 gen_helper_float_recip_s(fp0
, fp0
);
6269 gen_store_fpr32(fp0
, fd
);
6270 tcg_temp_free_i32(fp0
);
6277 TCGv_i32 fp0
= tcg_temp_new_i32();
6279 gen_load_fpr32(fp0
, fs
);
6280 gen_helper_float_rsqrt_s(fp0
, fp0
);
6281 gen_store_fpr32(fp0
, fd
);
6282 tcg_temp_free_i32(fp0
);
6287 check_cp1_64bitmode(ctx
);
6289 TCGv_i32 fp0
= tcg_temp_new_i32();
6290 TCGv_i32 fp1
= tcg_temp_new_i32();
6292 gen_load_fpr32(fp0
, fs
);
6293 gen_load_fpr32(fp1
, fd
);
6294 gen_helper_float_recip2_s(fp0
, fp0
, fp1
);
6295 tcg_temp_free_i32(fp1
);
6296 gen_store_fpr32(fp0
, fd
);
6297 tcg_temp_free_i32(fp0
);
6302 check_cp1_64bitmode(ctx
);
6304 TCGv_i32 fp0
= tcg_temp_new_i32();
6306 gen_load_fpr32(fp0
, fs
);
6307 gen_helper_float_recip1_s(fp0
, fp0
);
6308 gen_store_fpr32(fp0
, fd
);
6309 tcg_temp_free_i32(fp0
);
6314 check_cp1_64bitmode(ctx
);
6316 TCGv_i32 fp0
= tcg_temp_new_i32();
6318 gen_load_fpr32(fp0
, fs
);
6319 gen_helper_float_rsqrt1_s(fp0
, fp0
);
6320 gen_store_fpr32(fp0
, fd
);
6321 tcg_temp_free_i32(fp0
);
6326 check_cp1_64bitmode(ctx
);
6328 TCGv_i32 fp0
= tcg_temp_new_i32();
6329 TCGv_i32 fp1
= tcg_temp_new_i32();
6331 gen_load_fpr32(fp0
, fs
);
6332 gen_load_fpr32(fp1
, ft
);
6333 gen_helper_float_rsqrt2_s(fp0
, fp0
, fp1
);
6334 tcg_temp_free_i32(fp1
);
6335 gen_store_fpr32(fp0
, fd
);
6336 tcg_temp_free_i32(fp0
);
6341 check_cp1_registers(ctx
, fd
);
6343 TCGv_i32 fp32
= tcg_temp_new_i32();
6344 TCGv_i64 fp64
= tcg_temp_new_i64();
6346 gen_load_fpr32(fp32
, fs
);
6347 gen_helper_float_cvtd_s(fp64
, fp32
);
6348 tcg_temp_free_i32(fp32
);
6349 gen_store_fpr64(ctx
, fp64
, fd
);
6350 tcg_temp_free_i64(fp64
);
6356 TCGv_i32 fp0
= tcg_temp_new_i32();
6358 gen_load_fpr32(fp0
, fs
);
6359 gen_helper_float_cvtw_s(fp0
, fp0
);
6360 gen_store_fpr32(fp0
, fd
);
6361 tcg_temp_free_i32(fp0
);
6366 check_cp1_64bitmode(ctx
);
6368 TCGv_i32 fp32
= tcg_temp_new_i32();
6369 TCGv_i64 fp64
= tcg_temp_new_i64();
6371 gen_load_fpr32(fp32
, fs
);
6372 gen_helper_float_cvtl_s(fp64
, fp32
);
6373 tcg_temp_free_i32(fp32
);
6374 gen_store_fpr64(ctx
, fp64
, fd
);
6375 tcg_temp_free_i64(fp64
);
6380 check_cp1_64bitmode(ctx
);
6382 TCGv_i64 fp64
= tcg_temp_new_i64();
6383 TCGv_i32 fp32_0
= tcg_temp_new_i32();
6384 TCGv_i32 fp32_1
= tcg_temp_new_i32();
6386 gen_load_fpr32(fp32_0
, fs
);
6387 gen_load_fpr32(fp32_1
, ft
);
6388 tcg_gen_concat_i32_i64(fp64
, fp32_0
, fp32_1
);
6389 tcg_temp_free_i32(fp32_1
);
6390 tcg_temp_free_i32(fp32_0
);
6391 gen_store_fpr64(ctx
, fp64
, fd
);
6392 tcg_temp_free_i64(fp64
);
6413 TCGv_i32 fp0
= tcg_temp_new_i32();
6414 TCGv_i32 fp1
= tcg_temp_new_i32();
6416 gen_load_fpr32(fp0
, fs
);
6417 gen_load_fpr32(fp1
, ft
);
6418 if (ctx
->opcode
& (1 << 6)) {
6420 gen_cmpabs_s(func
-48, fp0
, fp1
, cc
);
6421 opn
= condnames_abs
[func
-48];
6423 gen_cmp_s(func
-48, fp0
, fp1
, cc
);
6424 opn
= condnames
[func
-48];
6426 tcg_temp_free_i32(fp0
);
6427 tcg_temp_free_i32(fp1
);
6431 check_cp1_registers(ctx
, fs
| ft
| fd
);
6433 TCGv_i64 fp0
= tcg_temp_new_i64();
6434 TCGv_i64 fp1
= tcg_temp_new_i64();
6436 gen_load_fpr64(ctx
, fp0
, fs
);
6437 gen_load_fpr64(ctx
, fp1
, ft
);
6438 gen_helper_float_add_d(fp0
, fp0
, fp1
);
6439 tcg_temp_free_i64(fp1
);
6440 gen_store_fpr64(ctx
, fp0
, fd
);
6441 tcg_temp_free_i64(fp0
);
6447 check_cp1_registers(ctx
, fs
| ft
| fd
);
6449 TCGv_i64 fp0
= tcg_temp_new_i64();
6450 TCGv_i64 fp1
= tcg_temp_new_i64();
6452 gen_load_fpr64(ctx
, fp0
, fs
);
6453 gen_load_fpr64(ctx
, fp1
, ft
);
6454 gen_helper_float_sub_d(fp0
, fp0
, fp1
);
6455 tcg_temp_free_i64(fp1
);
6456 gen_store_fpr64(ctx
, fp0
, fd
);
6457 tcg_temp_free_i64(fp0
);
6463 check_cp1_registers(ctx
, fs
| ft
| fd
);
6465 TCGv_i64 fp0
= tcg_temp_new_i64();
6466 TCGv_i64 fp1
= tcg_temp_new_i64();
6468 gen_load_fpr64(ctx
, fp0
, fs
);
6469 gen_load_fpr64(ctx
, fp1
, ft
);
6470 gen_helper_float_mul_d(fp0
, fp0
, fp1
);
6471 tcg_temp_free_i64(fp1
);
6472 gen_store_fpr64(ctx
, fp0
, fd
);
6473 tcg_temp_free_i64(fp0
);
6479 check_cp1_registers(ctx
, fs
| ft
| fd
);
6481 TCGv_i64 fp0
= tcg_temp_new_i64();
6482 TCGv_i64 fp1
= tcg_temp_new_i64();
6484 gen_load_fpr64(ctx
, fp0
, fs
);
6485 gen_load_fpr64(ctx
, fp1
, ft
);
6486 gen_helper_float_div_d(fp0
, fp0
, fp1
);
6487 tcg_temp_free_i64(fp1
);
6488 gen_store_fpr64(ctx
, fp0
, fd
);
6489 tcg_temp_free_i64(fp0
);
6495 check_cp1_registers(ctx
, fs
| fd
);
6497 TCGv_i64 fp0
= tcg_temp_new_i64();
6499 gen_load_fpr64(ctx
, fp0
, fs
);
6500 gen_helper_float_sqrt_d(fp0
, fp0
);
6501 gen_store_fpr64(ctx
, fp0
, fd
);
6502 tcg_temp_free_i64(fp0
);
6507 check_cp1_registers(ctx
, fs
| fd
);
6509 TCGv_i64 fp0
= tcg_temp_new_i64();
6511 gen_load_fpr64(ctx
, fp0
, fs
);
6512 gen_helper_float_abs_d(fp0
, fp0
);
6513 gen_store_fpr64(ctx
, fp0
, fd
);
6514 tcg_temp_free_i64(fp0
);
6519 check_cp1_registers(ctx
, fs
| fd
);
6521 TCGv_i64 fp0
= tcg_temp_new_i64();
6523 gen_load_fpr64(ctx
, fp0
, fs
);
6524 gen_store_fpr64(ctx
, fp0
, fd
);
6525 tcg_temp_free_i64(fp0
);
6530 check_cp1_registers(ctx
, fs
| fd
);
6532 TCGv_i64 fp0
= tcg_temp_new_i64();
6534 gen_load_fpr64(ctx
, fp0
, fs
);
6535 gen_helper_float_chs_d(fp0
, fp0
);
6536 gen_store_fpr64(ctx
, fp0
, fd
);
6537 tcg_temp_free_i64(fp0
);
6542 check_cp1_64bitmode(ctx
);
6544 TCGv_i64 fp0
= tcg_temp_new_i64();
6546 gen_load_fpr64(ctx
, fp0
, fs
);
6547 gen_helper_float_roundl_d(fp0
, fp0
);
6548 gen_store_fpr64(ctx
, fp0
, fd
);
6549 tcg_temp_free_i64(fp0
);
6554 check_cp1_64bitmode(ctx
);
6556 TCGv_i64 fp0
= tcg_temp_new_i64();
6558 gen_load_fpr64(ctx
, fp0
, fs
);
6559 gen_helper_float_truncl_d(fp0
, fp0
);
6560 gen_store_fpr64(ctx
, fp0
, fd
);
6561 tcg_temp_free_i64(fp0
);
6566 check_cp1_64bitmode(ctx
);
6568 TCGv_i64 fp0
= tcg_temp_new_i64();
6570 gen_load_fpr64(ctx
, fp0
, fs
);
6571 gen_helper_float_ceill_d(fp0
, fp0
);
6572 gen_store_fpr64(ctx
, fp0
, fd
);
6573 tcg_temp_free_i64(fp0
);
6578 check_cp1_64bitmode(ctx
);
6580 TCGv_i64 fp0
= tcg_temp_new_i64();
6582 gen_load_fpr64(ctx
, fp0
, fs
);
6583 gen_helper_float_floorl_d(fp0
, fp0
);
6584 gen_store_fpr64(ctx
, fp0
, fd
);
6585 tcg_temp_free_i64(fp0
);
6590 check_cp1_registers(ctx
, fs
);
6592 TCGv_i32 fp32
= tcg_temp_new_i32();
6593 TCGv_i64 fp64
= tcg_temp_new_i64();
6595 gen_load_fpr64(ctx
, fp64
, fs
);
6596 gen_helper_float_roundw_d(fp32
, fp64
);
6597 tcg_temp_free_i64(fp64
);
6598 gen_store_fpr32(fp32
, fd
);
6599 tcg_temp_free_i32(fp32
);
6604 check_cp1_registers(ctx
, fs
);
6606 TCGv_i32 fp32
= tcg_temp_new_i32();
6607 TCGv_i64 fp64
= tcg_temp_new_i64();
6609 gen_load_fpr64(ctx
, fp64
, fs
);
6610 gen_helper_float_truncw_d(fp32
, fp64
);
6611 tcg_temp_free_i64(fp64
);
6612 gen_store_fpr32(fp32
, fd
);
6613 tcg_temp_free_i32(fp32
);
6618 check_cp1_registers(ctx
, fs
);
6620 TCGv_i32 fp32
= tcg_temp_new_i32();
6621 TCGv_i64 fp64
= tcg_temp_new_i64();
6623 gen_load_fpr64(ctx
, fp64
, fs
);
6624 gen_helper_float_ceilw_d(fp32
, fp64
);
6625 tcg_temp_free_i64(fp64
);
6626 gen_store_fpr32(fp32
, fd
);
6627 tcg_temp_free_i32(fp32
);
6632 check_cp1_registers(ctx
, fs
);
6634 TCGv_i32 fp32
= tcg_temp_new_i32();
6635 TCGv_i64 fp64
= tcg_temp_new_i64();
6637 gen_load_fpr64(ctx
, fp64
, fs
);
6638 gen_helper_float_floorw_d(fp32
, fp64
);
6639 tcg_temp_free_i64(fp64
);
6640 gen_store_fpr32(fp32
, fd
);
6641 tcg_temp_free_i32(fp32
);
6646 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6651 int l1
= gen_new_label();
6655 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6657 fp0
= tcg_temp_new_i64();
6658 gen_load_fpr64(ctx
, fp0
, fs
);
6659 gen_store_fpr64(ctx
, fp0
, fd
);
6660 tcg_temp_free_i64(fp0
);
6667 int l1
= gen_new_label();
6671 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6672 fp0
= tcg_temp_new_i64();
6673 gen_load_fpr64(ctx
, fp0
, fs
);
6674 gen_store_fpr64(ctx
, fp0
, fd
);
6675 tcg_temp_free_i64(fp0
);
6682 check_cp1_64bitmode(ctx
);
6684 TCGv_i64 fp0
= tcg_temp_new_i64();
6686 gen_load_fpr64(ctx
, fp0
, fs
);
6687 gen_helper_float_recip_d(fp0
, fp0
);
6688 gen_store_fpr64(ctx
, fp0
, fd
);
6689 tcg_temp_free_i64(fp0
);
6694 check_cp1_64bitmode(ctx
);
6696 TCGv_i64 fp0
= tcg_temp_new_i64();
6698 gen_load_fpr64(ctx
, fp0
, fs
);
6699 gen_helper_float_rsqrt_d(fp0
, fp0
);
6700 gen_store_fpr64(ctx
, fp0
, fd
);
6701 tcg_temp_free_i64(fp0
);
6706 check_cp1_64bitmode(ctx
);
6708 TCGv_i64 fp0
= tcg_temp_new_i64();
6709 TCGv_i64 fp1
= tcg_temp_new_i64();
6711 gen_load_fpr64(ctx
, fp0
, fs
);
6712 gen_load_fpr64(ctx
, fp1
, ft
);
6713 gen_helper_float_recip2_d(fp0
, fp0
, fp1
);
6714 tcg_temp_free_i64(fp1
);
6715 gen_store_fpr64(ctx
, fp0
, fd
);
6716 tcg_temp_free_i64(fp0
);
6721 check_cp1_64bitmode(ctx
);
6723 TCGv_i64 fp0
= tcg_temp_new_i64();
6725 gen_load_fpr64(ctx
, fp0
, fs
);
6726 gen_helper_float_recip1_d(fp0
, fp0
);
6727 gen_store_fpr64(ctx
, fp0
, fd
);
6728 tcg_temp_free_i64(fp0
);
6733 check_cp1_64bitmode(ctx
);
6735 TCGv_i64 fp0
= tcg_temp_new_i64();
6737 gen_load_fpr64(ctx
, fp0
, fs
);
6738 gen_helper_float_rsqrt1_d(fp0
, fp0
);
6739 gen_store_fpr64(ctx
, fp0
, fd
);
6740 tcg_temp_free_i64(fp0
);
6745 check_cp1_64bitmode(ctx
);
6747 TCGv_i64 fp0
= tcg_temp_new_i64();
6748 TCGv_i64 fp1
= tcg_temp_new_i64();
6750 gen_load_fpr64(ctx
, fp0
, fs
);
6751 gen_load_fpr64(ctx
, fp1
, ft
);
6752 gen_helper_float_rsqrt2_d(fp0
, fp0
, fp1
);
6753 tcg_temp_free_i64(fp1
);
6754 gen_store_fpr64(ctx
, fp0
, fd
);
6755 tcg_temp_free_i64(fp0
);
6776 TCGv_i64 fp0
= tcg_temp_new_i64();
6777 TCGv_i64 fp1
= tcg_temp_new_i64();
6779 gen_load_fpr64(ctx
, fp0
, fs
);
6780 gen_load_fpr64(ctx
, fp1
, ft
);
6781 if (ctx
->opcode
& (1 << 6)) {
6783 check_cp1_registers(ctx
, fs
| ft
);
6784 gen_cmpabs_d(func
-48, fp0
, fp1
, cc
);
6785 opn
= condnames_abs
[func
-48];
6787 check_cp1_registers(ctx
, fs
| ft
);
6788 gen_cmp_d(func
-48, fp0
, fp1
, cc
);
6789 opn
= condnames
[func
-48];
6791 tcg_temp_free_i64(fp0
);
6792 tcg_temp_free_i64(fp1
);
6796 check_cp1_registers(ctx
, fs
);
6798 TCGv_i32 fp32
= tcg_temp_new_i32();
6799 TCGv_i64 fp64
= tcg_temp_new_i64();
6801 gen_load_fpr64(ctx
, fp64
, fs
);
6802 gen_helper_float_cvts_d(fp32
, fp64
);
6803 tcg_temp_free_i64(fp64
);
6804 gen_store_fpr32(fp32
, fd
);
6805 tcg_temp_free_i32(fp32
);
6810 check_cp1_registers(ctx
, fs
);
6812 TCGv_i32 fp32
= tcg_temp_new_i32();
6813 TCGv_i64 fp64
= tcg_temp_new_i64();
6815 gen_load_fpr64(ctx
, fp64
, fs
);
6816 gen_helper_float_cvtw_d(fp32
, fp64
);
6817 tcg_temp_free_i64(fp64
);
6818 gen_store_fpr32(fp32
, fd
);
6819 tcg_temp_free_i32(fp32
);
6824 check_cp1_64bitmode(ctx
);
6826 TCGv_i64 fp0
= tcg_temp_new_i64();
6828 gen_load_fpr64(ctx
, fp0
, fs
);
6829 gen_helper_float_cvtl_d(fp0
, fp0
);
6830 gen_store_fpr64(ctx
, fp0
, fd
);
6831 tcg_temp_free_i64(fp0
);
6837 TCGv_i32 fp0
= tcg_temp_new_i32();
6839 gen_load_fpr32(fp0
, fs
);
6840 gen_helper_float_cvts_w(fp0
, fp0
);
6841 gen_store_fpr32(fp0
, fd
);
6842 tcg_temp_free_i32(fp0
);
6847 check_cp1_registers(ctx
, fd
);
6849 TCGv_i32 fp32
= tcg_temp_new_i32();
6850 TCGv_i64 fp64
= tcg_temp_new_i64();
6852 gen_load_fpr32(fp32
, fs
);
6853 gen_helper_float_cvtd_w(fp64
, fp32
);
6854 tcg_temp_free_i32(fp32
);
6855 gen_store_fpr64(ctx
, fp64
, fd
);
6856 tcg_temp_free_i64(fp64
);
6861 check_cp1_64bitmode(ctx
);
6863 TCGv_i32 fp32
= tcg_temp_new_i32();
6864 TCGv_i64 fp64
= tcg_temp_new_i64();
6866 gen_load_fpr64(ctx
, fp64
, fs
);
6867 gen_helper_float_cvts_l(fp32
, fp64
);
6868 tcg_temp_free_i64(fp64
);
6869 gen_store_fpr32(fp32
, fd
);
6870 tcg_temp_free_i32(fp32
);
6875 check_cp1_64bitmode(ctx
);
6877 TCGv_i64 fp0
= tcg_temp_new_i64();
6879 gen_load_fpr64(ctx
, fp0
, fs
);
6880 gen_helper_float_cvtd_l(fp0
, fp0
);
6881 gen_store_fpr64(ctx
, fp0
, fd
);
6882 tcg_temp_free_i64(fp0
);
6887 check_cp1_64bitmode(ctx
);
6889 TCGv_i64 fp0
= tcg_temp_new_i64();
6891 gen_load_fpr64(ctx
, fp0
, fs
);
6892 gen_helper_float_cvtps_pw(fp0
, fp0
);
6893 gen_store_fpr64(ctx
, fp0
, fd
);
6894 tcg_temp_free_i64(fp0
);
6899 check_cp1_64bitmode(ctx
);
6901 TCGv_i64 fp0
= tcg_temp_new_i64();
6902 TCGv_i64 fp1
= tcg_temp_new_i64();
6904 gen_load_fpr64(ctx
, fp0
, fs
);
6905 gen_load_fpr64(ctx
, fp1
, ft
);
6906 gen_helper_float_add_ps(fp0
, fp0
, fp1
);
6907 tcg_temp_free_i64(fp1
);
6908 gen_store_fpr64(ctx
, fp0
, fd
);
6909 tcg_temp_free_i64(fp0
);
6914 check_cp1_64bitmode(ctx
);
6916 TCGv_i64 fp0
= tcg_temp_new_i64();
6917 TCGv_i64 fp1
= tcg_temp_new_i64();
6919 gen_load_fpr64(ctx
, fp0
, fs
);
6920 gen_load_fpr64(ctx
, fp1
, ft
);
6921 gen_helper_float_sub_ps(fp0
, fp0
, fp1
);
6922 tcg_temp_free_i64(fp1
);
6923 gen_store_fpr64(ctx
, fp0
, fd
);
6924 tcg_temp_free_i64(fp0
);
6929 check_cp1_64bitmode(ctx
);
6931 TCGv_i64 fp0
= tcg_temp_new_i64();
6932 TCGv_i64 fp1
= tcg_temp_new_i64();
6934 gen_load_fpr64(ctx
, fp0
, fs
);
6935 gen_load_fpr64(ctx
, fp1
, ft
);
6936 gen_helper_float_mul_ps(fp0
, fp0
, fp1
);
6937 tcg_temp_free_i64(fp1
);
6938 gen_store_fpr64(ctx
, fp0
, fd
);
6939 tcg_temp_free_i64(fp0
);
6944 check_cp1_64bitmode(ctx
);
6946 TCGv_i64 fp0
= tcg_temp_new_i64();
6948 gen_load_fpr64(ctx
, fp0
, fs
);
6949 gen_helper_float_abs_ps(fp0
, fp0
);
6950 gen_store_fpr64(ctx
, fp0
, fd
);
6951 tcg_temp_free_i64(fp0
);
6956 check_cp1_64bitmode(ctx
);
6958 TCGv_i64 fp0
= tcg_temp_new_i64();
6960 gen_load_fpr64(ctx
, fp0
, fs
);
6961 gen_store_fpr64(ctx
, fp0
, fd
);
6962 tcg_temp_free_i64(fp0
);
6967 check_cp1_64bitmode(ctx
);
6969 TCGv_i64 fp0
= tcg_temp_new_i64();
6971 gen_load_fpr64(ctx
, fp0
, fs
);
6972 gen_helper_float_chs_ps(fp0
, fp0
);
6973 gen_store_fpr64(ctx
, fp0
, fd
);
6974 tcg_temp_free_i64(fp0
);
6979 check_cp1_64bitmode(ctx
);
6980 gen_movcf_ps(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6984 check_cp1_64bitmode(ctx
);
6986 int l1
= gen_new_label();
6990 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6991 fp0
= tcg_temp_new_i64();
6992 gen_load_fpr64(ctx
, fp0
, fs
);
6993 gen_store_fpr64(ctx
, fp0
, fd
);
6994 tcg_temp_free_i64(fp0
);
7000 check_cp1_64bitmode(ctx
);
7002 int l1
= gen_new_label();
7006 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
7007 fp0
= tcg_temp_new_i64();
7008 gen_load_fpr64(ctx
, fp0
, fs
);
7009 gen_store_fpr64(ctx
, fp0
, fd
);
7010 tcg_temp_free_i64(fp0
);
7017 check_cp1_64bitmode(ctx
);
7019 TCGv_i64 fp0
= tcg_temp_new_i64();
7020 TCGv_i64 fp1
= tcg_temp_new_i64();
7022 gen_load_fpr64(ctx
, fp0
, ft
);
7023 gen_load_fpr64(ctx
, fp1
, fs
);
7024 gen_helper_float_addr_ps(fp0
, fp0
, fp1
);
7025 tcg_temp_free_i64(fp1
);
7026 gen_store_fpr64(ctx
, fp0
, fd
);
7027 tcg_temp_free_i64(fp0
);
7032 check_cp1_64bitmode(ctx
);
7034 TCGv_i64 fp0
= tcg_temp_new_i64();
7035 TCGv_i64 fp1
= tcg_temp_new_i64();
7037 gen_load_fpr64(ctx
, fp0
, ft
);
7038 gen_load_fpr64(ctx
, fp1
, fs
);
7039 gen_helper_float_mulr_ps(fp0
, fp0
, fp1
);
7040 tcg_temp_free_i64(fp1
);
7041 gen_store_fpr64(ctx
, fp0
, fd
);
7042 tcg_temp_free_i64(fp0
);
7047 check_cp1_64bitmode(ctx
);
7049 TCGv_i64 fp0
= tcg_temp_new_i64();
7050 TCGv_i64 fp1
= tcg_temp_new_i64();
7052 gen_load_fpr64(ctx
, fp0
, fs
);
7053 gen_load_fpr64(ctx
, fp1
, fd
);
7054 gen_helper_float_recip2_ps(fp0
, fp0
, fp1
);
7055 tcg_temp_free_i64(fp1
);
7056 gen_store_fpr64(ctx
, fp0
, fd
);
7057 tcg_temp_free_i64(fp0
);
7062 check_cp1_64bitmode(ctx
);
7064 TCGv_i64 fp0
= tcg_temp_new_i64();
7066 gen_load_fpr64(ctx
, fp0
, fs
);
7067 gen_helper_float_recip1_ps(fp0
, fp0
);
7068 gen_store_fpr64(ctx
, fp0
, fd
);
7069 tcg_temp_free_i64(fp0
);
7074 check_cp1_64bitmode(ctx
);
7076 TCGv_i64 fp0
= tcg_temp_new_i64();
7078 gen_load_fpr64(ctx
, fp0
, fs
);
7079 gen_helper_float_rsqrt1_ps(fp0
, fp0
);
7080 gen_store_fpr64(ctx
, fp0
, fd
);
7081 tcg_temp_free_i64(fp0
);
7086 check_cp1_64bitmode(ctx
);
7088 TCGv_i64 fp0
= tcg_temp_new_i64();
7089 TCGv_i64 fp1
= tcg_temp_new_i64();
7091 gen_load_fpr64(ctx
, fp0
, fs
);
7092 gen_load_fpr64(ctx
, fp1
, ft
);
7093 gen_helper_float_rsqrt2_ps(fp0
, fp0
, fp1
);
7094 tcg_temp_free_i64(fp1
);
7095 gen_store_fpr64(ctx
, fp0
, fd
);
7096 tcg_temp_free_i64(fp0
);
7101 check_cp1_64bitmode(ctx
);
7103 TCGv_i32 fp0
= tcg_temp_new_i32();
7105 gen_load_fpr32h(fp0
, fs
);
7106 gen_helper_float_cvts_pu(fp0
, fp0
);
7107 gen_store_fpr32(fp0
, fd
);
7108 tcg_temp_free_i32(fp0
);
7113 check_cp1_64bitmode(ctx
);
7115 TCGv_i64 fp0
= tcg_temp_new_i64();
7117 gen_load_fpr64(ctx
, fp0
, fs
);
7118 gen_helper_float_cvtpw_ps(fp0
, fp0
);
7119 gen_store_fpr64(ctx
, fp0
, fd
);
7120 tcg_temp_free_i64(fp0
);
7125 check_cp1_64bitmode(ctx
);
7127 TCGv_i32 fp0
= tcg_temp_new_i32();
7129 gen_load_fpr32(fp0
, fs
);
7130 gen_helper_float_cvts_pl(fp0
, fp0
);
7131 gen_store_fpr32(fp0
, fd
);
7132 tcg_temp_free_i32(fp0
);
7137 check_cp1_64bitmode(ctx
);
7139 TCGv_i32 fp0
= tcg_temp_new_i32();
7140 TCGv_i32 fp1
= tcg_temp_new_i32();
7142 gen_load_fpr32(fp0
, fs
);
7143 gen_load_fpr32(fp1
, ft
);
7144 gen_store_fpr32h(fp0
, fd
);
7145 gen_store_fpr32(fp1
, fd
);
7146 tcg_temp_free_i32(fp0
);
7147 tcg_temp_free_i32(fp1
);
7152 check_cp1_64bitmode(ctx
);
7154 TCGv_i32 fp0
= tcg_temp_new_i32();
7155 TCGv_i32 fp1
= tcg_temp_new_i32();
7157 gen_load_fpr32(fp0
, fs
);
7158 gen_load_fpr32h(fp1
, ft
);
7159 gen_store_fpr32(fp1
, fd
);
7160 gen_store_fpr32h(fp0
, fd
);
7161 tcg_temp_free_i32(fp0
);
7162 tcg_temp_free_i32(fp1
);
7167 check_cp1_64bitmode(ctx
);
7169 TCGv_i32 fp0
= tcg_temp_new_i32();
7170 TCGv_i32 fp1
= tcg_temp_new_i32();
7172 gen_load_fpr32h(fp0
, fs
);
7173 gen_load_fpr32(fp1
, ft
);
7174 gen_store_fpr32(fp1
, fd
);
7175 gen_store_fpr32h(fp0
, fd
);
7176 tcg_temp_free_i32(fp0
);
7177 tcg_temp_free_i32(fp1
);
7182 check_cp1_64bitmode(ctx
);
7184 TCGv_i32 fp0
= tcg_temp_new_i32();
7185 TCGv_i32 fp1
= tcg_temp_new_i32();
7187 gen_load_fpr32h(fp0
, fs
);
7188 gen_load_fpr32h(fp1
, ft
);
7189 gen_store_fpr32(fp1
, fd
);
7190 gen_store_fpr32h(fp0
, fd
);
7191 tcg_temp_free_i32(fp0
);
7192 tcg_temp_free_i32(fp1
);
7212 check_cp1_64bitmode(ctx
);
7214 TCGv_i64 fp0
= tcg_temp_new_i64();
7215 TCGv_i64 fp1
= tcg_temp_new_i64();
7217 gen_load_fpr64(ctx
, fp0
, fs
);
7218 gen_load_fpr64(ctx
, fp1
, ft
);
7219 if (ctx
->opcode
& (1 << 6)) {
7220 gen_cmpabs_ps(func
-48, fp0
, fp1
, cc
);
7221 opn
= condnames_abs
[func
-48];
7223 gen_cmp_ps(func
-48, fp0
, fp1
, cc
);
7224 opn
= condnames
[func
-48];
7226 tcg_temp_free_i64(fp0
);
7227 tcg_temp_free_i64(fp1
);
7232 generate_exception (ctx
, EXCP_RI
);
7237 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
7240 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
7243 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
7248 /* Coprocessor 3 (FPU) */
7249 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
7250 int fd
, int fs
, int base
, int index
)
7252 const char *opn
= "extended float load/store";
7254 TCGv t0
= tcg_temp_new();
7257 gen_load_gpr(t0
, index
);
7258 } else if (index
== 0) {
7259 gen_load_gpr(t0
, base
);
7261 gen_load_gpr(t0
, index
);
7262 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
]);
7264 /* Don't do NOP if destination is zero: we must perform the actual
7266 save_cpu_state(ctx
, 0);
7271 TCGv_i32 fp0
= tcg_temp_new_i32();
7273 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
7274 tcg_gen_trunc_tl_i32(fp0
, t0
);
7275 gen_store_fpr32(fp0
, fd
);
7276 tcg_temp_free_i32(fp0
);
7282 check_cp1_registers(ctx
, fd
);
7284 TCGv_i64 fp0
= tcg_temp_new_i64();
7286 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7287 gen_store_fpr64(ctx
, fp0
, fd
);
7288 tcg_temp_free_i64(fp0
);
7293 check_cp1_64bitmode(ctx
);
7294 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7296 TCGv_i64 fp0
= tcg_temp_new_i64();
7298 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7299 gen_store_fpr64(ctx
, fp0
, fd
);
7300 tcg_temp_free_i64(fp0
);
7307 TCGv_i32 fp0
= tcg_temp_new_i32();
7308 TCGv t1
= tcg_temp_new();
7310 gen_load_fpr32(fp0
, fs
);
7311 tcg_gen_extu_i32_tl(t1
, fp0
);
7312 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
7313 tcg_temp_free_i32(fp0
);
7321 check_cp1_registers(ctx
, fs
);
7323 TCGv_i64 fp0
= tcg_temp_new_i64();
7325 gen_load_fpr64(ctx
, fp0
, fs
);
7326 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7327 tcg_temp_free_i64(fp0
);
7333 check_cp1_64bitmode(ctx
);
7334 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7336 TCGv_i64 fp0
= tcg_temp_new_i64();
7338 gen_load_fpr64(ctx
, fp0
, fs
);
7339 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7340 tcg_temp_free_i64(fp0
);
7347 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
7348 regnames
[index
], regnames
[base
]);
7351 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
7352 int fd
, int fr
, int fs
, int ft
)
7354 const char *opn
= "flt3_arith";
7358 check_cp1_64bitmode(ctx
);
7360 TCGv t0
= tcg_temp_local_new();
7361 TCGv_i32 fp
= tcg_temp_new_i32();
7362 TCGv_i32 fph
= tcg_temp_new_i32();
7363 int l1
= gen_new_label();
7364 int l2
= gen_new_label();
7366 gen_load_gpr(t0
, fr
);
7367 tcg_gen_andi_tl(t0
, t0
, 0x7);
7369 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7370 gen_load_fpr32(fp
, fs
);
7371 gen_load_fpr32h(fph
, fs
);
7372 gen_store_fpr32(fp
, fd
);
7373 gen_store_fpr32h(fph
, fd
);
7376 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7378 #ifdef TARGET_WORDS_BIGENDIAN
7379 gen_load_fpr32(fp
, fs
);
7380 gen_load_fpr32h(fph
, ft
);
7381 gen_store_fpr32h(fp
, fd
);
7382 gen_store_fpr32(fph
, fd
);
7384 gen_load_fpr32h(fph
, fs
);
7385 gen_load_fpr32(fp
, ft
);
7386 gen_store_fpr32(fph
, fd
);
7387 gen_store_fpr32h(fp
, fd
);
7390 tcg_temp_free_i32(fp
);
7391 tcg_temp_free_i32(fph
);
7398 TCGv_i32 fp0
= tcg_temp_new_i32();
7399 TCGv_i32 fp1
= tcg_temp_new_i32();
7400 TCGv_i32 fp2
= tcg_temp_new_i32();
7402 gen_load_fpr32(fp0
, fs
);
7403 gen_load_fpr32(fp1
, ft
);
7404 gen_load_fpr32(fp2
, fr
);
7405 gen_helper_float_muladd_s(fp2
, fp0
, fp1
, fp2
);
7406 tcg_temp_free_i32(fp0
);
7407 tcg_temp_free_i32(fp1
);
7408 gen_store_fpr32(fp2
, fd
);
7409 tcg_temp_free_i32(fp2
);
7415 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7417 TCGv_i64 fp0
= tcg_temp_new_i64();
7418 TCGv_i64 fp1
= tcg_temp_new_i64();
7419 TCGv_i64 fp2
= tcg_temp_new_i64();
7421 gen_load_fpr64(ctx
, fp0
, fs
);
7422 gen_load_fpr64(ctx
, fp1
, ft
);
7423 gen_load_fpr64(ctx
, fp2
, fr
);
7424 gen_helper_float_muladd_d(fp2
, fp0
, fp1
, fp2
);
7425 tcg_temp_free_i64(fp0
);
7426 tcg_temp_free_i64(fp1
);
7427 gen_store_fpr64(ctx
, fp2
, fd
);
7428 tcg_temp_free_i64(fp2
);
7433 check_cp1_64bitmode(ctx
);
7435 TCGv_i64 fp0
= tcg_temp_new_i64();
7436 TCGv_i64 fp1
= tcg_temp_new_i64();
7437 TCGv_i64 fp2
= tcg_temp_new_i64();
7439 gen_load_fpr64(ctx
, fp0
, fs
);
7440 gen_load_fpr64(ctx
, fp1
, ft
);
7441 gen_load_fpr64(ctx
, fp2
, fr
);
7442 gen_helper_float_muladd_ps(fp2
, fp0
, fp1
, fp2
);
7443 tcg_temp_free_i64(fp0
);
7444 tcg_temp_free_i64(fp1
);
7445 gen_store_fpr64(ctx
, fp2
, fd
);
7446 tcg_temp_free_i64(fp2
);
7453 TCGv_i32 fp0
= tcg_temp_new_i32();
7454 TCGv_i32 fp1
= tcg_temp_new_i32();
7455 TCGv_i32 fp2
= tcg_temp_new_i32();
7457 gen_load_fpr32(fp0
, fs
);
7458 gen_load_fpr32(fp1
, ft
);
7459 gen_load_fpr32(fp2
, fr
);
7460 gen_helper_float_mulsub_s(fp2
, fp0
, fp1
, fp2
);
7461 tcg_temp_free_i32(fp0
);
7462 tcg_temp_free_i32(fp1
);
7463 gen_store_fpr32(fp2
, fd
);
7464 tcg_temp_free_i32(fp2
);
7470 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7472 TCGv_i64 fp0
= tcg_temp_new_i64();
7473 TCGv_i64 fp1
= tcg_temp_new_i64();
7474 TCGv_i64 fp2
= tcg_temp_new_i64();
7476 gen_load_fpr64(ctx
, fp0
, fs
);
7477 gen_load_fpr64(ctx
, fp1
, ft
);
7478 gen_load_fpr64(ctx
, fp2
, fr
);
7479 gen_helper_float_mulsub_d(fp2
, fp0
, fp1
, fp2
);
7480 tcg_temp_free_i64(fp0
);
7481 tcg_temp_free_i64(fp1
);
7482 gen_store_fpr64(ctx
, fp2
, fd
);
7483 tcg_temp_free_i64(fp2
);
7488 check_cp1_64bitmode(ctx
);
7490 TCGv_i64 fp0
= tcg_temp_new_i64();
7491 TCGv_i64 fp1
= tcg_temp_new_i64();
7492 TCGv_i64 fp2
= tcg_temp_new_i64();
7494 gen_load_fpr64(ctx
, fp0
, fs
);
7495 gen_load_fpr64(ctx
, fp1
, ft
);
7496 gen_load_fpr64(ctx
, fp2
, fr
);
7497 gen_helper_float_mulsub_ps(fp2
, fp0
, fp1
, fp2
);
7498 tcg_temp_free_i64(fp0
);
7499 tcg_temp_free_i64(fp1
);
7500 gen_store_fpr64(ctx
, fp2
, fd
);
7501 tcg_temp_free_i64(fp2
);
7508 TCGv_i32 fp0
= tcg_temp_new_i32();
7509 TCGv_i32 fp1
= tcg_temp_new_i32();
7510 TCGv_i32 fp2
= tcg_temp_new_i32();
7512 gen_load_fpr32(fp0
, fs
);
7513 gen_load_fpr32(fp1
, ft
);
7514 gen_load_fpr32(fp2
, fr
);
7515 gen_helper_float_nmuladd_s(fp2
, fp0
, fp1
, fp2
);
7516 tcg_temp_free_i32(fp0
);
7517 tcg_temp_free_i32(fp1
);
7518 gen_store_fpr32(fp2
, fd
);
7519 tcg_temp_free_i32(fp2
);
7525 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7527 TCGv_i64 fp0
= tcg_temp_new_i64();
7528 TCGv_i64 fp1
= tcg_temp_new_i64();
7529 TCGv_i64 fp2
= tcg_temp_new_i64();
7531 gen_load_fpr64(ctx
, fp0
, fs
);
7532 gen_load_fpr64(ctx
, fp1
, ft
);
7533 gen_load_fpr64(ctx
, fp2
, fr
);
7534 gen_helper_float_nmuladd_d(fp2
, fp0
, fp1
, fp2
);
7535 tcg_temp_free_i64(fp0
);
7536 tcg_temp_free_i64(fp1
);
7537 gen_store_fpr64(ctx
, fp2
, fd
);
7538 tcg_temp_free_i64(fp2
);
7543 check_cp1_64bitmode(ctx
);
7545 TCGv_i64 fp0
= tcg_temp_new_i64();
7546 TCGv_i64 fp1
= tcg_temp_new_i64();
7547 TCGv_i64 fp2
= tcg_temp_new_i64();
7549 gen_load_fpr64(ctx
, fp0
, fs
);
7550 gen_load_fpr64(ctx
, fp1
, ft
);
7551 gen_load_fpr64(ctx
, fp2
, fr
);
7552 gen_helper_float_nmuladd_ps(fp2
, fp0
, fp1
, fp2
);
7553 tcg_temp_free_i64(fp0
);
7554 tcg_temp_free_i64(fp1
);
7555 gen_store_fpr64(ctx
, fp2
, fd
);
7556 tcg_temp_free_i64(fp2
);
7563 TCGv_i32 fp0
= tcg_temp_new_i32();
7564 TCGv_i32 fp1
= tcg_temp_new_i32();
7565 TCGv_i32 fp2
= tcg_temp_new_i32();
7567 gen_load_fpr32(fp0
, fs
);
7568 gen_load_fpr32(fp1
, ft
);
7569 gen_load_fpr32(fp2
, fr
);
7570 gen_helper_float_nmulsub_s(fp2
, fp0
, fp1
, fp2
);
7571 tcg_temp_free_i32(fp0
);
7572 tcg_temp_free_i32(fp1
);
7573 gen_store_fpr32(fp2
, fd
);
7574 tcg_temp_free_i32(fp2
);
7580 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7582 TCGv_i64 fp0
= tcg_temp_new_i64();
7583 TCGv_i64 fp1
= tcg_temp_new_i64();
7584 TCGv_i64 fp2
= tcg_temp_new_i64();
7586 gen_load_fpr64(ctx
, fp0
, fs
);
7587 gen_load_fpr64(ctx
, fp1
, ft
);
7588 gen_load_fpr64(ctx
, fp2
, fr
);
7589 gen_helper_float_nmulsub_d(fp2
, fp0
, fp1
, fp2
);
7590 tcg_temp_free_i64(fp0
);
7591 tcg_temp_free_i64(fp1
);
7592 gen_store_fpr64(ctx
, fp2
, fd
);
7593 tcg_temp_free_i64(fp2
);
7598 check_cp1_64bitmode(ctx
);
7600 TCGv_i64 fp0
= tcg_temp_new_i64();
7601 TCGv_i64 fp1
= tcg_temp_new_i64();
7602 TCGv_i64 fp2
= tcg_temp_new_i64();
7604 gen_load_fpr64(ctx
, fp0
, fs
);
7605 gen_load_fpr64(ctx
, fp1
, ft
);
7606 gen_load_fpr64(ctx
, fp2
, fr
);
7607 gen_helper_float_nmulsub_ps(fp2
, fp0
, fp1
, fp2
);
7608 tcg_temp_free_i64(fp0
);
7609 tcg_temp_free_i64(fp1
);
7610 gen_store_fpr64(ctx
, fp2
, fd
);
7611 tcg_temp_free_i64(fp2
);
7617 generate_exception (ctx
, EXCP_RI
);
7620 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
7621 fregnames
[fs
], fregnames
[ft
]);
7624 /* ISA extensions (ASEs) */
7625 /* MIPS16 extension to MIPS32 */
7626 /* SmartMIPS extension to MIPS32 */
7628 #if defined(TARGET_MIPS64)
7630 /* MDMX extension to MIPS64 */
7634 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
7638 uint32_t op
, op1
, op2
;
7641 /* make sure instructions are on a word boundary */
7642 if (ctx
->pc
& 0x3) {
7643 env
->CP0_BadVAddr
= ctx
->pc
;
7644 generate_exception(ctx
, EXCP_AdEL
);
7648 /* Handle blikely not taken case */
7649 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
7650 int l1
= gen_new_label();
7652 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
7653 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
7654 tcg_gen_movi_i32(hflags
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
7655 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
7658 op
= MASK_OP_MAJOR(ctx
->opcode
);
7659 rs
= (ctx
->opcode
>> 21) & 0x1f;
7660 rt
= (ctx
->opcode
>> 16) & 0x1f;
7661 rd
= (ctx
->opcode
>> 11) & 0x1f;
7662 sa
= (ctx
->opcode
>> 6) & 0x1f;
7663 imm
= (int16_t)ctx
->opcode
;
7666 op1
= MASK_SPECIAL(ctx
->opcode
);
7668 case OPC_SLL
: /* Shift with immediate */
7671 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7673 case OPC_MOVN
: /* Conditional move */
7675 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7676 gen_cond_move(env
, op1
, rd
, rs
, rt
);
7678 case OPC_ADD
... OPC_SUBU
:
7679 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7681 case OPC_SLLV
: /* Shifts */
7684 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
7686 case OPC_SLT
: /* Set on less than */
7688 gen_slt(env
, op1
, rd
, rs
, rt
);
7690 case OPC_AND
: /* Logic*/
7694 gen_logic(env
, op1
, rd
, rs
, rt
);
7696 case OPC_MULT
... OPC_DIVU
:
7698 check_insn(env
, ctx
, INSN_VR54XX
);
7699 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
7700 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
7702 gen_muldiv(ctx
, op1
, rs
, rt
);
7704 case OPC_JR
... OPC_JALR
:
7705 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
7707 case OPC_TGE
... OPC_TEQ
: /* Traps */
7709 gen_trap(ctx
, op1
, rs
, rt
, -1);
7711 case OPC_MFHI
: /* Move from HI/LO */
7713 gen_HILO(ctx
, op1
, rd
);
7716 case OPC_MTLO
: /* Move to HI/LO */
7717 gen_HILO(ctx
, op1
, rs
);
7719 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
7720 #ifdef MIPS_STRICT_STANDARD
7721 MIPS_INVAL("PMON / selsl");
7722 generate_exception(ctx
, EXCP_RI
);
7724 gen_helper_0i(pmon
, sa
);
7728 generate_exception(ctx
, EXCP_SYSCALL
);
7729 ctx
->bstate
= BS_STOP
;
7732 generate_exception(ctx
, EXCP_BREAK
);
7735 #ifdef MIPS_STRICT_STANDARD
7737 generate_exception(ctx
, EXCP_RI
);
7739 /* Implemented as RI exception for now. */
7740 MIPS_INVAL("spim (unofficial)");
7741 generate_exception(ctx
, EXCP_RI
);
7749 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7750 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7751 check_cp1_enabled(ctx
);
7752 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
7753 (ctx
->opcode
>> 16) & 1);
7755 generate_exception_err(ctx
, EXCP_CpU
, 1);
7759 #if defined(TARGET_MIPS64)
7760 /* MIPS64 specific opcodes */
7767 check_insn(env
, ctx
, ISA_MIPS3
);
7769 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7771 case OPC_DADD
... OPC_DSUBU
:
7772 check_insn(env
, ctx
, ISA_MIPS3
);
7774 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7779 check_insn(env
, ctx
, ISA_MIPS3
);
7781 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
7783 case OPC_DMULT
... OPC_DDIVU
:
7784 check_insn(env
, ctx
, ISA_MIPS3
);
7786 gen_muldiv(ctx
, op1
, rs
, rt
);
7789 default: /* Invalid */
7790 MIPS_INVAL("special");
7791 generate_exception(ctx
, EXCP_RI
);
7796 op1
= MASK_SPECIAL2(ctx
->opcode
);
7798 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
7799 case OPC_MSUB
... OPC_MSUBU
:
7800 check_insn(env
, ctx
, ISA_MIPS32
);
7801 gen_muldiv(ctx
, op1
, rs
, rt
);
7804 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7808 check_insn(env
, ctx
, ISA_MIPS32
);
7809 gen_cl(ctx
, op1
, rd
, rs
);
7812 /* XXX: not clear which exception should be raised
7813 * when in debug mode...
7815 check_insn(env
, ctx
, ISA_MIPS32
);
7816 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
7817 generate_exception(ctx
, EXCP_DBp
);
7819 generate_exception(ctx
, EXCP_DBp
);
7823 #if defined(TARGET_MIPS64)
7826 check_insn(env
, ctx
, ISA_MIPS64
);
7828 gen_cl(ctx
, op1
, rd
, rs
);
7831 default: /* Invalid */
7832 MIPS_INVAL("special2");
7833 generate_exception(ctx
, EXCP_RI
);
7838 op1
= MASK_SPECIAL3(ctx
->opcode
);
7842 check_insn(env
, ctx
, ISA_MIPS32R2
);
7843 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7846 check_insn(env
, ctx
, ISA_MIPS32R2
);
7847 op2
= MASK_BSHFL(ctx
->opcode
);
7848 gen_bshfl(ctx
, op2
, rt
, rd
);
7851 check_insn(env
, ctx
, ISA_MIPS32R2
);
7853 TCGv t0
= tcg_temp_new();
7857 save_cpu_state(ctx
, 1);
7858 gen_helper_rdhwr_cpunum(t0
);
7859 gen_store_gpr(t0
, rt
);
7862 save_cpu_state(ctx
, 1);
7863 gen_helper_rdhwr_synci_step(t0
);
7864 gen_store_gpr(t0
, rt
);
7867 save_cpu_state(ctx
, 1);
7868 gen_helper_rdhwr_cc(t0
);
7869 gen_store_gpr(t0
, rt
);
7872 save_cpu_state(ctx
, 1);
7873 gen_helper_rdhwr_ccres(t0
);
7874 gen_store_gpr(t0
, rt
);
7877 #if defined(CONFIG_USER_ONLY)
7878 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
7879 gen_store_gpr(t0
, rt
);
7882 /* XXX: Some CPUs implement this in hardware.
7883 Not supported yet. */
7885 default: /* Invalid */
7886 MIPS_INVAL("rdhwr");
7887 generate_exception(ctx
, EXCP_RI
);
7894 check_insn(env
, ctx
, ASE_MT
);
7896 TCGv t0
= tcg_temp_new();
7897 TCGv t1
= tcg_temp_new();
7899 gen_load_gpr(t0
, rt
);
7900 gen_load_gpr(t1
, rs
);
7901 gen_helper_fork(t0
, t1
);
7907 check_insn(env
, ctx
, ASE_MT
);
7909 TCGv t0
= tcg_temp_new();
7911 save_cpu_state(ctx
, 1);
7912 gen_load_gpr(t0
, rs
);
7913 gen_helper_yield(t0
, t0
);
7914 gen_store_gpr(t0
, rd
);
7918 #if defined(TARGET_MIPS64)
7919 case OPC_DEXTM
... OPC_DEXT
:
7920 case OPC_DINSM
... OPC_DINS
:
7921 check_insn(env
, ctx
, ISA_MIPS64R2
);
7923 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7926 check_insn(env
, ctx
, ISA_MIPS64R2
);
7928 op2
= MASK_DBSHFL(ctx
->opcode
);
7929 gen_bshfl(ctx
, op2
, rt
, rd
);
7932 default: /* Invalid */
7933 MIPS_INVAL("special3");
7934 generate_exception(ctx
, EXCP_RI
);
7939 op1
= MASK_REGIMM(ctx
->opcode
);
7941 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
7942 case OPC_BLTZAL
... OPC_BGEZALL
:
7943 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
7945 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
7947 gen_trap(ctx
, op1
, rs
, -1, imm
);
7950 check_insn(env
, ctx
, ISA_MIPS32R2
);
7953 default: /* Invalid */
7954 MIPS_INVAL("regimm");
7955 generate_exception(ctx
, EXCP_RI
);
7960 check_cp0_enabled(ctx
);
7961 op1
= MASK_CP0(ctx
->opcode
);
7967 #if defined(TARGET_MIPS64)
7971 #ifndef CONFIG_USER_ONLY
7972 gen_cp0(env
, ctx
, op1
, rt
, rd
);
7973 #endif /* !CONFIG_USER_ONLY */
7975 case OPC_C0_FIRST
... OPC_C0_LAST
:
7976 #ifndef CONFIG_USER_ONLY
7977 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
7978 #endif /* !CONFIG_USER_ONLY */
7981 #ifndef CONFIG_USER_ONLY
7983 TCGv t0
= tcg_temp_new();
7985 op2
= MASK_MFMC0(ctx
->opcode
);
7988 check_insn(env
, ctx
, ASE_MT
);
7989 gen_helper_dmt(t0
, t0
);
7990 gen_store_gpr(t0
, rt
);
7993 check_insn(env
, ctx
, ASE_MT
);
7994 gen_helper_emt(t0
, t0
);
7995 gen_store_gpr(t0
, rt
);
7998 check_insn(env
, ctx
, ASE_MT
);
7999 gen_helper_dvpe(t0
, t0
);
8000 gen_store_gpr(t0
, rt
);
8003 check_insn(env
, ctx
, ASE_MT
);
8004 gen_helper_evpe(t0
, t0
);
8005 gen_store_gpr(t0
, rt
);
8008 check_insn(env
, ctx
, ISA_MIPS32R2
);
8009 save_cpu_state(ctx
, 1);
8011 gen_store_gpr(t0
, rt
);
8012 /* Stop translation as we may have switched the execution mode */
8013 ctx
->bstate
= BS_STOP
;
8016 check_insn(env
, ctx
, ISA_MIPS32R2
);
8017 save_cpu_state(ctx
, 1);
8019 gen_store_gpr(t0
, rt
);
8020 /* Stop translation as we may have switched the execution mode */
8021 ctx
->bstate
= BS_STOP
;
8023 default: /* Invalid */
8024 MIPS_INVAL("mfmc0");
8025 generate_exception(ctx
, EXCP_RI
);
8030 #endif /* !CONFIG_USER_ONLY */
8033 check_insn(env
, ctx
, ISA_MIPS32R2
);
8034 gen_load_srsgpr(rt
, rd
);
8037 check_insn(env
, ctx
, ISA_MIPS32R2
);
8038 gen_store_srsgpr(rt
, rd
);
8042 generate_exception(ctx
, EXCP_RI
);
8046 case OPC_ADDI
: /* Arithmetic with immediate opcode */
8048 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8050 case OPC_SLTI
: /* Set on less than with immediate opcode */
8052 gen_slt_imm(env
, op
, rt
, rs
, imm
);
8054 case OPC_ANDI
: /* Arithmetic with immediate opcode */
8058 gen_logic_imm(env
, op
, rt
, rs
, imm
);
8060 case OPC_J
... OPC_JAL
: /* Jump */
8061 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
8062 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
8064 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
8065 case OPC_BEQL
... OPC_BGTZL
:
8066 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
8068 case OPC_LB
... OPC_LWR
: /* Load and stores */
8069 case OPC_SB
... OPC_SW
:
8072 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8075 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
8078 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
8082 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
8086 /* Floating point (COP1). */
8091 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8092 check_cp1_enabled(ctx
);
8093 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
8095 generate_exception_err(ctx
, EXCP_CpU
, 1);
8100 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8101 check_cp1_enabled(ctx
);
8102 op1
= MASK_CP1(ctx
->opcode
);
8106 check_insn(env
, ctx
, ISA_MIPS32R2
);
8111 gen_cp1(ctx
, op1
, rt
, rd
);
8113 #if defined(TARGET_MIPS64)
8116 check_insn(env
, ctx
, ISA_MIPS3
);
8117 gen_cp1(ctx
, op1
, rt
, rd
);
8123 check_insn(env
, ctx
, ASE_MIPS3D
);
8126 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
8127 (rt
>> 2) & 0x7, imm
<< 2);
8134 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
8139 generate_exception (ctx
, EXCP_RI
);
8143 generate_exception_err(ctx
, EXCP_CpU
, 1);
8153 /* COP2: Not implemented. */
8154 generate_exception_err(ctx
, EXCP_CpU
, 2);
8158 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8159 check_cp1_enabled(ctx
);
8160 op1
= MASK_CP3(ctx
->opcode
);
8168 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
8186 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
8190 generate_exception (ctx
, EXCP_RI
);
8194 generate_exception_err(ctx
, EXCP_CpU
, 1);
8198 #if defined(TARGET_MIPS64)
8199 /* MIPS64 opcodes */
8201 case OPC_LDL
... OPC_LDR
:
8202 case OPC_SDL
... OPC_SDR
:
8206 check_insn(env
, ctx
, ISA_MIPS3
);
8208 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8211 check_insn(env
, ctx
, ISA_MIPS3
);
8213 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
8217 check_insn(env
, ctx
, ISA_MIPS3
);
8219 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8223 check_insn(env
, ctx
, ASE_MIPS16
);
8224 /* MIPS16: Not implemented. */
8226 check_insn(env
, ctx
, ASE_MDMX
);
8227 /* MDMX: Not implemented. */
8228 default: /* Invalid */
8229 MIPS_INVAL("major opcode");
8230 generate_exception(ctx
, EXCP_RI
);
8233 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
8234 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
8235 /* Branches completion */
8236 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
8237 ctx
->bstate
= BS_BRANCH
;
8238 save_cpu_state(ctx
, 0);
8239 /* FIXME: Need to clear can_do_io. */
8242 /* unconditional branch */
8243 MIPS_DEBUG("unconditional branch");
8244 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8247 /* blikely taken case */
8248 MIPS_DEBUG("blikely branch taken");
8249 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8252 /* Conditional branch */
8253 MIPS_DEBUG("conditional branch");
8255 int l1
= gen_new_label();
8257 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
8258 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
8260 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8264 /* unconditional branch to register */
8265 MIPS_DEBUG("branch to register");
8266 tcg_gen_mov_tl(cpu_PC
, btarget
);
8270 MIPS_DEBUG("unknown branch");
8277 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
8281 target_ulong pc_start
;
8282 uint16_t *gen_opc_end
;
8289 qemu_log("search pc %d\n", search_pc
);
8292 /* Leave some spare opc slots for branch handling. */
8293 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
- 16;
8297 ctx
.bstate
= BS_NONE
;
8298 /* Restore delay slot state from the tb context. */
8299 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
8300 restore_cpu_state(env
, &ctx
);
8301 #ifdef CONFIG_USER_ONLY
8302 ctx
.mem_idx
= MIPS_HFLAG_UM
;
8304 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
8307 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8309 max_insns
= CF_COUNT_MASK
;
8311 qemu_log_mask(CPU_LOG_TB_CPU
, "------------------------------------------------\n");
8312 /* FIXME: This may print out stale hflags from env... */
8313 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
8315 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb
, ctx
.mem_idx
, ctx
.hflags
);
8317 while (ctx
.bstate
== BS_NONE
) {
8318 if (unlikely(!TAILQ_EMPTY(&env
->breakpoints
))) {
8319 TAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8320 if (bp
->pc
== ctx
.pc
) {
8321 save_cpu_state(&ctx
, 1);
8322 ctx
.bstate
= BS_BRANCH
;
8323 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8324 /* Include the breakpoint location or the tb won't
8325 * be flushed when it must be. */
8327 goto done_generating
;
8333 j
= gen_opc_ptr
- gen_opc_buf
;
8337 gen_opc_instr_start
[lj
++] = 0;
8339 gen_opc_pc
[lj
] = ctx
.pc
;
8340 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
8341 gen_opc_instr_start
[lj
] = 1;
8342 gen_opc_icount
[lj
] = num_insns
;
8344 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8346 ctx
.opcode
= ldl_code(ctx
.pc
);
8347 decode_opc(env
, &ctx
);
8351 if (env
->singlestep_enabled
)
8354 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
8357 if (gen_opc_ptr
>= gen_opc_end
)
8360 if (num_insns
>= max_insns
)
8366 if (tb
->cflags
& CF_LAST_IO
)
8368 if (env
->singlestep_enabled
) {
8369 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
8370 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8372 switch (ctx
.bstate
) {
8374 gen_helper_interrupt_restart();
8375 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8378 save_cpu_state(&ctx
, 0);
8379 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8382 gen_helper_interrupt_restart();
8391 gen_icount_end(tb
, num_insns
);
8392 *gen_opc_ptr
= INDEX_op_end
;
8394 j
= gen_opc_ptr
- gen_opc_buf
;
8397 gen_opc_instr_start
[lj
++] = 0;
8399 tb
->size
= ctx
.pc
- pc_start
;
8400 tb
->icount
= num_insns
;
8404 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8405 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8406 log_target_disas(pc_start
, ctx
.pc
- pc_start
, 0);
8409 qemu_log_mask(CPU_LOG_TB_CPU
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
8413 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
8415 gen_intermediate_code_internal(env
, tb
, 0);
8418 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
8420 gen_intermediate_code_internal(env
, tb
, 1);
8423 static void fpu_dump_state(CPUState
*env
, FILE *f
,
8424 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8428 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
8430 #define printfpr(fp) \
8433 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
8434 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
8435 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
8438 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
8439 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
8440 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
8441 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
8442 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
8447 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
8448 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
, env
->active_fpu
.fp_status
,
8449 get_float_exception_flags(&env
->active_fpu
.fp_status
));
8450 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
8451 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
8452 printfpr(&env
->active_fpu
.fpr
[i
]);
8458 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8459 /* Debug help: The architecture requires 32bit code to maintain proper
8460 sign-extended values on 64bit machines. */
8462 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
8465 cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
8466 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8471 if (!SIGN_EXT_P(env
->active_tc
.PC
))
8472 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
8473 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
8474 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
8475 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
8476 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
8477 if (!SIGN_EXT_P(env
->btarget
))
8478 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
8480 for (i
= 0; i
< 32; i
++) {
8481 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
8482 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
8485 if (!SIGN_EXT_P(env
->CP0_EPC
))
8486 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
8487 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
8488 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
8492 void cpu_dump_state (CPUState
*env
, FILE *f
,
8493 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8498 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
8499 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
8500 env
->hflags
, env
->btarget
, env
->bcond
);
8501 for (i
= 0; i
< 32; i
++) {
8503 cpu_fprintf(f
, "GPR%02d:", i
);
8504 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
8506 cpu_fprintf(f
, "\n");
8509 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
8510 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
8511 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
8512 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
8513 if (env
->hflags
& MIPS_HFLAG_FPU
)
8514 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
8515 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8516 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
8520 static void mips_tcg_init(void)
8525 /* Initialize various static tables. */
8529 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
8530 TCGV_UNUSED(cpu_gpr
[0]);
8531 for (i
= 1; i
< 32; i
++)
8532 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
8533 offsetof(CPUState
, active_tc
.gpr
[i
]),
8535 cpu_PC
= tcg_global_mem_new(TCG_AREG0
,
8536 offsetof(CPUState
, active_tc
.PC
), "PC");
8537 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
8538 cpu_HI
[i
] = tcg_global_mem_new(TCG_AREG0
,
8539 offsetof(CPUState
, active_tc
.HI
[i
]),
8541 cpu_LO
[i
] = tcg_global_mem_new(TCG_AREG0
,
8542 offsetof(CPUState
, active_tc
.LO
[i
]),
8544 cpu_ACX
[i
] = tcg_global_mem_new(TCG_AREG0
,
8545 offsetof(CPUState
, active_tc
.ACX
[i
]),
8548 cpu_dspctrl
= tcg_global_mem_new(TCG_AREG0
,
8549 offsetof(CPUState
, active_tc
.DSPControl
),
8551 bcond
= tcg_global_mem_new(TCG_AREG0
,
8552 offsetof(CPUState
, bcond
), "bcond");
8553 btarget
= tcg_global_mem_new(TCG_AREG0
,
8554 offsetof(CPUState
, btarget
), "btarget");
8555 hflags
= tcg_global_mem_new_i32(TCG_AREG0
,
8556 offsetof(CPUState
, hflags
), "hflags");
8558 fpu_fcr0
= tcg_global_mem_new_i32(TCG_AREG0
,
8559 offsetof(CPUState
, active_fpu
.fcr0
),
8561 fpu_fcr31
= tcg_global_mem_new_i32(TCG_AREG0
,
8562 offsetof(CPUState
, active_fpu
.fcr31
),
8565 /* register helpers */
8566 #define GEN_HELPER 2
8572 #include "translate_init.c"
8574 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
8577 const mips_def_t
*def
;
8579 def
= cpu_mips_find_by_name(cpu_model
);
8582 env
= qemu_mallocz(sizeof(CPUMIPSState
));
8583 env
->cpu_model
= def
;
8586 env
->cpu_model_str
= cpu_model
;
8589 qemu_init_vcpu(env
);
8593 void cpu_reset (CPUMIPSState
*env
)
8595 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
8596 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
8597 log_cpu_state(env
, 0);
8600 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
8605 #if defined(CONFIG_USER_ONLY)
8606 env
->hflags
= MIPS_HFLAG_UM
;
8607 /* Enable access to the SYNCI_Step register. */
8608 env
->CP0_HWREna
|= (1 << 1);
8610 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
8611 /* If the exception was raised from a delay slot,
8612 come back to the jump. */
8613 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
8615 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
8617 env
->active_tc
.PC
= (int32_t)0xBFC00000;
8619 /* SMP not implemented */
8620 env
->CP0_EBase
= 0x80000000;
8621 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
8622 /* vectored interrupts not implemented, timer on int 7,
8623 no performance counters. */
8624 env
->CP0_IntCtl
= 0xe0000000;
8628 for (i
= 0; i
< 7; i
++) {
8629 env
->CP0_WatchLo
[i
] = 0;
8630 env
->CP0_WatchHi
[i
] = 0x80000000;
8632 env
->CP0_WatchLo
[7] = 0;
8633 env
->CP0_WatchHi
[7] = 0;
8635 /* Count register increments in debug mode, EJTAG version 1 */
8636 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
8637 env
->hflags
= MIPS_HFLAG_CP0
;
8639 env
->exception_index
= EXCP_NONE
;
8640 cpu_mips_register(env
, env
->cpu_model
);
8643 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
8644 unsigned long searched_pc
, int pc_pos
, void *puc
)
8646 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
8647 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
8648 env
->hflags
|= gen_opc_hflags
[pc_pos
];