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bios: Fix MADT table creation
[qemu-kvm/fedora.git] / kvm / bios / rombios32.c
blobcdae363b3605cb7ffbdda339bf0ed6b3320dcf75
1 /////////////////////////////////////////////////////////////////////////
2 // $Id: rombios32.c,v 1.11 2007/08/03 13:56:13 vruppert Exp $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // 32 bit Bochs BIOS init code
6 // Copyright (C) 2006 Fabrice Bellard
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <stdarg.h>
22 #include <stddef.h>
23
24 #include "rombios.h"
25
26 typedef signed char int8_t;
27 typedef short int16_t;
28 typedef int int32_t;
29 typedef long long int64_t;
30 typedef unsigned char uint8_t;
31 typedef unsigned short uint16_t;
32 typedef unsigned int uint32_t;
33 typedef unsigned long long uint64_t;
34
35 /* if true, put the MP float table and ACPI RSDT in EBDA and the MP
36 table in RAM. Unfortunately, Linux has bugs with that, so we prefer
37 to modify the BIOS in shadow RAM */
38 //#define BX_USE_EBDA_TABLES
39
40 /* define it if the (emulated) hardware supports SMM mode */
41 //#define BX_USE_SMM
42
43 #define cpuid(index, eax, ebx, ecx, edx) \
44 asm volatile ("cpuid" \
45 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
46 : "0" (index))
47
48 #define wbinvd() asm volatile("wbinvd")
49
50 #define CPUID_MSR (1 << 5)
51 #define CPUID_APIC (1 << 9)
52 #define CPUID_MTRR (1 << 12)
53
54 #define APIC_BASE ((uint8_t *)0xfee00000)
55 #define APIC_ICR_LOW 0x300
56 #define APIC_SVR 0x0F0
57 #define APIC_ID 0x020
58 #define APIC_LVT3 0x370
59
60 /* IRQs 5,9,10,11 */
61 #define PCI_ISA_IRQ_MASK 0x0e20U
62
63 #define APIC_ENABLED 0x0100
64
65 #define AP_BOOT_ADDR 0x9f000
66
67 #define MPTABLE_MAX_SIZE 0x00002000
68 #define SMI_CMD_IO_ADDR 0xb2
69
70 #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
71
72 #define MSR_MTRRcap 0x000000fe
73 #define MSR_MTRRfix64K_00000 0x00000250
74 #define MSR_MTRRfix16K_80000 0x00000258
75 #define MSR_MTRRfix16K_A0000 0x00000259
76 #define MSR_MTRRfix4K_C0000 0x00000268
77 #define MSR_MTRRfix4K_C8000 0x00000269
78 #define MSR_MTRRfix4K_D0000 0x0000026a
79 #define MSR_MTRRfix4K_D8000 0x0000026b
80 #define MSR_MTRRfix4K_E0000 0x0000026c
81 #define MSR_MTRRfix4K_E8000 0x0000026d
82 #define MSR_MTRRfix4K_F0000 0x0000026e
83 #define MSR_MTRRfix4K_F8000 0x0000026f
84 #define MSR_MTRRdefType 0x000002ff
85
86 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
87 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
88
89 #define MAX_INT_OVERRIDES 16
90
91 static inline void outl(int addr, int val)
92 {
93 asm volatile ("outl %1, %w0" : : "d" (addr), "a" (val));
94 }
95
96 static inline void outw(int addr, int val)
97 {
98 asm volatile ("outw %w1, %w0" : : "d" (addr), "a" (val));
99 }
100
101 static inline void outb(int addr, int val)
102 {
103 asm volatile ("outb %b1, %w0" : : "d" (addr), "a" (val));
104 }
105
106 static inline uint32_t inl(int addr)
107 {
108 uint32_t val;
109 asm volatile ("inl %w1, %0" : "=a" (val) : "d" (addr));
110 return val;
111 }
112
113 static inline uint16_t inw(int addr)
114 {
115 uint16_t val;
116 asm volatile ("inw %w1, %w0" : "=a" (val) : "d" (addr));
117 return val;
118 }
119
120 static inline uint8_t inb(int addr)
121 {
122 uint8_t val;
123 asm volatile ("inb %w1, %b0" : "=a" (val) : "d" (addr));
124 return val;
125 }
126
127 static inline void writel(void *addr, uint32_t val)
128 {
129 *(volatile uint32_t *)addr = val;
130 }
131
132 static inline void writew(void *addr, uint16_t val)
133 {
134 *(volatile uint16_t *)addr = val;
135 }
136
137 static inline void writeb(void *addr, uint8_t val)
138 {
139 *(volatile uint8_t *)addr = val;
140 }
141
142 static inline uint32_t readl(const void *addr)
143 {
144 return *(volatile const uint32_t *)addr;
145 }
146
147 static inline uint16_t readw(const void *addr)
148 {
149 return *(volatile const uint16_t *)addr;
150 }
151
152 static inline uint8_t readb(const void *addr)
153 {
154 return *(volatile const uint8_t *)addr;
155 }
156
157 static inline void putc(int c)
158 {
159 outb(INFO_PORT, c);
160 }
161
162 static uint64_t rdmsr(unsigned index)
163 {
164 unsigned long long ret;
165
166 asm ("rdmsr" : "=A"(ret) : "c"(index));
167 return ret;
168 }
169
170 static void wrmsr(unsigned index, uint64_t val)
171 {
172 asm volatile ("wrmsr" : : "c"(index), "A"(val));
173 }
174
175 static inline int isdigit(int c)
176 {
177 return c >= '0' && c <= '9';
178 }
179
180 void *memset(void *d1, int val, size_t len)
181 {
182 uint8_t *d = d1;
183
184 while (len--) {
185 *d++ = val;
186 }
187 return d1;
188 }
189
190 void *memcpy(void *d1, const void *s1, size_t len)
191 {
192 uint8_t *d = d1;
193 const uint8_t *s = s1;
194
195 while (len--) {
196 *d++ = *s++;
197 }
198 return d1;
199 }
200
201 void *memmove(void *d1, const void *s1, size_t len)
202 {
203 uint8_t *d = d1;
204 const uint8_t *s = s1;
205
206 if (d <= s) {
207 while (len--) {
208 *d++ = *s++;
209 }
210 } else {
211 d += len;
212 s += len;
213 while (len--) {
214 *--d = *--s;
215 }
216 }
217 return d1;
218 }
219
220 int memcmp(const void *s1, const void *s2, size_t len)
221 {
222 const int8_t *p1 = s1;
223 const int8_t *p2 = s2;
224
225 while (len--) {
226 int r = *p1++ - *p2++;
227 if(r)
228 return r;
229 }
230
231 return 0;
232 }
233
234 size_t strlen(const char *s)
235 {
236 const char *s1;
237 for(s1 = s; *s1 != '\0'; s1++);
238 return s1 - s;
239 }
240
241 /* from BSD ppp sources */
242 int vsnprintf(char *buf, int buflen, const char *fmt, va_list args)
243 {
244 int c, i, n;
245 int width, prec, fillch;
246 int base, len, neg;
247 unsigned long val = 0;
248 const char *f;
249 char *str, *buf0;
250 char num[32];
251 static const char hexchars[] = "0123456789abcdef";
252
253 buf0 = buf;
254 --buflen;
255 while (buflen > 0) {
256 for (f = fmt; *f != '%' && *f != 0; ++f)
257 ;
258 if (f > fmt) {
259 len = f - fmt;
260 if (len > buflen)
261 len = buflen;
262 memcpy(buf, fmt, len);
263 buf += len;
264 buflen -= len;
265 fmt = f;
266 }
267 if (*fmt == 0)
268 break;
269 c = *++fmt;
270 width = prec = 0;
271 fillch = ' ';
272 if (c == '0') {
273 fillch = '0';
274 c = *++fmt;
275 }
276 if (c == '*') {
277 width = va_arg(args, int);
278 c = *++fmt;
279 } else {
280 while (isdigit(c)) {
281 width = width * 10 + c - '0';
282 c = *++fmt;
283 }
284 }
285 if (c == '.') {
286 c = *++fmt;
287 if (c == '*') {
288 prec = va_arg(args, int);
289 c = *++fmt;
290 } else {
291 while (isdigit(c)) {
292 prec = prec * 10 + c - '0';
293 c = *++fmt;
294 }
295 }
296 }
297 /* modifiers */
298 switch(c) {
299 case 'l':
300 c = *++fmt;
301 break;
302 default:
303 break;
304 }
305 str = 0;
306 base = 0;
307 neg = 0;
308 ++fmt;
309 switch (c) {
310 case 'd':
311 i = va_arg(args, int);
312 if (i < 0) {
313 neg = 1;
314 val = -i;
315 } else
316 val = i;
317 base = 10;
318 break;
319 case 'o':
320 val = va_arg(args, unsigned int);
321 base = 8;
322 break;
323 case 'x':
324 case 'X':
325 val = va_arg(args, unsigned int);
326 base = 16;
327 break;
328 case 'p':
329 val = (unsigned long) va_arg(args, void *);
330 base = 16;
331 neg = 2;
332 break;
333 case 's':
334 str = va_arg(args, char *);
335 break;
336 case 'c':
337 num[0] = va_arg(args, int);
338 num[1] = 0;
339 str = num;
340 break;
341 default:
342 *buf++ = '%';
343 if (c != '%')
344 --fmt; /* so %z outputs %z etc. */
345 --buflen;
346 continue;
347 }
348 if (base != 0) {
349 str = num + sizeof(num);
350 *--str = 0;
351 while (str > num + neg) {
352 *--str = hexchars[val % base];
353 val = val / base;
354 if (--prec <= 0 && val == 0)
355 break;
356 }
357 switch (neg) {
358 case 1:
359 *--str = '-';
360 break;
361 case 2:
362 *--str = 'x';
363 *--str = '0';
364 break;
365 }
366 len = num + sizeof(num) - 1 - str;
367 } else {
368 len = strlen(str);
369 if (prec > 0 && len > prec)
370 len = prec;
371 }
372 if (width > 0) {
373 if (width > buflen)
374 width = buflen;
375 if ((n = width - len) > 0) {
376 buflen -= n;
377 for (; n > 0; --n)
378 *buf++ = fillch;
379 }
380 }
381 if (len > buflen)
382 len = buflen;
383 memcpy(buf, str, len);
384 buf += len;
385 buflen -= len;
386 }
387 *buf = 0;
388 return buf - buf0;
389 }
390
391 int snprintf(char * buf, size_t size, const char *fmt, ...)
392 {
393 va_list args;
394 int i;
395
396 va_start(args, fmt);
397 i=vsnprintf(buf,size,fmt,args);
398 va_end(args);
399 return i;
400 }
401
402 void bios_printf(int flags, const char *fmt, ...)
403 {
404 va_list ap;
405 char buf[1024];
406 const char *s;
407
408 if ((flags & BIOS_PRINTF_DEBHALT) == BIOS_PRINTF_DEBHALT)
409 outb(PANIC_PORT2, 0x00);
410
411 va_start(ap, fmt);
412 vsnprintf(buf, sizeof(buf), fmt, ap);
413 s = buf;
414 while (*s)
415 putc(*s++);
416 va_end(ap);
417 }
418
419 void delay_ms(int n)
420 {
421 int i, j;
422 for(i = 0; i < n; i++) {
423 #ifdef BX_QEMU
424 /* approximative ! */
425 for(j = 0; j < 1000000; j++);
426 #else
427 {
428 int r1, r2;
429 j = 66;
430 r1 = inb(0x61) & 0x10;
431 do {
432 r2 = inb(0x61) & 0x10;
433 if (r1 != r2) {
434 j--;
435 r1 = r2;
436 }
437 } while (j > 0);
438 }
439 #endif
440 }
441 }
442
443 uint16_t smp_cpus;
444 uint32_t cpuid_signature;
445 uint32_t cpuid_features;
446 uint32_t cpuid_ext_features;
447 unsigned long ram_size;
448 uint64_t ram_end;
449 #ifdef BX_USE_EBDA_TABLES
450 unsigned long ebda_cur_addr;
451 #endif
452 int acpi_enabled;
453 uint32_t pm_io_base, smb_io_base;
454 int pm_sci_int;
455 unsigned long bios_table_cur_addr;
456 unsigned long bios_table_end_addr;
457
458 void init_smp_msrs(void)
459 {
460 *(uint32_t *)SMP_MSR_ADDR = 0;
461 }
462
463 static inline uint64_t le64_to_cpu(uint64_t x)
464 {
465 return x;
466 }
467
468 void wrmsr_smp(uint32_t index, uint64_t val)
469 {
470 static struct { uint32_t ecx, eax, edx; } *p = (void *)SMP_MSR_ADDR;
471
472 wrmsr(index, val);
473 p->ecx = index;
474 p->eax = val;
475 p->edx = val >> 32;
476 ++p;
477 p->ecx = 0;
478 }
479
480 #ifdef BX_QEMU
481 #define QEMU_CFG_CTL_PORT 0x510
482 #define QEMU_CFG_DATA_PORT 0x511
483 #define QEMU_CFG_SIGNATURE 0x00
484 #define QEMU_CFG_ID 0x01
485 #define QEMU_CFG_UUID 0x02
486 #define QEMU_CFG_NUMA 0x0D
487 #define QEMU_CFG_ARCH_LOCAL 0x8000
488 #define QEMU_CFG_ACPI_TABLES (QEMU_CFG_ARCH_LOCAL + 0)
489 #define QEMU_CFG_SMBIOS_ENTRIES (QEMU_CFG_ARCH_LOCAL + 1)
490
491 int qemu_cfg_port;
492
493 void qemu_cfg_select(int f)
494 {
495 outw(QEMU_CFG_CTL_PORT, f);
496 }
497
498 int qemu_cfg_port_probe()
499 {
500 char *sig = "QEMU";
501 int i;
502
503 qemu_cfg_select(QEMU_CFG_SIGNATURE);
504
505 for (i = 0; i < 4; i++)
506 if (inb(QEMU_CFG_DATA_PORT) != sig[i])
507 return 0;
508
509 return 1;
510 }
511
512 void qemu_cfg_read(uint8_t *buf, int len)
513 {
514 while (len--)
515 *(buf++) = inb(QEMU_CFG_DATA_PORT);
516 }
517
518 static uint16_t acpi_additional_tables(void)
519 {
520 uint16_t cnt;
521
522 qemu_cfg_select(QEMU_CFG_ACPI_TABLES);
523 qemu_cfg_read((uint8_t*)&cnt, sizeof(cnt));
524
525 return cnt;
526 }
527
528 static int acpi_load_table(int i, uint32_t addr, uint16_t *len)
529 {
530 qemu_cfg_read((uint8_t*)len, sizeof(*len));
531
532 if (!*len)
533 return -1;
534
535 qemu_cfg_read((uint8_t*)addr, *len);
536 return 0;
537 }
538
539 static uint16_t smbios_entries(void)
540 {
541 uint16_t cnt;
542
543 qemu_cfg_select(QEMU_CFG_SMBIOS_ENTRIES);
544 qemu_cfg_read((uint8_t*)&cnt, sizeof(cnt));
545
546 return cnt;
547 }
548
549 uint64_t qemu_cfg_get64 (void)
550 {
551 uint64_t ret;
552
553 qemu_cfg_read((uint8_t*)&ret, 8);
554 return le64_to_cpu(ret);
555 }
556 #endif
557
558 void cpu_probe(void)
559 {
560 uint32_t eax, ebx, ecx, edx;
561 cpuid(1, eax, ebx, ecx, edx);
562 cpuid_signature = eax;
563 cpuid_features = edx;
564 cpuid_ext_features = ecx;
565 }
566
567 static int cmos_readb(int addr)
568 {
569 outb(0x70, addr);
570 return inb(0x71);
571 }
572
573 void setup_mtrr(void)
574 {
575 int i, vcnt, fix, wc;
576 uint32_t mtrr_cap;
577 union {
578 uint8_t valb[8];
579 uint64_t val;
580 } u;
581
582 if (!(cpuid_features & CPUID_MTRR))
583 return;
584
585 if (!(cpuid_features & CPUID_MSR))
586 return;
587
588 mtrr_cap = rdmsr(MSR_MTRRcap);
589 vcnt = mtrr_cap & 0xff;
590 fix = mtrr_cap & 0x100;
591 wc = mtrr_cap & 0x400;
592 if (!vcnt || !fix)
593 return;
594
595 u.val = 0;
596 for (i = 0; i < 8; ++i)
597 if (ram_size >= 65536 * (i + 1))
598 u.valb[i] = 6;
599 wrmsr_smp(MSR_MTRRfix64K_00000, u.val);
600 u.val = 0;
601 for (i = 0; i < 8; ++i)
602 if (ram_size >= 65536 * 8 + 16384 * (i + 1))
603 u.valb[i] = 6;
604 wrmsr_smp(MSR_MTRRfix16K_80000, u.val);
605 wrmsr_smp(MSR_MTRRfix16K_A0000, 0);
606 wrmsr_smp(MSR_MTRRfix4K_C0000, 0);
607 wrmsr_smp(MSR_MTRRfix4K_C8000, 0);
608 wrmsr_smp(MSR_MTRRfix4K_D0000, 0);
609 wrmsr_smp(MSR_MTRRfix4K_D8000, 0);
610 wrmsr_smp(MSR_MTRRfix4K_E0000, 0);
611 wrmsr_smp(MSR_MTRRfix4K_E8000, 0);
612 wrmsr_smp(MSR_MTRRfix4K_F0000, 0);
613 wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
614 /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
615 wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
616 wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
617 wrmsr_smp(MSR_MTRRdefType, 0xc06);
618 }
619
620 void ram_probe(void)
621 {
622 if (cmos_readb(0x34) | cmos_readb(0x35))
623 ram_size = (cmos_readb(0x34) | (cmos_readb(0x35) << 8)) * 65536 +
624 16 * 1024 * 1024;
625 else
626 ram_size = (cmos_readb(0x17) | (cmos_readb(0x18) << 8)) * 1024;
627
628 if (cmos_readb(0x5b) | cmos_readb(0x5c) | cmos_readb(0x5d))
629 ram_end = (((uint64_t)cmos_readb(0x5b) << 16) |
630 ((uint64_t)cmos_readb(0x5c) << 24) |
631 ((uint64_t)cmos_readb(0x5d) << 32)) + (1ull << 32);
632 else
633 ram_end = ram_size;
634
635 BX_INFO("end of ram=%ldMB\n", ram_end >> 20);
636
637 BX_INFO("ram_size=0x%08lx\n", ram_size);
638 #ifdef BX_USE_EBDA_TABLES
639 ebda_cur_addr = ((*(uint16_t *)(0x40e)) << 4) + 0x380;
640 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
641 #endif
642 }
643
644 /****************************************************/
645 /* SMP probe */
646
647 extern uint8_t smp_ap_boot_code_start;
648 extern uint8_t smp_ap_boot_code_end;
649
650 /* find the number of CPUs by launching a SIPI to them */
651 void smp_probe(void)
652 {
653 uint32_t val, sipi_vector;
654
655 writew(&smp_cpus, 1);
656 if (cpuid_features & CPUID_APIC) {
657
658 /* enable local APIC */
659 val = readl(APIC_BASE + APIC_SVR);
660 val |= APIC_ENABLED;
661 writel(APIC_BASE + APIC_SVR, val);
662
663 /* copy AP boot code */
664 memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
665 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
666
667 /* broadcast SIPI */
668 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
669 sipi_vector = AP_BOOT_ADDR >> 12;
670 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
671
672 #ifndef BX_QEMU
673 delay_ms(10);
674 #else
675 while (cmos_readb(0x5f) + 1 != readw(&smp_cpus))
676 ;
677 #endif
678 }
679 BX_INFO("Found %d cpu(s)\n", readw(&smp_cpus));
680 }
681
682 /****************************************************/
683 /* PCI init */
684
685 #define PCI_ADDRESS_SPACE_MEM 0x00
686 #define PCI_ADDRESS_SPACE_IO 0x01
687 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
688
689 #define PCI_ROM_SLOT 6
690 #define PCI_NUM_REGIONS 7
691
692 #define PCI_DEVICES_MAX 64
693
694 #define PCI_VENDOR_ID 0x00 /* 16 bits */
695 #define PCI_DEVICE_ID 0x02 /* 16 bits */
696 #define PCI_COMMAND 0x04 /* 16 bits */
697 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
698 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
699 #define PCI_CLASS_DEVICE 0x0a /* Device class */
700 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
701 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
702 #define PCI_MIN_GNT 0x3e /* 8 bits */
703 #define PCI_MAX_LAT 0x3f /* 8 bits */
704
705 #define PCI_VENDOR_ID_INTEL 0x8086
706 #define PCI_DEVICE_ID_INTEL_82441 0x1237
707 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
708 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
709 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
710 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
711 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
712
713 #define PCI_VENDOR_ID_IBM 0x1014
714 #define PCI_VENDOR_ID_APPLE 0x106b
715
716 typedef struct PCIDevice {
717 int bus;
718 int devfn;
719 } PCIDevice;
720
721 static uint32_t pci_bios_io_addr;
722 static uint32_t pci_bios_mem_addr;
723 static uint32_t pci_bios_bigmem_addr;
724 /* host irqs corresponding to PCI irqs A-D */
725 static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
726 static PCIDevice i440_pcidev;
727
728 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
729 {
730 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
731 outl(0xcfc, val);
732 }
733
734 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
735 {
736 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
737 outw(0xcfc + (addr & 2), val);
738 }
739
740 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
741 {
742 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
743 outb(0xcfc + (addr & 3), val);
744 }
745
746 static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
747 {
748 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
749 return inl(0xcfc);
750 }
751
752 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
753 {
754 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
755 return inw(0xcfc + (addr & 2));
756 }
757
758 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
759 {
760 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
761 return inb(0xcfc + (addr & 3));
762 }
763
764 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
765 {
766 uint16_t cmd;
767 uint32_t ofs, old_addr;
768
769 if ( region_num == PCI_ROM_SLOT ) {
770 ofs = 0x30;
771 }else{
772 ofs = 0x10 + region_num * 4;
773 }
774
775 old_addr = pci_config_readl(d, ofs);
776
777 pci_config_writel(d, ofs, addr);
778 BX_INFO("region %d: 0x%08x\n", region_num, addr);
779
780 /* enable memory mappings */
781 cmd = pci_config_readw(d, PCI_COMMAND);
782 if ( region_num == PCI_ROM_SLOT )
783 cmd |= 2;
784 else if (old_addr & PCI_ADDRESS_SPACE_IO)
785 cmd |= 1;
786 else
787 cmd |= 2;
788 pci_config_writew(d, PCI_COMMAND, cmd);
789 }
790
791 /* return the global irq number corresponding to a given device irq
792 pin. We could also use the bus number to have a more precise
793 mapping. */
794 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
795 {
796 int slot_addend;
797 slot_addend = (pci_dev->devfn >> 3) - 1;
798 return (irq_num + slot_addend) & 3;
799 }
800
801 static void find_bios_table_area(void)
802 {
803 unsigned long addr;
804 for(addr = 0xf0000; addr < 0x100000; addr += 16) {
805 if (*(uint32_t *)addr == 0xaafb4442) {
806 bios_table_cur_addr = addr + 8;
807 bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
808 BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
809 bios_table_cur_addr, bios_table_end_addr);
810 return;
811 }
812 }
813 return;
814 }
815
816 static void bios_shadow_init(PCIDevice *d)
817 {
818 int v;
819
820 if (bios_table_cur_addr == 0)
821 return;
822
823 /* remap the BIOS to shadow RAM an keep it read/write while we
824 are writing tables */
825 v = pci_config_readb(d, 0x59);
826 v &= 0xcf;
827 pci_config_writeb(d, 0x59, v);
828 memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
829 v |= 0x30;
830 pci_config_writeb(d, 0x59, v);
831 memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
832
833 i440_pcidev = *d;
834 }
835
836 static void bios_lock_shadow_ram(void)
837 {
838 PCIDevice *d = &i440_pcidev;
839 int v;
840
841 wbinvd();
842 v = pci_config_readb(d, 0x59);
843 v = (v & 0x0f) | (0x10);
844 pci_config_writeb(d, 0x59, v);
845 }
846
847 static void pci_bios_init_bridges(PCIDevice *d)
848 {
849 uint16_t vendor_id, device_id;
850
851 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
852 device_id = pci_config_readw(d, PCI_DEVICE_ID);
853
854 if (vendor_id == PCI_VENDOR_ID_INTEL &&
855 (device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
856 device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
857 int i, irq;
858 uint8_t elcr[2];
859
860 /* PIIX3/PIIX4 PCI to ISA bridge */
861
862 elcr[0] = 0x00;
863 elcr[1] = 0x00;
864 for(i = 0; i < 4; i++) {
865 irq = pci_irqs[i];
866 /* set to trigger level */
867 elcr[irq >> 3] |= (1 << (irq & 7));
868 /* activate irq remapping in PIIX */
869 pci_config_writeb(d, 0x60 + i, irq);
870 }
871 outb(0x4d0, elcr[0]);
872 outb(0x4d1, elcr[1]);
873 BX_INFO("PIIX3/PIIX4 init: elcr=%02x %02x\n",
874 elcr[0], elcr[1]);
875 } else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
876 /* i440 PCI bridge */
877 bios_shadow_init(d);
878 }
879 }
880
881 extern uint8_t smm_relocation_start, smm_relocation_end;
882 extern uint8_t smm_code_start, smm_code_end;
883
884 #ifdef BX_USE_SMM
885 static void smm_init(PCIDevice *d)
886 {
887 uint32_t value;
888
889 /* check if SMM init is already done */
890 value = pci_config_readl(d, 0x58);
891 if ((value & (1 << 25)) == 0) {
892
893 /* enable the SMM memory window */
894 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
895
896 /* save original memory content */
897 memcpy((void *)0xa8000, (void *)0x38000, 0x8000);
898
899 /* copy the SMM relocation code */
900 memcpy((void *)0x38000, &smm_relocation_start,
901 &smm_relocation_end - &smm_relocation_start);
902
903 /* enable SMI generation when writing to the APMC register */
904 pci_config_writel(d, 0x58, value | (1 << 25));
905
906 /* init APM status port */
907 outb(0xb3, 0x01);
908
909 /* raise an SMI interrupt */
910 outb(0xb2, 0x00);
911
912 /* wait until SMM code executed */
913 while (inb(0xb3) != 0x00);
914
915 /* restore original memory content */
916 memcpy((void *)0x38000, (void *)0xa8000, 0x8000);
917
918 /* copy the SMM code */
919 memcpy((void *)0xa8000, &smm_code_start,
920 &smm_code_end - &smm_code_start);
921 wbinvd();
922
923 /* close the SMM memory window and enable normal SMM */
924 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
925 }
926 }
927 #endif
928
929 static void piix4_pm_enable(PCIDevice *d)
930 {
931 /* PIIX4 Power Management device (for ACPI) */
932 pci_config_writel(d, 0x40, PM_IO_BASE | 1);
933 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
934 pci_config_writel(d, 0x90, SMB_IO_BASE | 1);
935 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
936 #ifdef BX_USE_SMM
937 smm_init(d);
938 #endif
939 }
940
941 static void pci_bios_init_device(PCIDevice *d)
942 {
943 int class;
944 uint32_t *paddr;
945 int i, pin, pic_irq, vendor_id, device_id;
946
947 class = pci_config_readw(d, PCI_CLASS_DEVICE);
948 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
949 device_id = pci_config_readw(d, PCI_DEVICE_ID);
950 BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x class=0x%04x\n",
951 d->bus, d->devfn, vendor_id, device_id, class);
952 switch(class) {
953 case 0x0101: /* Mass storage controller - IDE interface */
954 if (vendor_id == PCI_VENDOR_ID_INTEL &&
955 (device_id == PCI_DEVICE_ID_INTEL_82371SB_1 ||
956 device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
957 /* PIIX3/PIIX4 IDE */
958 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
959 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
960 goto default_map;
961 } else {
962 /* IDE: we map it as in ISA mode */
963 pci_set_io_region_addr(d, 0, 0x1f0);
964 pci_set_io_region_addr(d, 1, 0x3f4);
965 pci_set_io_region_addr(d, 2, 0x170);
966 pci_set_io_region_addr(d, 3, 0x374);
967 }
968 break;
969 case 0x0300: /* Display controller - VGA compatible controller */
970 if (vendor_id != 0x1234)
971 goto default_map;
972 /* VGA: map frame buffer to default Bochs VBE address */
973 pci_set_io_region_addr(d, 0, 0xE0000000);
974 break;
975 case 0x0800: /* Generic system peripheral - PIC */
976 if (vendor_id == PCI_VENDOR_ID_IBM) {
977 /* IBM */
978 if (device_id == 0x0046 || device_id == 0xFFFF) {
979 /* MPIC & MPIC2 */
980 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
981 }
982 }
983 break;
984 case 0xff00:
985 if (vendor_id == PCI_VENDOR_ID_APPLE &&
986 (device_id == 0x0017 || device_id == 0x0022)) {
987 /* macio bridge */
988 pci_set_io_region_addr(d, 0, 0x80800000);
989 }
990 break;
991 default:
992 default_map:
993 /* default memory mappings */
994 for(i = 0; i < PCI_NUM_REGIONS; i++) {
995 int ofs;
996 uint32_t val, size ;
997
998 if (i == PCI_ROM_SLOT)
999 ofs = 0x30;
1000 else
1001 ofs = 0x10 + i * 4;
1002 pci_config_writel(d, ofs, 0xffffffff);
1003 val = pci_config_readl(d, ofs);
1004 if (val != 0) {
1005 size = (~(val & ~0xf)) + 1;
1006 if (val & PCI_ADDRESS_SPACE_IO)
1007 paddr = &pci_bios_io_addr;
1008 else if (size >= 0x04000000)
1009 paddr = &pci_bios_bigmem_addr;
1010 else
1011 paddr = &pci_bios_mem_addr;
1012 *paddr = (*paddr + size - 1) & ~(size - 1);
1013 pci_set_io_region_addr(d, i, *paddr);
1014 *paddr += size;
1015 /* make memory address page aligned */
1016 if (!(val & PCI_ADDRESS_SPACE_IO))
1017 *paddr = (*paddr + 0xfff) & 0xfffff000;
1018 }
1019 }
1020 break;
1021 }
1022
1023 /* map the interrupt */
1024 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
1025 if (pin != 0) {
1026 pin = pci_slot_get_pirq(d, pin - 1);
1027 pic_irq = pci_irqs[pin];
1028 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1029 }
1030
1031 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
1032 /* PIIX4 Power Management device (for ACPI) */
1033
1034 // acpi sci is hardwired to 9
1035 pci_config_writeb(d, PCI_INTERRUPT_LINE, 9);
1036
1037 pm_io_base = PM_IO_BASE;
1038 smb_io_base = SMB_IO_BASE;
1039 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
1040 piix4_pm_enable(d);
1041 acpi_enabled = 1;
1042 }
1043 }
1044
1045 void pci_for_each_device(void (*init_func)(PCIDevice *d))
1046 {
1047 PCIDevice d1, *d = &d1;
1048 int bus, devfn;
1049 uint16_t vendor_id, device_id;
1050
1051 for(bus = 0; bus < 1; bus++) {
1052 for(devfn = 0; devfn < 256; devfn++) {
1053 d->bus = bus;
1054 d->devfn = devfn;
1055 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1056 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1057 if (vendor_id != 0xffff || device_id != 0xffff) {
1058 init_func(d);
1059 }
1060 }
1061 }
1062 }
1063
1064 void pci_bios_init(void)
1065 {
1066 pci_bios_io_addr = 0xc000;
1067 pci_bios_mem_addr = 0xf0000000;
1068 pci_bios_bigmem_addr = ram_size;
1069 if (pci_bios_bigmem_addr < 0x90000000)
1070 pci_bios_bigmem_addr = 0x90000000;
1071
1072 pci_for_each_device(pci_bios_init_bridges);
1073
1074 pci_for_each_device(pci_bios_init_device);
1075 }
1076
1077 /****************************************************/
1078 /* Multi Processor table init */
1079
1080 static void putb(uint8_t **pp, int val)
1081 {
1082 uint8_t *q;
1083 q = *pp;
1084 *q++ = val;
1085 *pp = q;
1086 }
1087
1088 static void putstr(uint8_t **pp, const char *str)
1089 {
1090 uint8_t *q;
1091 q = *pp;
1092 while (*str)
1093 *q++ = *str++;
1094 *pp = q;
1095 }
1096
1097 static void putle16(uint8_t **pp, int val)
1098 {
1099 uint8_t *q;
1100 q = *pp;
1101 *q++ = val;
1102 *q++ = val >> 8;
1103 *pp = q;
1104 }
1105
1106 static void putle32(uint8_t **pp, int val)
1107 {
1108 uint8_t *q;
1109 q = *pp;
1110 *q++ = val;
1111 *q++ = val >> 8;
1112 *q++ = val >> 16;
1113 *q++ = val >> 24;
1114 *pp = q;
1115 }
1116
1117 static int mpf_checksum(const uint8_t *data, int len)
1118 {
1119 int sum, i;
1120 sum = 0;
1121 for(i = 0; i < len; i++)
1122 sum += data[i];
1123 return sum & 0xff;
1124 }
1125
1126 static unsigned long align(unsigned long addr, unsigned long v)
1127 {
1128 return (addr + v - 1) & ~(v - 1);
1129 }
1130
1131 static void mptable_init(void)
1132 {
1133 uint8_t *mp_config_table, *q, *float_pointer_struct;
1134 int ioapic_id, i, len;
1135 int mp_config_table_size;
1136
1137 #ifdef BX_USE_EBDA_TABLES
1138 mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
1139 #else
1140 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1141 mp_config_table = (uint8_t *)bios_table_cur_addr;
1142 #endif
1143 q = mp_config_table;
1144 putstr(&q, "PCMP"); /* "PCMP signature */
1145 putle16(&q, 0); /* table length (patched later) */
1146 putb(&q, 4); /* spec rev */
1147 putb(&q, 0); /* checksum (patched later) */
1148 #ifdef BX_QEMU
1149 putstr(&q, "QEMUCPU "); /* OEM id */
1150 #else
1151 putstr(&q, "BOCHSCPU");
1152 #endif
1153 putstr(&q, "0.1 "); /* vendor id */
1154 putle32(&q, 0); /* OEM table ptr */
1155 putle16(&q, 0); /* OEM table size */
1156 putle16(&q, MAX_CPUS + 18); /* entry count */
1157 putle32(&q, 0xfee00000); /* local APIC addr */
1158 putle16(&q, 0); /* ext table length */
1159 putb(&q, 0); /* ext table checksum */
1160 putb(&q, 0); /* reserved */
1161
1162 for(i = 0; i < MAX_CPUS ; i++) {
1163 putb(&q, 0); /* entry type = processor */
1164 putb(&q, i); /* APIC id */
1165 putb(&q, 0x11); /* local APIC version number */
1166 if (i == 0)
1167 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
1168 else if ( i < smp_cpus)
1169 putb(&q, 1); /* cpu flags: enabled */
1170 else
1171 putb(&q, 0); /* cpu flags: disabled */
1172 putb(&q, 0); /* cpu signature */
1173 putb(&q, 6);
1174 putb(&q, 0);
1175 putb(&q, 0);
1176 putle16(&q, 0x201); /* feature flags */
1177 putle16(&q, 0);
1178
1179 putle16(&q, 0); /* reserved */
1180 putle16(&q, 0);
1181 putle16(&q, 0);
1182 putle16(&q, 0);
1183 }
1184
1185 /* isa bus */
1186 putb(&q, 1); /* entry type = bus */
1187 putb(&q, 0); /* bus ID */
1188 putstr(&q, "ISA ");
1189
1190 /* ioapic */
1191 ioapic_id = smp_cpus;
1192 putb(&q, 2); /* entry type = I/O APIC */
1193 putb(&q, ioapic_id); /* apic ID */
1194 putb(&q, 0x11); /* I/O APIC version number */
1195 putb(&q, 1); /* enable */
1196 putle32(&q, 0xfec00000); /* I/O APIC addr */
1197
1198 /* irqs */
1199 for(i = 0; i < 16; i++) {
1200 putb(&q, 3); /* entry type = I/O interrupt */
1201 putb(&q, 0); /* interrupt type = vectored interrupt */
1202 putb(&q, 0); /* flags: po=0, el=0 */
1203 putb(&q, 0);
1204 putb(&q, 0); /* source bus ID = ISA */
1205 putb(&q, i); /* source bus IRQ */
1206 putb(&q, ioapic_id); /* dest I/O APIC ID */
1207 putb(&q, i); /* dest I/O APIC interrupt in */
1208 }
1209 /* patch length */
1210 len = q - mp_config_table;
1211 mp_config_table[4] = len;
1212 mp_config_table[5] = len >> 8;
1213
1214 mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
1215
1216 mp_config_table_size = q - mp_config_table;
1217
1218 #ifndef BX_USE_EBDA_TABLES
1219 bios_table_cur_addr += mp_config_table_size;
1220 #endif
1221
1222 /* floating pointer structure */
1223 #ifdef BX_USE_EBDA_TABLES
1224 ebda_cur_addr = align(ebda_cur_addr, 16);
1225 float_pointer_struct = (uint8_t *)ebda_cur_addr;
1226 #else
1227 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1228 float_pointer_struct = (uint8_t *)bios_table_cur_addr;
1229 #endif
1230 q = float_pointer_struct;
1231 putstr(&q, "_MP_");
1232 /* pointer to MP config table */
1233 putle32(&q, (unsigned long)mp_config_table);
1234
1235 putb(&q, 1); /* length in 16 byte units */
1236 putb(&q, 4); /* MP spec revision */
1237 putb(&q, 0); /* checksum (patched later) */
1238 putb(&q, 0); /* MP feature byte 1 */
1239
1240 putb(&q, 0);
1241 putb(&q, 0);
1242 putb(&q, 0);
1243 putb(&q, 0);
1244 float_pointer_struct[10] =
1245 -mpf_checksum(float_pointer_struct, q - float_pointer_struct);
1246 #ifdef BX_USE_EBDA_TABLES
1247 ebda_cur_addr += (q - float_pointer_struct);
1248 #else
1249 bios_table_cur_addr += (q - float_pointer_struct);
1250 #endif
1251 BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
1252 (unsigned long)float_pointer_struct,
1253 (unsigned long)mp_config_table,
1254 mp_config_table_size);
1255 }
1256
1257 /****************************************************/
1258 /* ACPI tables init */
1259
1260 /* Table structure from Linux kernel (the ACPI tables are under the
1261 BSD license) */
1262
1263 /*
1264 * All tables must be byte-packed to match the ACPI specification, since
1265 * the tables are provided by the system BIOS.
1266 */
1267
1268 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
1269 uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
1270 uint32_t length; /* Length of table, in bytes, including header */\
1271 uint8_t revision; /* ACPI Specification minor version # */\
1272 uint8_t checksum; /* To make sum of entire table == 0 */\
1273 uint8_t oem_id [6]; /* OEM identification */\
1274 uint8_t oem_table_id [8]; /* OEM table identification */\
1275 uint32_t oem_revision; /* OEM revision number */\
1276 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
1277 uint32_t asl_compiler_revision; /* ASL compiler revision number */
1278
1279
1280 struct acpi_table_header /* ACPI common table header */
1281 {
1282 ACPI_TABLE_HEADER_DEF
1283 } __attribute__((__packed__));
1284
1285 struct rsdp_descriptor /* Root System Descriptor Pointer */
1286 {
1287 uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
1288 uint8_t checksum; /* To make sum of struct == 0 */
1289 uint8_t oem_id [6]; /* OEM identification */
1290 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
1291 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
1292 uint32_t length; /* XSDT Length in bytes including hdr */
1293 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
1294 uint8_t extended_checksum; /* Checksum of entire table */
1295 uint8_t reserved [3]; /* Reserved field must be 0 */
1296 } __attribute__((__packed__));
1297
1298 #define MAX_RSDT_ENTRIES 100
1299
1300 /*
1301 * ACPI 1.0 Root System Description Table (RSDT)
1302 */
1303 struct rsdt_descriptor_rev1
1304 {
1305 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1306 uint32_t table_offset_entry [MAX_RSDT_ENTRIES]; /* Array of pointers to other */
1307 /* ACPI tables */
1308 } __attribute__((__packed__));
1309
1310 /*
1311 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
1312 */
1313 struct facs_descriptor_rev1
1314 {
1315 uint8_t signature[4]; /* ACPI Signature */
1316 uint32_t length; /* Length of structure, in bytes */
1317 uint32_t hardware_signature; /* Hardware configuration signature */
1318 uint32_t firmware_waking_vector; /* ACPI OS waking vector */
1319 uint32_t global_lock; /* Global Lock */
1320 uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
1321 uint32_t reserved1 : 31; /* Must be 0 */
1322 uint8_t resverved3 [40]; /* Reserved - must be zero */
1323 } __attribute__((__packed__));
1324
1325
1326 /*
1327 * ACPI 1.0 Fixed ACPI Description Table (FADT)
1328 */
1329 struct fadt_descriptor_rev1
1330 {
1331 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1332 uint32_t firmware_ctrl; /* Physical address of FACS */
1333 uint32_t dsdt; /* Physical address of DSDT */
1334 uint8_t model; /* System Interrupt Model */
1335 uint8_t reserved1; /* Reserved */
1336 uint16_t sci_int; /* System vector of SCI interrupt */
1337 uint32_t smi_cmd; /* Port address of SMI command port */
1338 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
1339 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
1340 uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
1341 uint8_t reserved2; /* Reserved - must be zero */
1342 uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
1343 uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
1344 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
1345 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
1346 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
1347 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
1348 uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
1349 uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
1350 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
1351 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
1352 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
1353 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
1354 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
1355 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
1356 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
1357 uint8_t reserved3; /* Reserved */
1358 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
1359 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
1360 uint16_t flush_size; /* Size of area read to flush caches */
1361 uint16_t flush_stride; /* Stride used in flushing caches */
1362 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
1363 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
1364 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
1365 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
1366 uint8_t century; /* Index to century in RTC CMOS RAM */
1367 uint8_t reserved4; /* Reserved */
1368 uint8_t reserved4a; /* Reserved */
1369 uint8_t reserved4b; /* Reserved */
1370 #if 0
1371 uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
1372 uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
1373 uint32_t proc_c1 : 1; /* All processors support C1 state */
1374 uint32_t plvl2_up : 1; /* C2 state works on MP system */
1375 uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
1376 uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
1377 uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
1378 uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
1379 uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
1380 uint32_t reserved5 : 23; /* Reserved - must be zero */
1381 #else
1382 uint32_t flags;
1383 #endif
1384 } __attribute__((__packed__));
1385
1386 /*
1387 * MADT values and structures
1388 */
1389
1390 /* Values for MADT PCATCompat */
1391
1392 #define DUAL_PIC 0
1393 #define MULTIPLE_APIC 1
1394
1395
1396 /* Master MADT */
1397
1398 struct multiple_apic_table
1399 {
1400 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1401 uint32_t local_apic_address; /* Physical address of local APIC */
1402 #if 0
1403 uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
1404 uint32_t reserved1 : 31;
1405 #else
1406 uint32_t flags;
1407 #endif
1408 } __attribute__((__packed__));
1409
1410
1411 /* Values for Type in APIC sub-headers */
1412
1413 #define APIC_PROCESSOR 0
1414 #define APIC_IO 1
1415 #define APIC_XRUPT_OVERRIDE 2
1416 #define APIC_NMI 3
1417 #define APIC_LOCAL_NMI 4
1418 #define APIC_ADDRESS_OVERRIDE 5
1419 #define APIC_IO_SAPIC 6
1420 #define APIC_LOCAL_SAPIC 7
1421 #define APIC_XRUPT_SOURCE 8
1422 #define APIC_RESERVED 9 /* 9 and greater are reserved */
1423
1424 #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
1425 uint8_t type; \
1426 uint8_t length;
1427
1428 /*
1429 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
1430 */
1431 /* Sub-structures for MADT */
1432
1433 struct madt_processor_apic
1434 {
1435 ACPI_SUB_HEADER_DEF
1436 uint8_t processor_id; /* ACPI processor id */
1437 uint8_t local_apic_id; /* Processor's local APIC id */
1438 #if 0
1439 uint32_t processor_enabled: 1; /* Processor is usable if set */
1440 uint32_t reserved2 : 31; /* Reserved, must be zero */
1441 #else
1442 uint32_t flags;
1443 #endif
1444 } __attribute__((__packed__));
1445
1446 /*
1447 * SRAT (NUMA topology description) table
1448 */
1449
1450 #define SRAT_PROCESSOR 0
1451 #define SRAT_MEMORY 1
1452
1453 struct system_resource_affinity_table
1454 {
1455 ACPI_TABLE_HEADER_DEF
1456 uint32_t reserved1;
1457 uint32_t reserved2[2];
1458 };
1459
1460 struct srat_processor_affinity
1461 {
1462 ACPI_SUB_HEADER_DEF
1463 uint8_t proximity_lo;
1464 uint8_t local_apic_id;
1465 uint32_t flags;
1466 uint8_t local_sapic_eid;
1467 uint8_t proximity_hi[3];
1468 uint32_t reserved;
1469 };
1470
1471 struct srat_memory_affinity
1472 {
1473 ACPI_SUB_HEADER_DEF
1474 uint8_t proximity[4];
1475 uint16_t reserved1;
1476 uint32_t base_addr_low,base_addr_high;
1477 uint32_t length_low,length_high;
1478 uint32_t reserved2;
1479 uint32_t flags;
1480 uint32_t reserved3[2];
1481 };
1482
1483 #ifdef BX_QEMU
1484 /*
1485 * * ACPI 2.0 Generic Address Space definition.
1486 * */
1487 struct acpi_20_generic_address {
1488 uint8_t address_space_id;
1489 uint8_t register_bit_width;
1490 uint8_t register_bit_offset;
1491 uint8_t reserved;
1492 uint64_t address;
1493 } __attribute__((__packed__));
1494
1495 /*
1496 * * HPET Description Table
1497 * */
1498 struct acpi_20_hpet {
1499 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1500 uint32_t timer_block_id;
1501 struct acpi_20_generic_address addr;
1502 uint8_t hpet_number;
1503 uint16_t min_tick;
1504 uint8_t page_protect;
1505 } __attribute__((__packed__));
1506 #define ACPI_HPET_ADDRESS 0xFED00000UL
1507 #endif
1508
1509 struct madt_io_apic
1510 {
1511 ACPI_SUB_HEADER_DEF
1512 uint8_t io_apic_id; /* I/O APIC ID */
1513 uint8_t reserved; /* Reserved - must be zero */
1514 uint32_t address; /* APIC physical address */
1515 uint32_t interrupt; /* Global system interrupt where INTI
1516 * lines start */
1517 } __attribute__((__packed__));
1518
1519 #ifdef BX_QEMU
1520 struct madt_int_override
1521 {
1522 ACPI_SUB_HEADER_DEF
1523 uint8_t bus; /* Identifies ISA Bus */
1524 uint8_t source; /* Bus-relative interrupt source */
1525 uint32_t gsi; /* GSI that source will signal */
1526 uint16_t flags; /* MPS INTI flags */
1527 } __attribute__((__packed__));
1528 #endif
1529
1530 #include "acpi-dsdt.hex"
1531
1532 static inline uint16_t cpu_to_le16(uint16_t x)
1533 {
1534 return x;
1535 }
1536
1537 static inline uint32_t cpu_to_le32(uint32_t x)
1538 {
1539 return x;
1540 }
1541
1542 static int acpi_checksum(const uint8_t *data, int len)
1543 {
1544 int sum, i;
1545 sum = 0;
1546 for(i = 0; i < len; i++)
1547 sum += data[i];
1548 return (-sum) & 0xff;
1549 }
1550
1551 static void acpi_build_table_header(struct acpi_table_header *h,
1552 char *sig, int len, uint8_t rev)
1553 {
1554 memcpy(h->signature, sig, 4);
1555 h->length = cpu_to_le32(len);
1556 h->revision = rev;
1557 #ifdef BX_QEMU
1558 memcpy(h->oem_id, "QEMU ", 6);
1559 memcpy(h->oem_table_id, "QEMU", 4);
1560 #else
1561 memcpy(h->oem_id, "BOCHS ", 6);
1562 memcpy(h->oem_table_id, "BXPC", 4);
1563 #endif
1564 memcpy(h->oem_table_id + 4, sig, 4);
1565 h->oem_revision = cpu_to_le32(1);
1566 #ifdef BX_QEMU
1567 memcpy(h->asl_compiler_id, "QEMU", 4);
1568 #else
1569 memcpy(h->asl_compiler_id, "BXPC", 4);
1570 #endif
1571 h->asl_compiler_revision = cpu_to_le32(1);
1572 h->checksum = acpi_checksum((void *)h, len);
1573 }
1574
1575 static void acpi_build_srat_memory(struct srat_memory_affinity *numamem,
1576 uint64_t base, uint64_t len, int node, int enabled)
1577 {
1578 numamem->type = SRAT_MEMORY;
1579 numamem->length = sizeof(*numamem);
1580 memset (numamem->proximity, 0 ,4);
1581 numamem->proximity[0] = node;
1582 numamem->flags = cpu_to_le32(!!enabled);
1583 numamem->base_addr_low = base & 0xFFFFFFFF;
1584 numamem->base_addr_high = base >> 32;
1585 numamem->length_low = len & 0xFFFFFFFF;
1586 numamem->length_high = len >> 32;
1587 return;
1588 }
1589
1590 /* base_addr must be a multiple of 4KB */
1591 void acpi_bios_init(void)
1592 {
1593 struct rsdp_descriptor *rsdp;
1594 struct rsdt_descriptor_rev1 *rsdt;
1595 struct fadt_descriptor_rev1 *fadt;
1596 struct facs_descriptor_rev1 *facs;
1597 struct multiple_apic_table *madt;
1598 uint8_t *dsdt, *ssdt;
1599 #ifdef BX_QEMU
1600 struct system_resource_affinity_table *srat;
1601 struct acpi_20_hpet *hpet;
1602 uint32_t hpet_addr;
1603 #endif
1604 uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
1605 uint32_t acpi_tables_size, madt_addr, madt_size, rsdt_size, madt_end;
1606 uint32_t srat_addr,srat_size;
1607 uint16_t i, external_tables;
1608 int nb_numa_nodes;
1609 int nb_rsdt_entries = 0;
1610
1611 /* reserve memory space for tables */
1612 #ifdef BX_USE_EBDA_TABLES
1613 ebda_cur_addr = align(ebda_cur_addr, 16);
1614 rsdp = (void *)(ebda_cur_addr);
1615 ebda_cur_addr += sizeof(*rsdp);
1616 #else
1617 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1618 rsdp = (void *)(bios_table_cur_addr);
1619 bios_table_cur_addr += sizeof(*rsdp);
1620 #endif
1621
1622 #ifdef BX_QEMU
1623 external_tables = acpi_additional_tables();
1624 #else
1625 external_tables = 0;
1626 #endif
1627
1628 addr = base_addr = ram_size - ACPI_DATA_SIZE;
1629 rsdt_addr = addr;
1630 rsdt = (void *)(addr);
1631 rsdt_size = sizeof(*rsdt) + external_tables * 4;
1632 addr += rsdt_size;
1633
1634 fadt_addr = addr;
1635 fadt = (void *)(addr);
1636 addr += sizeof(*fadt);
1637
1638 /* XXX: FACS should be in RAM */
1639 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
1640 facs_addr = addr;
1641 facs = (void *)(addr);
1642 addr += sizeof(*facs);
1643
1644 dsdt_addr = addr;
1645 dsdt = (void *)(addr);
1646 addr += sizeof(AmlCode);
1647
1648 #ifdef BX_QEMU
1649 qemu_cfg_select(QEMU_CFG_NUMA);
1650 nb_numa_nodes = qemu_cfg_get64();
1651 #else
1652 nb_numa_nodes = 0;
1653 #endif
1654 if (nb_numa_nodes > 0) {
1655 addr = (addr + 7) & ~7;
1656 srat_addr = addr;
1657 srat_size = sizeof(*srat) +
1658 sizeof(struct srat_processor_affinity) * smp_cpus +
1659 sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2);
1660 srat = (void *)(addr);
1661 addr += srat_size;
1662 } else {
1663 srat_addr = addr;
1664 srat = (void*)(addr);
1665 srat_size = 0;
1666 }
1667
1668 addr = (addr + 7) & ~7;
1669 madt_addr = addr;
1670 madt_size = sizeof(*madt) +
1671 sizeof(struct madt_processor_apic) * MAX_CPUS +
1672 #ifdef BX_QEMU
1673 sizeof(struct madt_io_apic) + sizeof(struct madt_int_override) * MAX_INT_OVERRIDES;
1674 #else
1675 sizeof(struct madt_io_apic);
1676 #endif
1677 madt = (void *)(addr);
1678 addr += madt_size;
1679
1680 #ifdef BX_QEMU
1681 #ifdef HPET_WORKS_IN_KVM
1682 addr = (addr + 7) & ~7;
1683 hpet_addr = addr;
1684 hpet = (void *)(addr);
1685 addr += sizeof(*hpet);
1686 #endif
1687 #endif
1688
1689 /* RSDP */
1690 memset(rsdp, 0, sizeof(*rsdp));
1691 memcpy(rsdp->signature, "RSD PTR ", 8);
1692 #ifdef BX_QEMU
1693 memcpy(rsdp->oem_id, "QEMU ", 6);
1694 #else
1695 memcpy(rsdp->oem_id, "BOCHS ", 6);
1696 #endif
1697 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
1698 rsdp->checksum = acpi_checksum((void *)rsdp, 20);
1699
1700 /* FADT */
1701 memset(fadt, 0, sizeof(*fadt));
1702 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
1703 fadt->dsdt = cpu_to_le32(dsdt_addr);
1704 fadt->model = 1;
1705 fadt->reserved1 = 0;
1706 fadt->sci_int = cpu_to_le16(pm_sci_int);
1707 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
1708 fadt->acpi_enable = 0xf1;
1709 fadt->acpi_disable = 0xf0;
1710 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
1711 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
1712 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
1713 fadt->pm1_evt_len = 4;
1714 fadt->pm1_cnt_len = 2;
1715 fadt->pm_tmr_len = 4;
1716 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
1717 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
1718 fadt->gpe0_blk = cpu_to_le32(0xafe0);
1719 fadt->gpe0_blk_len = 4;
1720 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
1721 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
1722 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
1723 sizeof(*fadt), 1);
1724
1725 /* FACS */
1726 memset(facs, 0, sizeof(*facs));
1727 memcpy(facs->signature, "FACS", 4);
1728 facs->length = cpu_to_le32(sizeof(*facs));
1729 BX_INFO("Firmware waking vector %p\n", &facs->firmware_waking_vector);
1730
1731 /* DSDT */
1732 memcpy(dsdt, AmlCode, sizeof(AmlCode));
1733
1734 /* MADT */
1735 {
1736 struct madt_processor_apic *apic;
1737 struct madt_io_apic *io_apic;
1738 #ifdef BX_QEMU
1739 struct madt_int_override *int_override;
1740 #endif
1741
1742 memset(madt, 0, madt_size);
1743 madt->local_apic_address = cpu_to_le32(0xfee00000);
1744 madt->flags = cpu_to_le32(1);
1745 *(uint32_t*)APIC_MADT_PTR = apic = (void *)(madt + 1);
1746 for(i=0;i<MAX_CPUS;i++) {
1747 apic->type = APIC_PROCESSOR;
1748 apic->length = sizeof(*apic);
1749 apic->processor_id = i;
1750 apic->local_apic_id = i;
1751 if (i < smp_cpus)
1752 apic->flags = cpu_to_le32(1);
1753 else
1754 apic->flags = 0;
1755 apic++;
1756 }
1757 io_apic = (void *)apic;
1758 io_apic->type = APIC_IO;
1759 io_apic->length = sizeof(*io_apic);
1760 io_apic->io_apic_id = smp_cpus;
1761 io_apic->address = cpu_to_le32(0xfec00000);
1762 io_apic->interrupt = cpu_to_le32(0);
1763 #ifdef BX_QEMU
1764 #ifdef HPET_WORKS_IN_KVM
1765 io_apic++;
1766
1767 int_override = (void *)io_apic;
1768 int_override->type = APIC_XRUPT_OVERRIDE;
1769 int_override->length = sizeof(*int_override);
1770 int_override->bus = cpu_to_le32(0);
1771 int_override->source = cpu_to_le32(0);
1772 int_override->gsi = cpu_to_le32(2);
1773 int_override->flags = cpu_to_le32(0);
1774 #endif
1775 #endif
1776
1777 int_override = (struct madt_int_override*)(io_apic + 1);
1778 for ( i = 0; i < 16; i++ ) {
1779 if ( PCI_ISA_IRQ_MASK & (1U << i) ) {
1780 memset(int_override, 0, sizeof(*int_override));
1781 int_override->type = APIC_XRUPT_OVERRIDE;
1782 int_override->length = sizeof(*int_override);
1783 int_override->source = i;
1784 int_override->gsi = i;
1785 int_override->flags = 0xd; /* active high, level triggered */
1786 } else {
1787 /* No need for a INT source override structure. */
1788 continue;
1789 }
1790 int_override++;
1791 }
1792 madt_end = (uint32_t)int_override;
1793 madt_size = madt_end - madt_addr;
1794 acpi_build_table_header((struct acpi_table_header *)madt,
1795 "APIC", madt_size, 1);
1796 }
1797
1798 memset(rsdt, 0, rsdt_size);
1799 #ifdef BX_QEMU
1800 /* SRAT */
1801 if (nb_numa_nodes > 0) {
1802 struct srat_processor_affinity *core;
1803 struct srat_memory_affinity *numamem;
1804 int slots;
1805 uint64_t mem_len, mem_base, next_base = 0, curnode;
1806
1807 qemu_cfg_select(QEMU_CFG_NUMA);
1808 qemu_cfg_get64();
1809 memset (srat, 0 , srat_size);
1810 srat->reserved1=1;
1811
1812 core = (void*)(srat + 1);
1813 for (i = 0; i < smp_cpus; ++i) {
1814 core->type = SRAT_PROCESSOR;
1815 core->length = sizeof(*core);
1816 core->local_apic_id = i;
1817 curnode = qemu_cfg_get64();
1818 core->proximity_lo = curnode;
1819 memset (core->proximity_hi, 0, 3);
1820 core->local_sapic_eid = 0;
1821 if (i < smp_cpus)
1822 core->flags = cpu_to_le32(1);
1823 else
1824 core->flags = 0;
1825 core++;
1826 }
1827
1828 /* the memory map is a bit tricky, it contains at least one hole
1829 * from 640k-1M and possibly another one from 3.5G-4G.
1830 */
1831 numamem = (void*)core; slots = 0;
1832 acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
1833 next_base = 1024 * 1024; numamem++;slots++;
1834 for (i = 1; i < nb_numa_nodes + 1; ++i) {
1835 mem_base = next_base;
1836 mem_len = qemu_cfg_get64();
1837 if (i == 1) mem_len -= 1024 * 1024;
1838 next_base = mem_base + mem_len;
1839
1840 /* Cut out the PCI hole */
1841 if (mem_base <= ram_size && next_base > ram_size) {
1842 mem_len -= next_base - ram_size;
1843 if (mem_len > 0) {
1844 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
1845 numamem++; slots++;
1846 }
1847 mem_base = 1ULL << 32;
1848 mem_len = next_base - ram_size;
1849 next_base += (1ULL << 32) - ram_size;
1850 }
1851 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
1852 numamem++; slots++;
1853 }
1854 for (; slots < nb_numa_nodes + 2; slots++) {
1855 acpi_build_srat_memory(numamem, 0, 0, 0, 0);
1856 numamem++;
1857 }
1858
1859 acpi_build_table_header((struct acpi_table_header *)srat,
1860 "SRAT", srat_size, 1);
1861 }
1862
1863 /* HPET */
1864 #ifdef HPET_WORKS_IN_KVM
1865 memset(hpet, 0, sizeof(*hpet));
1866 /* Note timer_block_id value must be kept in sync with value advertised by
1867 * emulated hpet
1868 */
1869 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1870 hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
1871 acpi_build_table_header((struct acpi_table_header *)hpet,
1872 "HPET", sizeof(*hpet), 1);
1873 #endif
1874
1875 acpi_additional_tables(); /* resets cfg to required entry */
1876 for(i = 0; i < external_tables; i++) {
1877 uint16_t len;
1878 if(acpi_load_table(i, addr, &len) < 0)
1879 BX_PANIC("Failed to load ACPI table from QEMU\n");
1880 rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(addr);
1881 addr += len;
1882 if(addr >= ram_size)
1883 BX_PANIC("ACPI table overflow\n");
1884 }
1885 #endif
1886
1887 /* RSDT */
1888 rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(fadt_addr);
1889 rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(madt_addr);
1890 /* kvm has no ssdt (processors are in dsdt) */
1891 // rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(ssdt_addr);
1892 #ifdef BX_QEMU
1893 /* No HPET (yet) */
1894 // rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(hpet_addr);
1895 if (nb_numa_nodes > 0)
1896 rsdt->table_offset_entry[nb_rsdt_entries++] = cpu_to_le32(srat_addr);
1897 #endif
1898 rsdt_size -= MAX_RSDT_ENTRIES * 4;
1899 rsdt_size += nb_rsdt_entries * 4;
1900 acpi_build_table_header((struct acpi_table_header *)rsdt, "RSDT",
1901 rsdt_size, 1);
1902
1903 acpi_tables_size = addr - base_addr;
1904
1905 BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
1906 (unsigned long)rsdp,
1907 (unsigned long)rsdt, acpi_tables_size);
1908
1909 }
1910
1911 /* SMBIOS entry point -- must be written to a 16-bit aligned address
1912 between 0xf0000 and 0xfffff.
1913 */
1914 struct smbios_entry_point {
1915 char anchor_string[4];
1916 uint8_t checksum;
1917 uint8_t length;
1918 uint8_t smbios_major_version;
1919 uint8_t smbios_minor_version;
1920 uint16_t max_structure_size;
1921 uint8_t entry_point_revision;
1922 uint8_t formatted_area[5];
1923 char intermediate_anchor_string[5];
1924 uint8_t intermediate_checksum;
1925 uint16_t structure_table_length;
1926 uint32_t structure_table_address;
1927 uint16_t number_of_structures;
1928 uint8_t smbios_bcd_revision;
1929 } __attribute__((__packed__));
1930
1931 /* This goes at the beginning of every SMBIOS structure. */
1932 struct smbios_structure_header {
1933 uint8_t type;
1934 uint8_t length;
1935 uint16_t handle;
1936 } __attribute__((__packed__));
1937
1938 /* SMBIOS type 0 - BIOS Information */
1939 struct smbios_type_0 {
1940 struct smbios_structure_header header;
1941 uint8_t vendor_str;
1942 uint8_t bios_version_str;
1943 uint16_t bios_starting_address_segment;
1944 uint8_t bios_release_date_str;
1945 uint8_t bios_rom_size;
1946 uint8_t bios_characteristics[8];
1947 uint8_t bios_characteristics_extension_bytes[2];
1948 uint8_t system_bios_major_release;
1949 uint8_t system_bios_minor_release;
1950 uint8_t embedded_controller_major_release;
1951 uint8_t embedded_controller_minor_release;
1952 } __attribute__((__packed__));
1953
1954 /* SMBIOS type 1 - System Information */
1955 struct smbios_type_1 {
1956 struct smbios_structure_header header;
1957 uint8_t manufacturer_str;
1958 uint8_t product_name_str;
1959 uint8_t version_str;
1960 uint8_t serial_number_str;
1961 uint8_t uuid[16];
1962 uint8_t wake_up_type;
1963 uint8_t sku_number_str;
1964 uint8_t family_str;
1965 } __attribute__((__packed__));
1966
1967 /* SMBIOS type 3 - System Enclosure (v2.3) */
1968 struct smbios_type_3 {
1969 struct smbios_structure_header header;
1970 uint8_t manufacturer_str;
1971 uint8_t type;
1972 uint8_t version_str;
1973 uint8_t serial_number_str;
1974 uint8_t asset_tag_number_str;
1975 uint8_t boot_up_state;
1976 uint8_t power_supply_state;
1977 uint8_t thermal_state;
1978 uint8_t security_status;
1979 uint32_t oem_defined;
1980 uint8_t height;
1981 uint8_t number_of_power_cords;
1982 uint8_t contained_element_count;
1983 // contained elements follow
1984 } __attribute__((__packed__));
1985
1986 /* SMBIOS type 4 - Processor Information (v2.0) */
1987 struct smbios_type_4 {
1988 struct smbios_structure_header header;
1989 uint8_t socket_designation_str;
1990 uint8_t processor_type;
1991 uint8_t processor_family;
1992 uint8_t processor_manufacturer_str;
1993 uint32_t processor_id[2];
1994 uint8_t processor_version_str;
1995 uint8_t voltage;
1996 uint16_t external_clock;
1997 uint16_t max_speed;
1998 uint16_t current_speed;
1999 uint8_t status;
2000 uint8_t processor_upgrade;
2001 uint16_t l1_cache_handle;
2002 uint16_t l2_cache_handle;
2003 uint16_t l3_cache_handle;
2004 } __attribute__((__packed__));
2005
2006 /* SMBIOS type 16 - Physical Memory Array
2007 * Associated with one type 17 (Memory Device).
2008 */
2009 struct smbios_type_16 {
2010 struct smbios_structure_header header;
2011 uint8_t location;
2012 uint8_t use;
2013 uint8_t error_correction;
2014 uint32_t maximum_capacity;
2015 uint16_t memory_error_information_handle;
2016 uint16_t number_of_memory_devices;
2017 } __attribute__((__packed__));
2018
2019 /* SMBIOS type 17 - Memory Device
2020 * Associated with one type 19
2021 */
2022 struct smbios_type_17 {
2023 struct smbios_structure_header header;
2024 uint16_t physical_memory_array_handle;
2025 uint16_t memory_error_information_handle;
2026 uint16_t total_width;
2027 uint16_t data_width;
2028 uint16_t size;
2029 uint8_t form_factor;
2030 uint8_t device_set;
2031 uint8_t device_locator_str;
2032 uint8_t bank_locator_str;
2033 uint8_t memory_type;
2034 uint16_t type_detail;
2035 } __attribute__((__packed__));
2036
2037 /* SMBIOS type 19 - Memory Array Mapped Address */
2038 struct smbios_type_19 {
2039 struct smbios_structure_header header;
2040 uint32_t starting_address;
2041 uint32_t ending_address;
2042 uint16_t memory_array_handle;
2043 uint8_t partition_width;
2044 } __attribute__((__packed__));
2045
2046 /* SMBIOS type 20 - Memory Device Mapped Address */
2047 struct smbios_type_20 {
2048 struct smbios_structure_header header;
2049 uint32_t starting_address;
2050 uint32_t ending_address;
2051 uint16_t memory_device_handle;
2052 uint16_t memory_array_mapped_address_handle;
2053 uint8_t partition_row_position;
2054 uint8_t interleave_position;
2055 uint8_t interleaved_data_depth;
2056 } __attribute__((__packed__));
2057
2058 /* SMBIOS type 32 - System Boot Information */
2059 struct smbios_type_32 {
2060 struct smbios_structure_header header;
2061 uint8_t reserved[6];
2062 uint8_t boot_status;
2063 } __attribute__((__packed__));
2064
2065 /* SMBIOS type 127 -- End-of-table */
2066 struct smbios_type_127 {
2067 struct smbios_structure_header header;
2068 } __attribute__((__packed__));
2069
2070 static void
2071 smbios_entry_point_init(void *start,
2072 uint16_t max_structure_size,
2073 uint16_t structure_table_length,
2074 uint32_t structure_table_address,
2075 uint16_t number_of_structures)
2076 {
2077 uint8_t sum;
2078 int i;
2079 struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
2080
2081 memcpy(ep->anchor_string, "_SM_", 4);
2082 ep->length = 0x1f;
2083 ep->smbios_major_version = 2;
2084 ep->smbios_minor_version = 4;
2085 ep->max_structure_size = max_structure_size;
2086 ep->entry_point_revision = 0;
2087 memset(ep->formatted_area, 0, 5);
2088 memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
2089
2090 ep->structure_table_length = structure_table_length;
2091 ep->structure_table_address = structure_table_address;
2092 ep->number_of_structures = number_of_structures;
2093 ep->smbios_bcd_revision = 0x24;
2094
2095 ep->checksum = 0;
2096 ep->intermediate_checksum = 0;
2097
2098 sum = 0;
2099 for (i = 0; i < 0x10; i++)
2100 sum += ((int8_t *)start)[i];
2101 ep->checksum = -sum;
2102
2103 sum = 0;
2104 for (i = 0x10; i < ep->length; i++)
2105 sum += ((int8_t *)start)[i];
2106 ep->intermediate_checksum = -sum;
2107 }
2108
2109 struct smbios_header {
2110 uint16_t length;
2111 uint8_t type;
2112 } __attribute__((__packed__));
2113
2114 struct smbios_field {
2115 struct smbios_header header;
2116 uint8_t type;
2117 uint16_t offset;
2118 uint8_t data[];
2119 } __attribute__((__packed__));
2120
2121 struct smbios_table {
2122 struct smbios_header header;
2123 uint8_t data[];
2124 } __attribute__((__packed__));
2125
2126 #define SMBIOS_FIELD_ENTRY 0
2127 #define SMBIOS_TABLE_ENTRY 1
2128
2129 static size_t
2130 smbios_load_field(int type, size_t offset, void *addr)
2131 {
2132 #ifdef BX_QEMU
2133 int i;
2134
2135 for (i = smbios_entries(); i > 0; i--) {
2136 struct smbios_field field;
2137
2138 qemu_cfg_read((uint8_t *)&field, sizeof(struct smbios_header));
2139 field.header.length -= sizeof(struct smbios_header);
2140
2141 if (field.header.type != SMBIOS_FIELD_ENTRY) {
2142 while (field.header.length--)
2143 inb(QEMU_CFG_DATA_PORT);
2144 continue;
2145 }
2146
2147 qemu_cfg_read((uint8_t *)&field.type,
2148 sizeof(field) - sizeof(struct smbios_header));
2149 field.header.length -= sizeof(field) - sizeof(struct smbios_header);
2150
2151 if (field.type != type || field.offset != offset) {
2152 while (field.header.length--)
2153 inb(QEMU_CFG_DATA_PORT);
2154 continue;
2155 }
2156
2157 qemu_cfg_read(addr, field.header.length);
2158 return (size_t)field.header.length;
2159 }
2160 #endif
2161 return 0;
2162 }
2163
2164 #define load_str_field_with_default(type, field, def) do { \
2165 size = smbios_load_field(type, offsetof(struct smbios_type_##type, \
2166 field), end); \
2167 if (size > 0) { \
2168 end += size; \
2169 } else { \
2170 memcpy(end, def, sizeof(def)); \
2171 end += sizeof(def); \
2172 } \
2173 p->field = ++str_index; \
2174 } while (0)
2175
2176 #define load_str_field_or_skip(type, field) do { \
2177 size = smbios_load_field(type, offsetof(struct smbios_type_##type, \
2178 field), end); \
2179 if (size > 0) { \
2180 end += size; \
2181 p->field = ++str_index; \
2182 } else { \
2183 p->field = 0; \
2184 } \
2185 } while (0)
2186
2187 /* Type 0 -- BIOS Information */
2188 #define RELEASE_DATE_STR "01/01/2007"
2189 static void *
2190 smbios_init_type_0(void *start)
2191 {
2192 struct smbios_type_0 *p = (struct smbios_type_0 *)start;
2193 char *end = (char *)start + sizeof(struct smbios_type_0);
2194 size_t size;
2195 int str_index = 0;
2196
2197 p->header.type = 0;
2198 p->header.length = sizeof(struct smbios_type_0);
2199 p->header.handle = 0;
2200
2201 load_str_field_with_default(0, vendor_str, BX_APPNAME);
2202 load_str_field_with_default(0, bios_version_str, BX_APPNAME);
2203
2204 p->bios_starting_address_segment = 0xe800;
2205
2206 load_str_field_with_default(0, bios_release_date_str, RELEASE_DATE_STR);
2207
2208 p->bios_rom_size = 0; /* FIXME */
2209
2210 memset(p->bios_characteristics, 0, 8);
2211 p->bios_characteristics[0] = 0x08; /* BIOS characteristics not supported */
2212 p->bios_characteristics_extension_bytes[0] = 0;
2213 p->bios_characteristics_extension_bytes[1] = 0;
2214
2215 if (!smbios_load_field(0, offsetof(struct smbios_type_0,
2216 system_bios_major_release),
2217 &p->system_bios_major_release))
2218 p->system_bios_major_release = 1;
2219
2220 if (!smbios_load_field(0, offsetof(struct smbios_type_0,
2221 system_bios_minor_release),
2222 &p->system_bios_minor_release))
2223 p->system_bios_minor_release = 0;
2224
2225 p->embedded_controller_major_release = 0xff;
2226 p->embedded_controller_minor_release = 0xff;
2227
2228 *end = 0;
2229 end++;
2230
2231 return end;
2232 }
2233
2234 /* Type 1 -- System Information */
2235 static void *
2236 smbios_init_type_1(void *start)
2237 {
2238 struct smbios_type_1 *p = (struct smbios_type_1 *)start;
2239 char *end = (char *)start + sizeof(struct smbios_type_1);
2240 size_t size;
2241 int str_index = 0;
2242
2243 p->header.type = 1;
2244 p->header.length = sizeof(struct smbios_type_1);
2245 p->header.handle = 0x100;
2246
2247 load_str_field_or_skip(1, manufacturer_str);
2248 load_str_field_or_skip(1, product_name_str);
2249 load_str_field_or_skip(1, version_str);
2250 load_str_field_or_skip(1, serial_number_str);
2251
2252 size = smbios_load_field(1, offsetof(struct smbios_type_1,
2253 uuid), &p->uuid);
2254 if (size == 0)
2255 memset(p->uuid, 0, 16);
2256
2257 p->wake_up_type = 0x06; /* power switch */
2258
2259 load_str_field_or_skip(1, sku_number_str);
2260 load_str_field_or_skip(1, family_str);
2261
2262 *end = 0;
2263 end++;
2264 if (!str_index) {
2265 *end = 0;
2266 end++;
2267 }
2268
2269 return end;
2270 }
2271
2272 /* Type 3 -- System Enclosure */
2273 static void *
2274 smbios_init_type_3(void *start)
2275 {
2276 struct smbios_type_3 *p = (struct smbios_type_3 *)start;
2277
2278 p->header.type = 3;
2279 p->header.length = sizeof(struct smbios_type_3);
2280 p->header.handle = 0x300;
2281
2282 p->manufacturer_str = 0;
2283 p->type = 0x01; /* other */
2284 p->version_str = 0;
2285 p->serial_number_str = 0;
2286 p->asset_tag_number_str = 0;
2287 p->boot_up_state = 0x03; /* safe */
2288 p->power_supply_state = 0x03; /* safe */
2289 p->thermal_state = 0x03; /* safe */
2290 p->security_status = 0x02; /* unknown */
2291 p->oem_defined = 0;
2292 p->height = 0;
2293 p->number_of_power_cords = 0;
2294 p->contained_element_count = 0;
2295
2296 start += sizeof(struct smbios_type_3);
2297 *((uint16_t *)start) = 0;
2298
2299 return start+2;
2300 }
2301
2302 /* Type 4 -- Processor Information */
2303 static void *
2304 smbios_init_type_4(void *start, unsigned int cpu_number)
2305 {
2306 struct smbios_type_4 *p = (struct smbios_type_4 *)start;
2307
2308 p->header.type = 4;
2309 p->header.length = sizeof(struct smbios_type_4);
2310 p->header.handle = 0x400 + cpu_number;
2311
2312 p->socket_designation_str = 1;
2313 p->processor_type = 0x03; /* CPU */
2314 p->processor_family = 0x01; /* other */
2315 p->processor_manufacturer_str = 0;
2316
2317 p->processor_id[0] = cpuid_signature;
2318 p->processor_id[1] = cpuid_features;
2319
2320 p->processor_version_str = 0;
2321 p->voltage = 0;
2322 p->external_clock = 0;
2323
2324 p->max_speed = 0; /* unknown */
2325 p->current_speed = 0; /* unknown */
2326
2327 p->status = 0x41; /* socket populated, CPU enabled */
2328 p->processor_upgrade = 0x01; /* other */
2329
2330 p->l1_cache_handle = 0xffff; /* cache information structure not provided */
2331 p->l2_cache_handle = 0xffff;
2332 p->l3_cache_handle = 0xffff;
2333
2334 start += sizeof(struct smbios_type_4);
2335
2336 memcpy((char *)start, "CPU " "\0" "" "\0" "", 7);
2337 ((char *)start)[4] = cpu_number + '0';
2338
2339 return start+7;
2340 }
2341
2342 /* Type 16 -- Physical Memory Array */
2343 static void *
2344 smbios_init_type_16(void *start, uint32_t memsize, int nr_mem_devs)
2345 {
2346 struct smbios_type_16 *p = (struct smbios_type_16*)start;
2347
2348 p->header.type = 16;
2349 p->header.length = sizeof(struct smbios_type_16);
2350 p->header.handle = 0x1000;
2351
2352 p->location = 0x01; /* other */
2353 p->use = 0x03; /* system memory */
2354 p->error_correction = 0x01; /* other */
2355 p->maximum_capacity = memsize * 1024;
2356 p->memory_error_information_handle = 0xfffe; /* none provided */
2357 p->number_of_memory_devices = nr_mem_devs;
2358
2359 start += sizeof(struct smbios_type_16);
2360 *((uint16_t *)start) = 0;
2361
2362 return start + 2;
2363 }
2364
2365 /* Type 17 -- Memory Device */
2366 static void *
2367 smbios_init_type_17(void *start, uint32_t memory_size_mb, int instance)
2368 {
2369 struct smbios_type_17 *p = (struct smbios_type_17 *)start;
2370
2371 p->header.type = 17;
2372 p->header.length = sizeof(struct smbios_type_17);
2373 p->header.handle = 0x1100 + instance;
2374
2375 p->physical_memory_array_handle = 0x1000;
2376 p->total_width = 64;
2377 p->data_width = 64;
2378 /* TODO: should assert in case something is wrong ASSERT((memory_size_mb & ~0x7fff) == 0); */
2379 p->size = memory_size_mb;
2380 p->form_factor = 0x09; /* DIMM */
2381 p->device_set = 0;
2382 p->device_locator_str = 1;
2383 p->bank_locator_str = 0;
2384 p->memory_type = 0x07; /* RAM */
2385 p->type_detail = 0;
2386
2387 start += sizeof(struct smbios_type_17);
2388 snprintf(start, 8, "DIMM %d", instance);
2389 start += strlen(start) + 1;
2390 *((uint8_t *)start) = 0;
2391
2392 return start+1;
2393 }
2394
2395 /* Type 19 -- Memory Array Mapped Address */
2396 static void *
2397 smbios_init_type_19(void *start, uint32_t memory_size_mb, int instance)
2398 {
2399 struct smbios_type_19 *p = (struct smbios_type_19 *)start;
2400
2401 p->header.type = 19;
2402 p->header.length = sizeof(struct smbios_type_19);
2403 p->header.handle = 0x1300 + instance;
2404
2405 p->starting_address = instance << 24;
2406 p->ending_address = p->starting_address + (memory_size_mb << 10) - 1;
2407 p->memory_array_handle = 0x1000;
2408 p->partition_width = 1;
2409
2410 start += sizeof(struct smbios_type_19);
2411 *((uint16_t *)start) = 0;
2412
2413 return start + 2;
2414 }
2415
2416 /* Type 20 -- Memory Device Mapped Address */
2417 static void *
2418 smbios_init_type_20(void *start, uint32_t memory_size_mb, int instance)
2419 {
2420 struct smbios_type_20 *p = (struct smbios_type_20 *)start;
2421
2422 p->header.type = 20;
2423 p->header.length = sizeof(struct smbios_type_20);
2424 p->header.handle = 0x1400 + instance;
2425
2426 p->starting_address = instance << 24;
2427 p->ending_address = p->starting_address + (memory_size_mb << 10) - 1;
2428 p->memory_device_handle = 0x1100 + instance;
2429 p->memory_array_mapped_address_handle = 0x1300 + instance;
2430 p->partition_row_position = 1;
2431 p->interleave_position = 0;
2432 p->interleaved_data_depth = 0;
2433
2434 start += sizeof(struct smbios_type_20);
2435
2436 *((uint16_t *)start) = 0;
2437 return start+2;
2438 }
2439
2440 /* Type 32 -- System Boot Information */
2441 static void *
2442 smbios_init_type_32(void *start)
2443 {
2444 struct smbios_type_32 *p = (struct smbios_type_32 *)start;
2445
2446 p->header.type = 32;
2447 p->header.length = sizeof(struct smbios_type_32);
2448 p->header.handle = 0x2000;
2449 memset(p->reserved, 0, 6);
2450 p->boot_status = 0; /* no errors detected */
2451
2452 start += sizeof(struct smbios_type_32);
2453 *((uint16_t *)start) = 0;
2454
2455 return start+2;
2456 }
2457
2458 /* Type 127 -- End of Table */
2459 static void *
2460 smbios_init_type_127(void *start)
2461 {
2462 struct smbios_type_127 *p = (struct smbios_type_127 *)start;
2463
2464 p->header.type = 127;
2465 p->header.length = sizeof(struct smbios_type_127);
2466 p->header.handle = 0x7f00;
2467
2468 start += sizeof(struct smbios_type_127);
2469 *((uint16_t *)start) = 0;
2470
2471 return start + 2;
2472 }
2473
2474 static int
2475 smbios_load_external(int type, char **p, unsigned *nr_structs,
2476 unsigned *max_struct_size)
2477 {
2478 #ifdef BX_QEMU
2479 static uint64_t used_bitmap[4] = { 0 };
2480 char *start = *p;
2481 int i;
2482
2483 /* Check if we've already reported these tables */
2484 if (used_bitmap[(type >> 6) & 0x3] & (1ULL << (type & 0x3f)))
2485 return 1;
2486
2487 /* Don't introduce spurious end markers */
2488 if (type == 127)
2489 return 0;
2490
2491 for (i = smbios_entries(); i > 0; i--) {
2492 struct smbios_table table;
2493 struct smbios_structure_header *header = (void *)*p;
2494 int string;
2495
2496 qemu_cfg_read((uint8_t *)&table, sizeof(struct smbios_header));
2497 table.header.length -= sizeof(struct smbios_header);
2498
2499 if (table.header.type != SMBIOS_TABLE_ENTRY) {
2500 while (table.header.length--)
2501 inb(QEMU_CFG_DATA_PORT);
2502 continue;
2503 }
2504
2505 qemu_cfg_read((uint8_t *)*p, sizeof(struct smbios_structure_header));
2506 table.header.length -= sizeof(struct smbios_structure_header);
2507
2508 if (header->type != type) {
2509 while (table.header.length--)
2510 inb(QEMU_CFG_DATA_PORT);
2511 continue;
2512 }
2513
2514 *p += sizeof(struct smbios_structure_header);
2515
2516 /* Entries end with a double NULL char, if there's a string at
2517 * the end (length is greater than formatted length), the string
2518 * terminator provides the first NULL. */
2519 string = header->length < table.header.length +
2520 sizeof(struct smbios_structure_header);
2521
2522 /* Read the rest and terminate the entry */
2523 qemu_cfg_read((uint8_t *)*p, table.header.length);
2524 *p += table.header.length;
2525 *((uint8_t*)*p) = 0;
2526 (*p)++;
2527 if (!string) {
2528 *((uint8_t*)*p) = 0;
2529 (*p)++;
2530 }
2531
2532 (*nr_structs)++;
2533 if (*p - (char *)header > *max_struct_size)
2534 *max_struct_size = *p - (char *)header;
2535 }
2536
2537 /* Mark that we've reported on this type */
2538 used_bitmap[(type >> 6) & 0x3] |= (1ULL << (type & 0x3f));
2539
2540 return (start != *p);
2541 #else /* !BX_QEMU */
2542 return 0;
2543 #endif
2544 }
2545
2546 void smbios_init(void)
2547 {
2548 unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
2549 char *start, *p, *q;
2550 int memsize = (ram_end == ram_size) ? ram_size / (1024 * 1024) :
2551 (ram_end - (1ull << 32) + ram_size) / (1024 * 1024);
2552 int i, nr_mem_devs;
2553
2554 #ifdef BX_USE_EBDA_TABLES
2555 ebda_cur_addr = align(ebda_cur_addr, 16);
2556 start = (void *)(ebda_cur_addr);
2557 #else
2558 bios_table_cur_addr = align(bios_table_cur_addr, 16);
2559 start = (void *)(bios_table_cur_addr);
2560 #endif
2561
2562 p = (char *)start + sizeof(struct smbios_entry_point);
2563
2564 #define add_struct(type, args...) do { \
2565 if (!smbios_load_external(type, &p, &nr_structs, &max_struct_size)) { \
2566 q = smbios_init_type_##type(args); \
2567 nr_structs++; \
2568 if ((q - p) > max_struct_size) \
2569 max_struct_size = q - p; \
2570 p = q; \
2571 } \
2572 } while (0)
2573
2574 add_struct(0, p);
2575 add_struct(1, p);
2576 add_struct(3, p);
2577 for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
2578 add_struct(4, p, cpu_num);
2579
2580 /* Each 'memory device' covers up to 16GB of address space. */
2581 nr_mem_devs = (memsize + 0x3fff) >> 14;
2582 add_struct(16, p, memsize, nr_mem_devs);
2583 for ( i = 0; i < nr_mem_devs; i++ )
2584 {
2585 uint32_t dev_memsize = ((i == (nr_mem_devs - 1))
2586 ? (((memsize-1) & 0x3fff)+1) : 0x4000);
2587 add_struct(17, p, dev_memsize, i);
2588 add_struct(19, p, dev_memsize, i);
2589 add_struct(20, p, dev_memsize, i);
2590 }
2591
2592 add_struct(32, p);
2593 /* Add any remaining provided entries before the end marker */
2594 for (i = 0; i < 256; i++)
2595 smbios_load_external(i, &p, &nr_structs, &max_struct_size);
2596 add_struct(127, p);
2597
2598 #undef add_struct
2599
2600 smbios_entry_point_init(
2601 start, max_struct_size,
2602 (p - (char *)start) - sizeof(struct smbios_entry_point),
2603 (uint32_t)(start + sizeof(struct smbios_entry_point)),
2604 nr_structs);
2605
2606 #ifdef BX_USE_EBDA_TABLES
2607 ebda_cur_addr += (p - (char *)start);
2608 #else
2609 bios_table_cur_addr += (p - (char *)start);
2610 #endif
2611
2612 BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
2613 }
2614
2615 static uint32_t find_resume_vector(void)
2616 {
2617 unsigned long addr, start, end;
2618
2619 #ifdef BX_USE_EBDA_TABLES
2620 start = align(ebda_cur_addr, 16);
2621 end = 0xa000 << 4;
2622 #else
2623 if (bios_table_cur_addr == 0)
2624 return 0;
2625 start = align(bios_table_cur_addr, 16);
2626 end = bios_table_end_addr;
2627 #endif
2628
2629 for (addr = start; addr < end; addr += 16) {
2630 if (!memcmp((void*)addr, "RSD PTR ", 8)) {
2631 struct rsdp_descriptor *rsdp = (void*)addr;
2632 struct rsdt_descriptor_rev1 *rsdt = (void*)rsdp->rsdt_physical_address;
2633 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[0];
2634 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
2635 return facs->firmware_waking_vector;
2636 }
2637 }
2638
2639 return 0;
2640 }
2641
2642 static void find_440fx(PCIDevice *d)
2643 {
2644 uint16_t vendor_id, device_id;
2645
2646 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2647 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2648
2649 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441)
2650 i440_pcidev = *d;
2651 }
2652
2653 static void reinit_piix4_pm(PCIDevice *d)
2654 {
2655 uint16_t vendor_id, device_id;
2656
2657 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2658 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2659
2660 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3)
2661 piix4_pm_enable(d);
2662 }
2663
2664 void rombios32_init(uint32_t *s3_resume_vector, uint8_t *shutdown_flag)
2665 {
2666 BX_INFO("Starting rombios32\n");
2667 BX_INFO("Shutdown flag %x\n", *shutdown_flag);
2668
2669 #ifdef BX_QEMU
2670 qemu_cfg_port = qemu_cfg_port_probe();
2671 #endif
2672
2673 init_smp_msrs();
2674
2675 ram_probe();
2676
2677 cpu_probe();
2678
2679 setup_mtrr();
2680
2681 smp_probe();
2682
2683 find_bios_table_area();
2684
2685 if (*shutdown_flag == 0xfe) {
2686 /* redirect bios read access to RAM */
2687 pci_for_each_device(find_440fx);
2688 bios_lock_shadow_ram(); /* bios is already copied */
2689 *s3_resume_vector = find_resume_vector();
2690 if (!*s3_resume_vector) {
2691 BX_INFO("This is S3 resume but wakeup vector is NULL\n");
2692 } else {
2693 BX_INFO("S3 resume vector %p\n", *s3_resume_vector);
2694 pci_for_each_device(reinit_piix4_pm);
2695 }
2696 return;
2697 }
2698
2699 pci_bios_init();
2700
2701 if (bios_table_cur_addr != 0) {
2702
2703 mptable_init();
2704
2705 smbios_init();
2706
2707 if (acpi_enabled)
2708 acpi_bios_init();
2709
2710 bios_lock_shadow_ram();
2711
2712 BX_INFO("bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
2713 if (bios_table_cur_addr > bios_table_end_addr)
2714 BX_PANIC("bios_table_end_addr overflow!\n");
2715 #ifdef BX_USE_EBDA_TABLES
2716 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
2717 if (ebda_cur_addr > 0xA0000)
2718 BX_PANIC("ebda_cur_addr overflow!\n");
2719 #endif
2720 }
2721 }
Patches shipped by Fedora