hw/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3 /* PC-style peripherals (also used by other machines).  */
   4
   5 /* serial.c */
   6
   7 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
   8                          CharDriverState *chr);
   9 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
  10                              qemu_irq irq, int baudbase,
  11                              CharDriverState *chr, int ioregister);
  12 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
  13 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
  14 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
  15 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
  16 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
  17 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
  18
  19 /* parallel.c */
  20
  21 typedef struct ParallelState ParallelState;
  22 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
  23 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
  24
  25 /* i8259.c */
  26
  27 typedef struct PicState2 PicState2;
  28 extern PicState2 *isa_pic;
  29 void pic_set_irq(int irq, int level);
  30 void pic_set_irq_new(void *opaque, int irq, int level);
  31 qemu_irq *i8259_init(qemu_irq parent_irq);
  32 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
  33                           void *alt_irq_opaque);
  34 int pic_read_irq(PicState2 *s);
  35 void pic_update_irq(PicState2 *s);
  36 uint32_t pic_intack_read(PicState2 *s);
  37 void pic_info(void);
  38 void irq_info(void);
  39
  40 /* APIC */
  41 typedef struct IOAPICState IOAPICState;
  42
  43 int apic_init(CPUState *env);
  44 int apic_accept_pic_intr(CPUState *env);
  45 void apic_deliver_pic_intr(CPUState *env, int level);
  46 int apic_get_interrupt(CPUState *env);
  47 IOAPICState *ioapic_init(void);
  48 void ioapic_set_irq(void *opaque, int vector, int level);
  49
  50 /* i8254.c */
  51
  52 #define PIT_FREQ 1193182
  53
  54 typedef struct PITState PITState;
  55
  56 PITState *pit_init(int base, qemu_irq irq);
  57 void pit_set_gate(PITState *pit, int channel, int val);
  58 int pit_get_gate(PITState *pit, int channel);
  59 int pit_get_initial_count(PITState *pit, int channel);
  60 int pit_get_mode(PITState *pit, int channel);
  61 int pit_get_out(PITState *pit, int channel, int64_t current_time);
  62
  63 /* i8254-kvm.c */
  64
  65 PITState *kvm_pit_init(int base, qemu_irq irq);
  66
  67 /* vmport.c */
  68 void vmport_init(void);
  69 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
  70
  71 /* vmmouse.c */
  72 void *vmmouse_init(void *m);
  73
  74 /* pckbd.c */
  75
  76 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
  77 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
  78                    target_phys_addr_t base, int it_shift);
  79
  80 /* mc146818rtc.c */
  81
  82 typedef struct RTCState RTCState;
  83
  84 RTCState *rtc_init(int base, qemu_irq irq);
  85 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
  86 void rtc_set_memory(RTCState *s, int addr, int val);
  87 void rtc_set_date(RTCState *s, const struct tm *tm);
  88
  89 /* pc.c */
  90 extern int fd_bootchk;
  91
  92 void ioport_set_a20(int enable);
  93 int ioport_get_a20(void);
  94 CPUState *pc_new_cpu(int cpu, const char *cpu_model, int pci_enabled);
  95
  96 /* acpi.c */
  97 extern int acpi_enabled;
  98 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
  99                        qemu_irq sci_irq);
 100 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 101 void acpi_bios_init(void);
 102
 103 /* pcspk.c */
 104 void pcspk_init(PITState *);
 105 int pcspk_audio_init(AudioState *, qemu_irq *pic);
 106
 107 /* piix_pci.c */
 108 /* config space register for IRQ routing */
 109 #define PIIX_CONFIG_IRQ_ROUTE 0x60
 110
 111 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
 112 void i440fx_set_smm(PCIDevice *d, int val);
 113 int piix3_init(PCIBus *bus, int devfn);
 114 void i440fx_init_memory_mappings(PCIDevice *d);
 115
 116 extern PCIDevice *piix4_dev;
 117 int piix4_init(PCIBus *bus, int devfn);
 118
 119 int piix_get_irq(int pin);
 120
 121 int ipf_map_irq(PCIDevice *pci_dev, int irq_num);
 122
 123 /* vga.c */
 124 enum vga_retrace_method {
 125     VGA_RETRACE_DUMB,
 126     VGA_RETRACE_PRECISE
 127 };
 128
 129 extern enum vga_retrace_method vga_retrace_method;
 130
 131 #ifndef TARGET_SPARC
 132 #define VGA_RAM_SIZE (16 * 1024 * 1024)
 133 #else
 134 #define VGA_RAM_SIZE (17 * 1024 * 1024)
 135 #endif
 136
 137 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
 138                  unsigned long vga_ram_offset, int vga_ram_size);
 139 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 140                  unsigned long vga_ram_offset, int vga_ram_size,
 141                  unsigned long vga_bios_offset, int vga_bios_size);
 142 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
 143                     unsigned long vga_ram_offset, int vga_ram_size,
 144                     target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
 145                     int it_shift);
 146
 147 /* cirrus_vga.c */
 148 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 149                          ram_addr_t vga_ram_offset, int vga_ram_size);
 150 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
 151                          ram_addr_t vga_ram_offset, int vga_ram_size);
 152
 153 /* ide.c */
 154 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
 155                   BlockDriverState *hd0, BlockDriverState *hd1);
 156 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
 157                          int secondary_ide_enabled);
 158 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 159                         qemu_irq *pic);
 160 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 161                         qemu_irq *pic);
 162
 163 /* ne2000.c */
 164
 165 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
 166
 167 /* extboot.c */
 168
 169 void extboot_init(BlockDriverState *bs, int cmd);
 170
 171 /* virtio-balloon.h */
 172 void *virtio_balloon_init(PCIBus *bus);
 173
 174 #endif