libkvm: accept EAGAIN to restart kvm_run
[qemu-kvm/fedora.git] / cpu-exec.c
blobe1293add2cca927118ff642f17034fec93009d0b
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
38 #ifdef USE_KVM
39 #include "qemu-kvm.h"
40 extern int kvm_allowed;
41 #endif
43 int tb_invalidated_flag;
45 //#define DEBUG_EXEC
46 //#define DEBUG_SIGNAL
48 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
49 /* XXX: unify with i386 target */
50 void cpu_loop_exit(void)
52 longjmp(env->jmp_env, 1);
54 #endif
55 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
56 #define reg_T2
57 #endif
59 /* exit the current TB from a signal handler. The host registers are
60 restored in a state compatible with the CPU emulator
62 void cpu_resume_from_signal(CPUState *env1, void *puc)
64 #if !defined(CONFIG_SOFTMMU)
65 struct ucontext *uc = puc;
66 #endif
68 env = env1;
70 /* XXX: restore cpu registers saved in host registers */
72 #if !defined(CONFIG_SOFTMMU)
73 if (puc) {
74 /* XXX: use siglongjmp ? */
75 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
77 #endif
78 longjmp(env->jmp_env, 1);
82 static TranslationBlock *tb_find_slow(target_ulong pc,
83 target_ulong cs_base,
84 unsigned int flags)
86 TranslationBlock *tb, **ptb1;
87 int code_gen_size;
88 unsigned int h;
89 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
90 uint8_t *tc_ptr;
92 spin_lock(&tb_lock);
94 tb_invalidated_flag = 0;
96 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
98 /* find translated block using physical mappings */
99 phys_pc = get_phys_addr_code(env, pc);
100 phys_page1 = phys_pc & TARGET_PAGE_MASK;
101 phys_page2 = -1;
102 h = tb_phys_hash_func(phys_pc);
103 ptb1 = &tb_phys_hash[h];
104 for(;;) {
105 tb = *ptb1;
106 if (!tb)
107 goto not_found;
108 if (tb->pc == pc &&
109 tb->page_addr[0] == phys_page1 &&
110 tb->cs_base == cs_base &&
111 tb->flags == flags) {
112 /* check next page if needed */
113 if (tb->page_addr[1] != -1) {
114 virt_page2 = (pc & TARGET_PAGE_MASK) +
115 TARGET_PAGE_SIZE;
116 phys_page2 = get_phys_addr_code(env, virt_page2);
117 if (tb->page_addr[1] == phys_page2)
118 goto found;
119 } else {
120 goto found;
123 ptb1 = &tb->phys_hash_next;
125 not_found:
126 /* if no translated code available, then translate it now */
127 tb = tb_alloc(pc);
128 if (!tb) {
129 /* flush must be done */
130 tb_flush(env);
131 /* cannot fail at this point */
132 tb = tb_alloc(pc);
133 /* don't forget to invalidate previous TB info */
134 tb_invalidated_flag = 1;
136 tc_ptr = code_gen_ptr;
137 tb->tc_ptr = tc_ptr;
138 tb->cs_base = cs_base;
139 tb->flags = flags;
140 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
141 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
143 /* check next page if needed */
144 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
145 phys_page2 = -1;
146 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
147 phys_page2 = get_phys_addr_code(env, virt_page2);
149 tb_link_phys(tb, phys_pc, phys_page2);
151 found:
152 /* we add the TB in the virtual pc hash table */
153 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
154 spin_unlock(&tb_lock);
155 return tb;
158 static inline TranslationBlock *tb_find_fast(void)
160 TranslationBlock *tb;
161 target_ulong cs_base, pc;
162 unsigned int flags;
164 /* we record a subset of the CPU state. It will
165 always be the same before a given translated block
166 is executed. */
167 #if defined(TARGET_I386)
168 flags = env->hflags;
169 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
170 cs_base = env->segs[R_CS].base;
171 pc = cs_base + env->eip;
172 #elif defined(TARGET_ARM)
173 flags = env->thumb | (env->vfp.vec_len << 1)
174 | (env->vfp.vec_stride << 4);
175 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
176 flags |= (1 << 6);
177 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
178 flags |= (1 << 7);
179 cs_base = 0;
180 pc = env->regs[15];
181 #elif defined(TARGET_SPARC)
182 #ifdef TARGET_SPARC64
183 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
184 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
185 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
186 #else
187 // FPU enable . MMU enabled . MMU no-fault . Supervisor
188 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
189 | env->psrs;
190 #endif
191 cs_base = env->npc;
192 pc = env->pc;
193 #elif defined(TARGET_PPC)
194 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
195 (msr_se << MSR_SE) | (msr_le << MSR_LE);
196 cs_base = 0;
197 pc = env->nip;
198 #elif defined(TARGET_MIPS)
199 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
200 cs_base = 0;
201 pc = env->PC;
202 #elif defined(TARGET_M68K)
203 flags = env->fpcr & M68K_FPCR_PREC;
204 cs_base = 0;
205 pc = env->pc;
206 #elif defined(TARGET_SH4)
207 flags = env->sr & (SR_MD | SR_RB);
208 cs_base = 0; /* XXXXX */
209 pc = env->pc;
210 #else
211 #error unsupported CPU
212 #endif
213 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
214 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
215 tb->flags != flags, 0)) {
216 tb = tb_find_slow(pc, cs_base, flags);
217 /* Note: we do it here to avoid a gcc bug on Mac OS X when
218 doing it in tb_find_slow */
219 if (tb_invalidated_flag) {
220 /* as some TB could have been invalidated because
221 of memory exceptions while generating the code, we
222 must recompute the hash index here */
223 T0 = 0;
226 return tb;
230 /* main execution loop */
232 int cpu_exec(CPUState *env1)
234 #define DECLARE_HOST_REGS 1
235 #include "hostregs_helper.h"
236 #if defined(TARGET_SPARC)
237 #if defined(reg_REGWPTR)
238 uint32_t *saved_regwptr;
239 #endif
240 #endif
241 #if defined(__sparc__) && !defined(HOST_SOLARIS)
242 int saved_i7;
243 target_ulong tmp_T0;
244 #endif
245 int ret, interrupt_request;
246 void (*gen_func)(void);
247 TranslationBlock *tb;
248 uint8_t *tc_ptr;
250 #if defined(TARGET_I386)
251 /* handle exit of HALTED state */
252 if (env1->hflags & HF_HALTED_MASK) {
253 /* disable halt condition */
254 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
255 (env1->eflags & IF_MASK)) {
256 env1->hflags &= ~HF_HALTED_MASK;
257 } else {
258 return EXCP_HALTED;
261 #elif defined(TARGET_PPC)
262 if (env1->halted) {
263 if (env1->msr[MSR_EE] &&
264 (env1->interrupt_request &
265 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
266 env1->halted = 0;
267 } else {
268 return EXCP_HALTED;
271 #elif defined(TARGET_SPARC)
272 if (env1->halted) {
273 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
274 (env1->psret != 0)) {
275 env1->halted = 0;
276 } else {
277 return EXCP_HALTED;
280 #elif defined(TARGET_ARM)
281 if (env1->halted) {
282 /* An interrupt wakes the CPU even if the I and F CPSR bits are
283 set. */
284 if (env1->interrupt_request
285 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
286 env1->halted = 0;
287 } else {
288 return EXCP_HALTED;
291 #elif defined(TARGET_MIPS)
292 if (env1->halted) {
293 if (env1->interrupt_request &
294 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
295 env1->halted = 0;
296 } else {
297 return EXCP_HALTED;
300 #endif
302 cpu_single_env = env1;
304 /* first we save global registers */
305 #define SAVE_HOST_REGS 1
306 #include "hostregs_helper.h"
307 env = env1;
308 #if defined(__sparc__) && !defined(HOST_SOLARIS)
309 /* we also save i7 because longjmp may not restore it */
310 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
311 #endif
313 #if defined(TARGET_I386)
314 env_to_regs();
315 /* put eflags in CPU temporary format */
316 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
317 DF = 1 - (2 * ((env->eflags >> 10) & 1));
318 CC_OP = CC_OP_EFLAGS;
319 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
320 #elif defined(TARGET_ARM)
321 #elif defined(TARGET_SPARC)
322 #if defined(reg_REGWPTR)
323 saved_regwptr = REGWPTR;
324 #endif
325 #elif defined(TARGET_PPC)
326 #elif defined(TARGET_M68K)
327 env->cc_op = CC_OP_FLAGS;
328 env->cc_dest = env->sr & 0xf;
329 env->cc_x = (env->sr >> 4) & 1;
330 #elif defined(TARGET_MIPS)
331 #elif defined(TARGET_SH4)
332 /* XXXXX */
333 #else
334 #error unsupported target CPU
335 #endif
336 env->exception_index = -1;
338 /* prepare setjmp context for exception handling */
339 for(;;) {
340 if (setjmp(env->jmp_env) == 0) {
341 env->current_tb = NULL;
342 /* if an exception is pending, we execute it here */
343 if (env->exception_index >= 0) {
344 if (env->exception_index >= EXCP_INTERRUPT) {
345 /* exit request from the cpu execution loop */
346 ret = env->exception_index;
347 break;
348 } else if (env->user_mode_only) {
349 /* if user mode only, we simulate a fake exception
350 which will be handled outside the cpu execution
351 loop */
352 #if defined(TARGET_I386)
353 do_interrupt_user(env->exception_index,
354 env->exception_is_int,
355 env->error_code,
356 env->exception_next_eip);
357 #endif
358 ret = env->exception_index;
359 break;
360 } else {
361 #if defined(TARGET_I386)
362 /* simulate a real cpu exception. On i386, it can
363 trigger new exceptions, but we do not handle
364 double or triple faults yet. */
365 do_interrupt(env->exception_index,
366 env->exception_is_int,
367 env->error_code,
368 env->exception_next_eip, 0);
369 #elif defined(TARGET_PPC)
370 do_interrupt(env);
371 #elif defined(TARGET_MIPS)
372 do_interrupt(env);
373 #elif defined(TARGET_SPARC)
374 do_interrupt(env->exception_index);
375 #elif defined(TARGET_ARM)
376 do_interrupt(env);
377 #elif defined(TARGET_SH4)
378 do_interrupt(env);
379 #endif
381 env->exception_index = -1;
383 #ifdef USE_KQEMU
384 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
385 int ret;
386 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
387 ret = kqemu_cpu_exec(env);
388 /* put eflags in CPU temporary format */
389 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
390 DF = 1 - (2 * ((env->eflags >> 10) & 1));
391 CC_OP = CC_OP_EFLAGS;
392 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
393 if (ret == 1) {
394 /* exception */
395 longjmp(env->jmp_env, 1);
396 } else if (ret == 2) {
397 /* softmmu execution needed */
398 } else {
399 if (env->interrupt_request != 0) {
400 /* hardware interrupt will be executed just after */
401 } else {
402 /* otherwise, we restart */
403 longjmp(env->jmp_env, 1);
407 #endif
409 #ifdef USE_KVM
410 if (kvm_allowed) {
411 kvm_cpu_exec(env);
412 longjmp(env->jmp_env, 1);
414 #endif
415 T0 = 0; /* force lookup of first TB */
416 for(;;) {
417 #if defined(__sparc__) && !defined(HOST_SOLARIS)
418 /* g1 can be modified by some libc? functions */
419 tmp_T0 = T0;
420 #endif
421 interrupt_request = env->interrupt_request;
422 if (__builtin_expect(interrupt_request, 0)) {
423 #if defined(TARGET_I386)
424 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
425 !(env->hflags & HF_SMM_MASK)) {
426 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
427 do_smm_enter();
428 #if defined(__sparc__) && !defined(HOST_SOLARIS)
429 tmp_T0 = 0;
430 #else
431 T0 = 0;
432 #endif
433 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
434 (env->eflags & IF_MASK) &&
435 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
436 int intno;
437 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
438 intno = cpu_get_pic_interrupt(env);
439 if (loglevel & CPU_LOG_TB_IN_ASM) {
440 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
442 do_interrupt(intno, 0, 0, 0, 1);
443 /* ensure that no TB jump will be modified as
444 the program flow was changed */
445 #if defined(__sparc__) && !defined(HOST_SOLARIS)
446 tmp_T0 = 0;
447 #else
448 T0 = 0;
449 #endif
451 #elif defined(TARGET_PPC)
452 #if 0
453 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
454 cpu_ppc_reset(env);
456 #endif
457 if (msr_ee != 0) {
458 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
459 /* Raise it */
460 env->exception_index = EXCP_EXTERNAL;
461 env->error_code = 0;
462 do_interrupt(env);
463 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
464 #if defined(__sparc__) && !defined(HOST_SOLARIS)
465 tmp_T0 = 0;
466 #else
467 T0 = 0;
468 #endif
469 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
470 /* Raise it */
471 env->exception_index = EXCP_DECR;
472 env->error_code = 0;
473 do_interrupt(env);
474 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
475 #if defined(__sparc__) && !defined(HOST_SOLARIS)
476 tmp_T0 = 0;
477 #else
478 T0 = 0;
479 #endif
482 #elif defined(TARGET_MIPS)
483 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
484 (env->CP0_Status & (1 << CP0St_IE)) &&
485 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
486 !(env->hflags & MIPS_HFLAG_EXL) &&
487 !(env->hflags & MIPS_HFLAG_ERL) &&
488 !(env->hflags & MIPS_HFLAG_DM)) {
489 /* Raise it */
490 env->exception_index = EXCP_EXT_INTERRUPT;
491 env->error_code = 0;
492 do_interrupt(env);
493 #if defined(__sparc__) && !defined(HOST_SOLARIS)
494 tmp_T0 = 0;
495 #else
496 T0 = 0;
497 #endif
499 #elif defined(TARGET_SPARC)
500 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
501 (env->psret != 0)) {
502 int pil = env->interrupt_index & 15;
503 int type = env->interrupt_index & 0xf0;
505 if (((type == TT_EXTINT) &&
506 (pil == 15 || pil > env->psrpil)) ||
507 type != TT_EXTINT) {
508 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
509 do_interrupt(env->interrupt_index);
510 env->interrupt_index = 0;
511 #if defined(__sparc__) && !defined(HOST_SOLARIS)
512 tmp_T0 = 0;
513 #else
514 T0 = 0;
515 #endif
517 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
518 //do_interrupt(0, 0, 0, 0, 0);
519 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
520 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
521 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
522 env->halted = 1;
523 env->exception_index = EXCP_HLT;
524 cpu_loop_exit();
526 #elif defined(TARGET_ARM)
527 if (interrupt_request & CPU_INTERRUPT_FIQ
528 && !(env->uncached_cpsr & CPSR_F)) {
529 env->exception_index = EXCP_FIQ;
530 do_interrupt(env);
532 if (interrupt_request & CPU_INTERRUPT_HARD
533 && !(env->uncached_cpsr & CPSR_I)) {
534 env->exception_index = EXCP_IRQ;
535 do_interrupt(env);
537 #elif defined(TARGET_SH4)
538 /* XXXXX */
539 #endif
540 /* Don't use the cached interupt_request value,
541 do_interrupt may have updated the EXITTB flag. */
542 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
543 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
544 /* ensure that no TB jump will be modified as
545 the program flow was changed */
546 #if defined(__sparc__) && !defined(HOST_SOLARIS)
547 tmp_T0 = 0;
548 #else
549 T0 = 0;
550 #endif
552 if (interrupt_request & CPU_INTERRUPT_EXIT) {
553 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
554 env->exception_index = EXCP_INTERRUPT;
555 cpu_loop_exit();
558 #ifdef DEBUG_EXEC
559 if ((loglevel & CPU_LOG_TB_CPU)) {
560 #if defined(TARGET_I386)
561 /* restore flags in standard format */
562 #ifdef reg_EAX
563 env->regs[R_EAX] = EAX;
564 #endif
565 #ifdef reg_EBX
566 env->regs[R_EBX] = EBX;
567 #endif
568 #ifdef reg_ECX
569 env->regs[R_ECX] = ECX;
570 #endif
571 #ifdef reg_EDX
572 env->regs[R_EDX] = EDX;
573 #endif
574 #ifdef reg_ESI
575 env->regs[R_ESI] = ESI;
576 #endif
577 #ifdef reg_EDI
578 env->regs[R_EDI] = EDI;
579 #endif
580 #ifdef reg_EBP
581 env->regs[R_EBP] = EBP;
582 #endif
583 #ifdef reg_ESP
584 env->regs[R_ESP] = ESP;
585 #endif
586 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
587 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
588 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
589 #elif defined(TARGET_ARM)
590 cpu_dump_state(env, logfile, fprintf, 0);
591 #elif defined(TARGET_SPARC)
592 REGWPTR = env->regbase + (env->cwp * 16);
593 env->regwptr = REGWPTR;
594 cpu_dump_state(env, logfile, fprintf, 0);
595 #elif defined(TARGET_PPC)
596 cpu_dump_state(env, logfile, fprintf, 0);
597 #elif defined(TARGET_M68K)
598 cpu_m68k_flush_flags(env, env->cc_op);
599 env->cc_op = CC_OP_FLAGS;
600 env->sr = (env->sr & 0xffe0)
601 | env->cc_dest | (env->cc_x << 4);
602 cpu_dump_state(env, logfile, fprintf, 0);
603 #elif defined(TARGET_MIPS)
604 cpu_dump_state(env, logfile, fprintf, 0);
605 #elif defined(TARGET_SH4)
606 cpu_dump_state(env, logfile, fprintf, 0);
607 #else
608 #error unsupported target CPU
609 #endif
611 #endif
612 tb = tb_find_fast();
613 #ifdef DEBUG_EXEC
614 if ((loglevel & CPU_LOG_EXEC)) {
615 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
616 (long)tb->tc_ptr, tb->pc,
617 lookup_symbol(tb->pc));
619 #endif
620 #if defined(__sparc__) && !defined(HOST_SOLARIS)
621 T0 = tmp_T0;
622 #endif
623 /* see if we can patch the calling TB. When the TB
624 spans two pages, we cannot safely do a direct
625 jump. */
627 if (T0 != 0 &&
628 #if USE_KQEMU
629 (env->kqemu_enabled != 2) &&
630 #endif
631 tb->page_addr[1] == -1
632 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
633 && (tb->cflags & CF_CODE_COPY) ==
634 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
635 #endif
637 spin_lock(&tb_lock);
638 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
639 #if defined(USE_CODE_COPY)
640 /* propagates the FP use info */
641 ((TranslationBlock *)(T0 & ~3))->cflags |=
642 (tb->cflags & CF_FP_USED);
643 #endif
644 spin_unlock(&tb_lock);
647 tc_ptr = tb->tc_ptr;
648 env->current_tb = tb;
649 /* execute the generated code */
650 gen_func = (void *)tc_ptr;
651 #if defined(__sparc__)
652 __asm__ __volatile__("call %0\n\t"
653 "mov %%o7,%%i0"
654 : /* no outputs */
655 : "r" (gen_func)
656 : "i0", "i1", "i2", "i3", "i4", "i5",
657 "l0", "l1", "l2", "l3", "l4", "l5",
658 "l6", "l7");
659 #elif defined(__arm__)
660 asm volatile ("mov pc, %0\n\t"
661 ".global exec_loop\n\t"
662 "exec_loop:\n\t"
663 : /* no outputs */
664 : "r" (gen_func)
665 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
666 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
668 if (!(tb->cflags & CF_CODE_COPY)) {
669 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
670 save_native_fp_state(env);
672 gen_func();
673 } else {
674 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
675 restore_native_fp_state(env);
677 /* we work with native eflags */
678 CC_SRC = cc_table[CC_OP].compute_all();
679 CC_OP = CC_OP_EFLAGS;
680 asm(".globl exec_loop\n"
681 "\n"
682 "debug1:\n"
683 " pushl %%ebp\n"
684 " fs movl %10, %9\n"
685 " fs movl %11, %%eax\n"
686 " andl $0x400, %%eax\n"
687 " fs orl %8, %%eax\n"
688 " pushl %%eax\n"
689 " popf\n"
690 " fs movl %%esp, %12\n"
691 " fs movl %0, %%eax\n"
692 " fs movl %1, %%ecx\n"
693 " fs movl %2, %%edx\n"
694 " fs movl %3, %%ebx\n"
695 " fs movl %4, %%esp\n"
696 " fs movl %5, %%ebp\n"
697 " fs movl %6, %%esi\n"
698 " fs movl %7, %%edi\n"
699 " fs jmp *%9\n"
700 "exec_loop:\n"
701 " fs movl %%esp, %4\n"
702 " fs movl %12, %%esp\n"
703 " fs movl %%eax, %0\n"
704 " fs movl %%ecx, %1\n"
705 " fs movl %%edx, %2\n"
706 " fs movl %%ebx, %3\n"
707 " fs movl %%ebp, %5\n"
708 " fs movl %%esi, %6\n"
709 " fs movl %%edi, %7\n"
710 " pushf\n"
711 " popl %%eax\n"
712 " movl %%eax, %%ecx\n"
713 " andl $0x400, %%ecx\n"
714 " shrl $9, %%ecx\n"
715 " andl $0x8d5, %%eax\n"
716 " fs movl %%eax, %8\n"
717 " movl $1, %%eax\n"
718 " subl %%ecx, %%eax\n"
719 " fs movl %%eax, %11\n"
720 " fs movl %9, %%ebx\n" /* get T0 value */
721 " popl %%ebp\n"
723 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
724 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
725 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
726 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
727 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
728 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
729 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
730 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
731 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
732 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
733 "a" (gen_func),
734 "m" (*(uint8_t *)offsetof(CPUState, df)),
735 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
736 : "%ecx", "%edx"
740 #elif defined(__ia64)
741 struct fptr {
742 void *ip;
743 void *gp;
744 } fp;
746 fp.ip = tc_ptr;
747 fp.gp = code_gen_buffer + 2 * (1 << 20);
748 (*(void (*)(void)) &fp)();
749 #else
750 gen_func();
751 #endif
752 env->current_tb = NULL;
753 /* reset soft MMU for next block (it can currently
754 only be set by a memory fault) */
755 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
756 if (env->hflags & HF_SOFTMMU_MASK) {
757 env->hflags &= ~HF_SOFTMMU_MASK;
758 /* do not allow linking to another block */
759 T0 = 0;
761 #endif
762 #if defined(USE_KQEMU)
763 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
764 if (kqemu_is_ok(env) &&
765 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
766 cpu_loop_exit();
768 #endif
770 } else {
771 env_to_regs();
773 } /* for(;;) */
776 #if defined(TARGET_I386)
777 #if defined(USE_CODE_COPY)
778 if (env->native_fp_regs) {
779 save_native_fp_state(env);
781 #endif
782 /* restore flags in standard format */
783 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
784 #elif defined(TARGET_ARM)
785 /* XXX: Save/restore host fpu exception state?. */
786 #elif defined(TARGET_SPARC)
787 #if defined(reg_REGWPTR)
788 REGWPTR = saved_regwptr;
789 #endif
790 #elif defined(TARGET_PPC)
791 #elif defined(TARGET_M68K)
792 cpu_m68k_flush_flags(env, env->cc_op);
793 env->cc_op = CC_OP_FLAGS;
794 env->sr = (env->sr & 0xffe0)
795 | env->cc_dest | (env->cc_x << 4);
796 #elif defined(TARGET_MIPS)
797 #elif defined(TARGET_SH4)
798 /* XXXXX */
799 #else
800 #error unsupported target CPU
801 #endif
803 /* restore global registers */
804 #if defined(__sparc__) && !defined(HOST_SOLARIS)
805 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
806 #endif
807 #include "hostregs_helper.h"
809 /* fail safe : never use cpu_single_env outside cpu_exec() */
810 cpu_single_env = NULL;
811 return ret;
814 /* must only be called from the generated code as an exception can be
815 generated */
816 void tb_invalidate_page_range(target_ulong start, target_ulong end)
818 /* XXX: cannot enable it yet because it yields to MMU exception
819 where NIP != read address on PowerPC */
820 #if 0
821 target_ulong phys_addr;
822 phys_addr = get_phys_addr_code(env, start);
823 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
824 #endif
827 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
829 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
831 CPUX86State *saved_env;
833 saved_env = env;
834 env = s;
835 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
836 selector &= 0xffff;
837 cpu_x86_load_seg_cache(env, seg_reg, selector,
838 (selector << 4), 0xffff, 0);
839 } else {
840 load_seg(seg_reg, selector);
842 env = saved_env;
845 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
847 CPUX86State *saved_env;
849 saved_env = env;
850 env = s;
852 helper_fsave((target_ulong)ptr, data32);
854 env = saved_env;
857 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
859 CPUX86State *saved_env;
861 saved_env = env;
862 env = s;
864 helper_frstor((target_ulong)ptr, data32);
866 env = saved_env;
869 #endif /* TARGET_I386 */
871 #if !defined(CONFIG_SOFTMMU)
873 #if defined(TARGET_I386)
875 /* 'pc' is the host PC at which the exception was raised. 'address' is
876 the effective address of the memory exception. 'is_write' is 1 if a
877 write caused the exception and otherwise 0'. 'old_set' is the
878 signal set which should be restored */
879 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
880 int is_write, sigset_t *old_set,
881 void *puc)
883 TranslationBlock *tb;
884 int ret;
886 if (cpu_single_env)
887 env = cpu_single_env; /* XXX: find a correct solution for multithread */
888 #if defined(DEBUG_SIGNAL)
889 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
890 pc, address, is_write, *(unsigned long *)old_set);
891 #endif
892 /* XXX: locking issue */
893 if (is_write && page_unprotect(h2g(address), pc, puc)) {
894 return 1;
897 /* see if it is an MMU fault */
898 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
899 ((env->hflags & HF_CPL_MASK) == 3), 0);
900 if (ret < 0)
901 return 0; /* not an MMU fault */
902 if (ret == 0)
903 return 1; /* the MMU fault was handled without causing real CPU fault */
904 /* now we have a real cpu fault */
905 tb = tb_find_pc(pc);
906 if (tb) {
907 /* the PC is inside the translated code. It means that we have
908 a virtual CPU fault */
909 cpu_restore_state(tb, env, pc, puc);
911 if (ret == 1) {
912 #if 0
913 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
914 env->eip, env->cr[2], env->error_code);
915 #endif
916 /* we restore the process signal mask as the sigreturn should
917 do it (XXX: use sigsetjmp) */
918 sigprocmask(SIG_SETMASK, old_set, NULL);
919 raise_exception_err(env->exception_index, env->error_code);
920 } else {
921 /* activate soft MMU for this block */
922 env->hflags |= HF_SOFTMMU_MASK;
923 cpu_resume_from_signal(env, puc);
925 /* never comes here */
926 return 1;
929 #elif defined(TARGET_ARM)
930 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
931 int is_write, sigset_t *old_set,
932 void *puc)
934 TranslationBlock *tb;
935 int ret;
937 if (cpu_single_env)
938 env = cpu_single_env; /* XXX: find a correct solution for multithread */
939 #if defined(DEBUG_SIGNAL)
940 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
941 pc, address, is_write, *(unsigned long *)old_set);
942 #endif
943 /* XXX: locking issue */
944 if (is_write && page_unprotect(h2g(address), pc, puc)) {
945 return 1;
947 /* see if it is an MMU fault */
948 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
949 if (ret < 0)
950 return 0; /* not an MMU fault */
951 if (ret == 0)
952 return 1; /* the MMU fault was handled without causing real CPU fault */
953 /* now we have a real cpu fault */
954 tb = tb_find_pc(pc);
955 if (tb) {
956 /* the PC is inside the translated code. It means that we have
957 a virtual CPU fault */
958 cpu_restore_state(tb, env, pc, puc);
960 /* we restore the process signal mask as the sigreturn should
961 do it (XXX: use sigsetjmp) */
962 sigprocmask(SIG_SETMASK, old_set, NULL);
963 cpu_loop_exit();
965 #elif defined(TARGET_SPARC)
966 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
967 int is_write, sigset_t *old_set,
968 void *puc)
970 TranslationBlock *tb;
971 int ret;
973 if (cpu_single_env)
974 env = cpu_single_env; /* XXX: find a correct solution for multithread */
975 #if defined(DEBUG_SIGNAL)
976 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
977 pc, address, is_write, *(unsigned long *)old_set);
978 #endif
979 /* XXX: locking issue */
980 if (is_write && page_unprotect(h2g(address), pc, puc)) {
981 return 1;
983 /* see if it is an MMU fault */
984 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
985 if (ret < 0)
986 return 0; /* not an MMU fault */
987 if (ret == 0)
988 return 1; /* the MMU fault was handled without causing real CPU fault */
989 /* now we have a real cpu fault */
990 tb = tb_find_pc(pc);
991 if (tb) {
992 /* the PC is inside the translated code. It means that we have
993 a virtual CPU fault */
994 cpu_restore_state(tb, env, pc, puc);
996 /* we restore the process signal mask as the sigreturn should
997 do it (XXX: use sigsetjmp) */
998 sigprocmask(SIG_SETMASK, old_set, NULL);
999 cpu_loop_exit();
1001 #elif defined (TARGET_PPC)
1002 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1003 int is_write, sigset_t *old_set,
1004 void *puc)
1006 TranslationBlock *tb;
1007 int ret;
1009 if (cpu_single_env)
1010 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1011 #if defined(DEBUG_SIGNAL)
1012 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1013 pc, address, is_write, *(unsigned long *)old_set);
1014 #endif
1015 /* XXX: locking issue */
1016 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1017 return 1;
1020 /* see if it is an MMU fault */
1021 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1022 if (ret < 0)
1023 return 0; /* not an MMU fault */
1024 if (ret == 0)
1025 return 1; /* the MMU fault was handled without causing real CPU fault */
1027 /* now we have a real cpu fault */
1028 tb = tb_find_pc(pc);
1029 if (tb) {
1030 /* the PC is inside the translated code. It means that we have
1031 a virtual CPU fault */
1032 cpu_restore_state(tb, env, pc, puc);
1034 if (ret == 1) {
1035 #if 0
1036 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1037 env->nip, env->error_code, tb);
1038 #endif
1039 /* we restore the process signal mask as the sigreturn should
1040 do it (XXX: use sigsetjmp) */
1041 sigprocmask(SIG_SETMASK, old_set, NULL);
1042 do_raise_exception_err(env->exception_index, env->error_code);
1043 } else {
1044 /* activate soft MMU for this block */
1045 cpu_resume_from_signal(env, puc);
1047 /* never comes here */
1048 return 1;
1051 #elif defined(TARGET_M68K)
1052 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1053 int is_write, sigset_t *old_set,
1054 void *puc)
1056 TranslationBlock *tb;
1057 int ret;
1059 if (cpu_single_env)
1060 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1061 #if defined(DEBUG_SIGNAL)
1062 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1063 pc, address, is_write, *(unsigned long *)old_set);
1064 #endif
1065 /* XXX: locking issue */
1066 if (is_write && page_unprotect(address, pc, puc)) {
1067 return 1;
1069 /* see if it is an MMU fault */
1070 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1071 if (ret < 0)
1072 return 0; /* not an MMU fault */
1073 if (ret == 0)
1074 return 1; /* the MMU fault was handled without causing real CPU fault */
1075 /* now we have a real cpu fault */
1076 tb = tb_find_pc(pc);
1077 if (tb) {
1078 /* the PC is inside the translated code. It means that we have
1079 a virtual CPU fault */
1080 cpu_restore_state(tb, env, pc, puc);
1082 /* we restore the process signal mask as the sigreturn should
1083 do it (XXX: use sigsetjmp) */
1084 sigprocmask(SIG_SETMASK, old_set, NULL);
1085 cpu_loop_exit();
1086 /* never comes here */
1087 return 1;
1090 #elif defined (TARGET_MIPS)
1091 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1092 int is_write, sigset_t *old_set,
1093 void *puc)
1095 TranslationBlock *tb;
1096 int ret;
1098 if (cpu_single_env)
1099 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1100 #if defined(DEBUG_SIGNAL)
1101 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1102 pc, address, is_write, *(unsigned long *)old_set);
1103 #endif
1104 /* XXX: locking issue */
1105 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1106 return 1;
1109 /* see if it is an MMU fault */
1110 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1111 if (ret < 0)
1112 return 0; /* not an MMU fault */
1113 if (ret == 0)
1114 return 1; /* the MMU fault was handled without causing real CPU fault */
1116 /* now we have a real cpu fault */
1117 tb = tb_find_pc(pc);
1118 if (tb) {
1119 /* the PC is inside the translated code. It means that we have
1120 a virtual CPU fault */
1121 cpu_restore_state(tb, env, pc, puc);
1123 if (ret == 1) {
1124 #if 0
1125 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1126 env->nip, env->error_code, tb);
1127 #endif
1128 /* we restore the process signal mask as the sigreturn should
1129 do it (XXX: use sigsetjmp) */
1130 sigprocmask(SIG_SETMASK, old_set, NULL);
1131 do_raise_exception_err(env->exception_index, env->error_code);
1132 } else {
1133 /* activate soft MMU for this block */
1134 cpu_resume_from_signal(env, puc);
1136 /* never comes here */
1137 return 1;
1140 #elif defined (TARGET_SH4)
1141 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1142 int is_write, sigset_t *old_set,
1143 void *puc)
1145 TranslationBlock *tb;
1146 int ret;
1148 if (cpu_single_env)
1149 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1150 #if defined(DEBUG_SIGNAL)
1151 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1152 pc, address, is_write, *(unsigned long *)old_set);
1153 #endif
1154 /* XXX: locking issue */
1155 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1156 return 1;
1159 /* see if it is an MMU fault */
1160 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1161 if (ret < 0)
1162 return 0; /* not an MMU fault */
1163 if (ret == 0)
1164 return 1; /* the MMU fault was handled without causing real CPU fault */
1166 /* now we have a real cpu fault */
1167 tb = tb_find_pc(pc);
1168 if (tb) {
1169 /* the PC is inside the translated code. It means that we have
1170 a virtual CPU fault */
1171 cpu_restore_state(tb, env, pc, puc);
1173 #if 0
1174 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1175 env->nip, env->error_code, tb);
1176 #endif
1177 /* we restore the process signal mask as the sigreturn should
1178 do it (XXX: use sigsetjmp) */
1179 sigprocmask(SIG_SETMASK, old_set, NULL);
1180 cpu_loop_exit();
1181 /* never comes here */
1182 return 1;
1184 #else
1185 #error unsupported target CPU
1186 #endif
1188 #if defined(__i386__)
1190 #if defined(__APPLE__)
1191 # include <sys/ucontext.h>
1193 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1194 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1195 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1196 #else
1197 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1198 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1199 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1200 #endif
1202 #if defined(USE_CODE_COPY)
1203 static void cpu_send_trap(unsigned long pc, int trap,
1204 struct ucontext *uc)
1206 TranslationBlock *tb;
1208 if (cpu_single_env)
1209 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1210 /* now we have a real cpu fault */
1211 tb = tb_find_pc(pc);
1212 if (tb) {
1213 /* the PC is inside the translated code. It means that we have
1214 a virtual CPU fault */
1215 cpu_restore_state(tb, env, pc, uc);
1217 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1218 raise_exception_err(trap, env->error_code);
1220 #endif
1222 int cpu_signal_handler(int host_signum, void *pinfo,
1223 void *puc)
1225 siginfo_t *info = pinfo;
1226 struct ucontext *uc = puc;
1227 unsigned long pc;
1228 int trapno;
1230 #ifndef REG_EIP
1231 /* for glibc 2.1 */
1232 #define REG_EIP EIP
1233 #define REG_ERR ERR
1234 #define REG_TRAPNO TRAPNO
1235 #endif
1236 pc = EIP_sig(uc);
1237 trapno = TRAP_sig(uc);
1238 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1239 if (trapno == 0x00 || trapno == 0x05) {
1240 /* send division by zero or bound exception */
1241 cpu_send_trap(pc, trapno, uc);
1242 return 1;
1243 } else
1244 #endif
1245 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1246 trapno == 0xe ?
1247 (ERROR_sig(uc) >> 1) & 1 : 0,
1248 &uc->uc_sigmask, puc);
1251 #elif defined(__x86_64__)
1253 int cpu_signal_handler(int host_signum, void *pinfo,
1254 void *puc)
1256 siginfo_t *info = pinfo;
1257 struct ucontext *uc = puc;
1258 unsigned long pc;
1260 pc = uc->uc_mcontext.gregs[REG_RIP];
1261 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1262 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1263 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1264 &uc->uc_sigmask, puc);
1267 #elif defined(__powerpc__)
1269 /***********************************************************************
1270 * signal context platform-specific definitions
1271 * From Wine
1273 #ifdef linux
1274 /* All Registers access - only for local access */
1275 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1276 /* Gpr Registers access */
1277 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1278 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1279 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1280 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1281 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1282 # define LR_sig(context) REG_sig(link, context) /* Link register */
1283 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1284 /* Float Registers access */
1285 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1286 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1287 /* Exception Registers access */
1288 # define DAR_sig(context) REG_sig(dar, context)
1289 # define DSISR_sig(context) REG_sig(dsisr, context)
1290 # define TRAP_sig(context) REG_sig(trap, context)
1291 #endif /* linux */
1293 #ifdef __APPLE__
1294 # include <sys/ucontext.h>
1295 typedef struct ucontext SIGCONTEXT;
1296 /* All Registers access - only for local access */
1297 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1298 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1299 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1300 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1301 /* Gpr Registers access */
1302 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1303 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1304 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1305 # define CTR_sig(context) REG_sig(ctr, context)
1306 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1307 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1308 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1309 /* Float Registers access */
1310 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1311 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1312 /* Exception Registers access */
1313 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1314 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1315 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1316 #endif /* __APPLE__ */
1318 int cpu_signal_handler(int host_signum, void *pinfo,
1319 void *puc)
1321 siginfo_t *info = pinfo;
1322 struct ucontext *uc = puc;
1323 unsigned long pc;
1324 int is_write;
1326 pc = IAR_sig(uc);
1327 is_write = 0;
1328 #if 0
1329 /* ppc 4xx case */
1330 if (DSISR_sig(uc) & 0x00800000)
1331 is_write = 1;
1332 #else
1333 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1334 is_write = 1;
1335 #endif
1336 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1337 is_write, &uc->uc_sigmask, puc);
1340 #elif defined(__alpha__)
1342 int cpu_signal_handler(int host_signum, void *pinfo,
1343 void *puc)
1345 siginfo_t *info = pinfo;
1346 struct ucontext *uc = puc;
1347 uint32_t *pc = uc->uc_mcontext.sc_pc;
1348 uint32_t insn = *pc;
1349 int is_write = 0;
1351 /* XXX: need kernel patch to get write flag faster */
1352 switch (insn >> 26) {
1353 case 0x0d: // stw
1354 case 0x0e: // stb
1355 case 0x0f: // stq_u
1356 case 0x24: // stf
1357 case 0x25: // stg
1358 case 0x26: // sts
1359 case 0x27: // stt
1360 case 0x2c: // stl
1361 case 0x2d: // stq
1362 case 0x2e: // stl_c
1363 case 0x2f: // stq_c
1364 is_write = 1;
1367 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1368 is_write, &uc->uc_sigmask, puc);
1370 #elif defined(__sparc__)
1372 int cpu_signal_handler(int host_signum, void *pinfo,
1373 void *puc)
1375 siginfo_t *info = pinfo;
1376 uint32_t *regs = (uint32_t *)(info + 1);
1377 void *sigmask = (regs + 20);
1378 unsigned long pc;
1379 int is_write;
1380 uint32_t insn;
1382 /* XXX: is there a standard glibc define ? */
1383 pc = regs[1];
1384 /* XXX: need kernel patch to get write flag faster */
1385 is_write = 0;
1386 insn = *(uint32_t *)pc;
1387 if ((insn >> 30) == 3) {
1388 switch((insn >> 19) & 0x3f) {
1389 case 0x05: // stb
1390 case 0x06: // sth
1391 case 0x04: // st
1392 case 0x07: // std
1393 case 0x24: // stf
1394 case 0x27: // stdf
1395 case 0x25: // stfsr
1396 is_write = 1;
1397 break;
1400 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1401 is_write, sigmask, NULL);
1404 #elif defined(__arm__)
1406 int cpu_signal_handler(int host_signum, void *pinfo,
1407 void *puc)
1409 siginfo_t *info = pinfo;
1410 struct ucontext *uc = puc;
1411 unsigned long pc;
1412 int is_write;
1414 pc = uc->uc_mcontext.gregs[R15];
1415 /* XXX: compute is_write */
1416 is_write = 0;
1417 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1418 is_write,
1419 &uc->uc_sigmask, puc);
1422 #elif defined(__mc68000)
1424 int cpu_signal_handler(int host_signum, void *pinfo,
1425 void *puc)
1427 siginfo_t *info = pinfo;
1428 struct ucontext *uc = puc;
1429 unsigned long pc;
1430 int is_write;
1432 pc = uc->uc_mcontext.gregs[16];
1433 /* XXX: compute is_write */
1434 is_write = 0;
1435 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1436 is_write,
1437 &uc->uc_sigmask, puc);
1440 #elif defined(__ia64)
1442 #ifndef __ISR_VALID
1443 /* This ought to be in <bits/siginfo.h>... */
1444 # define __ISR_VALID 1
1445 #endif
1447 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1449 siginfo_t *info = pinfo;
1450 struct ucontext *uc = puc;
1451 unsigned long ip;
1452 int is_write = 0;
1454 ip = uc->uc_mcontext.sc_ip;
1455 switch (host_signum) {
1456 case SIGILL:
1457 case SIGFPE:
1458 case SIGSEGV:
1459 case SIGBUS:
1460 case SIGTRAP:
1461 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1462 /* ISR.W (write-access) is bit 33: */
1463 is_write = (info->si_isr >> 33) & 1;
1464 break;
1466 default:
1467 break;
1469 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1470 is_write,
1471 &uc->uc_sigmask, puc);
1474 #elif defined(__s390__)
1476 int cpu_signal_handler(int host_signum, void *pinfo,
1477 void *puc)
1479 siginfo_t *info = pinfo;
1480 struct ucontext *uc = puc;
1481 unsigned long pc;
1482 int is_write;
1484 pc = uc->uc_mcontext.psw.addr;
1485 /* XXX: compute is_write */
1486 is_write = 0;
1487 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1488 is_write,
1489 &uc->uc_sigmask, puc);
1492 #else
1494 #error host CPU specific signal handler needed
1496 #endif
1498 #endif /* !defined(CONFIG_SOFTMMU) */