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Remove devfn from BlockDriverState
[qemu-kvm/fedora.git] / kvm / bios / rombios32.c
blob868498776ea89a2c39962e7c260c965d0d56fbd0
1 /////////////////////////////////////////////////////////////////////////
2 // $Id: rombios32.c,v 1.11 2007/08/03 13:56:13 vruppert Exp $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // 32 bit Bochs BIOS init code
6 // Copyright (C) 2006 Fabrice Bellard
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <stdarg.h>
22 #include <stddef.h>
23
24 #include "rombios.h"
25
26 typedef signed char int8_t;
27 typedef short int16_t;
28 typedef int int32_t;
29 typedef long long int64_t;
30 typedef unsigned char uint8_t;
31 typedef unsigned short uint16_t;
32 typedef unsigned int uint32_t;
33 typedef unsigned long long uint64_t;
34
35 /* if true, put the MP float table and ACPI RSDT in EBDA and the MP
36 table in RAM. Unfortunately, Linux has bugs with that, so we prefer
37 to modify the BIOS in shadow RAM */
38 //#define BX_USE_EBDA_TABLES
39
40 /* define it if the (emulated) hardware supports SMM mode */
41 //#define BX_USE_SMM
42
43 #define cpuid(index, eax, ebx, ecx, edx) \
44 asm volatile ("cpuid" \
45 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
46 : "0" (index))
47
48 #define wbinvd() asm volatile("wbinvd")
49
50 #define CPUID_MSR (1 << 5)
51 #define CPUID_APIC (1 << 9)
52 #define CPUID_MTRR (1 << 12)
53
54 #define APIC_BASE ((uint8_t *)0xfee00000)
55 #define APIC_ICR_LOW 0x300
56 #define APIC_SVR 0x0F0
57 #define APIC_ID 0x020
58 #define APIC_LVT3 0x370
59
60 /* IRQs 5,9,10,11 */
61 #define PCI_ISA_IRQ_MASK 0x0e20U
62
63 #define APIC_ENABLED 0x0100
64
65 #define AP_BOOT_ADDR 0x9f000
66
67 #define MPTABLE_MAX_SIZE 0x00002000
68 #define SMI_CMD_IO_ADDR 0xb2
69
70 #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
71
72 #define MSR_MTRRcap 0x000000fe
73 #define MSR_MTRRfix64K_00000 0x00000250
74 #define MSR_MTRRfix16K_80000 0x00000258
75 #define MSR_MTRRfix16K_A0000 0x00000259
76 #define MSR_MTRRfix4K_C0000 0x00000268
77 #define MSR_MTRRfix4K_C8000 0x00000269
78 #define MSR_MTRRfix4K_D0000 0x0000026a
79 #define MSR_MTRRfix4K_D8000 0x0000026b
80 #define MSR_MTRRfix4K_E0000 0x0000026c
81 #define MSR_MTRRfix4K_E8000 0x0000026d
82 #define MSR_MTRRfix4K_F0000 0x0000026e
83 #define MSR_MTRRfix4K_F8000 0x0000026f
84 #define MSR_MTRRdefType 0x000002ff
85
86 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
87 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
88
89 static inline void outl(int addr, int val)
90 {
91 asm volatile ("outl %1, %w0" : : "d" (addr), "a" (val));
92 }
93
94 static inline void outw(int addr, int val)
95 {
96 asm volatile ("outw %w1, %w0" : : "d" (addr), "a" (val));
97 }
98
99 static inline void outb(int addr, int val)
100 {
101 asm volatile ("outb %b1, %w0" : : "d" (addr), "a" (val));
102 }
103
104 static inline uint32_t inl(int addr)
105 {
106 uint32_t val;
107 asm volatile ("inl %w1, %0" : "=a" (val) : "d" (addr));
108 return val;
109 }
110
111 static inline uint16_t inw(int addr)
112 {
113 uint16_t val;
114 asm volatile ("inw %w1, %w0" : "=a" (val) : "d" (addr));
115 return val;
116 }
117
118 static inline uint8_t inb(int addr)
119 {
120 uint8_t val;
121 asm volatile ("inb %w1, %b0" : "=a" (val) : "d" (addr));
122 return val;
123 }
124
125 static inline void writel(void *addr, uint32_t val)
126 {
127 *(volatile uint32_t *)addr = val;
128 }
129
130 static inline void writew(void *addr, uint16_t val)
131 {
132 *(volatile uint16_t *)addr = val;
133 }
134
135 static inline void writeb(void *addr, uint8_t val)
136 {
137 *(volatile uint8_t *)addr = val;
138 }
139
140 static inline uint32_t readl(const void *addr)
141 {
142 return *(volatile const uint32_t *)addr;
143 }
144
145 static inline uint16_t readw(const void *addr)
146 {
147 return *(volatile const uint16_t *)addr;
148 }
149
150 static inline uint8_t readb(const void *addr)
151 {
152 return *(volatile const uint8_t *)addr;
153 }
154
155 static inline void putc(int c)
156 {
157 outb(INFO_PORT, c);
158 }
159
160 static uint64_t rdmsr(unsigned index)
161 {
162 unsigned long long ret;
163
164 asm ("rdmsr" : "=A"(ret) : "c"(index));
165 return ret;
166 }
167
168 static void wrmsr(unsigned index, uint64_t val)
169 {
170 asm volatile ("wrmsr" : : "c"(index), "A"(val));
171 }
172
173 static inline int isdigit(int c)
174 {
175 return c >= '0' && c <= '9';
176 }
177
178 void *memset(void *d1, int val, size_t len)
179 {
180 uint8_t *d = d1;
181
182 while (len--) {
183 *d++ = val;
184 }
185 return d1;
186 }
187
188 void *memcpy(void *d1, const void *s1, size_t len)
189 {
190 uint8_t *d = d1;
191 const uint8_t *s = s1;
192
193 while (len--) {
194 *d++ = *s++;
195 }
196 return d1;
197 }
198
199 void *memmove(void *d1, const void *s1, size_t len)
200 {
201 uint8_t *d = d1;
202 const uint8_t *s = s1;
203
204 if (d <= s) {
205 while (len--) {
206 *d++ = *s++;
207 }
208 } else {
209 d += len;
210 s += len;
211 while (len--) {
212 *--d = *--s;
213 }
214 }
215 return d1;
216 }
217
218 int memcmp(const void *s1, const void *s2, size_t len)
219 {
220 const int8_t *p1 = s1;
221 const int8_t *p2 = s2;
222
223 while (len--) {
224 int r = *p1++ - *p2++;
225 if(r)
226 return r;
227 }
228
229 return 0;
230 }
231
232 size_t strlen(const char *s)
233 {
234 const char *s1;
235 for(s1 = s; *s1 != '\0'; s1++);
236 return s1 - s;
237 }
238
239 /* from BSD ppp sources */
240 int vsnprintf(char *buf, int buflen, const char *fmt, va_list args)
241 {
242 int c, i, n;
243 int width, prec, fillch;
244 int base, len, neg;
245 unsigned long val = 0;
246 const char *f;
247 char *str, *buf0;
248 char num[32];
249 static const char hexchars[] = "0123456789abcdef";
250
251 buf0 = buf;
252 --buflen;
253 while (buflen > 0) {
254 for (f = fmt; *f != '%' && *f != 0; ++f)
255 ;
256 if (f > fmt) {
257 len = f - fmt;
258 if (len > buflen)
259 len = buflen;
260 memcpy(buf, fmt, len);
261 buf += len;
262 buflen -= len;
263 fmt = f;
264 }
265 if (*fmt == 0)
266 break;
267 c = *++fmt;
268 width = prec = 0;
269 fillch = ' ';
270 if (c == '0') {
271 fillch = '0';
272 c = *++fmt;
273 }
274 if (c == '*') {
275 width = va_arg(args, int);
276 c = *++fmt;
277 } else {
278 while (isdigit(c)) {
279 width = width * 10 + c - '0';
280 c = *++fmt;
281 }
282 }
283 if (c == '.') {
284 c = *++fmt;
285 if (c == '*') {
286 prec = va_arg(args, int);
287 c = *++fmt;
288 } else {
289 while (isdigit(c)) {
290 prec = prec * 10 + c - '0';
291 c = *++fmt;
292 }
293 }
294 }
295 /* modifiers */
296 switch(c) {
297 case 'l':
298 c = *++fmt;
299 break;
300 default:
301 break;
302 }
303 str = 0;
304 base = 0;
305 neg = 0;
306 ++fmt;
307 switch (c) {
308 case 'd':
309 i = va_arg(args, int);
310 if (i < 0) {
311 neg = 1;
312 val = -i;
313 } else
314 val = i;
315 base = 10;
316 break;
317 case 'o':
318 val = va_arg(args, unsigned int);
319 base = 8;
320 break;
321 case 'x':
322 case 'X':
323 val = va_arg(args, unsigned int);
324 base = 16;
325 break;
326 case 'p':
327 val = (unsigned long) va_arg(args, void *);
328 base = 16;
329 neg = 2;
330 break;
331 case 's':
332 str = va_arg(args, char *);
333 break;
334 case 'c':
335 num[0] = va_arg(args, int);
336 num[1] = 0;
337 str = num;
338 break;
339 default:
340 *buf++ = '%';
341 if (c != '%')
342 --fmt; /* so %z outputs %z etc. */
343 --buflen;
344 continue;
345 }
346 if (base != 0) {
347 str = num + sizeof(num);
348 *--str = 0;
349 while (str > num + neg) {
350 *--str = hexchars[val % base];
351 val = val / base;
352 if (--prec <= 0 && val == 0)
353 break;
354 }
355 switch (neg) {
356 case 1:
357 *--str = '-';
358 break;
359 case 2:
360 *--str = 'x';
361 *--str = '0';
362 break;
363 }
364 len = num + sizeof(num) - 1 - str;
365 } else {
366 len = strlen(str);
367 if (prec > 0 && len > prec)
368 len = prec;
369 }
370 if (width > 0) {
371 if (width > buflen)
372 width = buflen;
373 if ((n = width - len) > 0) {
374 buflen -= n;
375 for (; n > 0; --n)
376 *buf++ = fillch;
377 }
378 }
379 if (len > buflen)
380 len = buflen;
381 memcpy(buf, str, len);
382 buf += len;
383 buflen -= len;
384 }
385 *buf = 0;
386 return buf - buf0;
387 }
388
389 int snprintf(char * buf, size_t size, const char *fmt, ...)
390 {
391 va_list args;
392 int i;
393
394 va_start(args, fmt);
395 i=vsnprintf(buf,size,fmt,args);
396 va_end(args);
397 return i;
398 }
399
400 void bios_printf(int flags, const char *fmt, ...)
401 {
402 va_list ap;
403 char buf[1024];
404 const char *s;
405
406 if ((flags & BIOS_PRINTF_DEBHALT) == BIOS_PRINTF_DEBHALT)
407 outb(PANIC_PORT2, 0x00);
408
409 va_start(ap, fmt);
410 vsnprintf(buf, sizeof(buf), fmt, ap);
411 s = buf;
412 while (*s)
413 putc(*s++);
414 va_end(ap);
415 }
416
417 void delay_ms(int n)
418 {
419 int i, j;
420 for(i = 0; i < n; i++) {
421 #ifdef BX_QEMU
422 /* approximative ! */
423 for(j = 0; j < 1000000; j++);
424 #else
425 {
426 int r1, r2;
427 j = 66;
428 r1 = inb(0x61) & 0x10;
429 do {
430 r2 = inb(0x61) & 0x10;
431 if (r1 != r2) {
432 j--;
433 r1 = r2;
434 }
435 } while (j > 0);
436 }
437 #endif
438 }
439 }
440
441 uint16_t smp_cpus;
442 uint32_t cpuid_signature;
443 uint32_t cpuid_features;
444 uint32_t cpuid_ext_features;
445 unsigned long ram_size;
446 uint64_t ram_end;
447 uint8_t bios_uuid[16];
448 #ifdef BX_USE_EBDA_TABLES
449 unsigned long ebda_cur_addr;
450 #endif
451 int acpi_enabled;
452 uint32_t pm_io_base, smb_io_base;
453 int pm_sci_int;
454 unsigned long bios_table_cur_addr;
455 unsigned long bios_table_end_addr;
456
457 void init_smp_msrs(void)
458 {
459 *(uint32_t *)SMP_MSR_ADDR = 0;
460 }
461
462 void wrmsr_smp(uint32_t index, uint64_t val)
463 {
464 static struct { uint32_t ecx, eax, edx; } *p = (void *)SMP_MSR_ADDR;
465
466 wrmsr(index, val);
467 p->ecx = index;
468 p->eax = val;
469 p->edx = val >> 32;
470 ++p;
471 p->ecx = 0;
472 }
473
474 #ifdef BX_QEMU
475 #define QEMU_CFG_CTL_PORT 0x510
476 #define QEMU_CFG_DATA_PORT 0x511
477 #define QEMU_CFG_SIGNATURE 0x00
478 #define QEMU_CFG_ID 0x01
479 #define QEMU_CFG_UUID 0x02
480
481 int qemu_cfg_port;
482
483 void qemu_cfg_select(int f)
484 {
485 outw(QEMU_CFG_CTL_PORT, f);
486 }
487
488 int qemu_cfg_port_probe()
489 {
490 char *sig = "QEMU";
491 int i;
492
493 qemu_cfg_select(QEMU_CFG_SIGNATURE);
494
495 for (i = 0; i < 4; i++)
496 if (inb(QEMU_CFG_DATA_PORT) != sig[i])
497 return 0;
498
499 return 1;
500 }
501
502 void qemu_cfg_read(uint8_t *buf, int len)
503 {
504 while (len--)
505 *(buf++) = inb(QEMU_CFG_DATA_PORT);
506 }
507 #endif
508
509 void uuid_probe(void)
510 {
511 #ifdef BX_QEMU
512 if(qemu_cfg_port) {
513 qemu_cfg_select(QEMU_CFG_UUID);
514 qemu_cfg_read(bios_uuid, 16);
515 return;
516 }
517 #endif
518 memset(bios_uuid, 0, 16);
519 }
520
521 void cpu_probe(void)
522 {
523 uint32_t eax, ebx, ecx, edx;
524 cpuid(1, eax, ebx, ecx, edx);
525 cpuid_signature = eax;
526 cpuid_features = edx;
527 cpuid_ext_features = ecx;
528 }
529
530 static int cmos_readb(int addr)
531 {
532 outb(0x70, addr);
533 return inb(0x71);
534 }
535
536 void setup_mtrr(void)
537 {
538 int i, vcnt, fix, wc;
539 uint32_t mtrr_cap;
540 union {
541 uint8_t valb[8];
542 uint64_t val;
543 } u;
544
545 if (!(cpuid_features & CPUID_MTRR))
546 return;
547
548 if (!(cpuid_features & CPUID_MSR))
549 return;
550
551 mtrr_cap = rdmsr(MSR_MTRRcap);
552 vcnt = mtrr_cap & 0xff;
553 fix = mtrr_cap & 0x100;
554 wc = mtrr_cap & 0x400;
555 if (!vcnt || !fix)
556 return;
557
558 u.val = 0;
559 for (i = 0; i < 8; ++i)
560 if (ram_size >= 65536 * (i + 1))
561 u.valb[i] = 6;
562 wrmsr_smp(MSR_MTRRfix64K_00000, u.val);
563 u.val = 0;
564 for (i = 0; i < 8; ++i)
565 if (ram_size >= 65536 * 8 + 16384 * (i + 1))
566 u.valb[i] = 6;
567 wrmsr_smp(MSR_MTRRfix16K_80000, u.val);
568 wrmsr_smp(MSR_MTRRfix16K_A0000, 0);
569 wrmsr_smp(MSR_MTRRfix4K_C0000, 0);
570 wrmsr_smp(MSR_MTRRfix4K_C8000, 0);
571 wrmsr_smp(MSR_MTRRfix4K_D0000, 0);
572 wrmsr_smp(MSR_MTRRfix4K_D8000, 0);
573 wrmsr_smp(MSR_MTRRfix4K_E0000, 0);
574 wrmsr_smp(MSR_MTRRfix4K_E8000, 0);
575 wrmsr_smp(MSR_MTRRfix4K_F0000, 0);
576 wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
577 /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
578 wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
579 wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
580 wrmsr_smp(MSR_MTRRdefType, 0xc06);
581 }
582
583 void ram_probe(void)
584 {
585 if (cmos_readb(0x34) | cmos_readb(0x35))
586 ram_size = (cmos_readb(0x34) | (cmos_readb(0x35) << 8)) * 65536 +
587 16 * 1024 * 1024;
588 else
589 ram_size = (cmos_readb(0x17) | (cmos_readb(0x18) << 8)) * 1024;
590
591 if (cmos_readb(0x5b) | cmos_readb(0x5c) | cmos_readb(0x5d))
592 ram_end = (((uint64_t)cmos_readb(0x5b) << 16) |
593 ((uint64_t)cmos_readb(0x5c) << 24) |
594 ((uint64_t)cmos_readb(0x5d) << 32)) + (1ull << 32);
595 else
596 ram_end = ram_size;
597
598 BX_INFO("end of ram=%ldMB\n", ram_end >> 20);
599
600 BX_INFO("ram_size=0x%08lx\n", ram_size);
601 #ifdef BX_USE_EBDA_TABLES
602 ebda_cur_addr = ((*(uint16_t *)(0x40e)) << 4) + 0x380;
603 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
604 #endif
605 }
606
607 /****************************************************/
608 /* SMP probe */
609
610 extern uint8_t smp_ap_boot_code_start;
611 extern uint8_t smp_ap_boot_code_end;
612
613 /* find the number of CPUs by launching a SIPI to them */
614 void smp_probe(void)
615 {
616 uint32_t val, sipi_vector;
617
618 writew(&smp_cpus, 1);
619 if (cpuid_features & CPUID_APIC) {
620
621 /* enable local APIC */
622 val = readl(APIC_BASE + APIC_SVR);
623 val |= APIC_ENABLED;
624 writel(APIC_BASE + APIC_SVR, val);
625
626 /* copy AP boot code */
627 memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
628 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
629
630 /* broadcast SIPI */
631 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
632 sipi_vector = AP_BOOT_ADDR >> 12;
633 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
634
635 #ifndef BX_QEMU
636 delay_ms(10);
637 #else
638 while (cmos_readb(0x5f) + 1 != readw(&smp_cpus))
639 ;
640 #endif
641 }
642 BX_INFO("Found %d cpu(s)\n", readw(&smp_cpus));
643 }
644
645 /****************************************************/
646 /* PCI init */
647
648 #define PCI_ADDRESS_SPACE_MEM 0x00
649 #define PCI_ADDRESS_SPACE_IO 0x01
650 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
651
652 #define PCI_ROM_SLOT 6
653 #define PCI_NUM_REGIONS 7
654
655 #define PCI_DEVICES_MAX 64
656
657 #define PCI_VENDOR_ID 0x00 /* 16 bits */
658 #define PCI_DEVICE_ID 0x02 /* 16 bits */
659 #define PCI_COMMAND 0x04 /* 16 bits */
660 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
661 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
662 #define PCI_CLASS_DEVICE 0x0a /* Device class */
663 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
664 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
665 #define PCI_MIN_GNT 0x3e /* 8 bits */
666 #define PCI_MAX_LAT 0x3f /* 8 bits */
667
668 #define PCI_VENDOR_ID_INTEL 0x8086
669 #define PCI_DEVICE_ID_INTEL_82441 0x1237
670 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
671 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
672 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
673 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
674 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
675
676 #define PCI_VENDOR_ID_IBM 0x1014
677 #define PCI_VENDOR_ID_APPLE 0x106b
678
679 typedef struct PCIDevice {
680 int bus;
681 int devfn;
682 } PCIDevice;
683
684 static uint32_t pci_bios_io_addr;
685 static uint32_t pci_bios_mem_addr;
686 static uint32_t pci_bios_bigmem_addr;
687 /* host irqs corresponding to PCI irqs A-D */
688 static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
689 static PCIDevice i440_pcidev;
690
691 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
692 {
693 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
694 outl(0xcfc, val);
695 }
696
697 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
698 {
699 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
700 outw(0xcfc + (addr & 2), val);
701 }
702
703 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
704 {
705 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
706 outb(0xcfc + (addr & 3), val);
707 }
708
709 static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
710 {
711 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
712 return inl(0xcfc);
713 }
714
715 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
716 {
717 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
718 return inw(0xcfc + (addr & 2));
719 }
720
721 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
722 {
723 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
724 return inb(0xcfc + (addr & 3));
725 }
726
727 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
728 {
729 uint16_t cmd;
730 uint32_t ofs, old_addr;
731
732 if ( region_num == PCI_ROM_SLOT ) {
733 ofs = 0x30;
734 }else{
735 ofs = 0x10 + region_num * 4;
736 }
737
738 old_addr = pci_config_readl(d, ofs);
739
740 pci_config_writel(d, ofs, addr);
741 BX_INFO("region %d: 0x%08x\n", region_num, addr);
742
743 /* enable memory mappings */
744 cmd = pci_config_readw(d, PCI_COMMAND);
745 if ( region_num == PCI_ROM_SLOT )
746 cmd |= 2;
747 else if (old_addr & PCI_ADDRESS_SPACE_IO)
748 cmd |= 1;
749 else
750 cmd |= 2;
751 pci_config_writew(d, PCI_COMMAND, cmd);
752 }
753
754 /* return the global irq number corresponding to a given device irq
755 pin. We could also use the bus number to have a more precise
756 mapping. */
757 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
758 {
759 int slot_addend;
760 slot_addend = (pci_dev->devfn >> 3) - 1;
761 return (irq_num + slot_addend) & 3;
762 }
763
764 static void find_bios_table_area(void)
765 {
766 unsigned long addr;
767 for(addr = 0xf0000; addr < 0x100000; addr += 16) {
768 if (*(uint32_t *)addr == 0xaafb4442) {
769 bios_table_cur_addr = addr + 8;
770 bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
771 BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
772 bios_table_cur_addr, bios_table_end_addr);
773 return;
774 }
775 }
776 return;
777 }
778
779 static void bios_shadow_init(PCIDevice *d)
780 {
781 int v;
782
783 if (bios_table_cur_addr == 0)
784 return;
785
786 /* remap the BIOS to shadow RAM an keep it read/write while we
787 are writing tables */
788 v = pci_config_readb(d, 0x59);
789 v &= 0xcf;
790 pci_config_writeb(d, 0x59, v);
791 memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
792 v |= 0x30;
793 pci_config_writeb(d, 0x59, v);
794 memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
795
796 i440_pcidev = *d;
797 }
798
799 static void bios_lock_shadow_ram(void)
800 {
801 PCIDevice *d = &i440_pcidev;
802 int v;
803
804 wbinvd();
805 v = pci_config_readb(d, 0x59);
806 v = (v & 0x0f) | (0x10);
807 pci_config_writeb(d, 0x59, v);
808 }
809
810 static void pci_bios_init_bridges(PCIDevice *d)
811 {
812 uint16_t vendor_id, device_id;
813
814 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
815 device_id = pci_config_readw(d, PCI_DEVICE_ID);
816
817 if (vendor_id == PCI_VENDOR_ID_INTEL &&
818 (device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
819 device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
820 int i, irq;
821 uint8_t elcr[2];
822
823 /* PIIX3/PIIX4 PCI to ISA bridge */
824
825 elcr[0] = 0x00;
826 elcr[1] = 0x00;
827 for(i = 0; i < 4; i++) {
828 irq = pci_irqs[i];
829 /* set to trigger level */
830 elcr[irq >> 3] |= (1 << (irq & 7));
831 /* activate irq remapping in PIIX */
832 pci_config_writeb(d, 0x60 + i, irq);
833 }
834 outb(0x4d0, elcr[0]);
835 outb(0x4d1, elcr[1]);
836 BX_INFO("PIIX3/PIIX4 init: elcr=%02x %02x\n",
837 elcr[0], elcr[1]);
838 } else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
839 /* i440 PCI bridge */
840 bios_shadow_init(d);
841 }
842 }
843
844 extern uint8_t smm_relocation_start, smm_relocation_end;
845 extern uint8_t smm_code_start, smm_code_end;
846
847 #ifdef BX_USE_SMM
848 static void smm_init(PCIDevice *d)
849 {
850 uint32_t value;
851
852 /* check if SMM init is already done */
853 value = pci_config_readl(d, 0x58);
854 if ((value & (1 << 25)) == 0) {
855
856 /* enable the SMM memory window */
857 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
858
859 /* save original memory content */
860 memcpy((void *)0xa8000, (void *)0x38000, 0x8000);
861
862 /* copy the SMM relocation code */
863 memcpy((void *)0x38000, &smm_relocation_start,
864 &smm_relocation_end - &smm_relocation_start);
865
866 /* enable SMI generation when writing to the APMC register */
867 pci_config_writel(d, 0x58, value | (1 << 25));
868
869 /* init APM status port */
870 outb(0xb3, 0x01);
871
872 /* raise an SMI interrupt */
873 outb(0xb2, 0x00);
874
875 /* wait until SMM code executed */
876 while (inb(0xb3) != 0x00);
877
878 /* restore original memory content */
879 memcpy((void *)0x38000, (void *)0xa8000, 0x8000);
880
881 /* copy the SMM code */
882 memcpy((void *)0xa8000, &smm_code_start,
883 &smm_code_end - &smm_code_start);
884 wbinvd();
885
886 /* close the SMM memory window and enable normal SMM */
887 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
888 }
889 }
890 #endif
891
892 static void piix4_pm_enable(PCIDevice *d)
893 {
894 /* PIIX4 Power Management device (for ACPI) */
895 pci_config_writel(d, 0x40, PM_IO_BASE | 1);
896 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
897 pci_config_writel(d, 0x90, SMB_IO_BASE | 1);
898 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
899 #ifdef BX_USE_SMM
900 smm_init(d);
901 #endif
902 }
903
904 static void pci_bios_init_device(PCIDevice *d)
905 {
906 int class;
907 uint32_t *paddr;
908 int i, pin, pic_irq, vendor_id, device_id;
909
910 class = pci_config_readw(d, PCI_CLASS_DEVICE);
911 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
912 device_id = pci_config_readw(d, PCI_DEVICE_ID);
913 BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x class=0x%04x\n",
914 d->bus, d->devfn, vendor_id, device_id, class);
915 switch(class) {
916 case 0x0101: /* Mass storage controller - IDE interface */
917 if (vendor_id == PCI_VENDOR_ID_INTEL &&
918 (device_id == PCI_DEVICE_ID_INTEL_82371SB_1 ||
919 device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
920 /* PIIX3/PIIX4 IDE */
921 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
922 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
923 goto default_map;
924 } else {
925 /* IDE: we map it as in ISA mode */
926 pci_set_io_region_addr(d, 0, 0x1f0);
927 pci_set_io_region_addr(d, 1, 0x3f4);
928 pci_set_io_region_addr(d, 2, 0x170);
929 pci_set_io_region_addr(d, 3, 0x374);
930 }
931 break;
932 case 0x0300: /* Display controller - VGA compatible controller */
933 if (vendor_id != 0x1234)
934 goto default_map;
935 /* VGA: map frame buffer to default Bochs VBE address */
936 pci_set_io_region_addr(d, 0, 0xE0000000);
937 break;
938 case 0x0800: /* Generic system peripheral - PIC */
939 if (vendor_id == PCI_VENDOR_ID_IBM) {
940 /* IBM */
941 if (device_id == 0x0046 || device_id == 0xFFFF) {
942 /* MPIC & MPIC2 */
943 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
944 }
945 }
946 break;
947 case 0xff00:
948 if (vendor_id == PCI_VENDOR_ID_APPLE &&
949 (device_id == 0x0017 || device_id == 0x0022)) {
950 /* macio bridge */
951 pci_set_io_region_addr(d, 0, 0x80800000);
952 }
953 break;
954 default:
955 default_map:
956 /* default memory mappings */
957 for(i = 0; i < PCI_NUM_REGIONS; i++) {
958 int ofs;
959 uint32_t val, size ;
960
961 if (i == PCI_ROM_SLOT)
962 ofs = 0x30;
963 else
964 ofs = 0x10 + i * 4;
965 pci_config_writel(d, ofs, 0xffffffff);
966 val = pci_config_readl(d, ofs);
967 if (val != 0) {
968 size = (~(val & ~0xf)) + 1;
969 if (val & PCI_ADDRESS_SPACE_IO)
970 paddr = &pci_bios_io_addr;
971 else if (size >= 0x04000000)
972 paddr = &pci_bios_bigmem_addr;
973 else
974 paddr = &pci_bios_mem_addr;
975 *paddr = (*paddr + size - 1) & ~(size - 1);
976 pci_set_io_region_addr(d, i, *paddr);
977 *paddr += size;
978 /* make memory address page aligned */
979 if (!(val & PCI_ADDRESS_SPACE_IO))
980 *paddr = (*paddr + 0xfff) & 0xfffff000;
981 }
982 }
983 break;
984 }
985
986 /* map the interrupt */
987 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
988 if (pin != 0) {
989 pin = pci_slot_get_pirq(d, pin - 1);
990 pic_irq = pci_irqs[pin];
991 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
992 }
993
994 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
995 /* PIIX4 Power Management device (for ACPI) */
996
997 // acpi sci is hardwired to 9
998 pci_config_writeb(d, PCI_INTERRUPT_LINE, 9);
999
1000 pm_io_base = PM_IO_BASE;
1001 smb_io_base = SMB_IO_BASE;
1002 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
1003 piix4_pm_enable(d);
1004 acpi_enabled = 1;
1005 }
1006 }
1007
1008 void pci_for_each_device(void (*init_func)(PCIDevice *d))
1009 {
1010 PCIDevice d1, *d = &d1;
1011 int bus, devfn;
1012 uint16_t vendor_id, device_id;
1013
1014 for(bus = 0; bus < 1; bus++) {
1015 for(devfn = 0; devfn < 256; devfn++) {
1016 d->bus = bus;
1017 d->devfn = devfn;
1018 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1019 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1020 if (vendor_id != 0xffff || device_id != 0xffff) {
1021 init_func(d);
1022 }
1023 }
1024 }
1025 }
1026
1027 void pci_bios_init(void)
1028 {
1029 pci_bios_io_addr = 0xc000;
1030 pci_bios_mem_addr = 0xf0000000;
1031 pci_bios_bigmem_addr = ram_size;
1032 if (pci_bios_bigmem_addr < 0x90000000)
1033 pci_bios_bigmem_addr = 0x90000000;
1034
1035 pci_for_each_device(pci_bios_init_bridges);
1036
1037 pci_for_each_device(pci_bios_init_device);
1038 }
1039
1040 /****************************************************/
1041 /* Multi Processor table init */
1042
1043 static void putb(uint8_t **pp, int val)
1044 {
1045 uint8_t *q;
1046 q = *pp;
1047 *q++ = val;
1048 *pp = q;
1049 }
1050
1051 static void putstr(uint8_t **pp, const char *str)
1052 {
1053 uint8_t *q;
1054 q = *pp;
1055 while (*str)
1056 *q++ = *str++;
1057 *pp = q;
1058 }
1059
1060 static void putle16(uint8_t **pp, int val)
1061 {
1062 uint8_t *q;
1063 q = *pp;
1064 *q++ = val;
1065 *q++ = val >> 8;
1066 *pp = q;
1067 }
1068
1069 static void putle32(uint8_t **pp, int val)
1070 {
1071 uint8_t *q;
1072 q = *pp;
1073 *q++ = val;
1074 *q++ = val >> 8;
1075 *q++ = val >> 16;
1076 *q++ = val >> 24;
1077 *pp = q;
1078 }
1079
1080 static int mpf_checksum(const uint8_t *data, int len)
1081 {
1082 int sum, i;
1083 sum = 0;
1084 for(i = 0; i < len; i++)
1085 sum += data[i];
1086 return sum & 0xff;
1087 }
1088
1089 static unsigned long align(unsigned long addr, unsigned long v)
1090 {
1091 return (addr + v - 1) & ~(v - 1);
1092 }
1093
1094 static void mptable_init(void)
1095 {
1096 uint8_t *mp_config_table, *q, *float_pointer_struct;
1097 int ioapic_id, i, len;
1098 int mp_config_table_size;
1099
1100 #ifdef BX_USE_EBDA_TABLES
1101 mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
1102 #else
1103 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1104 mp_config_table = (uint8_t *)bios_table_cur_addr;
1105 #endif
1106 q = mp_config_table;
1107 putstr(&q, "PCMP"); /* "PCMP signature */
1108 putle16(&q, 0); /* table length (patched later) */
1109 putb(&q, 4); /* spec rev */
1110 putb(&q, 0); /* checksum (patched later) */
1111 #ifdef BX_QEMU
1112 putstr(&q, "QEMUCPU "); /* OEM id */
1113 #else
1114 putstr(&q, "BOCHSCPU");
1115 #endif
1116 putstr(&q, "0.1 "); /* vendor id */
1117 putle32(&q, 0); /* OEM table ptr */
1118 putle16(&q, 0); /* OEM table size */
1119 putle16(&q, MAX_CPUS + 18); /* entry count */
1120 putle32(&q, 0xfee00000); /* local APIC addr */
1121 putle16(&q, 0); /* ext table length */
1122 putb(&q, 0); /* ext table checksum */
1123 putb(&q, 0); /* reserved */
1124
1125 for(i = 0; i < MAX_CPUS ; i++) {
1126 putb(&q, 0); /* entry type = processor */
1127 putb(&q, i); /* APIC id */
1128 putb(&q, 0x11); /* local APIC version number */
1129 if (i == 0)
1130 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
1131 else if ( i < smp_cpus)
1132 putb(&q, 1); /* cpu flags: enabled */
1133 else
1134 putb(&q, 0); /* cpu flags: disabled */
1135 putb(&q, 0); /* cpu signature */
1136 putb(&q, 6);
1137 putb(&q, 0);
1138 putb(&q, 0);
1139 putle16(&q, 0x201); /* feature flags */
1140 putle16(&q, 0);
1141
1142 putle16(&q, 0); /* reserved */
1143 putle16(&q, 0);
1144 putle16(&q, 0);
1145 putle16(&q, 0);
1146 }
1147
1148 /* isa bus */
1149 putb(&q, 1); /* entry type = bus */
1150 putb(&q, 0); /* bus ID */
1151 putstr(&q, "ISA ");
1152
1153 /* ioapic */
1154 ioapic_id = smp_cpus;
1155 putb(&q, 2); /* entry type = I/O APIC */
1156 putb(&q, ioapic_id); /* apic ID */
1157 putb(&q, 0x11); /* I/O APIC version number */
1158 putb(&q, 1); /* enable */
1159 putle32(&q, 0xfec00000); /* I/O APIC addr */
1160
1161 /* irqs */
1162 for(i = 0; i < 16; i++) {
1163 putb(&q, 3); /* entry type = I/O interrupt */
1164 putb(&q, 0); /* interrupt type = vectored interrupt */
1165 putb(&q, 0); /* flags: po=0, el=0 */
1166 putb(&q, 0);
1167 putb(&q, 0); /* source bus ID = ISA */
1168 putb(&q, i); /* source bus IRQ */
1169 putb(&q, ioapic_id); /* dest I/O APIC ID */
1170 putb(&q, i); /* dest I/O APIC interrupt in */
1171 }
1172 /* patch length */
1173 len = q - mp_config_table;
1174 mp_config_table[4] = len;
1175 mp_config_table[5] = len >> 8;
1176
1177 mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
1178
1179 mp_config_table_size = q - mp_config_table;
1180
1181 #ifndef BX_USE_EBDA_TABLES
1182 bios_table_cur_addr += mp_config_table_size;
1183 #endif
1184
1185 /* floating pointer structure */
1186 #ifdef BX_USE_EBDA_TABLES
1187 ebda_cur_addr = align(ebda_cur_addr, 16);
1188 float_pointer_struct = (uint8_t *)ebda_cur_addr;
1189 #else
1190 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1191 float_pointer_struct = (uint8_t *)bios_table_cur_addr;
1192 #endif
1193 q = float_pointer_struct;
1194 putstr(&q, "_MP_");
1195 /* pointer to MP config table */
1196 putle32(&q, (unsigned long)mp_config_table);
1197
1198 putb(&q, 1); /* length in 16 byte units */
1199 putb(&q, 4); /* MP spec revision */
1200 putb(&q, 0); /* checksum (patched later) */
1201 putb(&q, 0); /* MP feature byte 1 */
1202
1203 putb(&q, 0);
1204 putb(&q, 0);
1205 putb(&q, 0);
1206 putb(&q, 0);
1207 float_pointer_struct[10] =
1208 -mpf_checksum(float_pointer_struct, q - float_pointer_struct);
1209 #ifdef BX_USE_EBDA_TABLES
1210 ebda_cur_addr += (q - float_pointer_struct);
1211 #else
1212 bios_table_cur_addr += (q - float_pointer_struct);
1213 #endif
1214 BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
1215 (unsigned long)float_pointer_struct,
1216 (unsigned long)mp_config_table,
1217 mp_config_table_size);
1218 }
1219
1220 /****************************************************/
1221 /* ACPI tables init */
1222
1223 /* Table structure from Linux kernel (the ACPI tables are under the
1224 BSD license) */
1225
1226 /*
1227 * All tables must be byte-packed to match the ACPI specification, since
1228 * the tables are provided by the system BIOS.
1229 */
1230
1231 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
1232 uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
1233 uint32_t length; /* Length of table, in bytes, including header */\
1234 uint8_t revision; /* ACPI Specification minor version # */\
1235 uint8_t checksum; /* To make sum of entire table == 0 */\
1236 uint8_t oem_id [6]; /* OEM identification */\
1237 uint8_t oem_table_id [8]; /* OEM table identification */\
1238 uint32_t oem_revision; /* OEM revision number */\
1239 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
1240 uint32_t asl_compiler_revision; /* ASL compiler revision number */
1241
1242
1243 struct acpi_table_header /* ACPI common table header */
1244 {
1245 ACPI_TABLE_HEADER_DEF
1246 } __attribute__((__packed__));
1247
1248 struct rsdp_descriptor /* Root System Descriptor Pointer */
1249 {
1250 uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
1251 uint8_t checksum; /* To make sum of struct == 0 */
1252 uint8_t oem_id [6]; /* OEM identification */
1253 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
1254 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
1255 uint32_t length; /* XSDT Length in bytes including hdr */
1256 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
1257 uint8_t extended_checksum; /* Checksum of entire table */
1258 uint8_t reserved [3]; /* Reserved field must be 0 */
1259 } __attribute__((__packed__));
1260
1261 /*
1262 * ACPI 1.0 Root System Description Table (RSDT)
1263 */
1264 struct rsdt_descriptor_rev1
1265 {
1266 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1267 #ifdef BX_QEMU
1268 uint32_t table_offset_entry [2]; /* Array of pointers to other */
1269 // uint32_t table_offset_entry [4]; /* Array of pointers to other */
1270 #else
1271 uint32_t table_offset_entry [3]; /* Array of pointers to other */
1272 #endif
1273 /* ACPI tables */
1274 } __attribute__((__packed__));
1275
1276 /*
1277 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
1278 */
1279 struct facs_descriptor_rev1
1280 {
1281 uint8_t signature[4]; /* ACPI Signature */
1282 uint32_t length; /* Length of structure, in bytes */
1283 uint32_t hardware_signature; /* Hardware configuration signature */
1284 uint32_t firmware_waking_vector; /* ACPI OS waking vector */
1285 uint32_t global_lock; /* Global Lock */
1286 uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
1287 uint32_t reserved1 : 31; /* Must be 0 */
1288 uint8_t resverved3 [40]; /* Reserved - must be zero */
1289 } __attribute__((__packed__));
1290
1291
1292 /*
1293 * ACPI 1.0 Fixed ACPI Description Table (FADT)
1294 */
1295 struct fadt_descriptor_rev1
1296 {
1297 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1298 uint32_t firmware_ctrl; /* Physical address of FACS */
1299 uint32_t dsdt; /* Physical address of DSDT */
1300 uint8_t model; /* System Interrupt Model */
1301 uint8_t reserved1; /* Reserved */
1302 uint16_t sci_int; /* System vector of SCI interrupt */
1303 uint32_t smi_cmd; /* Port address of SMI command port */
1304 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
1305 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
1306 uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
1307 uint8_t reserved2; /* Reserved - must be zero */
1308 uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
1309 uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
1310 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
1311 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
1312 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
1313 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
1314 uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
1315 uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
1316 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
1317 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
1318 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
1319 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
1320 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
1321 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
1322 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
1323 uint8_t reserved3; /* Reserved */
1324 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
1325 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
1326 uint16_t flush_size; /* Size of area read to flush caches */
1327 uint16_t flush_stride; /* Stride used in flushing caches */
1328 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
1329 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
1330 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
1331 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
1332 uint8_t century; /* Index to century in RTC CMOS RAM */
1333 uint8_t reserved4; /* Reserved */
1334 uint8_t reserved4a; /* Reserved */
1335 uint8_t reserved4b; /* Reserved */
1336 #if 0
1337 uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
1338 uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
1339 uint32_t proc_c1 : 1; /* All processors support C1 state */
1340 uint32_t plvl2_up : 1; /* C2 state works on MP system */
1341 uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
1342 uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
1343 uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
1344 uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
1345 uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
1346 uint32_t reserved5 : 23; /* Reserved - must be zero */
1347 #else
1348 uint32_t flags;
1349 #endif
1350 } __attribute__((__packed__));
1351
1352 /*
1353 * MADT values and structures
1354 */
1355
1356 /* Values for MADT PCATCompat */
1357
1358 #define DUAL_PIC 0
1359 #define MULTIPLE_APIC 1
1360
1361
1362 /* Master MADT */
1363
1364 struct multiple_apic_table
1365 {
1366 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1367 uint32_t local_apic_address; /* Physical address of local APIC */
1368 #if 0
1369 uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
1370 uint32_t reserved1 : 31;
1371 #else
1372 uint32_t flags;
1373 #endif
1374 } __attribute__((__packed__));
1375
1376
1377 /* Values for Type in APIC_HEADER_DEF */
1378
1379 #define APIC_PROCESSOR 0
1380 #define APIC_IO 1
1381 #define APIC_XRUPT_OVERRIDE 2
1382 #define APIC_NMI 3
1383 #define APIC_LOCAL_NMI 4
1384 #define APIC_ADDRESS_OVERRIDE 5
1385 #define APIC_IO_SAPIC 6
1386 #define APIC_LOCAL_SAPIC 7
1387 #define APIC_XRUPT_SOURCE 8
1388 #define APIC_RESERVED 9 /* 9 and greater are reserved */
1389
1390 /*
1391 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
1392 */
1393 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
1394 uint8_t type; \
1395 uint8_t length;
1396
1397 /* Sub-structures for MADT */
1398
1399 struct madt_processor_apic
1400 {
1401 APIC_HEADER_DEF
1402 uint8_t processor_id; /* ACPI processor id */
1403 uint8_t local_apic_id; /* Processor's local APIC id */
1404 #if 0
1405 uint32_t processor_enabled: 1; /* Processor is usable if set */
1406 uint32_t reserved2 : 31; /* Reserved, must be zero */
1407 #else
1408 uint32_t flags;
1409 #endif
1410 } __attribute__((__packed__));
1411
1412 #ifdef BX_QEMU
1413 /*
1414 * * ACPI 2.0 Generic Address Space definition.
1415 * */
1416 struct acpi_20_generic_address {
1417 uint8_t address_space_id;
1418 uint8_t register_bit_width;
1419 uint8_t register_bit_offset;
1420 uint8_t reserved;
1421 uint64_t address;
1422 } __attribute__((__packed__));
1423
1424 /*
1425 * * HPET Description Table
1426 * */
1427 struct acpi_20_hpet {
1428 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1429 uint32_t timer_block_id;
1430 struct acpi_20_generic_address addr;
1431 uint8_t hpet_number;
1432 uint16_t min_tick;
1433 uint8_t page_protect;
1434 } __attribute__((__packed__));
1435 #define ACPI_HPET_ADDRESS 0xFED00000UL
1436 #endif
1437
1438 struct madt_io_apic
1439 {
1440 APIC_HEADER_DEF
1441 uint8_t io_apic_id; /* I/O APIC ID */
1442 uint8_t reserved; /* Reserved - must be zero */
1443 uint32_t address; /* APIC physical address */
1444 uint32_t interrupt; /* Global system interrupt where INTI
1445 * lines start */
1446 } __attribute__((__packed__));
1447
1448 #ifdef BX_QEMU
1449 struct madt_int_override
1450 {
1451 APIC_HEADER_DEF
1452 uint8_t bus; /* Identifies ISA Bus */
1453 uint8_t source; /* Bus-relative interrupt source */
1454 uint32_t gsi; /* GSI that source will signal */
1455 uint16_t flags; /* MPS INTI flags */
1456 } __attribute__((__packed__));
1457 #endif
1458
1459 #include "acpi-dsdt.hex"
1460
1461 static inline uint16_t cpu_to_le16(uint16_t x)
1462 {
1463 return x;
1464 }
1465
1466 static inline uint32_t cpu_to_le32(uint32_t x)
1467 {
1468 return x;
1469 }
1470
1471 static int acpi_checksum(const uint8_t *data, int len)
1472 {
1473 int sum, i;
1474 sum = 0;
1475 for(i = 0; i < len; i++)
1476 sum += data[i];
1477 return (-sum) & 0xff;
1478 }
1479
1480 static void acpi_build_table_header(struct acpi_table_header *h,
1481 char *sig, int len, uint8_t rev)
1482 {
1483 memcpy(h->signature, sig, 4);
1484 h->length = cpu_to_le32(len);
1485 h->revision = rev;
1486 #ifdef BX_QEMU
1487 memcpy(h->oem_id, "QEMU ", 6);
1488 memcpy(h->oem_table_id, "QEMU", 4);
1489 #else
1490 memcpy(h->oem_id, "BOCHS ", 6);
1491 memcpy(h->oem_table_id, "BXPC", 4);
1492 #endif
1493 memcpy(h->oem_table_id + 4, sig, 4);
1494 h->oem_revision = cpu_to_le32(1);
1495 #ifdef BX_QEMU
1496 memcpy(h->asl_compiler_id, "QEMU", 4);
1497 #else
1498 memcpy(h->asl_compiler_id, "BXPC", 4);
1499 #endif
1500 h->asl_compiler_revision = cpu_to_le32(1);
1501 h->checksum = acpi_checksum((void *)h, len);
1502 }
1503
1504 /* base_addr must be a multiple of 4KB */
1505 void acpi_bios_init(void)
1506 {
1507 struct rsdp_descriptor *rsdp;
1508 struct rsdt_descriptor_rev1 *rsdt;
1509 struct fadt_descriptor_rev1 *fadt;
1510 struct facs_descriptor_rev1 *facs;
1511 struct multiple_apic_table *madt;
1512 uint8_t *dsdt, *ssdt;
1513 #ifdef BX_QEMU
1514 struct acpi_20_hpet *hpet;
1515 uint32_t hpet_addr;
1516 #endif
1517 uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
1518 uint32_t acpi_tables_size, madt_addr, madt_size;
1519 int i;
1520
1521 /* reserve memory space for tables */
1522 #ifdef BX_USE_EBDA_TABLES
1523 ebda_cur_addr = align(ebda_cur_addr, 16);
1524 rsdp = (void *)(ebda_cur_addr);
1525 ebda_cur_addr += sizeof(*rsdp);
1526 #else
1527 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1528 rsdp = (void *)(bios_table_cur_addr);
1529 bios_table_cur_addr += sizeof(*rsdp);
1530 #endif
1531
1532 addr = base_addr = ram_size - ACPI_DATA_SIZE;
1533 rsdt_addr = addr;
1534 rsdt = (void *)(addr);
1535 addr += sizeof(*rsdt);
1536
1537 fadt_addr = addr;
1538 fadt = (void *)(addr);
1539 addr += sizeof(*fadt);
1540
1541 /* XXX: FACS should be in RAM */
1542 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
1543 facs_addr = addr;
1544 facs = (void *)(addr);
1545 addr += sizeof(*facs);
1546
1547 dsdt_addr = addr;
1548 dsdt = (void *)(addr);
1549 addr += sizeof(AmlCode);
1550
1551 addr = (addr + 7) & ~7;
1552 madt_addr = addr;
1553 madt_size = sizeof(*madt) +
1554 sizeof(struct madt_processor_apic) * MAX_CPUS +
1555 #ifdef BX_QEMU
1556 sizeof(struct madt_io_apic) /* + sizeof(struct madt_int_override) */;
1557 #else
1558 sizeof(struct madt_io_apic);
1559 #endif
1560 madt = (void *)(addr);
1561 addr += madt_size;
1562
1563 #ifdef BX_QEMU
1564 #ifdef HPET_WORKS_IN_KVM
1565 addr = (addr + 7) & ~7;
1566 hpet_addr = addr;
1567 hpet = (void *)(addr);
1568 addr += sizeof(*hpet);
1569 #endif
1570 #endif
1571
1572 acpi_tables_size = addr - base_addr;
1573
1574 BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
1575 (unsigned long)rsdp,
1576 (unsigned long)rsdt, acpi_tables_size);
1577
1578 /* RSDP */
1579 memset(rsdp, 0, sizeof(*rsdp));
1580 memcpy(rsdp->signature, "RSD PTR ", 8);
1581 #ifdef BX_QEMU
1582 memcpy(rsdp->oem_id, "QEMU ", 6);
1583 #else
1584 memcpy(rsdp->oem_id, "BOCHS ", 6);
1585 #endif
1586 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
1587 rsdp->checksum = acpi_checksum((void *)rsdp, 20);
1588
1589 /* RSDT */
1590 memset(rsdt, 0, sizeof(*rsdt));
1591 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
1592 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
1593 //rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
1594 #ifdef BX_QEMU
1595 //rsdt->table_offset_entry[3] = cpu_to_le32(hpet_addr);
1596 #endif
1597 acpi_build_table_header((struct acpi_table_header *)rsdt,
1598 "RSDT", sizeof(*rsdt), 1);
1599
1600 /* FADT */
1601 memset(fadt, 0, sizeof(*fadt));
1602 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
1603 fadt->dsdt = cpu_to_le32(dsdt_addr);
1604 fadt->model = 1;
1605 fadt->reserved1 = 0;
1606 fadt->sci_int = cpu_to_le16(pm_sci_int);
1607 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
1608 fadt->acpi_enable = 0xf1;
1609 fadt->acpi_disable = 0xf0;
1610 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
1611 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
1612 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
1613 fadt->pm1_evt_len = 4;
1614 fadt->pm1_cnt_len = 2;
1615 fadt->pm_tmr_len = 4;
1616 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
1617 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
1618 fadt->gpe0_blk = cpu_to_le32(0xafe0);
1619 fadt->gpe0_blk_len = 4;
1620 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
1621 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
1622 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
1623 sizeof(*fadt), 1);
1624
1625 /* FACS */
1626 memset(facs, 0, sizeof(*facs));
1627 memcpy(facs->signature, "FACS", 4);
1628 facs->length = cpu_to_le32(sizeof(*facs));
1629 BX_INFO("Firmware waking vector %p\n", &facs->firmware_waking_vector);
1630
1631 /* DSDT */
1632 memcpy(dsdt, AmlCode, sizeof(AmlCode));
1633
1634 /* MADT */
1635 {
1636 struct madt_processor_apic *apic;
1637 struct madt_io_apic *io_apic;
1638 #ifdef BX_QEMU
1639 struct madt_int_override *int_override;
1640 #endif
1641
1642 memset(madt, 0, madt_size);
1643 madt->local_apic_address = cpu_to_le32(0xfee00000);
1644 madt->flags = cpu_to_le32(1);
1645 apic = (void *)(madt + 1);
1646 for(i=0;i<MAX_CPUS;i++) {
1647 apic->type = APIC_PROCESSOR;
1648 apic->length = sizeof(*apic);
1649 apic->processor_id = i;
1650 apic->local_apic_id = i;
1651 if (i < smp_cpus)
1652 apic->flags = cpu_to_le32(1);
1653 else
1654 apic->flags = 0;
1655 apic++;
1656 }
1657 io_apic = (void *)apic;
1658 io_apic->type = APIC_IO;
1659 io_apic->length = sizeof(*io_apic);
1660 io_apic->io_apic_id = smp_cpus;
1661 io_apic->address = cpu_to_le32(0xfec00000);
1662 io_apic->interrupt = cpu_to_le32(0);
1663 #ifdef BX_QEMU
1664 #ifdef HPET_WORKS_IN_KVM
1665 io_apic++;
1666
1667 int_override = (void *)io_apic;
1668 int_override->type = APIC_XRUPT_OVERRIDE;
1669 int_override->length = sizeof(*int_override);
1670 int_override->bus = cpu_to_le32(0);
1671 int_override->source = cpu_to_le32(0);
1672 int_override->gsi = cpu_to_le32(2);
1673 int_override->flags = cpu_to_le32(0);
1674 #endif
1675 #endif
1676
1677 int_override = (struct madt_int_override*)(io_apic + 1);
1678 for ( i = 0; i < 16; i++ ) {
1679 if ( PCI_ISA_IRQ_MASK & (1U << i) ) {
1680 memset(int_override, 0, sizeof(*int_override));
1681 int_override->type = APIC_XRUPT_OVERRIDE;
1682 int_override->length = sizeof(*int_override);
1683 int_override->source = i;
1684 int_override->gsi = i;
1685 int_override->flags = 0xd; /* active high, level triggered */
1686 } else {
1687 /* No need for a INT source override structure. */
1688 continue;
1689 }
1690 int_override++;
1691 madt_size += sizeof(struct madt_int_override);
1692 }
1693 acpi_build_table_header((struct acpi_table_header *)madt,
1694 "APIC", madt_size, 1);
1695 }
1696
1697 #ifdef BX_QEMU
1698 /* HPET */
1699 #ifdef HPET_WORKS_IN_KVM
1700 memset(hpet, 0, sizeof(*hpet));
1701 /* Note timer_block_id value must be kept in sync with value advertised by
1702 * emulated hpet
1703 */
1704 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1705 hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
1706 acpi_build_table_header((struct acpi_table_header *)hpet,
1707 "HPET", sizeof(*hpet), 1);
1708 #endif
1709 #endif
1710
1711 }
1712
1713 /* SMBIOS entry point -- must be written to a 16-bit aligned address
1714 between 0xf0000 and 0xfffff.
1715 */
1716 struct smbios_entry_point {
1717 char anchor_string[4];
1718 uint8_t checksum;
1719 uint8_t length;
1720 uint8_t smbios_major_version;
1721 uint8_t smbios_minor_version;
1722 uint16_t max_structure_size;
1723 uint8_t entry_point_revision;
1724 uint8_t formatted_area[5];
1725 char intermediate_anchor_string[5];
1726 uint8_t intermediate_checksum;
1727 uint16_t structure_table_length;
1728 uint32_t structure_table_address;
1729 uint16_t number_of_structures;
1730 uint8_t smbios_bcd_revision;
1731 } __attribute__((__packed__));
1732
1733 /* This goes at the beginning of every SMBIOS structure. */
1734 struct smbios_structure_header {
1735 uint8_t type;
1736 uint8_t length;
1737 uint16_t handle;
1738 } __attribute__((__packed__));
1739
1740 /* SMBIOS type 0 - BIOS Information */
1741 struct smbios_type_0 {
1742 struct smbios_structure_header header;
1743 uint8_t vendor_str;
1744 uint8_t bios_version_str;
1745 uint16_t bios_starting_address_segment;
1746 uint8_t bios_release_date_str;
1747 uint8_t bios_rom_size;
1748 uint8_t bios_characteristics[8];
1749 uint8_t bios_characteristics_extension_bytes[2];
1750 uint8_t system_bios_major_release;
1751 uint8_t system_bios_minor_release;
1752 uint8_t embedded_controller_major_release;
1753 uint8_t embedded_controller_minor_release;
1754 } __attribute__((__packed__));
1755
1756 /* SMBIOS type 1 - System Information */
1757 struct smbios_type_1 {
1758 struct smbios_structure_header header;
1759 uint8_t manufacturer_str;
1760 uint8_t product_name_str;
1761 uint8_t version_str;
1762 uint8_t serial_number_str;
1763 uint8_t uuid[16];
1764 uint8_t wake_up_type;
1765 uint8_t sku_number_str;
1766 uint8_t family_str;
1767 } __attribute__((__packed__));
1768
1769 /* SMBIOS type 3 - System Enclosure (v2.3) */
1770 struct smbios_type_3 {
1771 struct smbios_structure_header header;
1772 uint8_t manufacturer_str;
1773 uint8_t type;
1774 uint8_t version_str;
1775 uint8_t serial_number_str;
1776 uint8_t asset_tag_number_str;
1777 uint8_t boot_up_state;
1778 uint8_t power_supply_state;
1779 uint8_t thermal_state;
1780 uint8_t security_status;
1781 uint32_t oem_defined;
1782 uint8_t height;
1783 uint8_t number_of_power_cords;
1784 uint8_t contained_element_count;
1785 // contained elements follow
1786 } __attribute__((__packed__));
1787
1788 /* SMBIOS type 4 - Processor Information (v2.0) */
1789 struct smbios_type_4 {
1790 struct smbios_structure_header header;
1791 uint8_t socket_designation_str;
1792 uint8_t processor_type;
1793 uint8_t processor_family;
1794 uint8_t processor_manufacturer_str;
1795 uint32_t processor_id[2];
1796 uint8_t processor_version_str;
1797 uint8_t voltage;
1798 uint16_t external_clock;
1799 uint16_t max_speed;
1800 uint16_t current_speed;
1801 uint8_t status;
1802 uint8_t processor_upgrade;
1803 uint16_t l1_cache_handle;
1804 uint16_t l2_cache_handle;
1805 uint16_t l3_cache_handle;
1806 } __attribute__((__packed__));
1807
1808 /* SMBIOS type 16 - Physical Memory Array
1809 * Associated with one type 17 (Memory Device).
1810 */
1811 struct smbios_type_16 {
1812 struct smbios_structure_header header;
1813 uint8_t location;
1814 uint8_t use;
1815 uint8_t error_correction;
1816 uint32_t maximum_capacity;
1817 uint16_t memory_error_information_handle;
1818 uint16_t number_of_memory_devices;
1819 } __attribute__((__packed__));
1820
1821 /* SMBIOS type 17 - Memory Device
1822 * Associated with one type 19
1823 */
1824 struct smbios_type_17 {
1825 struct smbios_structure_header header;
1826 uint16_t physical_memory_array_handle;
1827 uint16_t memory_error_information_handle;
1828 uint16_t total_width;
1829 uint16_t data_width;
1830 uint16_t size;
1831 uint8_t form_factor;
1832 uint8_t device_set;
1833 uint8_t device_locator_str;
1834 uint8_t bank_locator_str;
1835 uint8_t memory_type;
1836 uint16_t type_detail;
1837 } __attribute__((__packed__));
1838
1839 /* SMBIOS type 19 - Memory Array Mapped Address */
1840 struct smbios_type_19 {
1841 struct smbios_structure_header header;
1842 uint32_t starting_address;
1843 uint32_t ending_address;
1844 uint16_t memory_array_handle;
1845 uint8_t partition_width;
1846 } __attribute__((__packed__));
1847
1848 /* SMBIOS type 20 - Memory Device Mapped Address */
1849 struct smbios_type_20 {
1850 struct smbios_structure_header header;
1851 uint32_t starting_address;
1852 uint32_t ending_address;
1853 uint16_t memory_device_handle;
1854 uint16_t memory_array_mapped_address_handle;
1855 uint8_t partition_row_position;
1856 uint8_t interleave_position;
1857 uint8_t interleaved_data_depth;
1858 } __attribute__((__packed__));
1859
1860 /* SMBIOS type 32 - System Boot Information */
1861 struct smbios_type_32 {
1862 struct smbios_structure_header header;
1863 uint8_t reserved[6];
1864 uint8_t boot_status;
1865 } __attribute__((__packed__));
1866
1867 /* SMBIOS type 127 -- End-of-table */
1868 struct smbios_type_127 {
1869 struct smbios_structure_header header;
1870 } __attribute__((__packed__));
1871
1872 static void
1873 smbios_entry_point_init(void *start,
1874 uint16_t max_structure_size,
1875 uint16_t structure_table_length,
1876 uint32_t structure_table_address,
1877 uint16_t number_of_structures)
1878 {
1879 uint8_t sum;
1880 int i;
1881 struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
1882
1883 memcpy(ep->anchor_string, "_SM_", 4);
1884 ep->length = 0x1f;
1885 ep->smbios_major_version = 2;
1886 ep->smbios_minor_version = 4;
1887 ep->max_structure_size = max_structure_size;
1888 ep->entry_point_revision = 0;
1889 memset(ep->formatted_area, 0, 5);
1890 memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
1891
1892 ep->structure_table_length = structure_table_length;
1893 ep->structure_table_address = structure_table_address;
1894 ep->number_of_structures = number_of_structures;
1895 ep->smbios_bcd_revision = 0x24;
1896
1897 ep->checksum = 0;
1898 ep->intermediate_checksum = 0;
1899
1900 sum = 0;
1901 for (i = 0; i < 0x10; i++)
1902 sum += ((int8_t *)start)[i];
1903 ep->checksum = -sum;
1904
1905 sum = 0;
1906 for (i = 0x10; i < ep->length; i++)
1907 sum += ((int8_t *)start)[i];
1908 ep->intermediate_checksum = -sum;
1909 }
1910
1911 /* Type 0 -- BIOS Information */
1912 #define RELEASE_DATE_STR "01/01/2007"
1913 static void *
1914 smbios_type_0_init(void *start)
1915 {
1916 struct smbios_type_0 *p = (struct smbios_type_0 *)start;
1917
1918 p->header.type = 0;
1919 p->header.length = sizeof(struct smbios_type_0);
1920 p->header.handle = 0;
1921
1922 p->vendor_str = 1;
1923 p->bios_version_str = 1;
1924 p->bios_starting_address_segment = 0xe800;
1925 p->bios_release_date_str = 2;
1926 p->bios_rom_size = 0; /* FIXME */
1927
1928 memset(p->bios_characteristics, 0, 8);
1929 p->bios_characteristics[0] = 0x08; /* BIOS characteristics not supported */
1930 p->bios_characteristics_extension_bytes[0] = 0;
1931 p->bios_characteristics_extension_bytes[1] = 0;
1932
1933 p->system_bios_major_release = 1;
1934 p->system_bios_minor_release = 0;
1935 p->embedded_controller_major_release = 0xff;
1936 p->embedded_controller_minor_release = 0xff;
1937
1938 start += sizeof(struct smbios_type_0);
1939 memcpy((char *)start, BX_APPNAME, sizeof(BX_APPNAME));
1940 start += sizeof(BX_APPNAME);
1941 memcpy((char *)start, RELEASE_DATE_STR, sizeof(RELEASE_DATE_STR));
1942 start += sizeof(RELEASE_DATE_STR);
1943 *((uint8_t *)start) = 0;
1944
1945 return start+1;
1946 }
1947
1948 /* Type 1 -- System Information */
1949 static void *
1950 smbios_type_1_init(void *start)
1951 {
1952 struct smbios_type_1 *p = (struct smbios_type_1 *)start;
1953 p->header.type = 1;
1954 p->header.length = sizeof(struct smbios_type_1);
1955 p->header.handle = 0x100;
1956
1957 p->manufacturer_str = 0;
1958 p->product_name_str = 0;
1959 p->version_str = 0;
1960 p->serial_number_str = 0;
1961
1962 memcpy(p->uuid, bios_uuid, 16);
1963
1964 p->wake_up_type = 0x06; /* power switch */
1965 p->sku_number_str = 0;
1966 p->family_str = 0;
1967
1968 start += sizeof(struct smbios_type_1);
1969 *((uint16_t *)start) = 0;
1970
1971 return start+2;
1972 }
1973
1974 /* Type 3 -- System Enclosure */
1975 static void *
1976 smbios_type_3_init(void *start)
1977 {
1978 struct smbios_type_3 *p = (struct smbios_type_3 *)start;
1979
1980 p->header.type = 3;
1981 p->header.length = sizeof(struct smbios_type_3);
1982 p->header.handle = 0x300;
1983
1984 p->manufacturer_str = 0;
1985 p->type = 0x01; /* other */
1986 p->version_str = 0;
1987 p->serial_number_str = 0;
1988 p->asset_tag_number_str = 0;
1989 p->boot_up_state = 0x03; /* safe */
1990 p->power_supply_state = 0x03; /* safe */
1991 p->thermal_state = 0x03; /* safe */
1992 p->security_status = 0x02; /* unknown */
1993 p->oem_defined = 0;
1994 p->height = 0;
1995 p->number_of_power_cords = 0;
1996 p->contained_element_count = 0;
1997
1998 start += sizeof(struct smbios_type_3);
1999 *((uint16_t *)start) = 0;
2000
2001 return start+2;
2002 }
2003
2004 /* Type 4 -- Processor Information */
2005 static void *
2006 smbios_type_4_init(void *start, unsigned int cpu_number)
2007 {
2008 struct smbios_type_4 *p = (struct smbios_type_4 *)start;
2009
2010 p->header.type = 4;
2011 p->header.length = sizeof(struct smbios_type_4);
2012 p->header.handle = 0x400 + cpu_number;
2013
2014 p->socket_designation_str = 1;
2015 p->processor_type = 0x03; /* CPU */
2016 p->processor_family = 0x01; /* other */
2017 p->processor_manufacturer_str = 0;
2018
2019 p->processor_id[0] = cpuid_signature;
2020 p->processor_id[1] = cpuid_features;
2021
2022 p->processor_version_str = 0;
2023 p->voltage = 0;
2024 p->external_clock = 0;
2025
2026 p->max_speed = 0; /* unknown */
2027 p->current_speed = 0; /* unknown */
2028
2029 p->status = 0x41; /* socket populated, CPU enabled */
2030 p->processor_upgrade = 0x01; /* other */
2031
2032 p->l1_cache_handle = 0xffff; /* cache information structure not provided */
2033 p->l2_cache_handle = 0xffff;
2034 p->l3_cache_handle = 0xffff;
2035
2036 start += sizeof(struct smbios_type_4);
2037
2038 memcpy((char *)start, "CPU " "\0" "" "\0" "", 7);
2039 ((char *)start)[4] = cpu_number + '0';
2040
2041 return start+7;
2042 }
2043
2044 /* Type 16 -- Physical Memory Array */
2045 static void *
2046 smbios_type_16_init(void *start, uint32_t memsize, int nr_mem_devs)
2047 {
2048 struct smbios_type_16 *p = (struct smbios_type_16*)start;
2049
2050 p->header.type = 16;
2051 p->header.length = sizeof(struct smbios_type_16);
2052 p->header.handle = 0x1000;
2053
2054 p->location = 0x01; /* other */
2055 p->use = 0x03; /* system memory */
2056 p->error_correction = 0x01; /* other */
2057 p->maximum_capacity = memsize * 1024;
2058 p->memory_error_information_handle = 0xfffe; /* none provided */
2059 p->number_of_memory_devices = nr_mem_devs;
2060
2061 start += sizeof(struct smbios_type_16);
2062 *((uint16_t *)start) = 0;
2063
2064 return start + 2;
2065 }
2066
2067 /* Type 17 -- Memory Device */
2068 static void *
2069 smbios_type_17_init(void *start, uint32_t memory_size_mb, int instance)
2070 {
2071 struct smbios_type_17 *p = (struct smbios_type_17 *)start;
2072
2073 p->header.type = 17;
2074 p->header.length = sizeof(struct smbios_type_17);
2075 p->header.handle = 0x1100 + instance;
2076
2077 p->physical_memory_array_handle = 0x1000;
2078 p->total_width = 64;
2079 p->data_width = 64;
2080 /* TODO: should assert in case something is wrong ASSERT((memory_size_mb & ~0x7fff) == 0); */
2081 p->size = memory_size_mb;
2082 p->form_factor = 0x09; /* DIMM */
2083 p->device_set = 0;
2084 p->device_locator_str = 1;
2085 p->bank_locator_str = 0;
2086 p->memory_type = 0x07; /* RAM */
2087 p->type_detail = 0;
2088
2089 start += sizeof(struct smbios_type_17);
2090 snprintf(start, 8, "DIMM %d", instance);
2091 start += strlen(start) + 1;
2092 *((uint8_t *)start) = 0;
2093
2094 return start+1;
2095 }
2096
2097 /* Type 19 -- Memory Array Mapped Address */
2098 static void *
2099 smbios_type_19_init(void *start, uint32_t memory_size_mb, int instance)
2100 {
2101 struct smbios_type_19 *p = (struct smbios_type_19 *)start;
2102
2103 p->header.type = 19;
2104 p->header.length = sizeof(struct smbios_type_19);
2105 p->header.handle = 0x1300 + instance;
2106
2107 p->starting_address = instance << 24;
2108 p->ending_address = p->starting_address + (memory_size_mb << 10) - 1;
2109 p->memory_array_handle = 0x1000;
2110 p->partition_width = 1;
2111
2112 start += sizeof(struct smbios_type_19);
2113 *((uint16_t *)start) = 0;
2114
2115 return start + 2;
2116 }
2117
2118 /* Type 20 -- Memory Device Mapped Address */
2119 static void *
2120 smbios_type_20_init(void *start, uint32_t memory_size_mb, int instance)
2121 {
2122 struct smbios_type_20 *p = (struct smbios_type_20 *)start;
2123
2124 p->header.type = 20;
2125 p->header.length = sizeof(struct smbios_type_20);
2126 p->header.handle = 0x1400 + instance;
2127
2128 p->starting_address = instance << 24;
2129 p->ending_address = p->starting_address + (memory_size_mb << 10) - 1;
2130 p->memory_device_handle = 0x1100 + instance;
2131 p->memory_array_mapped_address_handle = 0x1300 + instance;
2132 p->partition_row_position = 1;
2133 p->interleave_position = 0;
2134 p->interleaved_data_depth = 0;
2135
2136 start += sizeof(struct smbios_type_20);
2137
2138 *((uint16_t *)start) = 0;
2139 return start+2;
2140 }
2141
2142 /* Type 32 -- System Boot Information */
2143 static void *
2144 smbios_type_32_init(void *start)
2145 {
2146 struct smbios_type_32 *p = (struct smbios_type_32 *)start;
2147
2148 p->header.type = 32;
2149 p->header.length = sizeof(struct smbios_type_32);
2150 p->header.handle = 0x2000;
2151 memset(p->reserved, 0, 6);
2152 p->boot_status = 0; /* no errors detected */
2153
2154 start += sizeof(struct smbios_type_32);
2155 *((uint16_t *)start) = 0;
2156
2157 return start+2;
2158 }
2159
2160 /* Type 127 -- End of Table */
2161 static void *
2162 smbios_type_127_init(void *start)
2163 {
2164 struct smbios_type_127 *p = (struct smbios_type_127 *)start;
2165
2166 p->header.type = 127;
2167 p->header.length = sizeof(struct smbios_type_127);
2168 p->header.handle = 0x7f00;
2169
2170 start += sizeof(struct smbios_type_127);
2171 *((uint16_t *)start) = 0;
2172
2173 return start + 2;
2174 }
2175
2176 void smbios_init(void)
2177 {
2178 unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
2179 char *start, *p, *q;
2180 int memsize = (ram_end == ram_size) ? ram_size / (1024 * 1024) :
2181 (ram_end - (1ull << 32) + ram_size) / (1024 * 1024);
2182 int i, nr_mem_devs;
2183
2184 #ifdef BX_USE_EBDA_TABLES
2185 ebda_cur_addr = align(ebda_cur_addr, 16);
2186 start = (void *)(ebda_cur_addr);
2187 #else
2188 bios_table_cur_addr = align(bios_table_cur_addr, 16);
2189 start = (void *)(bios_table_cur_addr);
2190 #endif
2191
2192 p = (char *)start + sizeof(struct smbios_entry_point);
2193
2194 #define add_struct(fn) do{ \
2195 q = (fn); \
2196 nr_structs++; \
2197 if ((q - p) > max_struct_size) \
2198 max_struct_size = q - p; \
2199 p = q; \
2200 }while (0)
2201
2202 add_struct(smbios_type_0_init(p));
2203 add_struct(smbios_type_1_init(p));
2204 add_struct(smbios_type_3_init(p));
2205 for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
2206 add_struct(smbios_type_4_init(p, cpu_num));
2207
2208 /* Each 'memory device' covers up to 16GB of address space. */
2209 nr_mem_devs = (memsize + 0x3fff) >> 14;
2210 add_struct(smbios_type_16_init(p, memsize, nr_mem_devs));
2211 for ( i = 0; i < nr_mem_devs; i++ )
2212 {
2213 uint32_t dev_memsize = ((i == (nr_mem_devs - 1))
2214 ? (((memsize-1) & 0x3fff)+1) : 0x4000);
2215 add_struct(smbios_type_17_init(p, dev_memsize, i));
2216 add_struct(smbios_type_19_init(p, dev_memsize, i));
2217 add_struct(smbios_type_20_init(p, dev_memsize, i));
2218 }
2219
2220 add_struct(smbios_type_32_init(p));
2221 add_struct(smbios_type_127_init(p));
2222
2223 #undef add_struct
2224
2225 smbios_entry_point_init(
2226 start, max_struct_size,
2227 (p - (char *)start) - sizeof(struct smbios_entry_point),
2228 (uint32_t)(start + sizeof(struct smbios_entry_point)),
2229 nr_structs);
2230
2231 #ifdef BX_USE_EBDA_TABLES
2232 ebda_cur_addr += (p - (char *)start);
2233 #else
2234 bios_table_cur_addr += (p - (char *)start);
2235 #endif
2236
2237 BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
2238 }
2239
2240 static uint32_t find_resume_vector(void)
2241 {
2242 unsigned long addr, start, end;
2243
2244 #ifdef BX_USE_EBDA_TABLES
2245 start = align(ebda_cur_addr, 16);
2246 end = 0xa000 << 4;
2247 #else
2248 if (bios_table_cur_addr == 0)
2249 return 0;
2250 start = align(bios_table_cur_addr, 16);
2251 end = bios_table_end_addr;
2252 #endif
2253
2254 for (addr = start; addr < end; addr += 16) {
2255 if (!memcmp((void*)addr, "RSD PTR ", 8)) {
2256 struct rsdp_descriptor *rsdp = (void*)addr;
2257 struct rsdt_descriptor_rev1 *rsdt = (void*)rsdp->rsdt_physical_address;
2258 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[0];
2259 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
2260 return facs->firmware_waking_vector;
2261 }
2262 }
2263
2264 return 0;
2265 }
2266
2267 static void find_440fx(PCIDevice *d)
2268 {
2269 uint16_t vendor_id, device_id;
2270
2271 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2272 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2273
2274 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441)
2275 i440_pcidev = *d;
2276 }
2277
2278 static void reinit_piix4_pm(PCIDevice *d)
2279 {
2280 uint16_t vendor_id, device_id;
2281
2282 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2283 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2284
2285 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3)
2286 piix4_pm_enable(d);
2287 }
2288
2289 void rombios32_init(uint32_t *s3_resume_vector, uint8_t *shutdown_flag)
2290 {
2291 BX_INFO("Starting rombios32\n");
2292 BX_INFO("Shutdown flag %x\n", *shutdown_flag);
2293
2294 #ifdef BX_QEMU
2295 qemu_cfg_port = qemu_cfg_port_probe();
2296 #endif
2297
2298 init_smp_msrs();
2299
2300 ram_probe();
2301
2302 cpu_probe();
2303
2304 setup_mtrr();
2305
2306 smp_probe();
2307
2308 find_bios_table_area();
2309
2310 if (*shutdown_flag == 0xfe) {
2311 /* redirect bios read access to RAM */
2312 pci_for_each_device(find_440fx);
2313 bios_lock_shadow_ram(); /* bios is already copied */
2314 *s3_resume_vector = find_resume_vector();
2315 if (!*s3_resume_vector) {
2316 BX_INFO("This is S3 resume but wakeup vector is NULL\n");
2317 } else {
2318 BX_INFO("S3 resume vector %p\n", *s3_resume_vector);
2319 pci_for_each_device(reinit_piix4_pm);
2320 }
2321 return;
2322 }
2323
2324 pci_bios_init();
2325
2326 if (bios_table_cur_addr != 0) {
2327
2328 mptable_init();
2329
2330 uuid_probe();
2331
2332 smbios_init();
2333
2334 if (acpi_enabled)
2335 acpi_bios_init();
2336
2337 bios_lock_shadow_ram();
2338
2339 BX_INFO("bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
2340 if (bios_table_cur_addr > bios_table_end_addr)
2341 BX_PANIC("bios_table_end_addr overflow!\n");
2342 #ifdef BX_USE_EBDA_TABLES
2343 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
2344 if (ebda_cur_addr > 0xA0000)
2345 BX_PANIC("ebda_cur_addr overflow!\n");
2346 #endif
2347 }
2348 }
Patches shipped by Fedora