hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7
   8 /* PCI includes legacy ISA access.  */
   9 #include "isa.h"
  10
  11 /* imported from <linux/pci.h> */
  12 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  13 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  14
  15 /* PCI bus */
  16 extern target_phys_addr_t pci_mem_base;
  17
  18 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  19 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  20 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  21
  22 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  23 #include "pci_ids.h"
  24
  25 /* QEMU-specific Vendor and Device ID definitions */
  26
  27 /* IBM (0x1014) */
  28 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  29 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  30
  31 /* Hitachi (0x1054) */
  32 #define PCI_VENDOR_ID_HITACHI            0x1054
  33 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  34
  35 /* Apple (0x106b) */
  36 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  37 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  40 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  41
  42 /* Realtek (0x10ec) */
  43 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  44
  45 /* Xilinx (0x10ee) */
  46 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  47
  48 /* Marvell (0x11ab) */
  49 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  50
  51 /* QEMU/Bochs VGA (0x1234) */
  52 #define PCI_VENDOR_ID_QEMU               0x1234
  53 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  54
  55 /* VMWare (0x15ad) */
  56 #define PCI_VENDOR_ID_VMWARE             0x15ad
  57 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  58 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  59 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  60 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  61 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  62
  63 /* Intel (0x8086) */
  64 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  65
  66 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  67 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  68 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  69 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  70
  71 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  72 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  73 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  74 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  75
  76 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  77                                 uint32_t address, uint32_t data, int len);
  78 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  79                                    uint32_t address, int len);
  80 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  81                                 uint32_t addr, uint32_t size, int type);
  82 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  83
  84 typedef void PCICapConfigWriteFunc(PCIDevice *pci_dev,
  85                                    uint32_t address, uint32_t val, int len);
  86 typedef uint32_t PCICapConfigReadFunc(PCIDevice *pci_dev,
  87                                       uint32_t address, int len);
  88 typedef int PCICapConfigInitFunc(PCIDevice *pci_dev);
  89
  90 #define PCI_ADDRESS_SPACE_MEM           0x00
  91 #define PCI_ADDRESS_SPACE_IO            0x01
  92 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
  93
  94 typedef struct PCIIORegion {
  95     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
  96     uint32_t size;
  97     uint8_t type;
  98     PCIMapIORegionFunc *map_func;
  99 } PCIIORegion;
 100
 101 #define PCI_ROM_SLOT 6
 102 #define PCI_NUM_REGIONS 7
 103
 104 #define PCI_DEVICES_MAX 64
 105
 106 /* Declarations from linux/pci_regs.h */
 107 #define PCI_VENDOR_ID           0x00    /* 16 bits */
 108 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 109 #define PCI_COMMAND             0x04    /* 16 bits */
 110 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 111 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 112 #define PCI_STATUS              0x06    /* 16 bits */
 113 #define PCI_REVISION_ID         0x08    /* 8 bits  */
 114 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 115 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
 116 #define  PCI_HEADER_TYPE_NORMAL         0
 117 #define  PCI_HEADER_TYPE_BRIDGE         1
 118 #define  PCI_HEADER_TYPE_CARDBUS        2
 119 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 120 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
 121 #define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
 122 #define PCI_CAPABILITY_LIST     0x34
 123 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 124 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 125 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 126 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 127
 128 #define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */
 129 #define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
 130 #define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */
 131
 132 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 133 #define PCI_STATUS_RESERVED1    0x007
 134 #define PCI_STATUS_INT_STATUS   0x008
 135 #define PCI_STATUS_CAPABILITIES 0x010
 136
 137 #ifndef PCI_STATUS_66MHZ
 138 #define PCI_STATUS_66MHZ        0x020
 139 #endif
 140
 141 #define PCI_STATUS_RESERVED2    0x040
 142
 143 #ifndef PCI_STATUS_FAST_BACK
 144 #define PCI_STATUS_FAST_BACK    0x080
 145 #endif
 146
 147 #define PCI_STATUS_DEVSEL       0x600
 148
 149 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 150                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 151                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 152
 153 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 154
 155 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 156 #define PCI_COMMAND_RESERVED    0xf800
 157
 158 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 159
 160 #define PCI_CAPABILITY_CONFIG_MAX_LENGTH 0x60
 161 #define PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR 0x40
 162 #define PCI_CAPABILITY_CONFIG_MSI_LENGTH 0x10
 163 #define PCI_CAPABILITY_CONFIG_MSIX_LENGTH 0x10
 164
 165 struct PCIDevice {
 166     DeviceState qdev;
 167     /* PCI config space */
 168     uint8_t config[256];
 169
 170     /* the following fields are read only */
 171     PCIBus *bus;
 172     int devfn;
 173     char name[64];
 174     PCIIORegion io_regions[PCI_NUM_REGIONS];
 175
 176     /* do not access the following fields */
 177     PCIConfigReadFunc *config_read;
 178     PCIConfigWriteFunc *config_write;
 179     PCIUnregisterFunc *unregister;
 180     /* ??? This is a PC-specific hack, and should be removed.  */
 181     int irq_index;
 182
 183     /* IRQ objects for the INTA-INTD pins.  */
 184     qemu_irq *irq;
 185
 186     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 187     int irq_state[4];
 188
 189     /* Device capability configuration space */
 190     struct {
 191         int supported;
 192         unsigned int start, length;
 193         PCICapConfigReadFunc *config_read;
 194         PCICapConfigWriteFunc *config_write;
 195     } cap;
 196 };
 197
 198 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 199                                int instance_size, int devfn,
 200                                PCIConfigReadFunc *config_read,
 201                                PCIConfigWriteFunc *config_write);
 202 int pci_unregister_device(PCIDevice *pci_dev);
 203
 204 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 205                             uint32_t size, int type,
 206                             PCIMapIORegionFunc *map_func);
 207
 208 int pci_enable_capability_support(PCIDevice *pci_dev,
 209                                   uint32_t config_start,
 210                                   PCICapConfigReadFunc *config_read,
 211                                   PCICapConfigWriteFunc *config_write,
 212                                   PCICapConfigInitFunc *config_init);
 213
 214 int pci_map_irq(PCIDevice *pci_dev, int pin);
 215 uint32_t pci_default_read_config(PCIDevice *d,
 216                                  uint32_t address, int len);
 217 void pci_default_write_config(PCIDevice *d,
 218                               uint32_t address, uint32_t val, int len);
 219 void pci_device_save(PCIDevice *s, QEMUFile *f);
 220 int pci_device_load(PCIDevice *s, QEMUFile *f);
 221 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 222                                      uint32_t address, int len);
 223 void pci_default_cap_write_config(PCIDevice *pci_dev,
 224                                   uint32_t address, uint32_t val, int len);
 225 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len);
 226
 227 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
 228 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 229 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 230                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 231                          qemu_irq *pic, int devfn_min, int nirq);
 232
 233 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 234                   const char *default_model);
 235 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 236 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 237 int pci_bus_num(PCIBus *s);
 238 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 239 PCIBus *pci_find_bus(int bus_num);
 240 PCIDevice *pci_find_device(int bus_num, int slot, int function);
 241
 242 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);
 243 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);
 244
 245 int pci_parse_host_devaddr(const char *addr, int *busp,
 246                            int *slotp, int *funcp);
 247
 248 void pci_info(Monitor *mon);
 249 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 250                         pci_map_irq_fn map_irq, const char *name);
 251
 252 static inline void
 253 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 254 {
 255     cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
 256 }
 257
 258 static inline void
 259 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 260 {
 261     cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
 262 }
 263
 264 static inline void
 265 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 266 {
 267     cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
 268 }
 269
 270 typedef void (*pci_qdev_initfn)(PCIDevice *dev);
 271 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init);
 272
 273 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 274
 275 /* lsi53c895a.c */
 276 #define LSI_MAX_DEVS 7
 277 void lsi_scsi_attach(DeviceState *host, BlockDriverState *bd, int id);
 278
 279 /* vmware_vga.c */
 280 void pci_vmsvga_init(PCIBus *bus);
 281
 282 /* usb-uhci.c */
 283 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 284 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 285
 286 /* usb-ohci.c */
 287 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
 288
 289 /* prep_pci.c */
 290 PCIBus *pci_prep_init(qemu_irq *pic);
 291
 292 /* apb_pci.c */
 293 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 294                      target_phys_addr_t mem_base,
 295                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
 296
 297 /* sh_pci.c */
 298 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 299                             qemu_irq *pic, int devfn_min, int nirq);
 300
 301 #endif