target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25
  26 //#define DEBUG_KVM
  27
  28 #ifdef DEBUG_KVM
  29 #define dprintf(fmt, ...) \
  30     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  31 #else
  32 #define dprintf(fmt, ...) \
  33     do { } while (0)
  34 #endif
  35
  36 int kvm_arch_init_vcpu(CPUState *env)
  37 {
  38     struct {
  39         struct kvm_cpuid2 cpuid;
  40         struct kvm_cpuid_entry2 entries[100];
  41     } __attribute__((packed)) cpuid_data;
  42     uint32_t limit, i, j, cpuid_i;
  43     uint32_t unused;
  44
  45     cpuid_i = 0;
  46
  47     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
  48
  49     for (i = 0; i <= limit; i++) {
  50         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
  51
  52         switch (i) {
  53         case 2: {
  54             /* Keep reading function 2 till all the input is received */
  55             int times;
  56
  57             c->function = i;
  58             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
  59                        KVM_CPUID_FLAG_STATE_READ_NEXT;
  60             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
  61             times = c->eax & 0xff;
  62
  63             for (j = 1; j < times; ++j) {
  64                 c = &cpuid_data.entries[cpuid_i++];
  65                 c->function = i;
  66                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
  67                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
  68             }
  69             break;
  70         }
  71         case 4:
  72         case 0xb:
  73         case 0xd:
  74             for (j = 0; ; j++) {
  75                 c->function = i;
  76                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
  77                 c->index = j;
  78                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
  79
  80                 if (i == 4 && c->eax == 0)
  81                     break;
  82                 if (i == 0xb && !(c->ecx & 0xff00))
  83                     break;
  84                 if (i == 0xd && c->eax == 0)
  85                     break;
  86
  87                 c = &cpuid_data.entries[cpuid_i++];
  88             }
  89             break;
  90         default:
  91             c->function = i;
  92             c->flags = 0;
  93             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
  94             break;
  95         }
  96     }
  97     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
  98
  99     for (i = 0x80000000; i <= limit; i++) {
 100         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 101
 102         c->function = i;
 103         c->flags = 0;
 104         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 105     }
 106
 107     cpuid_data.cpuid.nent = cpuid_i;
 108
 109     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 110 }
 111
 112 static int kvm_has_msr_star(CPUState *env)
 113 {
 114     static int has_msr_star;
 115     int ret;
 116
 117     /* first time */
 118     if (has_msr_star == 0) {
 119         struct kvm_msr_list msr_list, *kvm_msr_list;
 120
 121         has_msr_star = -1;
 122
 123         /* Obtain MSR list from KVM.  These are the MSRs that we must
 124          * save/restore */
 125         msr_list.nmsrs = 0;
 126         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 127         if (ret < 0)
 128             return 0;
 129
 130         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 131                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 132
 133         kvm_msr_list->nmsrs = msr_list.nmsrs;
 134         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 135         if (ret >= 0) {
 136             int i;
 137
 138             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 139                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 140                     has_msr_star = 1;
 141                     break;
 142                 }
 143             }
 144         }
 145
 146         free(kvm_msr_list);
 147     }
 148
 149     if (has_msr_star == 1)
 150         return 1;
 151     return 0;
 152 }
 153
 154 int kvm_arch_init(KVMState *s, int smp_cpus)
 155 {
 156     int ret;
 157
 158     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 159      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 160      * must be part of guest physical memory, we need to allocate it.  Older
 161      * versions of KVM just assumed that it would be at the end of physical
 162      * memory but that doesn't work with more than 4GB of memory.  We simply
 163      * refuse to work with those older versions of KVM. */
 164     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 165     if (ret <= 0) {
 166         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 167         return ret;
 168     }
 169
 170     /* this address is 3 pages before the bios, and the bios should present
 171      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 172      * this?
 173      */
 174     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 175 }
 176
 177 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 178 {
 179     lhs->selector = rhs->selector;
 180     lhs->base = rhs->base;
 181     lhs->limit = rhs->limit;
 182     lhs->type = 3;
 183     lhs->present = 1;
 184     lhs->dpl = 3;
 185     lhs->db = 0;
 186     lhs->s = 1;
 187     lhs->l = 0;
 188     lhs->g = 0;
 189     lhs->avl = 0;
 190     lhs->unusable = 0;
 191 }
 192
 193 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 194 {
 195     unsigned flags = rhs->flags;
 196     lhs->selector = rhs->selector;
 197     lhs->base = rhs->base;
 198     lhs->limit = rhs->limit;
 199     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 200     lhs->present = (flags & DESC_P_MASK) != 0;
 201     lhs->dpl = rhs->selector & 3;
 202     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 203     lhs->s = (flags & DESC_S_MASK) != 0;
 204     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 205     lhs->g = (flags & DESC_G_MASK) != 0;
 206     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 207     lhs->unusable = 0;
 208 }
 209
 210 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 211 {
 212     lhs->selector = rhs->selector;
 213     lhs->base = rhs->base;
 214     lhs->limit = rhs->limit;
 215     lhs->flags =
 216         (rhs->type << DESC_TYPE_SHIFT)
 217         | (rhs->present * DESC_P_MASK)
 218         | (rhs->dpl << DESC_DPL_SHIFT)
 219         | (rhs->db << DESC_B_SHIFT)
 220         | (rhs->s * DESC_S_MASK)
 221         | (rhs->l << DESC_L_SHIFT)
 222         | (rhs->g * DESC_G_MASK)
 223         | (rhs->avl * DESC_AVL_MASK);
 224 }
 225
 226 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 227 {
 228     if (set)
 229         *kvm_reg = *qemu_reg;
 230     else
 231         *qemu_reg = *kvm_reg;
 232 }
 233
 234 static int kvm_getput_regs(CPUState *env, int set)
 235 {
 236     struct kvm_regs regs;
 237     int ret = 0;
 238
 239     if (!set) {
 240         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 241         if (ret < 0)
 242             return ret;
 243     }
 244
 245     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 246     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 247     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 248     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 249     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 250     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 251     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 252     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 253 #ifdef TARGET_X86_64
 254     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 255     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 256     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 257     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 258     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 259     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 260     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 261     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 262 #endif
 263
 264     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 265     kvm_getput_reg(&regs.rip, &env->eip, set);
 266
 267     if (set)
 268         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 269
 270     return ret;
 271 }
 272
 273 static int kvm_put_fpu(CPUState *env)
 274 {
 275     struct kvm_fpu fpu;
 276     int i;
 277
 278     memset(&fpu, 0, sizeof fpu);
 279     fpu.fsw = env->fpus & ~(7 << 11);
 280     fpu.fsw |= (env->fpstt & 7) << 11;
 281     fpu.fcw = env->fpuc;
 282     for (i = 0; i < 8; ++i)
 283         fpu.ftwx |= (!env->fptags[i]) << i;
 284     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 285     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 286     fpu.mxcsr = env->mxcsr;
 287
 288     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 289 }
 290
 291 static int kvm_put_sregs(CPUState *env)
 292 {
 293     struct kvm_sregs sregs;
 294
 295     memcpy(sregs.interrupt_bitmap,
 296            env->interrupt_bitmap,
 297            sizeof(sregs.interrupt_bitmap));
 298
 299     if ((env->eflags & VM_MASK)) {
 300             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 301             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 302             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 303             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 304             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 305             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 306     } else {
 307             set_seg(&sregs.cs, &env->segs[R_CS]);
 308             set_seg(&sregs.ds, &env->segs[R_DS]);
 309             set_seg(&sregs.es, &env->segs[R_ES]);
 310             set_seg(&sregs.fs, &env->segs[R_FS]);
 311             set_seg(&sregs.gs, &env->segs[R_GS]);
 312             set_seg(&sregs.ss, &env->segs[R_SS]);
 313
 314             if (env->cr[0] & CR0_PE_MASK) {
 315                 /* force ss cpl to cs cpl */
 316                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 317                         (sregs.cs.selector & 3);
 318                 sregs.ss.dpl = sregs.ss.selector & 3;
 319             }
 320     }
 321
 322     set_seg(&sregs.tr, &env->tr);
 323     set_seg(&sregs.ldt, &env->ldt);
 324
 325     sregs.idt.limit = env->idt.limit;
 326     sregs.idt.base = env->idt.base;
 327     sregs.gdt.limit = env->gdt.limit;
 328     sregs.gdt.base = env->gdt.base;
 329
 330     sregs.cr0 = env->cr[0];
 331     sregs.cr2 = env->cr[2];
 332     sregs.cr3 = env->cr[3];
 333     sregs.cr4 = env->cr[4];
 334
 335     sregs.cr8 = cpu_get_apic_tpr(env);
 336     sregs.apic_base = cpu_get_apic_base(env);
 337
 338     sregs.efer = env->efer;
 339
 340     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 341 }
 342
 343 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 344                               uint32_t index, uint64_t value)
 345 {
 346     entry->index = index;
 347     entry->data = value;
 348 }
 349
 350 static int kvm_put_msrs(CPUState *env)
 351 {
 352     struct {
 353         struct kvm_msrs info;
 354         struct kvm_msr_entry entries[100];
 355     } msr_data;
 356     struct kvm_msr_entry *msrs = msr_data.entries;
 357     int n = 0;
 358
 359     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 360     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 361     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 362     if (kvm_has_msr_star(env))
 363         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 364     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 365     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 366 #ifdef TARGET_X86_64
 367     /* FIXME if lm capable */
 368     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 369     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 370     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 371     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 372 #endif
 373     msr_data.info.nmsrs = n;
 374
 375     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 376
 377 }
 378
 379
 380 static int kvm_get_fpu(CPUState *env)
 381 {
 382     struct kvm_fpu fpu;
 383     int i, ret;
 384
 385     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 386     if (ret < 0)
 387         return ret;
 388
 389     env->fpstt = (fpu.fsw >> 11) & 7;
 390     env->fpus = fpu.fsw;
 391     env->fpuc = fpu.fcw;
 392     for (i = 0; i < 8; ++i)
 393         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 394     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 395     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 396     env->mxcsr = fpu.mxcsr;
 397
 398     return 0;
 399 }
 400
 401 static int kvm_get_sregs(CPUState *env)
 402 {
 403     struct kvm_sregs sregs;
 404     uint32_t hflags;
 405     int ret;
 406
 407     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 408     if (ret < 0)
 409         return ret;
 410
 411     memcpy(env->interrupt_bitmap,
 412            sregs.interrupt_bitmap,
 413            sizeof(sregs.interrupt_bitmap));
 414
 415     get_seg(&env->segs[R_CS], &sregs.cs);
 416     get_seg(&env->segs[R_DS], &sregs.ds);
 417     get_seg(&env->segs[R_ES], &sregs.es);
 418     get_seg(&env->segs[R_FS], &sregs.fs);
 419     get_seg(&env->segs[R_GS], &sregs.gs);
 420     get_seg(&env->segs[R_SS], &sregs.ss);
 421
 422     get_seg(&env->tr, &sregs.tr);
 423     get_seg(&env->ldt, &sregs.ldt);
 424
 425     env->idt.limit = sregs.idt.limit;
 426     env->idt.base = sregs.idt.base;
 427     env->gdt.limit = sregs.gdt.limit;
 428     env->gdt.base = sregs.gdt.base;
 429
 430     env->cr[0] = sregs.cr0;
 431     env->cr[2] = sregs.cr2;
 432     env->cr[3] = sregs.cr3;
 433     env->cr[4] = sregs.cr4;
 434
 435     cpu_set_apic_base(env, sregs.apic_base);
 436
 437     env->efer = sregs.efer;
 438     //cpu_set_apic_tpr(env, sregs.cr8);
 439
 440 #define HFLAG_COPY_MASK ~( \
 441                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 442                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 443                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 444                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 445
 446
 447
 448     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 449     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 450     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 451             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 452     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 453     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 454             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 455
 456     if (env->efer & MSR_EFER_LMA) {
 457         hflags |= HF_LMA_MASK;
 458     }
 459
 460     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 461         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 462     } else {
 463         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 464                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 465         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 466                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 467         if (!(env->cr[0] & CR0_PE_MASK) ||
 468                    (env->eflags & VM_MASK) ||
 469                    !(hflags & HF_CS32_MASK)) {
 470                 hflags |= HF_ADDSEG_MASK;
 471             } else {
 472                 hflags |= ((env->segs[R_DS].base |
 473                                 env->segs[R_ES].base |
 474                                 env->segs[R_SS].base) != 0) <<
 475                     HF_ADDSEG_SHIFT;
 476             }
 477     }
 478     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 479
 480     return 0;
 481 }
 482
 483 static int kvm_get_msrs(CPUState *env)
 484 {
 485     struct {
 486         struct kvm_msrs info;
 487         struct kvm_msr_entry entries[100];
 488     } msr_data;
 489     struct kvm_msr_entry *msrs = msr_data.entries;
 490     int ret, i, n;
 491
 492     n = 0;
 493     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 494     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 495     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 496     if (kvm_has_msr_star(env))
 497         msrs[n++].index = MSR_STAR;
 498     msrs[n++].index = MSR_IA32_TSC;
 499     msrs[n++].index = MSR_VM_HSAVE_PA;
 500 #ifdef TARGET_X86_64
 501     /* FIXME lm_capable_kernel */
 502     msrs[n++].index = MSR_CSTAR;
 503     msrs[n++].index = MSR_KERNELGSBASE;
 504     msrs[n++].index = MSR_FMASK;
 505     msrs[n++].index = MSR_LSTAR;
 506 #endif
 507     msr_data.info.nmsrs = n;
 508     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 509     if (ret < 0)
 510         return ret;
 511
 512     for (i = 0; i < ret; i++) {
 513         switch (msrs[i].index) {
 514         case MSR_IA32_SYSENTER_CS:
 515             env->sysenter_cs = msrs[i].data;
 516             break;
 517         case MSR_IA32_SYSENTER_ESP:
 518             env->sysenter_esp = msrs[i].data;
 519             break;
 520         case MSR_IA32_SYSENTER_EIP:
 521             env->sysenter_eip = msrs[i].data;
 522             break;
 523         case MSR_STAR:
 524             env->star = msrs[i].data;
 525             break;
 526 #ifdef TARGET_X86_64
 527         case MSR_CSTAR:
 528             env->cstar = msrs[i].data;
 529             break;
 530         case MSR_KERNELGSBASE:
 531             env->kernelgsbase = msrs[i].data;
 532             break;
 533         case MSR_FMASK:
 534             env->fmask = msrs[i].data;
 535             break;
 536         case MSR_LSTAR:
 537             env->lstar = msrs[i].data;
 538             break;
 539 #endif
 540         case MSR_IA32_TSC:
 541             env->tsc = msrs[i].data;
 542             break;
 543         case MSR_VM_HSAVE_PA:
 544             env->vm_hsave = msrs[i].data;
 545             break;
 546         }
 547     }
 548
 549     return 0;
 550 }
 551
 552 int kvm_arch_put_registers(CPUState *env)
 553 {
 554     int ret;
 555
 556     ret = kvm_getput_regs(env, 1);
 557     if (ret < 0)
 558         return ret;
 559
 560     ret = kvm_put_fpu(env);
 561     if (ret < 0)
 562         return ret;
 563
 564     ret = kvm_put_sregs(env);
 565     if (ret < 0)
 566         return ret;
 567
 568     ret = kvm_put_msrs(env);
 569     if (ret < 0)
 570         return ret;
 571
 572     return 0;
 573 }
 574
 575 int kvm_arch_get_registers(CPUState *env)
 576 {
 577     int ret;
 578
 579     ret = kvm_getput_regs(env, 0);
 580     if (ret < 0)
 581         return ret;
 582
 583     ret = kvm_get_fpu(env);
 584     if (ret < 0)
 585         return ret;
 586
 587     ret = kvm_get_sregs(env);
 588     if (ret < 0)
 589         return ret;
 590
 591     ret = kvm_get_msrs(env);
 592     if (ret < 0)
 593         return ret;
 594
 595     return 0;
 596 }
 597
 598 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 599 {
 600     /* Try to inject an interrupt if the guest can accept it */
 601     if (run->ready_for_interrupt_injection &&
 602         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 603         (env->eflags & IF_MASK)) {
 604         int irq;
 605
 606         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 607         irq = cpu_get_pic_interrupt(env);
 608         if (irq >= 0) {
 609             struct kvm_interrupt intr;
 610             intr.irq = irq;
 611             /* FIXME: errors */
 612             dprintf("injected interrupt %d\n", irq);
 613             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 614         }
 615     }
 616
 617     /* If we have an interrupt but the guest is not ready to receive an
 618      * interrupt, request an interrupt window exit.  This will
 619      * cause a return to userspace as soon as the guest is ready to
 620      * receive interrupts. */
 621     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 622         run->request_interrupt_window = 1;
 623     else
 624         run->request_interrupt_window = 0;
 625
 626     dprintf("setting tpr\n");
 627     run->cr8 = cpu_get_apic_tpr(env);
 628
 629     return 0;
 630 }
 631
 632 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 633 {
 634     if (run->if_flag)
 635         env->eflags |= IF_MASK;
 636     else
 637         env->eflags &= ~IF_MASK;
 638
 639     cpu_set_apic_tpr(env, run->cr8);
 640     cpu_set_apic_base(env, run->apic_base);
 641
 642     return 0;
 643 }
 644
 645 static int kvm_handle_halt(CPUState *env)
 646 {
 647     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 648           (env->eflags & IF_MASK)) &&
 649         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 650         env->halted = 1;
 651         env->exception_index = EXCP_HLT;
 652         return 0;
 653     }
 654
 655     return 1;
 656 }
 657
 658 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 659 {
 660     int ret = 0;
 661
 662     switch (run->exit_reason) {
 663     case KVM_EXIT_HLT:
 664         dprintf("handle_hlt\n");
 665         ret = kvm_handle_halt(env);
 666         break;
 667     }
 668
 669     return ret;
 670 }