hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24
  25 #include "qemu-kvm.h"
  26
  27 //#define DEBUG_APIC
  28 //#define DEBUG_IOAPIC
  29
  30 /* APIC Local Vector Table */
  31 #define APIC_LVT_TIMER   0
  32 #define APIC_LVT_THERMAL 1
  33 #define APIC_LVT_PERFORM 2
  34 #define APIC_LVT_LINT0   3
  35 #define APIC_LVT_LINT1   4
  36 #define APIC_LVT_ERROR   5
  37 #define APIC_LVT_NB      6
  38
  39 /* APIC delivery modes */
  40 #define APIC_DM_FIXED   0
  41 #define APIC_DM_LOWPRI  1
  42 #define APIC_DM_SMI     2
  43 #define APIC_DM_NMI     4
  44 #define APIC_DM_INIT    5
  45 #define APIC_DM_SIPI    6
  46 #define APIC_DM_EXTINT  7
  47
  48 /* APIC destination mode */
  49 #define APIC_DESTMODE_FLAT      0xf
  50 #define APIC_DESTMODE_CLUSTER   1
  51
  52 #define APIC_TRIGGER_EDGE  0
  53 #define APIC_TRIGGER_LEVEL 1
  54
  55 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  56 #define APIC_LVT_MASKED                 (1<<16)
  57 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  58 #define APIC_LVT_REMOTE_IRR             (1<<14)
  59 #define APIC_INPUT_POLARITY             (1<<13)
  60 #define APIC_SEND_PENDING               (1<<12)
  61
  62 /* FIXME: it's now hard coded to be equal with KVM_IOAPIC_NUM_PINS */
  63 #define IOAPIC_NUM_PINS                 0x18
  64 #define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
  65
  66 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  67
  68 #define APIC_SV_ENABLE (1 << 8)
  69
  70 #define MAX_APICS 255
  71 #define MAX_APIC_WORDS 8
  72
  73 typedef struct APICState {
  74     CPUState *cpu_env;
  75     uint32_t apicbase;
  76     uint8_t id;
  77     uint8_t arb_id;
  78     uint8_t tpr;
  79     uint32_t spurious_vec;
  80     uint8_t log_dest;
  81     uint8_t dest_mode;
  82     uint32_t isr[8];  /* in service register */
  83     uint32_t tmr[8];  /* trigger mode register */
  84     uint32_t irr[8]; /* interrupt request register */
  85     uint32_t lvt[APIC_LVT_NB];
  86     uint32_t esr; /* error register */
  87     uint32_t icr[2];
  88
  89     uint32_t divide_conf;
  90     int count_shift;
  91     uint32_t initial_count;
  92     int64_t initial_count_load_time, next_time;
  93     QEMUTimer *timer;
  94 } APICState;
  95
  96 struct IOAPICState {
  97     uint8_t id;
  98     uint8_t ioregsel;
  99     uint64_t base_address;
 100
 101     uint32_t irr;
 102     uint64_t ioredtbl[IOAPIC_NUM_PINS];
 103 };
 104
 105 static int apic_io_memory;
 106 static APICState *local_apics[MAX_APICS + 1];
 107 static int last_apic_id = 0;
 108 static int apic_irq_delivered;
 109
 110
 111 static void apic_init_ipi(APICState *s);
 112 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 113 static void apic_update_irq(APICState *s);
 114
 115 /* Find first bit starting from msb */
 116 static int fls_bit(uint32_t value)
 117 {
 118     return 31 - clz32(value);
 119 }
 120
 121 /* Find first bit starting from lsb */
 122 static int ffs_bit(uint32_t value)
 123 {
 124     return ctz32(value);
 125 }
 126
 127 static inline void set_bit(uint32_t *tab, int index)
 128 {
 129     int i, mask;
 130     i = index >> 5;
 131     mask = 1 << (index & 0x1f);
 132     tab[i] |= mask;
 133 }
 134
 135 static inline void reset_bit(uint32_t *tab, int index)
 136 {
 137     int i, mask;
 138     i = index >> 5;
 139     mask = 1 << (index & 0x1f);
 140     tab[i] &= ~mask;
 141 }
 142
 143 static inline int get_bit(uint32_t *tab, int index)
 144 {
 145     int i, mask;
 146     i = index >> 5;
 147     mask = 1 << (index & 0x1f);
 148     return !!(tab[i] & mask);
 149 }
 150
 151 static void apic_local_deliver(CPUState *env, int vector)
 152 {
 153     APICState *s = env->apic_state;
 154     uint32_t lvt = s->lvt[vector];
 155     int trigger_mode;
 156
 157     if (lvt & APIC_LVT_MASKED)
 158         return;
 159
 160     switch ((lvt >> 8) & 7) {
 161     case APIC_DM_SMI:
 162         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 163         break;
 164
 165     case APIC_DM_NMI:
 166         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 167         break;
 168
 169     case APIC_DM_EXTINT:
 170         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 171         break;
 172
 173     case APIC_DM_FIXED:
 174         trigger_mode = APIC_TRIGGER_EDGE;
 175         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 176             (lvt & APIC_LVT_LEVEL_TRIGGER))
 177             trigger_mode = APIC_TRIGGER_LEVEL;
 178         apic_set_irq(s, lvt & 0xff, trigger_mode);
 179     }
 180 }
 181
 182 void apic_deliver_pic_intr(CPUState *env, int level)
 183 {
 184     if (level)
 185         apic_local_deliver(env, APIC_LVT_LINT0);
 186     else {
 187         APICState *s = env->apic_state;
 188         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 189
 190         switch ((lvt >> 8) & 7) {
 191         case APIC_DM_FIXED:
 192             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 193                 break;
 194             reset_bit(s->irr, lvt & 0xff);
 195             /* fall through */
 196         case APIC_DM_EXTINT:
 197             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 198             break;
 199         }
 200     }
 201 }
 202
 203 #define foreach_apic(apic, deliver_bitmask, code) \
 204 {\
 205     int __i, __j, __mask;\
 206     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 207         __mask = deliver_bitmask[__i];\
 208         if (__mask) {\
 209             for(__j = 0; __j < 32; __j++) {\
 210                 if (__mask & (1 << __j)) {\
 211                     apic = local_apics[__i * 32 + __j];\
 212                     if (apic) {\
 213                         code;\
 214                     }\
 215                 }\
 216             }\
 217         }\
 218     }\
 219 }
 220
 221 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 222                              uint8_t delivery_mode,
 223                              uint8_t vector_num, uint8_t polarity,
 224                              uint8_t trigger_mode)
 225 {
 226     APICState *apic_iter;
 227
 228     switch (delivery_mode) {
 229         case APIC_DM_LOWPRI:
 230             /* XXX: search for focus processor, arbitration */
 231             {
 232                 int i, d;
 233                 d = -1;
 234                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 235                     if (deliver_bitmask[i]) {
 236                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 237                         break;
 238                     }
 239                 }
 240                 if (d >= 0) {
 241                     apic_iter = local_apics[d];
 242                     if (apic_iter) {
 243                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 244                     }
 245                 }
 246             }
 247             return;
 248
 249         case APIC_DM_FIXED:
 250             break;
 251
 252         case APIC_DM_SMI:
 253             foreach_apic(apic_iter, deliver_bitmask,
 254                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 255             return;
 256
 257         case APIC_DM_NMI:
 258             foreach_apic(apic_iter, deliver_bitmask,
 259                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 260             return;
 261
 262         case APIC_DM_INIT:
 263             /* normal INIT IPI sent to processors */
 264             foreach_apic(apic_iter, deliver_bitmask,
 265                          apic_init_ipi(apic_iter) );
 266             return;
 267
 268         case APIC_DM_EXTINT:
 269             /* handled in I/O APIC code */
 270             break;
 271
 272         default:
 273             return;
 274     }
 275
 276     foreach_apic(apic_iter, deliver_bitmask,
 277                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 278 }
 279
 280 void cpu_set_apic_base(CPUState *env, uint64_t val)
 281 {
 282     APICState *s = env->apic_state;
 283 #ifdef DEBUG_APIC
 284     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 285 #endif
 286     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel())
 287         s->apicbase = val;
 288     else
 289         s->apicbase = (val & 0xfffff000) |
 290             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 291     /* if disabled, cannot be enabled again */
 292     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 293         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 294         env->cpuid_features &= ~CPUID_APIC;
 295         s->spurious_vec &= ~APIC_SV_ENABLE;
 296     }
 297 }
 298
 299 uint64_t cpu_get_apic_base(CPUState *env)
 300 {
 301     APICState *s = env->apic_state;
 302 #ifdef DEBUG_APIC
 303     printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
 304 #endif
 305     return s->apicbase;
 306 }
 307
 308 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 309 {
 310     APICState *s = env->apic_state;
 311     s->tpr = (val & 0x0f) << 4;
 312     apic_update_irq(s);
 313 }
 314
 315 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 316 {
 317     APICState *s = env->apic_state;
 318     return s->tpr >> 4;
 319 }
 320
 321 /* return -1 if no bit is set */
 322 static int get_highest_priority_int(uint32_t *tab)
 323 {
 324     int i;
 325     for(i = 7; i >= 0; i--) {
 326         if (tab[i] != 0) {
 327             return i * 32 + fls_bit(tab[i]);
 328         }
 329     }
 330     return -1;
 331 }
 332
 333 static int apic_get_ppr(APICState *s)
 334 {
 335     int tpr, isrv, ppr;
 336
 337     tpr = (s->tpr >> 4);
 338     isrv = get_highest_priority_int(s->isr);
 339     if (isrv < 0)
 340         isrv = 0;
 341     isrv >>= 4;
 342     if (tpr >= isrv)
 343         ppr = s->tpr;
 344     else
 345         ppr = isrv << 4;
 346     return ppr;
 347 }
 348
 349 static int apic_get_arb_pri(APICState *s)
 350 {
 351     /* XXX: arbitration */
 352     return 0;
 353 }
 354
 355 /* signal the CPU if an irq is pending */
 356 static void apic_update_irq(APICState *s)
 357 {
 358     int irrv, ppr;
 359     if (!(s->spurious_vec & APIC_SV_ENABLE))
 360         return;
 361     irrv = get_highest_priority_int(s->irr);
 362     if (irrv < 0)
 363         return;
 364     ppr = apic_get_ppr(s);
 365     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 366         return;
 367     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 368 }
 369
 370 void apic_reset_irq_delivered(void)
 371 {
 372     apic_irq_delivered = 0;
 373 }
 374
 375 int apic_get_irq_delivered(void)
 376 {
 377     return apic_irq_delivered;
 378 }
 379
 380 void apic_set_irq_delivered(void)
 381 {
 382     apic_irq_delivered = 1;
 383 }
 384
 385 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 386 {
 387     apic_irq_delivered += !get_bit(s->irr, vector_num);
 388
 389     set_bit(s->irr, vector_num);
 390     if (trigger_mode)
 391         set_bit(s->tmr, vector_num);
 392     else
 393         reset_bit(s->tmr, vector_num);
 394     apic_update_irq(s);
 395 }
 396
 397 static void apic_eoi(APICState *s)
 398 {
 399     int isrv;
 400     isrv = get_highest_priority_int(s->isr);
 401     if (isrv < 0)
 402         return;
 403     reset_bit(s->isr, isrv);
 404     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 405             set the remote IRR bit for level triggered interrupts. */
 406     apic_update_irq(s);
 407 }
 408
 409 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 410                                       uint8_t dest, uint8_t dest_mode)
 411 {
 412     APICState *apic_iter;
 413     int i;
 414
 415     if (dest_mode == 0) {
 416         if (dest == 0xff) {
 417             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 418         } else {
 419             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 420             set_bit(deliver_bitmask, dest);
 421         }
 422     } else {
 423         /* XXX: cluster mode */
 424         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 425         for(i = 0; i < MAX_APICS; i++) {
 426             apic_iter = local_apics[i];
 427             if (apic_iter) {
 428                 if (apic_iter->dest_mode == 0xf) {
 429                     if (dest & apic_iter->log_dest)
 430                         set_bit(deliver_bitmask, i);
 431                 } else if (apic_iter->dest_mode == 0x0) {
 432                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 433                         (dest & apic_iter->log_dest & 0x0f)) {
 434                         set_bit(deliver_bitmask, i);
 435                     }
 436                 }
 437             }
 438         }
 439     }
 440 }
 441
 442
 443 static void apic_init_ipi(APICState *s)
 444 {
 445     int i;
 446
 447     s->tpr = 0;
 448     s->spurious_vec = 0xff;
 449     s->log_dest = 0;
 450     s->dest_mode = 0xf;
 451     memset(s->isr, 0, sizeof(s->isr));
 452     memset(s->tmr, 0, sizeof(s->tmr));
 453     memset(s->irr, 0, sizeof(s->irr));
 454     for(i = 0; i < APIC_LVT_NB; i++)
 455         s->lvt[i] = 1 << 16; /* mask LVT */
 456     s->esr = 0;
 457     memset(s->icr, 0, sizeof(s->icr));
 458     s->divide_conf = 0;
 459     s->count_shift = 0;
 460     s->initial_count = 0;
 461     s->initial_count_load_time = 0;
 462     s->next_time = 0;
 463
 464     cpu_reset(s->cpu_env);
 465
 466     if (!(s->apicbase & MSR_IA32_APICBASE_BSP) &&
 467         (!kvm_enabled() || !qemu_kvm_irqchip_in_kernel()))
 468         s->cpu_env->halted = 1;
 469
 470     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 471         if (s->cpu_env)
 472             kvm_apic_init(s->cpu_env);
 473 }
 474
 475 /* send a SIPI message to the CPU to start it */
 476 static void apic_startup(APICState *s, int vector_num)
 477 {
 478     CPUState *env = s->cpu_env;
 479     if (!env->halted)
 480         return;
 481     env->eip = 0;
 482     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
 483                            0xffff, 0);
 484     env->halted = 0;
 485     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 486         kvm_update_after_sipi(env);
 487 }
 488
 489 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 490                          uint8_t delivery_mode, uint8_t vector_num,
 491                          uint8_t polarity, uint8_t trigger_mode)
 492 {
 493     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 494     int dest_shorthand = (s->icr[0] >> 18) & 3;
 495     APICState *apic_iter;
 496
 497     switch (dest_shorthand) {
 498     case 0:
 499         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 500         break;
 501     case 1:
 502         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 503         set_bit(deliver_bitmask, s->id);
 504         break;
 505     case 2:
 506         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 507         break;
 508     case 3:
 509         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 510         reset_bit(deliver_bitmask, s->id);
 511         break;
 512     }
 513
 514     switch (delivery_mode) {
 515         case APIC_DM_INIT:
 516             {
 517                 int trig_mode = (s->icr[0] >> 15) & 1;
 518                 int level = (s->icr[0] >> 14) & 1;
 519                 if (level == 0 && trig_mode == 1) {
 520                     foreach_apic(apic_iter, deliver_bitmask,
 521                                  apic_iter->arb_id = apic_iter->id );
 522                     return;
 523                 }
 524             }
 525             break;
 526
 527         case APIC_DM_SIPI:
 528             foreach_apic(apic_iter, deliver_bitmask,
 529                          apic_startup(apic_iter, vector_num) );
 530             return;
 531     }
 532
 533     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 534                      trigger_mode);
 535 }
 536
 537 int apic_get_interrupt(CPUState *env)
 538 {
 539     APICState *s = env->apic_state;
 540     int intno;
 541
 542     /* if the APIC is installed or enabled, we let the 8259 handle the
 543        IRQs */
 544     if (!s)
 545         return -1;
 546     if (!(s->spurious_vec & APIC_SV_ENABLE))
 547         return -1;
 548
 549     /* XXX: spurious IRQ handling */
 550     intno = get_highest_priority_int(s->irr);
 551     if (intno < 0)
 552         return -1;
 553     if (s->tpr && intno <= s->tpr)
 554         return s->spurious_vec & 0xff;
 555     reset_bit(s->irr, intno);
 556     set_bit(s->isr, intno);
 557     apic_update_irq(s);
 558     return intno;
 559 }
 560
 561 int apic_accept_pic_intr(CPUState *env)
 562 {
 563     APICState *s = env->apic_state;
 564     uint32_t lvt0;
 565
 566     if (!s)
 567         return -1;
 568
 569     lvt0 = s->lvt[APIC_LVT_LINT0];
 570
 571     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 572         (lvt0 & APIC_LVT_MASKED) == 0)
 573         return 1;
 574
 575     return 0;
 576 }
 577
 578 static uint32_t apic_get_current_count(APICState *s)
 579 {
 580     int64_t d;
 581     uint32_t val;
 582     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 583         s->count_shift;
 584     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 585         /* periodic */
 586         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 587     } else {
 588         if (d >= s->initial_count)
 589             val = 0;
 590         else
 591             val = s->initial_count - d;
 592     }
 593     return val;
 594 }
 595
 596 static void apic_timer_update(APICState *s, int64_t current_time)
 597 {
 598     int64_t next_time, d;
 599
 600     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 601         d = (current_time - s->initial_count_load_time) >>
 602             s->count_shift;
 603         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 604             if (!s->initial_count)
 605                 goto no_timer;
 606             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 607         } else {
 608             if (d >= s->initial_count)
 609                 goto no_timer;
 610             d = (uint64_t)s->initial_count + 1;
 611         }
 612         next_time = s->initial_count_load_time + (d << s->count_shift);
 613         qemu_mod_timer(s->timer, next_time);
 614         s->next_time = next_time;
 615     } else {
 616     no_timer:
 617         qemu_del_timer(s->timer);
 618     }
 619 }
 620
 621 static void apic_timer(void *opaque)
 622 {
 623     APICState *s = opaque;
 624
 625     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 626     apic_timer_update(s, s->next_time);
 627 }
 628
 629 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 630 {
 631     return 0;
 632 }
 633
 634 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 635 {
 636     return 0;
 637 }
 638
 639 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 640 {
 641 }
 642
 643 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 644 {
 645 }
 646
 647 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 648 {
 649     CPUState *env;
 650     APICState *s;
 651     uint32_t val;
 652     int index;
 653
 654     env = cpu_single_env;
 655     if (!env)
 656         return 0;
 657     s = env->apic_state;
 658
 659     index = (addr >> 4) & 0xff;
 660     switch(index) {
 661     case 0x02: /* id */
 662         val = s->id << 24;
 663         break;
 664     case 0x03: /* version */
 665         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 666         break;
 667     case 0x08:
 668         val = s->tpr;
 669         break;
 670     case 0x09:
 671         val = apic_get_arb_pri(s);
 672         break;
 673     case 0x0a:
 674         /* ppr */
 675         val = apic_get_ppr(s);
 676         break;
 677     case 0x0b:
 678         val = 0;
 679         break;
 680     case 0x0d:
 681         val = s->log_dest << 24;
 682         break;
 683     case 0x0e:
 684         val = s->dest_mode << 28;
 685         break;
 686     case 0x0f:
 687         val = s->spurious_vec;
 688         break;
 689     case 0x10 ... 0x17:
 690         val = s->isr[index & 7];
 691         break;
 692     case 0x18 ... 0x1f:
 693         val = s->tmr[index & 7];
 694         break;
 695     case 0x20 ... 0x27:
 696         val = s->irr[index & 7];
 697         break;
 698     case 0x28:
 699         val = s->esr;
 700         break;
 701     case 0x30:
 702     case 0x31:
 703         val = s->icr[index & 1];
 704         break;
 705     case 0x32 ... 0x37:
 706         val = s->lvt[index - 0x32];
 707         break;
 708     case 0x38:
 709         val = s->initial_count;
 710         break;
 711     case 0x39:
 712         val = apic_get_current_count(s);
 713         break;
 714     case 0x3e:
 715         val = s->divide_conf;
 716         break;
 717     default:
 718         s->esr |= ESR_ILLEGAL_ADDRESS;
 719         val = 0;
 720         break;
 721     }
 722 #ifdef DEBUG_APIC
 723     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 724 #endif
 725     return val;
 726 }
 727
 728 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 729 {
 730     CPUState *env;
 731     APICState *s;
 732     int index;
 733
 734     env = cpu_single_env;
 735     if (!env)
 736         return;
 737     s = env->apic_state;
 738
 739 #ifdef DEBUG_APIC
 740     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 741 #endif
 742
 743     index = (addr >> 4) & 0xff;
 744     switch(index) {
 745     case 0x02:
 746         s->id = (val >> 24);
 747         break;
 748     case 0x03:
 749         break;
 750     case 0x08:
 751         s->tpr = val;
 752         apic_update_irq(s);
 753         break;
 754     case 0x09:
 755     case 0x0a:
 756         break;
 757     case 0x0b: /* EOI */
 758         apic_eoi(s);
 759         break;
 760     case 0x0d:
 761         s->log_dest = val >> 24;
 762         break;
 763     case 0x0e:
 764         s->dest_mode = val >> 28;
 765         break;
 766     case 0x0f:
 767         s->spurious_vec = val & 0x1ff;
 768         apic_update_irq(s);
 769         break;
 770     case 0x10 ... 0x17:
 771     case 0x18 ... 0x1f:
 772     case 0x20 ... 0x27:
 773     case 0x28:
 774         break;
 775     case 0x30:
 776         s->icr[0] = val;
 777         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 778                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 779                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 780         break;
 781     case 0x31:
 782         s->icr[1] = val;
 783         break;
 784     case 0x32 ... 0x37:
 785         {
 786             int n = index - 0x32;
 787             s->lvt[n] = val;
 788             if (n == APIC_LVT_TIMER)
 789                 apic_timer_update(s, qemu_get_clock(vm_clock));
 790         }
 791         break;
 792     case 0x38:
 793         s->initial_count = val;
 794         s->initial_count_load_time = qemu_get_clock(vm_clock);
 795         apic_timer_update(s, s->initial_count_load_time);
 796         break;
 797     case 0x39:
 798         break;
 799     case 0x3e:
 800         {
 801             int v;
 802             s->divide_conf = val & 0xb;
 803             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 804             s->count_shift = (v + 1) & 7;
 805         }
 806         break;
 807     default:
 808         s->esr |= ESR_ILLEGAL_ADDRESS;
 809         break;
 810     }
 811 }
 812
 813 #ifdef KVM_CAP_IRQCHIP
 814
 815 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 816 {
 817     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 818 }
 819
 820 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 821                                  int reg_id, uint32_t val)
 822 {
 823     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 824 }
 825
 826 static void kvm_kernel_lapic_save_to_user(APICState *s)
 827 {
 828     struct kvm_lapic_state apic;
 829     struct kvm_lapic_state *kapic = &apic;
 830     int i, v;
 831
 832     kvm_get_lapic(kvm_context, s->cpu_env->cpu_index, kapic);
 833
 834     s->id = kapic_reg(kapic, 0x2) >> 24;
 835     s->tpr = kapic_reg(kapic, 0x8);
 836     s->arb_id = kapic_reg(kapic, 0x9);
 837     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 838     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 839     s->spurious_vec = kapic_reg(kapic, 0xf);
 840     for (i = 0; i < 8; i++) {
 841         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 842         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 843         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 844     }
 845     s->esr = kapic_reg(kapic, 0x28);
 846     s->icr[0] = kapic_reg(kapic, 0x30);
 847     s->icr[1] = kapic_reg(kapic, 0x31);
 848     for (i = 0; i < APIC_LVT_NB; i++)
 849         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 850     s->initial_count = kapic_reg(kapic, 0x38);
 851     s->divide_conf = kapic_reg(kapic, 0x3e);
 852
 853     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 854     s->count_shift = (v + 1) & 7;
 855
 856     s->initial_count_load_time = qemu_get_clock(vm_clock);
 857     apic_timer_update(s, s->initial_count_load_time);
 858 }
 859
 860 static void kvm_kernel_lapic_load_from_user(APICState *s)
 861 {
 862     struct kvm_lapic_state apic;
 863     struct kvm_lapic_state *klapic = &apic;
 864     int i;
 865
 866     memset(klapic, 0, sizeof apic);
 867     kapic_set_reg(klapic, 0x2, s->id << 24);
 868     kapic_set_reg(klapic, 0x8, s->tpr);
 869     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 870     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 871     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 872     for (i = 0; i < 8; i++) {
 873         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 874         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 875         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 876     }
 877     kapic_set_reg(klapic, 0x28, s->esr);
 878     kapic_set_reg(klapic, 0x30, s->icr[0]);
 879     kapic_set_reg(klapic, 0x31, s->icr[1]);
 880     for (i = 0; i < APIC_LVT_NB; i++)
 881         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 882     kapic_set_reg(klapic, 0x38, s->initial_count);
 883     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 884
 885     kvm_set_lapic(kvm_context, s->cpu_env->cpu_index, klapic);
 886 }
 887
 888 #endif
 889
 890 static void apic_save(QEMUFile *f, void *opaque)
 891 {
 892     APICState *s = opaque;
 893     int i;
 894
 895 #ifdef KVM_CAP_IRQCHIP
 896     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 897         kvm_kernel_lapic_save_to_user(s);
 898     }
 899 #endif
 900
 901     qemu_put_be32s(f, &s->apicbase);
 902     qemu_put_8s(f, &s->id);
 903     qemu_put_8s(f, &s->arb_id);
 904     qemu_put_8s(f, &s->tpr);
 905     qemu_put_be32s(f, &s->spurious_vec);
 906     qemu_put_8s(f, &s->log_dest);
 907     qemu_put_8s(f, &s->dest_mode);
 908     for (i = 0; i < 8; i++) {
 909         qemu_put_be32s(f, &s->isr[i]);
 910         qemu_put_be32s(f, &s->tmr[i]);
 911         qemu_put_be32s(f, &s->irr[i]);
 912     }
 913     for (i = 0; i < APIC_LVT_NB; i++) {
 914         qemu_put_be32s(f, &s->lvt[i]);
 915     }
 916     qemu_put_be32s(f, &s->esr);
 917     qemu_put_be32s(f, &s->icr[0]);
 918     qemu_put_be32s(f, &s->icr[1]);
 919     qemu_put_be32s(f, &s->divide_conf);
 920     qemu_put_be32(f, s->count_shift);
 921     qemu_put_be32s(f, &s->initial_count);
 922     qemu_put_be64(f, s->initial_count_load_time);
 923     qemu_put_be64(f, s->next_time);
 924
 925     qemu_put_timer(f, s->timer);
 926 }
 927
 928 static int apic_load(QEMUFile *f, void *opaque, int version_id)
 929 {
 930     APICState *s = opaque;
 931     int i;
 932
 933     if (version_id > 2)
 934         return -EINVAL;
 935
 936     /* XXX: what if the base changes? (registered memory regions) */
 937     qemu_get_be32s(f, &s->apicbase);
 938     qemu_get_8s(f, &s->id);
 939     qemu_get_8s(f, &s->arb_id);
 940     qemu_get_8s(f, &s->tpr);
 941     qemu_get_be32s(f, &s->spurious_vec);
 942     qemu_get_8s(f, &s->log_dest);
 943     qemu_get_8s(f, &s->dest_mode);
 944     for (i = 0; i < 8; i++) {
 945         qemu_get_be32s(f, &s->isr[i]);
 946         qemu_get_be32s(f, &s->tmr[i]);
 947         qemu_get_be32s(f, &s->irr[i]);
 948     }
 949     for (i = 0; i < APIC_LVT_NB; i++) {
 950         qemu_get_be32s(f, &s->lvt[i]);
 951     }
 952     qemu_get_be32s(f, &s->esr);
 953     qemu_get_be32s(f, &s->icr[0]);
 954     qemu_get_be32s(f, &s->icr[1]);
 955     qemu_get_be32s(f, &s->divide_conf);
 956     s->count_shift=qemu_get_be32(f);
 957     qemu_get_be32s(f, &s->initial_count);
 958     s->initial_count_load_time=qemu_get_be64(f);
 959     s->next_time=qemu_get_be64(f);
 960
 961     if (version_id >= 2)
 962         qemu_get_timer(f, s->timer);
 963
 964 #ifdef KVM_CAP_IRQCHIP
 965     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 966         kvm_kernel_lapic_load_from_user(s);
 967     }
 968 #endif
 969
 970     return 0;
 971 }
 972
 973 static void apic_reset(void *opaque)
 974 {
 975     APICState *s = opaque;
 976
 977     s->apicbase = 0xfee00000 |
 978         (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
 979
 980     apic_init_ipi(s);
 981
 982     if (s->id == 0) {
 983         /*
 984          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 985          * time typically by BIOS, so PIC interrupt can be delivered to the
 986          * processor when local APIC is enabled.
 987          */
 988         s->lvt[APIC_LVT_LINT0] = 0x700;
 989     }
 990 #ifdef KVM_CAP_IRQCHIP
 991     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 992         kvm_kernel_lapic_load_from_user(s);
 993     }
 994 #endif
 995 }
 996
 997 static CPUReadMemoryFunc *apic_mem_read[3] = {
 998     apic_mem_readb,
 999     apic_mem_readw,
1000     apic_mem_readl,
1001 };
1002
1003 static CPUWriteMemoryFunc *apic_mem_write[3] = {
1004     apic_mem_writeb,
1005     apic_mem_writew,
1006     apic_mem_writel,
1007 };
1008
1009 int apic_init(CPUState *env)
1010 {
1011     APICState *s;
1012
1013     if (last_apic_id >= MAX_APICS)
1014         return -1;
1015     s = qemu_mallocz(sizeof(APICState));
1016     env->apic_state = s;
1017     s->id = last_apic_id++;
1018     env->cpuid_apic_id = s->id;
1019     s->cpu_env = env;
1020
1021     apic_reset(s);
1022
1023     /* XXX: mapping more APICs at the same memory location */
1024     if (apic_io_memory == 0) {
1025         /* NOTE: the APIC is directly connected to the CPU - it is not
1026            on the global memory bus. */
1027         apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1028                                                 apic_mem_write, NULL);
1029         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1030                                      apic_io_memory);
1031     }
1032     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1033
1034     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
1035     qemu_register_reset(apic_reset, s);
1036
1037     local_apics[s->id] = s;
1038     return 0;
1039 }
1040
1041 static void ioapic_service(IOAPICState *s)
1042 {
1043     uint8_t i;
1044     uint8_t trig_mode;
1045     uint8_t vector;
1046     uint8_t delivery_mode;
1047     uint32_t mask;
1048     uint64_t entry;
1049     uint8_t dest;
1050     uint8_t dest_mode;
1051     uint8_t polarity;
1052     uint32_t deliver_bitmask[MAX_APIC_WORDS];
1053
1054     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1055         mask = 1 << i;
1056         if (s->irr & mask) {
1057             entry = s->ioredtbl[i];
1058             if (!(entry & APIC_LVT_MASKED)) {
1059                 trig_mode = ((entry >> 15) & 1);
1060                 dest = entry >> 56;
1061                 dest_mode = (entry >> 11) & 1;
1062                 delivery_mode = (entry >> 8) & 7;
1063                 polarity = (entry >> 13) & 1;
1064                 if (trig_mode == APIC_TRIGGER_EDGE)
1065                     s->irr &= ~mask;
1066                 if (delivery_mode == APIC_DM_EXTINT)
1067                     vector = pic_read_irq(isa_pic);
1068                 else
1069                     vector = entry & 0xff;
1070
1071                 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
1072                 apic_bus_deliver(deliver_bitmask, delivery_mode,
1073                                  vector, polarity, trig_mode);
1074             }
1075         }
1076     }
1077 }
1078
1079 void ioapic_set_irq(void *opaque, int vector, int level)
1080 {
1081     IOAPICState *s = opaque;
1082
1083 #if 0
1084     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
1085      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
1086      * the cleanest way of doing it but it should work. */
1087
1088     if (vector == 0)
1089         vector = 2;
1090 #endif
1091
1092     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1093         uint32_t mask = 1 << vector;
1094         uint64_t entry = s->ioredtbl[vector];
1095
1096         if ((entry >> 15) & 1) {
1097             /* level triggered */
1098             if (level) {
1099                 s->irr |= mask;
1100                 ioapic_service(s);
1101             } else {
1102                 s->irr &= ~mask;
1103             }
1104         } else {
1105             /* edge triggered */
1106             if (level) {
1107                 s->irr |= mask;
1108                 ioapic_service(s);
1109             }
1110         }
1111     }
1112 }
1113
1114 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1115 {
1116     IOAPICState *s = opaque;
1117     int index;
1118     uint32_t val = 0;
1119
1120     addr &= 0xff;
1121     if (addr == 0x00) {
1122         val = s->ioregsel;
1123     } else if (addr == 0x10) {
1124         switch (s->ioregsel) {
1125             case 0x00:
1126                 val = s->id << 24;
1127                 break;
1128             case 0x01:
1129                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1130                 break;
1131             case 0x02:
1132                 val = 0;
1133                 break;
1134             default:
1135                 index = (s->ioregsel - 0x10) >> 1;
1136                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1137                     if (s->ioregsel & 1)
1138                         val = s->ioredtbl[index] >> 32;
1139                     else
1140                         val = s->ioredtbl[index] & 0xffffffff;
1141                 }
1142         }
1143 #ifdef DEBUG_IOAPIC
1144         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
1145 #endif
1146     }
1147     return val;
1148 }
1149
1150 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1151 {
1152     IOAPICState *s = opaque;
1153     int index;
1154
1155     addr &= 0xff;
1156     if (addr == 0x00)  {
1157         s->ioregsel = val;
1158         return;
1159     } else if (addr == 0x10) {
1160 #ifdef DEBUG_IOAPIC
1161         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
1162 #endif
1163         switch (s->ioregsel) {
1164             case 0x00:
1165                 s->id = (val >> 24) & 0xff;
1166                 return;
1167             case 0x01:
1168             case 0x02:
1169                 return;
1170             default:
1171                 index = (s->ioregsel - 0x10) >> 1;
1172                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1173                     if (s->ioregsel & 1) {
1174                         s->ioredtbl[index] &= 0xffffffff;
1175                         s->ioredtbl[index] |= (uint64_t)val << 32;
1176                     } else {
1177                         s->ioredtbl[index] &= ~0xffffffffULL;
1178                         s->ioredtbl[index] |= val;
1179                     }
1180                     ioapic_service(s);
1181                 }
1182         }
1183     }
1184 }
1185
1186 static void kvm_kernel_ioapic_save_to_user(IOAPICState *s)
1187 {
1188 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
1189     struct kvm_irqchip chip;
1190     struct kvm_ioapic_state *kioapic;
1191     int i;
1192
1193     chip.chip_id = KVM_IRQCHIP_IOAPIC;
1194     kvm_get_irqchip(kvm_context, &chip);
1195     kioapic = &chip.chip.ioapic;
1196
1197     s->id = kioapic->id;
1198     s->ioregsel = kioapic->ioregsel;
1199     s->base_address = kioapic->base_address;
1200     s->irr = kioapic->irr;
1201     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1202         s->ioredtbl[i] = kioapic->redirtbl[i].bits;
1203     }
1204 #endif
1205 }
1206
1207 static void kvm_kernel_ioapic_load_from_user(IOAPICState *s)
1208 {
1209 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
1210     struct kvm_irqchip chip;
1211     struct kvm_ioapic_state *kioapic;
1212     int i;
1213
1214     chip.chip_id = KVM_IRQCHIP_IOAPIC;
1215     kioapic = &chip.chip.ioapic;
1216
1217     kioapic->id = s->id;
1218     kioapic->ioregsel = s->ioregsel;
1219     kioapic->base_address = s->base_address;
1220     kioapic->irr = s->irr;
1221     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1222         kioapic->redirtbl[i].bits = s->ioredtbl[i];
1223     }
1224
1225     kvm_set_irqchip(kvm_context, &chip);
1226 #endif
1227 }
1228
1229 static void ioapic_save(QEMUFile *f, void *opaque)
1230 {
1231     IOAPICState *s = opaque;
1232     int i;
1233
1234     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1235         kvm_kernel_ioapic_save_to_user(s);
1236     }
1237
1238     qemu_put_8s(f, &s->id);
1239     qemu_put_8s(f, &s->ioregsel);
1240     qemu_put_be64s(f, &s->base_address);
1241     qemu_put_be32s(f, &s->irr);
1242     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1243         qemu_put_be64s(f, &s->ioredtbl[i]);
1244     }
1245 }
1246
1247 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1248 {
1249     IOAPICState *s = opaque;
1250     int i;
1251
1252     if (version_id < 1 || version_id > 2)
1253         return -EINVAL;
1254
1255     qemu_get_8s(f, &s->id);
1256     qemu_get_8s(f, &s->ioregsel);
1257     if (version_id == 2) {
1258       /* for version 2, we get this data off of the wire */
1259       qemu_get_be64s(f, &s->base_address);
1260       qemu_get_be32s(f, &s->irr);
1261     }
1262     else {
1263       /* in case we are doing version 1, we just set these to sane values */
1264       s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
1265       s->irr = 0;
1266     }
1267     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1268         qemu_get_be64s(f, &s->ioredtbl[i]);
1269     }
1270
1271     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1272         kvm_kernel_ioapic_load_from_user(s);
1273     }
1274
1275     return 0;
1276 }
1277
1278 static void ioapic_reset(void *opaque)
1279 {
1280     IOAPICState *s = opaque;
1281     int i;
1282
1283     memset(s, 0, sizeof(*s));
1284     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
1285     for(i = 0; i < IOAPIC_NUM_PINS; i++)
1286         s->ioredtbl[i] = 1 << 16; /* mask LVT */
1287 #ifdef KVM_CAP_IRQCHIP
1288     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1289         kvm_kernel_ioapic_load_from_user(s);
1290     }
1291 #endif
1292 }
1293
1294 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1295     ioapic_mem_readl,
1296     ioapic_mem_readl,
1297     ioapic_mem_readl,
1298 };
1299
1300 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1301     ioapic_mem_writel,
1302     ioapic_mem_writel,
1303     ioapic_mem_writel,
1304 };
1305
1306 IOAPICState *ioapic_init(void)
1307 {
1308     IOAPICState *s;
1309     int io_memory;
1310
1311     s = qemu_mallocz(sizeof(IOAPICState));
1312     ioapic_reset(s);
1313     s->id = last_apic_id++;
1314
1315     io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1316                                        ioapic_mem_write, s);
1317     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1318
1319     register_savevm("ioapic", 0, 2, ioapic_save, ioapic_load, s);
1320     qemu_register_reset(ioapic_reset, s);
1321
1322     return s;
1323 }