2 #include "host-utils.h"
4 #if !defined(CONFIG_USER_ONLY)
5 #include "softmmu_exec.h"
6 #endif /* !defined(CONFIG_USER_ONLY) */
10 //#define DEBUG_UNALIGNED
11 //#define DEBUG_UNASSIGNED
15 #define DPRINTF_MMU(fmt, args...) \
16 do { printf("MMU: " fmt , ##args); } while (0)
18 #define DPRINTF_MMU(fmt, args...) do {} while (0)
22 #define DPRINTF_MXCC(fmt, args...) \
23 do { printf("MXCC: " fmt , ##args); } while (0)
25 #define DPRINTF_MXCC(fmt, args...) do {} while (0)
29 #define DPRINTF_ASI(fmt, args...) \
30 do { printf("ASI: " fmt , ##args); } while (0)
32 #define DPRINTF_ASI(fmt, args...) do {} while (0)
36 #define ABI32_MASK(addr) do { (addr) &= 0xffffffffULL; } while (0)
38 #define ABI32_MASK(addr) do {} while (0)
41 void raise_exception(int tt
)
43 env
->exception_index
= tt
;
47 void helper_trap(target_ulong nb_trap
)
49 env
->exception_index
= TT_TRAP
+ (nb_trap
& 0x7f);
53 void helper_trapcc(target_ulong nb_trap
, target_ulong do_trap
)
56 env
->exception_index
= TT_TRAP
+ (nb_trap
& 0x7f);
61 void helper_check_align(target_ulong addr
, uint32_t align
)
64 #ifdef DEBUG_UNALIGNED
65 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
68 raise_exception(TT_UNALIGNED
);
72 #define F_HELPER(name, p) void helper_f##name##p(void)
74 #define F_BINOP(name) \
77 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
81 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
85 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
94 void helper_fsmuld(void)
96 DT0
= float64_mul(float32_to_float64(FT0
, &env
->fp_status
),
97 float32_to_float64(FT1
, &env
->fp_status
),
101 void helper_fdmulq(void)
103 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
104 float64_to_float128(DT1
, &env
->fp_status
),
110 FT0
= float32_chs(FT1
);
113 #ifdef TARGET_SPARC64
116 DT0
= float64_chs(DT1
);
121 QT0
= float128_chs(QT1
);
125 /* Integer to float conversion. */
128 FT0
= int32_to_float32(*((int32_t *)&FT1
), &env
->fp_status
);
133 DT0
= int32_to_float64(*((int32_t *)&FT1
), &env
->fp_status
);
138 QT0
= int32_to_float128(*((int32_t *)&FT1
), &env
->fp_status
);
141 #ifdef TARGET_SPARC64
144 FT0
= int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
149 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
154 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
159 /* floating point conversion */
160 void helper_fdtos(void)
162 FT0
= float64_to_float32(DT1
, &env
->fp_status
);
165 void helper_fstod(void)
167 DT0
= float32_to_float64(FT1
, &env
->fp_status
);
170 void helper_fqtos(void)
172 FT0
= float128_to_float32(QT1
, &env
->fp_status
);
175 void helper_fstoq(void)
177 QT0
= float32_to_float128(FT1
, &env
->fp_status
);
180 void helper_fqtod(void)
182 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
185 void helper_fdtoq(void)
187 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
190 /* Float to integer conversion. */
191 void helper_fstoi(void)
193 *((int32_t *)&FT0
) = float32_to_int32_round_to_zero(FT1
, &env
->fp_status
);
196 void helper_fdtoi(void)
198 *((int32_t *)&FT0
) = float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
201 void helper_fqtoi(void)
203 *((int32_t *)&FT0
) = float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
206 #ifdef TARGET_SPARC64
207 void helper_fstox(void)
209 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(FT1
, &env
->fp_status
);
212 void helper_fdtox(void)
214 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
217 void helper_fqtox(void)
219 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
222 void helper_faligndata(void)
226 tmp
= (*((uint64_t *)&DT0
)) << ((env
->gsr
& 7) * 8);
227 tmp
|= (*((uint64_t *)&DT1
)) >> (64 - (env
->gsr
& 7) * 8);
228 *((uint64_t *)&DT0
) = tmp
;
231 void helper_movl_FT0_0(void)
233 *((uint32_t *)&FT0
) = 0;
236 void helper_movl_DT0_0(void)
238 *((uint64_t *)&DT0
) = 0;
241 void helper_movl_FT0_1(void)
243 *((uint32_t *)&FT0
) = 0xffffffff;
246 void helper_movl_DT0_1(void)
248 *((uint64_t *)&DT0
) = 0xffffffffffffffffULL
;
251 void helper_fnot(void)
253 *(uint64_t *)&DT0
= ~*(uint64_t *)&DT1
;
256 void helper_fnots(void)
258 *(uint32_t *)&FT0
= ~*(uint32_t *)&FT1
;
261 void helper_fnor(void)
263 *(uint64_t *)&DT0
= ~(*(uint64_t *)&DT0
| *(uint64_t *)&DT1
);
266 void helper_fnors(void)
268 *(uint32_t *)&FT0
= ~(*(uint32_t *)&FT0
| *(uint32_t *)&FT1
);
271 void helper_for(void)
273 *(uint64_t *)&DT0
|= *(uint64_t *)&DT1
;
276 void helper_fors(void)
278 *(uint32_t *)&FT0
|= *(uint32_t *)&FT1
;
281 void helper_fxor(void)
283 *(uint64_t *)&DT0
^= *(uint64_t *)&DT1
;
286 void helper_fxors(void)
288 *(uint32_t *)&FT0
^= *(uint32_t *)&FT1
;
291 void helper_fand(void)
293 *(uint64_t *)&DT0
&= *(uint64_t *)&DT1
;
296 void helper_fands(void)
298 *(uint32_t *)&FT0
&= *(uint32_t *)&FT1
;
301 void helper_fornot(void)
303 *(uint64_t *)&DT0
= *(uint64_t *)&DT0
| ~*(uint64_t *)&DT1
;
306 void helper_fornots(void)
308 *(uint32_t *)&FT0
= *(uint32_t *)&FT0
| ~*(uint32_t *)&FT1
;
311 void helper_fandnot(void)
313 *(uint64_t *)&DT0
= *(uint64_t *)&DT0
& ~*(uint64_t *)&DT1
;
316 void helper_fandnots(void)
318 *(uint32_t *)&FT0
= *(uint32_t *)&FT0
& ~*(uint32_t *)&FT1
;
321 void helper_fnand(void)
323 *(uint64_t *)&DT0
= ~(*(uint64_t *)&DT0
& *(uint64_t *)&DT1
);
326 void helper_fnands(void)
328 *(uint32_t *)&FT0
= ~(*(uint32_t *)&FT0
& *(uint32_t *)&FT1
);
331 void helper_fxnor(void)
333 *(uint64_t *)&DT0
^= ~*(uint64_t *)&DT1
;
336 void helper_fxnors(void)
338 *(uint32_t *)&FT0
^= ~*(uint32_t *)&FT1
;
341 #ifdef WORDS_BIGENDIAN
342 #define VIS_B64(n) b[7 - (n)]
343 #define VIS_W64(n) w[3 - (n)]
344 #define VIS_SW64(n) sw[3 - (n)]
345 #define VIS_L64(n) l[1 - (n)]
346 #define VIS_B32(n) b[3 - (n)]
347 #define VIS_W32(n) w[1 - (n)]
349 #define VIS_B64(n) b[n]
350 #define VIS_W64(n) w[n]
351 #define VIS_SW64(n) sw[n]
352 #define VIS_L64(n) l[n]
353 #define VIS_B32(n) b[n]
354 #define VIS_W32(n) w[n]
372 void helper_fpmerge(void)
379 // Reverse calculation order to handle overlap
380 d
.VIS_B64(7) = s
.VIS_B64(3);
381 d
.VIS_B64(6) = d
.VIS_B64(3);
382 d
.VIS_B64(5) = s
.VIS_B64(2);
383 d
.VIS_B64(4) = d
.VIS_B64(2);
384 d
.VIS_B64(3) = s
.VIS_B64(1);
385 d
.VIS_B64(2) = d
.VIS_B64(1);
386 d
.VIS_B64(1) = s
.VIS_B64(0);
387 //d.VIS_B64(0) = d.VIS_B64(0);
392 void helper_fmul8x16(void)
401 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
402 if ((tmp & 0xff) > 0x7f) \
404 d.VIS_W64(r) = tmp >> 8;
415 void helper_fmul8x16al(void)
424 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
425 if ((tmp & 0xff) > 0x7f) \
427 d.VIS_W64(r) = tmp >> 8;
438 void helper_fmul8x16au(void)
447 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
448 if ((tmp & 0xff) > 0x7f) \
450 d.VIS_W64(r) = tmp >> 8;
461 void helper_fmul8sux16(void)
470 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
471 if ((tmp & 0xff) > 0x7f) \
473 d.VIS_W64(r) = tmp >> 8;
484 void helper_fmul8ulx16(void)
493 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
494 if ((tmp & 0xff) > 0x7f) \
496 d.VIS_W64(r) = tmp >> 8;
507 void helper_fmuld8sux16(void)
516 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
517 if ((tmp & 0xff) > 0x7f) \
521 // Reverse calculation order to handle overlap
529 void helper_fmuld8ulx16(void)
538 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
539 if ((tmp & 0xff) > 0x7f) \
543 // Reverse calculation order to handle overlap
551 void helper_fexpand(void)
556 s
.l
= (uint32_t)(*(uint64_t *)&DT0
& 0xffffffff);
558 d
.VIS_L64(0) = s
.VIS_W32(0) << 4;
559 d
.VIS_L64(1) = s
.VIS_W32(1) << 4;
560 d
.VIS_L64(2) = s
.VIS_W32(2) << 4;
561 d
.VIS_L64(3) = s
.VIS_W32(3) << 4;
566 #define VIS_HELPER(name, F) \
567 void name##16(void) \
574 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
575 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
576 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
577 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
582 void name##16s(void) \
589 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
590 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
595 void name##32(void) \
602 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
603 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
608 void name##32s(void) \
620 #define FADD(a, b) ((a) + (b))
621 #define FSUB(a, b) ((a) - (b))
622 VIS_HELPER(helper_fpadd
, FADD
)
623 VIS_HELPER(helper_fpsub
, FSUB
)
625 #define VIS_CMPHELPER(name, F) \
626 void name##16(void) \
633 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
634 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
635 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
636 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
641 void name##32(void) \
648 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
649 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
654 #define FCMPGT(a, b) ((a) > (b))
655 #define FCMPEQ(a, b) ((a) == (b))
656 #define FCMPLE(a, b) ((a) <= (b))
657 #define FCMPNE(a, b) ((a) != (b))
659 VIS_CMPHELPER(helper_fcmpgt
, FCMPGT
)
660 VIS_CMPHELPER(helper_fcmpeq
, FCMPEQ
)
661 VIS_CMPHELPER(helper_fcmple
, FCMPLE
)
662 VIS_CMPHELPER(helper_fcmpne
, FCMPNE
)
665 void helper_check_ieee_exceptions(void)
669 status
= get_float_exception_flags(&env
->fp_status
);
671 /* Copy IEEE 754 flags into FSR */
672 if (status
& float_flag_invalid
)
674 if (status
& float_flag_overflow
)
676 if (status
& float_flag_underflow
)
678 if (status
& float_flag_divbyzero
)
680 if (status
& float_flag_inexact
)
683 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
684 /* Unmasked exception, generate a trap */
685 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
686 raise_exception(TT_FP_EXCP
);
688 /* Accumulate exceptions */
689 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
694 void helper_clear_float_exceptions(void)
696 set_float_exception_flags(0, &env
->fp_status
);
699 void helper_fabss(void)
701 FT0
= float32_abs(FT1
);
704 #ifdef TARGET_SPARC64
705 void helper_fabsd(void)
707 DT0
= float64_abs(DT1
);
710 void helper_fabsq(void)
712 QT0
= float128_abs(QT1
);
716 void helper_fsqrts(void)
718 FT0
= float32_sqrt(FT1
, &env
->fp_status
);
721 void helper_fsqrtd(void)
723 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
726 void helper_fsqrtq(void)
728 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
731 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
732 void glue(helper_, name) (void) \
734 target_ulong new_fsr; \
736 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
737 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
738 case float_relation_unordered: \
739 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
740 if ((env->fsr & FSR_NVM) || TRAP) { \
741 env->fsr |= new_fsr; \
742 env->fsr |= FSR_NVC; \
743 env->fsr |= FSR_FTT_IEEE_EXCP; \
744 raise_exception(TT_FP_EXCP); \
746 env->fsr |= FSR_NVA; \
749 case float_relation_less: \
750 new_fsr = FSR_FCC0 << FS; \
752 case float_relation_greater: \
753 new_fsr = FSR_FCC1 << FS; \
759 env->fsr |= new_fsr; \
762 GEN_FCMP(fcmps
, float32
, FT0
, FT1
, 0, 0);
763 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
765 GEN_FCMP(fcmpes
, float32
, FT0
, FT1
, 0, 1);
766 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
768 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
769 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
771 #ifdef TARGET_SPARC64
772 GEN_FCMP(fcmps_fcc1
, float32
, FT0
, FT1
, 22, 0);
773 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
774 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
776 GEN_FCMP(fcmps_fcc2
, float32
, FT0
, FT1
, 24, 0);
777 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
778 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
780 GEN_FCMP(fcmps_fcc3
, float32
, FT0
, FT1
, 26, 0);
781 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
782 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
784 GEN_FCMP(fcmpes_fcc1
, float32
, FT0
, FT1
, 22, 1);
785 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
786 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
788 GEN_FCMP(fcmpes_fcc2
, float32
, FT0
, FT1
, 24, 1);
789 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
790 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
792 GEN_FCMP(fcmpes_fcc3
, float32
, FT0
, FT1
, 26, 1);
793 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
794 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
797 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
799 static void dump_mxcc(CPUState
*env
)
801 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
802 env
->mxccdata
[0], env
->mxccdata
[1],
803 env
->mxccdata
[2], env
->mxccdata
[3]);
804 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
805 " %016llx %016llx %016llx %016llx\n",
806 env
->mxccregs
[0], env
->mxccregs
[1],
807 env
->mxccregs
[2], env
->mxccregs
[3],
808 env
->mxccregs
[4], env
->mxccregs
[5],
809 env
->mxccregs
[6], env
->mxccregs
[7]);
813 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
814 && defined(DEBUG_ASI)
815 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
821 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
822 addr
, asi
, r1
& 0xff);
825 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
826 addr
, asi
, r1
& 0xffff);
829 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
830 addr
, asi
, r1
& 0xffffffff);
833 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
840 #ifndef TARGET_SPARC64
841 #ifndef CONFIG_USER_ONLY
842 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
845 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
846 uint32_t last_addr
= addr
;
849 helper_check_align(addr
, size
- 1);
851 case 2: /* SuperSparc MXCC registers */
853 case 0x01c00a00: /* MXCC control register */
855 ret
= env
->mxccregs
[3];
857 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
860 case 0x01c00a04: /* MXCC control register */
862 ret
= env
->mxccregs
[3];
864 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
867 case 0x01c00c00: /* Module reset register */
869 ret
= env
->mxccregs
[5];
870 // should we do something here?
872 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
875 case 0x01c00f00: /* MBus port address register */
877 ret
= env
->mxccregs
[7];
879 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
883 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
887 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
888 "addr = %08x -> ret = %08x,"
889 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
894 case 3: /* MMU probe */
898 mmulev
= (addr
>> 8) & 15;
902 ret
= mmu_probe(env
, addr
, mmulev
);
903 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
907 case 4: /* read MMU regs */
909 int reg
= (addr
>> 8) & 0x1f;
911 ret
= env
->mmuregs
[reg
];
912 if (reg
== 3) /* Fault status cleared on read */
914 else if (reg
== 0x13) /* Fault status read */
915 ret
= env
->mmuregs
[3];
916 else if (reg
== 0x14) /* Fault address read */
917 ret
= env
->mmuregs
[4];
918 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
921 case 5: // Turbosparc ITLB Diagnostic
922 case 6: // Turbosparc DTLB Diagnostic
923 case 7: // Turbosparc IOTLB Diagnostic
925 case 9: /* Supervisor code access */
928 ret
= ldub_code(addr
);
931 ret
= lduw_code(addr
);
935 ret
= ldl_code(addr
);
938 ret
= ldq_code(addr
);
942 case 0xa: /* User data access */
945 ret
= ldub_user(addr
);
948 ret
= lduw_user(addr
);
952 ret
= ldl_user(addr
);
955 ret
= ldq_user(addr
);
959 case 0xb: /* Supervisor data access */
962 ret
= ldub_kernel(addr
);
965 ret
= lduw_kernel(addr
);
969 ret
= ldl_kernel(addr
);
972 ret
= ldq_kernel(addr
);
976 case 0xc: /* I-cache tag */
977 case 0xd: /* I-cache data */
978 case 0xe: /* D-cache tag */
979 case 0xf: /* D-cache data */
981 case 0x20: /* MMU passthrough */
984 ret
= ldub_phys(addr
);
987 ret
= lduw_phys(addr
);
991 ret
= ldl_phys(addr
);
994 ret
= ldq_phys(addr
);
998 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1001 ret
= ldub_phys((target_phys_addr_t
)addr
1002 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1005 ret
= lduw_phys((target_phys_addr_t
)addr
1006 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1010 ret
= ldl_phys((target_phys_addr_t
)addr
1011 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1014 ret
= ldq_phys((target_phys_addr_t
)addr
1015 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1019 case 0x30: // Turbosparc secondary cache diagnostic
1020 case 0x31: // Turbosparc RAM snoop
1021 case 0x32: // Turbosparc page table descriptor diagnostic
1022 case 0x39: /* data cache diagnostic register */
1025 case 8: /* User code access, XXX */
1027 do_unassigned_access(addr
, 0, 0, asi
);
1037 ret
= (int16_t) ret
;
1040 ret
= (int32_t) ret
;
1047 dump_asi("read ", last_addr
, asi
, size
, ret
);
1052 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
1054 helper_check_align(addr
, size
- 1);
1056 case 2: /* SuperSparc MXCC registers */
1058 case 0x01c00000: /* MXCC stream data register 0 */
1060 env
->mxccdata
[0] = val
;
1062 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1065 case 0x01c00008: /* MXCC stream data register 1 */
1067 env
->mxccdata
[1] = val
;
1069 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1072 case 0x01c00010: /* MXCC stream data register 2 */
1074 env
->mxccdata
[2] = val
;
1076 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1079 case 0x01c00018: /* MXCC stream data register 3 */
1081 env
->mxccdata
[3] = val
;
1083 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1086 case 0x01c00100: /* MXCC stream source */
1088 env
->mxccregs
[0] = val
;
1090 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1092 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1094 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1096 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1098 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1101 case 0x01c00200: /* MXCC stream destination */
1103 env
->mxccregs
[1] = val
;
1105 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1107 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
1109 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
1111 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
1113 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
1116 case 0x01c00a00: /* MXCC control register */
1118 env
->mxccregs
[3] = val
;
1120 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1123 case 0x01c00a04: /* MXCC control register */
1125 env
->mxccregs
[3] = (env
->mxccregs
[0xa] & 0xffffffff00000000ULL
)
1128 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1131 case 0x01c00e00: /* MXCC error register */
1132 // writing a 1 bit clears the error
1134 env
->mxccregs
[6] &= ~val
;
1136 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1139 case 0x01c00f00: /* MBus port address register */
1141 env
->mxccregs
[7] = val
;
1143 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1147 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1151 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi
,
1157 case 3: /* MMU flush */
1161 mmulev
= (addr
>> 8) & 15;
1162 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
1164 case 0: // flush page
1165 tlb_flush_page(env
, addr
& 0xfffff000);
1167 case 1: // flush segment (256k)
1168 case 2: // flush region (16M)
1169 case 3: // flush context (4G)
1170 case 4: // flush entire
1181 case 4: /* write MMU regs */
1183 int reg
= (addr
>> 8) & 0x1f;
1186 oldreg
= env
->mmuregs
[reg
];
1188 case 0: // Control Register
1189 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1191 // Mappings generated during no-fault mode or MMU
1192 // disabled mode are invalid in normal mode
1193 if ((oldreg
& (MMU_E
| MMU_NF
| env
->mmu_bm
)) !=
1194 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->mmu_bm
)))
1197 case 1: // Context Table Pointer Register
1198 env
->mmuregs
[reg
] = val
& env
->mmu_ctpr_mask
;
1200 case 2: // Context Register
1201 env
->mmuregs
[reg
] = val
& env
->mmu_cxr_mask
;
1202 if (oldreg
!= env
->mmuregs
[reg
]) {
1203 /* we flush when the MMU context changes because
1204 QEMU has no MMU context support */
1208 case 3: // Synchronous Fault Status Register with Clear
1209 case 4: // Synchronous Fault Address Register
1211 case 0x10: // TLB Replacement Control Register
1212 env
->mmuregs
[reg
] = val
& env
->mmu_trcr_mask
;
1214 case 0x13: // Synchronous Fault Status Register with Read and Clear
1215 env
->mmuregs
[3] = val
& env
->mmu_sfsr_mask
;
1217 case 0x14: // Synchronous Fault Address Register
1218 env
->mmuregs
[4] = val
;
1221 env
->mmuregs
[reg
] = val
;
1224 if (oldreg
!= env
->mmuregs
[reg
]) {
1225 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1226 reg
, oldreg
, env
->mmuregs
[reg
]);
1233 case 5: // Turbosparc ITLB Diagnostic
1234 case 6: // Turbosparc DTLB Diagnostic
1235 case 7: // Turbosparc IOTLB Diagnostic
1237 case 0xa: /* User data access */
1240 stb_user(addr
, val
);
1243 stw_user(addr
, val
);
1247 stl_user(addr
, val
);
1250 stq_user(addr
, val
);
1254 case 0xb: /* Supervisor data access */
1257 stb_kernel(addr
, val
);
1260 stw_kernel(addr
, val
);
1264 stl_kernel(addr
, val
);
1267 stq_kernel(addr
, val
);
1271 case 0xc: /* I-cache tag */
1272 case 0xd: /* I-cache data */
1273 case 0xe: /* D-cache tag */
1274 case 0xf: /* D-cache data */
1275 case 0x10: /* I/D-cache flush page */
1276 case 0x11: /* I/D-cache flush segment */
1277 case 0x12: /* I/D-cache flush region */
1278 case 0x13: /* I/D-cache flush context */
1279 case 0x14: /* I/D-cache flush user */
1281 case 0x17: /* Block copy, sta access */
1287 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
1289 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
1290 temp
= ldl_kernel(src
);
1291 stl_kernel(dst
, temp
);
1295 case 0x1f: /* Block fill, stda access */
1298 // fill 32 bytes with val
1300 uint32_t dst
= addr
& 7;
1302 for (i
= 0; i
< 32; i
+= 8, dst
+= 8)
1303 stq_kernel(dst
, val
);
1306 case 0x20: /* MMU passthrough */
1310 stb_phys(addr
, val
);
1313 stw_phys(addr
, val
);
1317 stl_phys(addr
, val
);
1320 stq_phys(addr
, val
);
1325 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1329 stb_phys((target_phys_addr_t
)addr
1330 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1333 stw_phys((target_phys_addr_t
)addr
1334 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1338 stl_phys((target_phys_addr_t
)addr
1339 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1342 stq_phys((target_phys_addr_t
)addr
1343 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1348 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1349 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1350 // Turbosparc snoop RAM
1351 case 0x32: // store buffer control or Turbosparc page table
1352 // descriptor diagnostic
1353 case 0x36: /* I-cache flash clear */
1354 case 0x37: /* D-cache flash clear */
1355 case 0x38: /* breakpoint diagnostics */
1356 case 0x4c: /* breakpoint action */
1358 case 8: /* User code access, XXX */
1359 case 9: /* Supervisor code access, XXX */
1361 do_unassigned_access(addr
, 1, 0, asi
);
1365 dump_asi("write", addr
, asi
, size
, val
);
1369 #endif /* CONFIG_USER_ONLY */
1370 #else /* TARGET_SPARC64 */
1372 #ifdef CONFIG_USER_ONLY
1373 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1376 #if defined(DEBUG_ASI)
1377 target_ulong last_addr
= addr
;
1381 raise_exception(TT_PRIV_ACT
);
1383 helper_check_align(addr
, size
- 1);
1387 case 0x80: // Primary
1388 case 0x82: // Primary no-fault
1389 case 0x88: // Primary LE
1390 case 0x8a: // Primary no-fault LE
1394 ret
= ldub_raw(addr
);
1397 ret
= lduw_raw(addr
);
1400 ret
= ldl_raw(addr
);
1404 ret
= ldq_raw(addr
);
1409 case 0x81: // Secondary
1410 case 0x83: // Secondary no-fault
1411 case 0x89: // Secondary LE
1412 case 0x8b: // Secondary no-fault LE
1419 /* Convert from little endian */
1421 case 0x88: // Primary LE
1422 case 0x89: // Secondary LE
1423 case 0x8a: // Primary no-fault LE
1424 case 0x8b: // Secondary no-fault LE
1442 /* Convert to signed number */
1449 ret
= (int16_t) ret
;
1452 ret
= (int32_t) ret
;
1459 dump_asi("read ", last_addr
, asi
, size
, ret
);
1464 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
1467 dump_asi("write", addr
, asi
, size
, val
);
1470 raise_exception(TT_PRIV_ACT
);
1472 helper_check_align(addr
, size
- 1);
1475 /* Convert to little endian */
1477 case 0x88: // Primary LE
1478 case 0x89: // Secondary LE
1481 addr
= bswap16(addr
);
1484 addr
= bswap32(addr
);
1487 addr
= bswap64(addr
);
1497 case 0x80: // Primary
1498 case 0x88: // Primary LE
1517 case 0x81: // Secondary
1518 case 0x89: // Secondary LE
1522 case 0x82: // Primary no-fault, RO
1523 case 0x83: // Secondary no-fault, RO
1524 case 0x8a: // Primary no-fault LE, RO
1525 case 0x8b: // Secondary no-fault LE, RO
1527 do_unassigned_access(addr
, 1, 0, 1);
1532 #else /* CONFIG_USER_ONLY */
1534 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1537 #if defined(DEBUG_ASI)
1538 target_ulong last_addr
= addr
;
1541 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1542 || (asi
>= 0x30 && asi
< 0x80 && !(env
->hpstate
& HS_PRIV
)))
1543 raise_exception(TT_PRIV_ACT
);
1545 helper_check_align(addr
, size
- 1);
1547 case 0x10: // As if user primary
1548 case 0x18: // As if user primary LE
1549 case 0x80: // Primary
1550 case 0x82: // Primary no-fault
1551 case 0x88: // Primary LE
1552 case 0x8a: // Primary no-fault LE
1553 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1554 if (env
->hpstate
& HS_PRIV
) {
1557 ret
= ldub_hypv(addr
);
1560 ret
= lduw_hypv(addr
);
1563 ret
= ldl_hypv(addr
);
1567 ret
= ldq_hypv(addr
);
1573 ret
= ldub_kernel(addr
);
1576 ret
= lduw_kernel(addr
);
1579 ret
= ldl_kernel(addr
);
1583 ret
= ldq_kernel(addr
);
1590 ret
= ldub_user(addr
);
1593 ret
= lduw_user(addr
);
1596 ret
= ldl_user(addr
);
1600 ret
= ldq_user(addr
);
1605 case 0x14: // Bypass
1606 case 0x15: // Bypass, non-cacheable
1607 case 0x1c: // Bypass LE
1608 case 0x1d: // Bypass, non-cacheable LE
1612 ret
= ldub_phys(addr
);
1615 ret
= lduw_phys(addr
);
1618 ret
= ldl_phys(addr
);
1622 ret
= ldq_phys(addr
);
1627 case 0x04: // Nucleus
1628 case 0x0c: // Nucleus Little Endian (LE)
1629 case 0x11: // As if user secondary
1630 case 0x19: // As if user secondary LE
1631 case 0x24: // Nucleus quad LDD 128 bit atomic
1632 case 0x2c: // Nucleus quad LDD 128 bit atomic
1633 case 0x4a: // UPA config
1634 case 0x81: // Secondary
1635 case 0x83: // Secondary no-fault
1636 case 0x89: // Secondary LE
1637 case 0x8b: // Secondary no-fault LE
1643 case 0x50: // I-MMU regs
1645 int reg
= (addr
>> 3) & 0xf;
1647 ret
= env
->immuregs
[reg
];
1650 case 0x51: // I-MMU 8k TSB pointer
1651 case 0x52: // I-MMU 64k TSB pointer
1652 case 0x55: // I-MMU data access
1655 case 0x56: // I-MMU tag read
1659 for (i
= 0; i
< 64; i
++) {
1660 // Valid, ctx match, vaddr match
1661 if ((env
->itlb_tte
[i
] & 0x8000000000000000ULL
) != 0 &&
1662 env
->itlb_tag
[i
] == addr
) {
1663 ret
= env
->itlb_tag
[i
];
1669 case 0x58: // D-MMU regs
1671 int reg
= (addr
>> 3) & 0xf;
1673 ret
= env
->dmmuregs
[reg
];
1676 case 0x5e: // D-MMU tag read
1680 for (i
= 0; i
< 64; i
++) {
1681 // Valid, ctx match, vaddr match
1682 if ((env
->dtlb_tte
[i
] & 0x8000000000000000ULL
) != 0 &&
1683 env
->dtlb_tag
[i
] == addr
) {
1684 ret
= env
->dtlb_tag
[i
];
1690 case 0x59: // D-MMU 8k TSB pointer
1691 case 0x5a: // D-MMU 64k TSB pointer
1692 case 0x5b: // D-MMU data pointer
1693 case 0x5d: // D-MMU data access
1694 case 0x48: // Interrupt dispatch, RO
1695 case 0x49: // Interrupt data receive
1696 case 0x7f: // Incoming interrupt vector, RO
1699 case 0x54: // I-MMU data in, WO
1700 case 0x57: // I-MMU demap, WO
1701 case 0x5c: // D-MMU data in, WO
1702 case 0x5f: // D-MMU demap, WO
1703 case 0x77: // Interrupt vector, WO
1705 do_unassigned_access(addr
, 0, 0, 1);
1710 /* Convert from little endian */
1712 case 0x0c: // Nucleus Little Endian (LE)
1713 case 0x18: // As if user primary LE
1714 case 0x19: // As if user secondary LE
1715 case 0x1c: // Bypass LE
1716 case 0x1d: // Bypass, non-cacheable LE
1717 case 0x88: // Primary LE
1718 case 0x89: // Secondary LE
1719 case 0x8a: // Primary no-fault LE
1720 case 0x8b: // Secondary no-fault LE
1738 /* Convert to signed number */
1745 ret
= (int16_t) ret
;
1748 ret
= (int32_t) ret
;
1755 dump_asi("read ", last_addr
, asi
, size
, ret
);
1760 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
1763 dump_asi("write", addr
, asi
, size
, val
);
1765 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1766 || (asi
>= 0x30 && asi
< 0x80 && !(env
->hpstate
& HS_PRIV
)))
1767 raise_exception(TT_PRIV_ACT
);
1769 helper_check_align(addr
, size
- 1);
1770 /* Convert to little endian */
1772 case 0x0c: // Nucleus Little Endian (LE)
1773 case 0x18: // As if user primary LE
1774 case 0x19: // As if user secondary LE
1775 case 0x1c: // Bypass LE
1776 case 0x1d: // Bypass, non-cacheable LE
1777 case 0x88: // Primary LE
1778 case 0x89: // Secondary LE
1781 addr
= bswap16(addr
);
1784 addr
= bswap32(addr
);
1787 addr
= bswap64(addr
);
1797 case 0x10: // As if user primary
1798 case 0x18: // As if user primary LE
1799 case 0x80: // Primary
1800 case 0x88: // Primary LE
1801 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1802 if (env
->hpstate
& HS_PRIV
) {
1805 stb_hypv(addr
, val
);
1808 stw_hypv(addr
, val
);
1811 stl_hypv(addr
, val
);
1815 stq_hypv(addr
, val
);
1821 stb_kernel(addr
, val
);
1824 stw_kernel(addr
, val
);
1827 stl_kernel(addr
, val
);
1831 stq_kernel(addr
, val
);
1838 stb_user(addr
, val
);
1841 stw_user(addr
, val
);
1844 stl_user(addr
, val
);
1848 stq_user(addr
, val
);
1853 case 0x14: // Bypass
1854 case 0x15: // Bypass, non-cacheable
1855 case 0x1c: // Bypass LE
1856 case 0x1d: // Bypass, non-cacheable LE
1860 stb_phys(addr
, val
);
1863 stw_phys(addr
, val
);
1866 stl_phys(addr
, val
);
1870 stq_phys(addr
, val
);
1875 case 0x04: // Nucleus
1876 case 0x0c: // Nucleus Little Endian (LE)
1877 case 0x11: // As if user secondary
1878 case 0x19: // As if user secondary LE
1879 case 0x24: // Nucleus quad LDD 128 bit atomic
1880 case 0x2c: // Nucleus quad LDD 128 bit atomic
1881 case 0x4a: // UPA config
1882 case 0x81: // Secondary
1883 case 0x89: // Secondary LE
1891 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1892 // Mappings generated during D/I MMU disabled mode are
1893 // invalid in normal mode
1894 if (oldreg
!= env
->lsu
) {
1895 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
1904 case 0x50: // I-MMU regs
1906 int reg
= (addr
>> 3) & 0xf;
1909 oldreg
= env
->immuregs
[reg
];
1914 case 1: // Not in I-MMU
1921 val
= 0; // Clear SFSR
1923 case 5: // TSB access
1924 case 6: // Tag access
1928 env
->immuregs
[reg
] = val
;
1929 if (oldreg
!= env
->immuregs
[reg
]) {
1930 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64
" -> 0x%08"
1931 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1938 case 0x54: // I-MMU data in
1942 // Try finding an invalid entry
1943 for (i
= 0; i
< 64; i
++) {
1944 if ((env
->itlb_tte
[i
] & 0x8000000000000000ULL
) == 0) {
1945 env
->itlb_tag
[i
] = env
->immuregs
[6];
1946 env
->itlb_tte
[i
] = val
;
1950 // Try finding an unlocked entry
1951 for (i
= 0; i
< 64; i
++) {
1952 if ((env
->itlb_tte
[i
] & 0x40) == 0) {
1953 env
->itlb_tag
[i
] = env
->immuregs
[6];
1954 env
->itlb_tte
[i
] = val
;
1961 case 0x55: // I-MMU data access
1963 unsigned int i
= (addr
>> 3) & 0x3f;
1965 env
->itlb_tag
[i
] = env
->immuregs
[6];
1966 env
->itlb_tte
[i
] = val
;
1969 case 0x57: // I-MMU demap
1972 case 0x58: // D-MMU regs
1974 int reg
= (addr
>> 3) & 0xf;
1977 oldreg
= env
->dmmuregs
[reg
];
1983 if ((val
& 1) == 0) {
1984 val
= 0; // Clear SFSR, Fault address
1985 env
->dmmuregs
[4] = 0;
1987 env
->dmmuregs
[reg
] = val
;
1989 case 1: // Primary context
1990 case 2: // Secondary context
1991 case 5: // TSB access
1992 case 6: // Tag access
1993 case 7: // Virtual Watchpoint
1994 case 8: // Physical Watchpoint
1998 env
->dmmuregs
[reg
] = val
;
1999 if (oldreg
!= env
->dmmuregs
[reg
]) {
2000 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64
" -> 0x%08"
2001 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
2008 case 0x5c: // D-MMU data in
2012 // Try finding an invalid entry
2013 for (i
= 0; i
< 64; i
++) {
2014 if ((env
->dtlb_tte
[i
] & 0x8000000000000000ULL
) == 0) {
2015 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
2016 env
->dtlb_tte
[i
] = val
;
2020 // Try finding an unlocked entry
2021 for (i
= 0; i
< 64; i
++) {
2022 if ((env
->dtlb_tte
[i
] & 0x40) == 0) {
2023 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
2024 env
->dtlb_tte
[i
] = val
;
2031 case 0x5d: // D-MMU data access
2033 unsigned int i
= (addr
>> 3) & 0x3f;
2035 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
2036 env
->dtlb_tte
[i
] = val
;
2039 case 0x5f: // D-MMU demap
2040 case 0x49: // Interrupt data receive
2043 case 0x51: // I-MMU 8k TSB pointer, RO
2044 case 0x52: // I-MMU 64k TSB pointer, RO
2045 case 0x56: // I-MMU tag read, RO
2046 case 0x59: // D-MMU 8k TSB pointer, RO
2047 case 0x5a: // D-MMU 64k TSB pointer, RO
2048 case 0x5b: // D-MMU data pointer, RO
2049 case 0x5e: // D-MMU tag read, RO
2050 case 0x48: // Interrupt dispatch, RO
2051 case 0x7f: // Incoming interrupt vector, RO
2052 case 0x82: // Primary no-fault, RO
2053 case 0x83: // Secondary no-fault, RO
2054 case 0x8a: // Primary no-fault LE, RO
2055 case 0x8b: // Secondary no-fault LE, RO
2057 do_unassigned_access(addr
, 1, 0, 1);
2061 #endif /* CONFIG_USER_ONLY */
2063 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2068 helper_check_align(addr
, 3);
2070 case 0xf0: // Block load primary
2071 case 0xf1: // Block load secondary
2072 case 0xf8: // Block load primary LE
2073 case 0xf9: // Block load secondary LE
2075 raise_exception(TT_ILL_INSN
);
2078 helper_check_align(addr
, 0x3f);
2079 for (i
= 0; i
< 16; i
++) {
2080 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
2090 val
= helper_ld_asi(addr
, asi
, size
, 0);
2094 *((uint32_t *)&FT0
) = val
;
2097 *((int64_t *)&DT0
) = val
;
2105 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2108 target_ulong val
= 0;
2110 helper_check_align(addr
, 3);
2112 case 0xf0: // Block store primary
2113 case 0xf1: // Block store secondary
2114 case 0xf8: // Block store primary LE
2115 case 0xf9: // Block store secondary LE
2117 raise_exception(TT_ILL_INSN
);
2120 helper_check_align(addr
, 0x3f);
2121 for (i
= 0; i
< 16; i
++) {
2122 val
= *(uint32_t *)&env
->fpr
[rd
++];
2123 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
2135 val
= *((uint32_t *)&FT0
);
2138 val
= *((int64_t *)&DT0
);
2144 helper_st_asi(addr
, val
, asi
, size
);
2147 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
2148 target_ulong val2
, uint32_t asi
)
2152 val1
&= 0xffffffffUL
;
2153 ret
= helper_ld_asi(addr
, asi
, 4, 0);
2154 ret
&= 0xffffffffUL
;
2156 helper_st_asi(addr
, val2
& 0xffffffffUL
, asi
, 4);
2160 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
2161 target_ulong val2
, uint32_t asi
)
2165 ret
= helper_ld_asi(addr
, asi
, 8, 0);
2167 helper_st_asi(addr
, val2
, asi
, 8);
2170 #endif /* TARGET_SPARC64 */
2172 #ifndef TARGET_SPARC64
2173 void helper_rett(void)
2177 if (env
->psret
== 1)
2178 raise_exception(TT_ILL_INSN
);
2181 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1) ;
2182 if (env
->wim
& (1 << cwp
)) {
2183 raise_exception(TT_WIN_UNF
);
2186 env
->psrs
= env
->psrps
;
2190 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
2195 x0
= a
| ((uint64_t) (env
->y
) << 32);
2199 raise_exception(TT_DIV_ZERO
);
2203 if (x0
> 0xffffffff) {
2212 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
2217 x0
= a
| ((int64_t) (env
->y
) << 32);
2221 raise_exception(TT_DIV_ZERO
);
2225 if ((int32_t) x0
!= x0
) {
2227 return x0
< 0? 0x80000000: 0x7fffffff;
2234 uint64_t helper_pack64(target_ulong high
, target_ulong low
)
2236 return ((uint64_t)high
<< 32) | (uint64_t)(low
& 0xffffffff);
2239 void helper_stdf(target_ulong addr
, int mem_idx
)
2241 helper_check_align(addr
, 7);
2242 #if !defined(CONFIG_USER_ONLY)
2245 stfq_user(addr
, DT0
);
2248 stfq_kernel(addr
, DT0
);
2250 #ifdef TARGET_SPARC64
2252 stfq_hypv(addr
, DT0
);
2260 stfq_raw(addr
, DT0
);
2264 void helper_lddf(target_ulong addr
, int mem_idx
)
2266 helper_check_align(addr
, 7);
2267 #if !defined(CONFIG_USER_ONLY)
2270 DT0
= ldfq_user(addr
);
2273 DT0
= ldfq_kernel(addr
);
2275 #ifdef TARGET_SPARC64
2277 DT0
= ldfq_hypv(addr
);
2285 DT0
= ldfq_raw(addr
);
2289 void helper_ldqf(target_ulong addr
, int mem_idx
)
2291 // XXX add 128 bit load
2294 helper_check_align(addr
, 7);
2295 #if !defined(CONFIG_USER_ONLY)
2298 u
.ll
.upper
= ldq_user(addr
);
2299 u
.ll
.lower
= ldq_user(addr
+ 8);
2303 u
.ll
.upper
= ldq_kernel(addr
);
2304 u
.ll
.lower
= ldq_kernel(addr
+ 8);
2307 #ifdef TARGET_SPARC64
2309 u
.ll
.upper
= ldq_hypv(addr
);
2310 u
.ll
.lower
= ldq_hypv(addr
+ 8);
2319 u
.ll
.upper
= ldq_raw(addr
);
2320 u
.ll
.lower
= ldq_raw((addr
+ 8) & 0xffffffffULL
);
2325 void helper_stqf(target_ulong addr
, int mem_idx
)
2327 // XXX add 128 bit store
2330 helper_check_align(addr
, 7);
2331 #if !defined(CONFIG_USER_ONLY)
2335 stq_user(addr
, u
.ll
.upper
);
2336 stq_user(addr
+ 8, u
.ll
.lower
);
2340 stq_kernel(addr
, u
.ll
.upper
);
2341 stq_kernel(addr
+ 8, u
.ll
.lower
);
2343 #ifdef TARGET_SPARC64
2346 stq_hypv(addr
, u
.ll
.upper
);
2347 stq_hypv(addr
+ 8, u
.ll
.lower
);
2356 stq_raw(addr
, u
.ll
.upper
);
2357 stq_raw((addr
+ 8) & 0xffffffffULL
, u
.ll
.lower
);
2361 void helper_ldfsr(void)
2365 PUT_FSR32(env
, *((uint32_t *) &FT0
));
2366 switch (env
->fsr
& FSR_RD_MASK
) {
2367 case FSR_RD_NEAREST
:
2368 rnd_mode
= float_round_nearest_even
;
2372 rnd_mode
= float_round_to_zero
;
2375 rnd_mode
= float_round_up
;
2378 rnd_mode
= float_round_down
;
2381 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
2384 void helper_stfsr(void)
2386 *((uint32_t *) &FT0
) = GET_FSR32(env
);
2389 void helper_debug(void)
2391 env
->exception_index
= EXCP_DEBUG
;
2395 #ifndef TARGET_SPARC64
2396 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2398 void helper_save(void)
2402 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
2403 if (env
->wim
& (1 << cwp
)) {
2404 raise_exception(TT_WIN_OVF
);
2409 void helper_restore(void)
2413 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1);
2414 if (env
->wim
& (1 << cwp
)) {
2415 raise_exception(TT_WIN_UNF
);
2420 void helper_wrpsr(target_ulong new_psr
)
2422 if ((new_psr
& PSR_CWP
) >= env
->nwindows
)
2423 raise_exception(TT_ILL_INSN
);
2425 PUT_PSR(env
, new_psr
);
2428 target_ulong
helper_rdpsr(void)
2430 return GET_PSR(env
);
2434 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2436 void helper_save(void)
2440 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
2441 if (env
->cansave
== 0) {
2442 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
2443 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
2444 ((env
->wstate
& 0x7) << 2)));
2446 if (env
->cleanwin
- env
->canrestore
== 0) {
2447 // XXX Clean windows without trap
2448 raise_exception(TT_CLRWIN
);
2457 void helper_restore(void)
2461 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1);
2462 if (env
->canrestore
== 0) {
2463 raise_exception(TT_FILL
| (env
->otherwin
!= 0 ?
2464 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
2465 ((env
->wstate
& 0x7) << 2)));
2473 void helper_flushw(void)
2475 if (env
->cansave
!= env
->nwindows
- 2) {
2476 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
2477 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
2478 ((env
->wstate
& 0x7) << 2)));
2482 void helper_saved(void)
2485 if (env
->otherwin
== 0)
2491 void helper_restored(void)
2494 if (env
->cleanwin
< env
->nwindows
- 1)
2496 if (env
->otherwin
== 0)
2502 target_ulong
helper_rdccr(void)
2504 return GET_CCR(env
);
2507 void helper_wrccr(target_ulong new_ccr
)
2509 PUT_CCR(env
, new_ccr
);
2512 // CWP handling is reversed in V9, but we still use the V8 register
2514 target_ulong
helper_rdcwp(void)
2516 return GET_CWP64(env
);
2519 void helper_wrcwp(target_ulong new_cwp
)
2521 PUT_CWP64(env
, new_cwp
);
2524 // This function uses non-native bit order
2525 #define GET_FIELD(X, FROM, TO) \
2526 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2528 // This function uses the order in the manuals, i.e. bit 0 is 2^0
2529 #define GET_FIELD_SP(X, FROM, TO) \
2530 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2532 target_ulong
helper_array8(target_ulong pixel_addr
, target_ulong cubesize
)
2534 return (GET_FIELD_SP(pixel_addr
, 60, 63) << (17 + 2 * cubesize
)) |
2535 (GET_FIELD_SP(pixel_addr
, 39, 39 + cubesize
- 1) << (17 + cubesize
)) |
2536 (GET_FIELD_SP(pixel_addr
, 17 + cubesize
- 1, 17) << 17) |
2537 (GET_FIELD_SP(pixel_addr
, 56, 59) << 13) |
2538 (GET_FIELD_SP(pixel_addr
, 35, 38) << 9) |
2539 (GET_FIELD_SP(pixel_addr
, 13, 16) << 5) |
2540 (((pixel_addr
>> 55) & 1) << 4) |
2541 (GET_FIELD_SP(pixel_addr
, 33, 34) << 2) |
2542 GET_FIELD_SP(pixel_addr
, 11, 12);
2545 target_ulong
helper_alignaddr(target_ulong addr
, target_ulong offset
)
2549 tmp
= addr
+ offset
;
2551 env
->gsr
|= tmp
& 7ULL;
2555 target_ulong
helper_popc(target_ulong val
)
2557 return ctpop64(val
);
2560 static inline uint64_t *get_gregset(uint64_t pstate
)
2575 void change_pstate(uint64_t new_pstate
)
2577 uint64_t pstate_regs
, new_pstate_regs
;
2578 uint64_t *src
, *dst
;
2580 pstate_regs
= env
->pstate
& 0xc01;
2581 new_pstate_regs
= new_pstate
& 0xc01;
2582 if (new_pstate_regs
!= pstate_regs
) {
2583 // Switch global register bank
2584 src
= get_gregset(new_pstate_regs
);
2585 dst
= get_gregset(pstate_regs
);
2586 memcpy32(dst
, env
->gregs
);
2587 memcpy32(env
->gregs
, src
);
2589 env
->pstate
= new_pstate
;
2592 void helper_wrpstate(target_ulong new_state
)
2594 change_pstate(new_state
& 0xf3f);
2597 void helper_done(void)
2600 env
->tsptr
= &env
->ts
[env
->tl
];
2601 env
->pc
= env
->tsptr
->tpc
;
2602 env
->npc
= env
->tsptr
->tnpc
+ 4;
2603 PUT_CCR(env
, env
->tsptr
->tstate
>> 32);
2604 env
->asi
= (env
->tsptr
->tstate
>> 24) & 0xff;
2605 change_pstate((env
->tsptr
->tstate
>> 8) & 0xf3f);
2606 PUT_CWP64(env
, env
->tsptr
->tstate
& 0xff);
2609 void helper_retry(void)
2612 env
->tsptr
= &env
->ts
[env
->tl
];
2613 env
->pc
= env
->tsptr
->tpc
;
2614 env
->npc
= env
->tsptr
->tnpc
;
2615 PUT_CCR(env
, env
->tsptr
->tstate
>> 32);
2616 env
->asi
= (env
->tsptr
->tstate
>> 24) & 0xff;
2617 change_pstate((env
->tsptr
->tstate
>> 8) & 0xf3f);
2618 PUT_CWP64(env
, env
->tsptr
->tstate
& 0xff);
2622 void cpu_set_cwp(CPUState
*env1
, int new_cwp
)
2624 /* put the modified wrap registers at their proper location */
2625 if (env1
->cwp
== env1
->nwindows
- 1)
2626 memcpy32(env1
->regbase
, env1
->regbase
+ env1
->nwindows
* 16);
2627 env1
->cwp
= new_cwp
;
2628 /* put the wrap registers at their temporary location */
2629 if (new_cwp
== env1
->nwindows
- 1)
2630 memcpy32(env1
->regbase
+ env1
->nwindows
* 16, env1
->regbase
);
2631 env1
->regwptr
= env1
->regbase
+ (new_cwp
* 16);
2634 void set_cwp(int new_cwp
)
2636 cpu_set_cwp(env
, new_cwp
);
2639 void helper_flush(target_ulong addr
)
2642 tb_invalidate_page_range(addr
, addr
+ 8);
2645 #if !defined(CONFIG_USER_ONLY)
2647 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
2650 #define MMUSUFFIX _mmu
2651 #define ALIGNED_ONLY
2654 #include "softmmu_template.h"
2657 #include "softmmu_template.h"
2660 #include "softmmu_template.h"
2663 #include "softmmu_template.h"
2665 /* XXX: make it generic ? */
2666 static void cpu_restore_state2(void *retaddr
)
2668 TranslationBlock
*tb
;
2672 /* now we have a real cpu fault */
2673 pc
= (unsigned long)retaddr
;
2674 tb
= tb_find_pc(pc
);
2676 /* the PC is inside the translated code. It means that we have
2677 a virtual CPU fault */
2678 cpu_restore_state(tb
, env
, pc
, (void *)(long)env
->cond
);
2683 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
2686 #ifdef DEBUG_UNALIGNED
2687 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
2688 "\n", addr
, env
->pc
);
2690 cpu_restore_state2(retaddr
);
2691 raise_exception(TT_UNALIGNED
);
2694 /* try to fill the TLB and return an exception if error. If retaddr is
2695 NULL, it means that the function was called in C code (i.e. not
2696 from generated code or from helper.c) */
2697 /* XXX: fix it to restore all registers */
2698 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
2701 CPUState
*saved_env
;
2703 /* XXX: hack to restore env in all cases, even if not called from
2706 env
= cpu_single_env
;
2708 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
2710 cpu_restore_state2(retaddr
);
2718 #ifndef TARGET_SPARC64
2719 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
2722 CPUState
*saved_env
;
2724 /* XXX: hack to restore env in all cases, even if not called from
2727 env
= cpu_single_env
;
2728 #ifdef DEBUG_UNASSIGNED
2730 printf("Unassigned mem %s access to " TARGET_FMT_plx
2731 " asi 0x%02x from " TARGET_FMT_lx
"\n",
2732 is_exec
? "exec" : is_write
? "write" : "read", addr
, is_asi
,
2735 printf("Unassigned mem %s access to " TARGET_FMT_plx
" from "
2737 is_exec
? "exec" : is_write
? "write" : "read", addr
, env
->pc
);
2739 if (env
->mmuregs
[3]) /* Fault status register */
2740 env
->mmuregs
[3] = 1; /* overflow (not read before another fault) */
2742 env
->mmuregs
[3] |= 1 << 16;
2744 env
->mmuregs
[3] |= 1 << 5;
2746 env
->mmuregs
[3] |= 1 << 6;
2748 env
->mmuregs
[3] |= 1 << 7;
2749 env
->mmuregs
[3] |= (5 << 2) | 2;
2750 env
->mmuregs
[4] = addr
; /* Fault address register */
2751 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
2753 raise_exception(TT_CODE_ACCESS
);
2755 raise_exception(TT_DATA_ACCESS
);
2760 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
2763 #ifdef DEBUG_UNASSIGNED
2764 CPUState
*saved_env
;
2766 /* XXX: hack to restore env in all cases, even if not called from
2769 env
= cpu_single_env
;
2770 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
2771 "\n", addr
, env
->pc
);
2775 raise_exception(TT_CODE_ACCESS
);
2777 raise_exception(TT_DATA_ACCESS
);