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Shuffle contents of tcg_target_reg_alloc_order
[qemu-kvm/fedora.git] / target-sparc / helper.c
blob7b87d592c49a93d7ba1c36856bef890d1c95f663
1 /*
2 * sparc helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "qemu-common.h"
31 #include "helper.h"
32
33 //#define DEBUG_MMU
34 //#define DEBUG_FEATURES
35 //#define DEBUG_PCALL
36
37 typedef struct sparc_def_t sparc_def_t;
38
39 struct sparc_def_t {
40 const char *name;
41 target_ulong iu_version;
42 uint32_t fpu_version;
43 uint32_t mmu_version;
44 uint32_t mmu_bm;
45 uint32_t mmu_ctpr_mask;
46 uint32_t mmu_cxr_mask;
47 uint32_t mmu_sfsr_mask;
48 uint32_t mmu_trcr_mask;
49 uint32_t features;
50 uint32_t nwindows;
51 };
52
53 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
54
55 /* Sparc MMU emulation */
56
57 /* thread support */
58
59 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
60
61 void cpu_lock(void)
62 {
63 spin_lock(&global_cpu_lock);
64 }
65
66 void cpu_unlock(void)
67 {
68 spin_unlock(&global_cpu_lock);
69 }
70
71 #if defined(CONFIG_USER_ONLY)
72
73 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
74 int mmu_idx, int is_softmmu)
75 {
76 if (rw & 2)
77 env1->exception_index = TT_TFAULT;
78 else
79 env1->exception_index = TT_DFAULT;
80 return 1;
81 }
82
83 #else
84
85 #ifndef TARGET_SPARC64
86 /*
87 * Sparc V8 Reference MMU (SRMMU)
88 */
89 static const int access_table[8][8] = {
90 { 0, 0, 0, 0, 2, 0, 3, 3 },
91 { 0, 0, 0, 0, 2, 0, 0, 0 },
92 { 2, 2, 0, 0, 0, 2, 3, 3 },
93 { 2, 2, 0, 0, 0, 2, 0, 0 },
94 { 2, 0, 2, 0, 2, 2, 3, 3 },
95 { 2, 0, 2, 0, 2, 0, 2, 0 },
96 { 2, 2, 2, 0, 2, 2, 3, 3 },
97 { 2, 2, 2, 0, 2, 2, 2, 0 }
98 };
99
100 static const int perm_table[2][8] = {
101 {
102 PAGE_READ,
103 PAGE_READ | PAGE_WRITE,
104 PAGE_READ | PAGE_EXEC,
105 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
106 PAGE_EXEC,
107 PAGE_READ | PAGE_WRITE,
108 PAGE_READ | PAGE_EXEC,
109 PAGE_READ | PAGE_WRITE | PAGE_EXEC
110 },
111 {
112 PAGE_READ,
113 PAGE_READ | PAGE_WRITE,
114 PAGE_READ | PAGE_EXEC,
115 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
116 PAGE_EXEC,
117 PAGE_READ,
118 0,
119 0,
120 }
121 };
122
123 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
124 int *prot, int *access_index,
125 target_ulong address, int rw, int mmu_idx)
126 {
127 int access_perms = 0;
128 target_phys_addr_t pde_ptr;
129 uint32_t pde;
130 target_ulong virt_addr;
131 int error_code = 0, is_dirty, is_user;
132 unsigned long page_offset;
133
134 is_user = mmu_idx == MMU_USER_IDX;
135 virt_addr = address & TARGET_PAGE_MASK;
136
137 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
138 // Boot mode: instruction fetches are taken from PROM
139 if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
140 *physical = env->prom_addr | (address & 0x7ffffULL);
141 *prot = PAGE_READ | PAGE_EXEC;
142 return 0;
143 }
144 *physical = address;
145 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
146 return 0;
147 }
148
149 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
150 *physical = 0xffffffffffff0000ULL;
151
152 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
153 /* Context base + context number */
154 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
155 pde = ldl_phys(pde_ptr);
156
157 /* Ctx pde */
158 switch (pde & PTE_ENTRYTYPE_MASK) {
159 default:
160 case 0: /* Invalid */
161 return 1 << 2;
162 case 2: /* L0 PTE, maybe should not happen? */
163 case 3: /* Reserved */
164 return 4 << 2;
165 case 1: /* L0 PDE */
166 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
167 pde = ldl_phys(pde_ptr);
168
169 switch (pde & PTE_ENTRYTYPE_MASK) {
170 default:
171 case 0: /* Invalid */
172 return (1 << 8) | (1 << 2);
173 case 3: /* Reserved */
174 return (1 << 8) | (4 << 2);
175 case 1: /* L1 PDE */
176 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
177 pde = ldl_phys(pde_ptr);
178
179 switch (pde & PTE_ENTRYTYPE_MASK) {
180 default:
181 case 0: /* Invalid */
182 return (2 << 8) | (1 << 2);
183 case 3: /* Reserved */
184 return (2 << 8) | (4 << 2);
185 case 1: /* L2 PDE */
186 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
187 pde = ldl_phys(pde_ptr);
188
189 switch (pde & PTE_ENTRYTYPE_MASK) {
190 default:
191 case 0: /* Invalid */
192 return (3 << 8) | (1 << 2);
193 case 1: /* PDE, should not happen */
194 case 3: /* Reserved */
195 return (3 << 8) | (4 << 2);
196 case 2: /* L3 PTE */
197 virt_addr = address & TARGET_PAGE_MASK;
198 page_offset = (address & TARGET_PAGE_MASK) &
199 (TARGET_PAGE_SIZE - 1);
200 }
201 break;
202 case 2: /* L2 PTE */
203 virt_addr = address & ~0x3ffff;
204 page_offset = address & 0x3ffff;
205 }
206 break;
207 case 2: /* L1 PTE */
208 virt_addr = address & ~0xffffff;
209 page_offset = address & 0xffffff;
210 }
211 }
212
213 /* update page modified and dirty bits */
214 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
215 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
216 pde |= PG_ACCESSED_MASK;
217 if (is_dirty)
218 pde |= PG_MODIFIED_MASK;
219 stl_phys_notdirty(pde_ptr, pde);
220 }
221 /* check access */
222 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
223 error_code = access_table[*access_index][access_perms];
224 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
225 return error_code;
226
227 /* the page can be put in the TLB */
228 *prot = perm_table[is_user][access_perms];
229 if (!(pde & PG_MODIFIED_MASK)) {
230 /* only set write access if already dirty... otherwise wait
231 for dirty access */
232 *prot &= ~PAGE_WRITE;
233 }
234
235 /* Even if large ptes, we map only one 4KB page in the cache to
236 avoid filling it too fast */
237 *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
238 return error_code;
239 }
240
241 /* Perform address translation */
242 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
243 int mmu_idx, int is_softmmu)
244 {
245 target_phys_addr_t paddr;
246 target_ulong vaddr;
247 int error_code = 0, prot, ret = 0, access_index;
248
249 error_code = get_physical_address(env, &paddr, &prot, &access_index,
250 address, rw, mmu_idx);
251 if (error_code == 0) {
252 vaddr = address & TARGET_PAGE_MASK;
253 paddr &= TARGET_PAGE_MASK;
254 #ifdef DEBUG_MMU
255 printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
256 TARGET_FMT_lx "\n", address, paddr, vaddr);
257 #endif
258 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
259 return ret;
260 }
261
262 if (env->mmuregs[3]) /* Fault status register */
263 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
264 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
265 env->mmuregs[4] = address; /* Fault address register */
266
267 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
268 // No fault mode: if a mapping is available, just override
269 // permissions. If no mapping is available, redirect accesses to
270 // neverland. Fake/overridden mappings will be flushed when
271 // switching to normal mode.
272 vaddr = address & TARGET_PAGE_MASK;
273 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
274 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
275 return ret;
276 } else {
277 if (rw & 2)
278 env->exception_index = TT_TFAULT;
279 else
280 env->exception_index = TT_DFAULT;
281 return 1;
282 }
283 }
284
285 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
286 {
287 target_phys_addr_t pde_ptr;
288 uint32_t pde;
289
290 /* Context base + context number */
291 pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
292 (env->mmuregs[2] << 2);
293 pde = ldl_phys(pde_ptr);
294
295 switch (pde & PTE_ENTRYTYPE_MASK) {
296 default:
297 case 0: /* Invalid */
298 case 2: /* PTE, maybe should not happen? */
299 case 3: /* Reserved */
300 return 0;
301 case 1: /* L1 PDE */
302 if (mmulev == 3)
303 return pde;
304 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
305 pde = ldl_phys(pde_ptr);
306
307 switch (pde & PTE_ENTRYTYPE_MASK) {
308 default:
309 case 0: /* Invalid */
310 case 3: /* Reserved */
311 return 0;
312 case 2: /* L1 PTE */
313 return pde;
314 case 1: /* L2 PDE */
315 if (mmulev == 2)
316 return pde;
317 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
318 pde = ldl_phys(pde_ptr);
319
320 switch (pde & PTE_ENTRYTYPE_MASK) {
321 default:
322 case 0: /* Invalid */
323 case 3: /* Reserved */
324 return 0;
325 case 2: /* L2 PTE */
326 return pde;
327 case 1: /* L3 PDE */
328 if (mmulev == 1)
329 return pde;
330 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
331 pde = ldl_phys(pde_ptr);
332
333 switch (pde & PTE_ENTRYTYPE_MASK) {
334 default:
335 case 0: /* Invalid */
336 case 1: /* PDE, should not happen */
337 case 3: /* Reserved */
338 return 0;
339 case 2: /* L3 PTE */
340 return pde;
341 }
342 }
343 }
344 }
345 return 0;
346 }
347
348 #ifdef DEBUG_MMU
349 void dump_mmu(CPUState *env)
350 {
351 target_ulong va, va1, va2;
352 unsigned int n, m, o;
353 target_phys_addr_t pde_ptr, pa;
354 uint32_t pde;
355
356 printf("MMU dump:\n");
357 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
358 pde = ldl_phys(pde_ptr);
359 printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
360 (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
361 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
362 pde = mmu_probe(env, va, 2);
363 if (pde) {
364 pa = cpu_get_phys_page_debug(env, va);
365 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
366 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
367 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
368 pde = mmu_probe(env, va1, 1);
369 if (pde) {
370 pa = cpu_get_phys_page_debug(env, va1);
371 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
372 " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
373 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
374 pde = mmu_probe(env, va2, 0);
375 if (pde) {
376 pa = cpu_get_phys_page_debug(env, va2);
377 printf(" VA: " TARGET_FMT_lx ", PA: "
378 TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
379 va2, pa, pde);
380 }
381 }
382 }
383 }
384 }
385 }
386 printf("MMU dump ends\n");
387 }
388 #endif /* DEBUG_MMU */
389
390 #else /* !TARGET_SPARC64 */
391 /*
392 * UltraSparc IIi I/DMMUs
393 */
394 static int get_physical_address_data(CPUState *env,
395 target_phys_addr_t *physical, int *prot,
396 target_ulong address, int rw, int is_user)
397 {
398 target_ulong mask;
399 unsigned int i;
400
401 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
402 *physical = address;
403 *prot = PAGE_READ | PAGE_WRITE;
404 return 0;
405 }
406
407 for (i = 0; i < 64; i++) {
408 switch ((env->dtlb_tte[i] >> 61) & 3) {
409 default:
410 case 0x0: // 8k
411 mask = 0xffffffffffffe000ULL;
412 break;
413 case 0x1: // 64k
414 mask = 0xffffffffffff0000ULL;
415 break;
416 case 0x2: // 512k
417 mask = 0xfffffffffff80000ULL;
418 break;
419 case 0x3: // 4M
420 mask = 0xffffffffffc00000ULL;
421 break;
422 }
423 // ctx match, vaddr match?
424 if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
425 (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
426 // valid, access ok?
427 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
428 ((env->dtlb_tte[i] & 0x4) && is_user) ||
429 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
430 if (env->dmmuregs[3]) /* Fault status register */
431 env->dmmuregs[3] = 2; /* overflow (not read before
432 another fault) */
433 env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
434 env->dmmuregs[4] = address; /* Fault address register */
435 env->exception_index = TT_DFAULT;
436 #ifdef DEBUG_MMU
437 printf("DFAULT at 0x%" PRIx64 "\n", address);
438 #endif
439 return 1;
440 }
441 *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
442 (address & ~mask & 0x1fffffff000ULL);
443 *prot = PAGE_READ;
444 if (env->dtlb_tte[i] & 0x2)
445 *prot |= PAGE_WRITE;
446 return 0;
447 }
448 }
449 #ifdef DEBUG_MMU
450 printf("DMISS at 0x%" PRIx64 "\n", address);
451 #endif
452 env->exception_index = TT_DMISS;
453 return 1;
454 }
455
456 static int get_physical_address_code(CPUState *env,
457 target_phys_addr_t *physical, int *prot,
458 target_ulong address, int is_user)
459 {
460 target_ulong mask;
461 unsigned int i;
462
463 if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
464 *physical = address;
465 *prot = PAGE_EXEC;
466 return 0;
467 }
468
469 for (i = 0; i < 64; i++) {
470 switch ((env->itlb_tte[i] >> 61) & 3) {
471 default:
472 case 0x0: // 8k
473 mask = 0xffffffffffffe000ULL;
474 break;
475 case 0x1: // 64k
476 mask = 0xffffffffffff0000ULL;
477 break;
478 case 0x2: // 512k
479 mask = 0xfffffffffff80000ULL;
480 break;
481 case 0x3: // 4M
482 mask = 0xffffffffffc00000ULL;
483 break;
484 }
485 // ctx match, vaddr match?
486 if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
487 (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
488 // valid, access ok?
489 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
490 ((env->itlb_tte[i] & 0x4) && is_user)) {
491 if (env->immuregs[3]) /* Fault status register */
492 env->immuregs[3] = 2; /* overflow (not read before
493 another fault) */
494 env->immuregs[3] |= (is_user << 3) | 1;
495 env->exception_index = TT_TFAULT;
496 #ifdef DEBUG_MMU
497 printf("TFAULT at 0x%" PRIx64 "\n", address);
498 #endif
499 return 1;
500 }
501 *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
502 (address & ~mask & 0x1fffffff000ULL);
503 *prot = PAGE_EXEC;
504 return 0;
505 }
506 }
507 #ifdef DEBUG_MMU
508 printf("TMISS at 0x%" PRIx64 "\n", address);
509 #endif
510 env->exception_index = TT_TMISS;
511 return 1;
512 }
513
514 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
515 int *prot, int *access_index,
516 target_ulong address, int rw, int mmu_idx)
517 {
518 int is_user = mmu_idx == MMU_USER_IDX;
519
520 if (rw == 2)
521 return get_physical_address_code(env, physical, prot, address,
522 is_user);
523 else
524 return get_physical_address_data(env, physical, prot, address, rw,
525 is_user);
526 }
527
528 /* Perform address translation */
529 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
530 int mmu_idx, int is_softmmu)
531 {
532 target_ulong virt_addr, vaddr;
533 target_phys_addr_t paddr;
534 int error_code = 0, prot, ret = 0, access_index;
535
536 error_code = get_physical_address(env, &paddr, &prot, &access_index,
537 address, rw, mmu_idx);
538 if (error_code == 0) {
539 virt_addr = address & TARGET_PAGE_MASK;
540 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
541 (TARGET_PAGE_SIZE - 1));
542 #ifdef DEBUG_MMU
543 printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
544 "\n", address, paddr, vaddr);
545 #endif
546 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
547 return ret;
548 }
549 // XXX
550 return 1;
551 }
552
553 #ifdef DEBUG_MMU
554 void dump_mmu(CPUState *env)
555 {
556 unsigned int i;
557 const char *mask;
558
559 printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
560 env->dmmuregs[1], env->dmmuregs[2]);
561 if ((env->lsu & DMMU_E) == 0) {
562 printf("DMMU disabled\n");
563 } else {
564 printf("DMMU dump:\n");
565 for (i = 0; i < 64; i++) {
566 switch ((env->dtlb_tte[i] >> 61) & 3) {
567 default:
568 case 0x0:
569 mask = " 8k";
570 break;
571 case 0x1:
572 mask = " 64k";
573 break;
574 case 0x2:
575 mask = "512k";
576 break;
577 case 0x3:
578 mask = " 4M";
579 break;
580 }
581 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
582 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
583 ", %s, %s, %s, %s, ctx %" PRId64 "\n",
584 env->dtlb_tag[i] & ~0x1fffULL,
585 env->dtlb_tte[i] & 0x1ffffffe000ULL,
586 mask,
587 env->dtlb_tte[i] & 0x4? "priv": "user",
588 env->dtlb_tte[i] & 0x2? "RW": "RO",
589 env->dtlb_tte[i] & 0x40? "locked": "unlocked",
590 env->dtlb_tag[i] & 0x1fffULL);
591 }
592 }
593 }
594 if ((env->lsu & IMMU_E) == 0) {
595 printf("IMMU disabled\n");
596 } else {
597 printf("IMMU dump:\n");
598 for (i = 0; i < 64; i++) {
599 switch ((env->itlb_tte[i] >> 61) & 3) {
600 default:
601 case 0x0:
602 mask = " 8k";
603 break;
604 case 0x1:
605 mask = " 64k";
606 break;
607 case 0x2:
608 mask = "512k";
609 break;
610 case 0x3:
611 mask = " 4M";
612 break;
613 }
614 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
615 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
616 ", %s, %s, %s, ctx %" PRId64 "\n",
617 env->itlb_tag[i] & ~0x1fffULL,
618 env->itlb_tte[i] & 0x1ffffffe000ULL,
619 mask,
620 env->itlb_tte[i] & 0x4? "priv": "user",
621 env->itlb_tte[i] & 0x40? "locked": "unlocked",
622 env->itlb_tag[i] & 0x1fffULL);
623 }
624 }
625 }
626 }
627 #endif /* DEBUG_MMU */
628
629 #endif /* TARGET_SPARC64 */
630 #endif /* !CONFIG_USER_ONLY */
631
632
633 #if defined(CONFIG_USER_ONLY)
634 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
635 {
636 return addr;
637 }
638
639 #else
640 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
641 {
642 target_phys_addr_t phys_addr;
643 int prot, access_index;
644
645 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
646 MMU_KERNEL_IDX) != 0)
647 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
648 0, MMU_KERNEL_IDX) != 0)
649 return -1;
650 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
651 return -1;
652 return phys_addr;
653 }
654 #endif
655
656 #ifdef TARGET_SPARC64
657 #ifdef DEBUG_PCALL
658 static const char * const excp_names[0x50] = {
659 [TT_TFAULT] = "Instruction Access Fault",
660 [TT_TMISS] = "Instruction Access MMU Miss",
661 [TT_CODE_ACCESS] = "Instruction Access Error",
662 [TT_ILL_INSN] = "Illegal Instruction",
663 [TT_PRIV_INSN] = "Privileged Instruction",
664 [TT_NFPU_INSN] = "FPU Disabled",
665 [TT_FP_EXCP] = "FPU Exception",
666 [TT_TOVF] = "Tag Overflow",
667 [TT_CLRWIN] = "Clean Windows",
668 [TT_DIV_ZERO] = "Division By Zero",
669 [TT_DFAULT] = "Data Access Fault",
670 [TT_DMISS] = "Data Access MMU Miss",
671 [TT_DATA_ACCESS] = "Data Access Error",
672 [TT_DPROT] = "Data Protection Error",
673 [TT_UNALIGNED] = "Unaligned Memory Access",
674 [TT_PRIV_ACT] = "Privileged Action",
675 [TT_EXTINT | 0x1] = "External Interrupt 1",
676 [TT_EXTINT | 0x2] = "External Interrupt 2",
677 [TT_EXTINT | 0x3] = "External Interrupt 3",
678 [TT_EXTINT | 0x4] = "External Interrupt 4",
679 [TT_EXTINT | 0x5] = "External Interrupt 5",
680 [TT_EXTINT | 0x6] = "External Interrupt 6",
681 [TT_EXTINT | 0x7] = "External Interrupt 7",
682 [TT_EXTINT | 0x8] = "External Interrupt 8",
683 [TT_EXTINT | 0x9] = "External Interrupt 9",
684 [TT_EXTINT | 0xa] = "External Interrupt 10",
685 [TT_EXTINT | 0xb] = "External Interrupt 11",
686 [TT_EXTINT | 0xc] = "External Interrupt 12",
687 [TT_EXTINT | 0xd] = "External Interrupt 13",
688 [TT_EXTINT | 0xe] = "External Interrupt 14",
689 [TT_EXTINT | 0xf] = "External Interrupt 15",
690 };
691 #endif
692
693 void do_interrupt(CPUState *env)
694 {
695 int intno = env->exception_index;
696
697 #ifdef DEBUG_PCALL
698 if (loglevel & CPU_LOG_INT) {
699 static int count;
700 const char *name;
701
702 if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
703 name = "Unknown";
704 else if (intno >= 0x100)
705 name = "Trap Instruction";
706 else if (intno >= 0xc0)
707 name = "Window Fill";
708 else if (intno >= 0x80)
709 name = "Window Spill";
710 else {
711 name = excp_names[intno];
712 if (!name)
713 name = "Unknown";
714 }
715
716 fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
717 " SP=%016" PRIx64 "\n",
718 count, name, intno,
719 env->pc,
720 env->npc, env->regwptr[6]);
721 cpu_dump_state(env, logfile, fprintf, 0);
722 #if 0
723 {
724 int i;
725 uint8_t *ptr;
726
727 fprintf(logfile, " code=");
728 ptr = (uint8_t *)env->pc;
729 for(i = 0; i < 16; i++) {
730 fprintf(logfile, " %02x", ldub(ptr + i));
731 }
732 fprintf(logfile, "\n");
733 }
734 #endif
735 count++;
736 }
737 #endif
738 #if !defined(CONFIG_USER_ONLY)
739 if (env->tl == MAXTL) {
740 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",
741 env->exception_index);
742 return;
743 }
744 #endif
745 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
746 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
747 GET_CWP64(env);
748 env->tsptr->tpc = env->pc;
749 env->tsptr->tnpc = env->npc;
750 env->tsptr->tt = intno;
751 change_pstate(PS_PEF | PS_PRIV | PS_AG);
752
753 if (intno == TT_CLRWIN)
754 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
755 else if ((intno & 0x1c0) == TT_SPILL)
756 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
757 else if ((intno & 0x1c0) == TT_FILL)
758 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
759 env->tbr &= ~0x7fffULL;
760 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
761 if (env->tl < MAXTL - 1) {
762 env->tl++;
763 } else {
764 env->pstate |= PS_RED;
765 if (env->tl != MAXTL)
766 env->tl++;
767 }
768 env->tsptr = &env->ts[env->tl];
769 env->pc = env->tbr;
770 env->npc = env->pc + 4;
771 env->exception_index = 0;
772 }
773 #else
774 #ifdef DEBUG_PCALL
775 static const char * const excp_names[0x80] = {
776 [TT_TFAULT] = "Instruction Access Fault",
777 [TT_ILL_INSN] = "Illegal Instruction",
778 [TT_PRIV_INSN] = "Privileged Instruction",
779 [TT_NFPU_INSN] = "FPU Disabled",
780 [TT_WIN_OVF] = "Window Overflow",
781 [TT_WIN_UNF] = "Window Underflow",
782 [TT_UNALIGNED] = "Unaligned Memory Access",
783 [TT_FP_EXCP] = "FPU Exception",
784 [TT_DFAULT] = "Data Access Fault",
785 [TT_TOVF] = "Tag Overflow",
786 [TT_EXTINT | 0x1] = "External Interrupt 1",
787 [TT_EXTINT | 0x2] = "External Interrupt 2",
788 [TT_EXTINT | 0x3] = "External Interrupt 3",
789 [TT_EXTINT | 0x4] = "External Interrupt 4",
790 [TT_EXTINT | 0x5] = "External Interrupt 5",
791 [TT_EXTINT | 0x6] = "External Interrupt 6",
792 [TT_EXTINT | 0x7] = "External Interrupt 7",
793 [TT_EXTINT | 0x8] = "External Interrupt 8",
794 [TT_EXTINT | 0x9] = "External Interrupt 9",
795 [TT_EXTINT | 0xa] = "External Interrupt 10",
796 [TT_EXTINT | 0xb] = "External Interrupt 11",
797 [TT_EXTINT | 0xc] = "External Interrupt 12",
798 [TT_EXTINT | 0xd] = "External Interrupt 13",
799 [TT_EXTINT | 0xe] = "External Interrupt 14",
800 [TT_EXTINT | 0xf] = "External Interrupt 15",
801 [TT_TOVF] = "Tag Overflow",
802 [TT_CODE_ACCESS] = "Instruction Access Error",
803 [TT_DATA_ACCESS] = "Data Access Error",
804 [TT_DIV_ZERO] = "Division By Zero",
805 [TT_NCP_INSN] = "Coprocessor Disabled",
806 };
807 #endif
808
809 void do_interrupt(CPUState *env)
810 {
811 int cwp, intno = env->exception_index;
812
813 #ifdef DEBUG_PCALL
814 if (loglevel & CPU_LOG_INT) {
815 static int count;
816 const char *name;
817
818 if (intno < 0 || intno >= 0x100)
819 name = "Unknown";
820 else if (intno >= 0x80)
821 name = "Trap Instruction";
822 else {
823 name = excp_names[intno];
824 if (!name)
825 name = "Unknown";
826 }
827
828 fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
829 count, name, intno,
830 env->pc,
831 env->npc, env->regwptr[6]);
832 cpu_dump_state(env, logfile, fprintf, 0);
833 #if 0
834 {
835 int i;
836 uint8_t *ptr;
837
838 fprintf(logfile, " code=");
839 ptr = (uint8_t *)env->pc;
840 for(i = 0; i < 16; i++) {
841 fprintf(logfile, " %02x", ldub(ptr + i));
842 }
843 fprintf(logfile, "\n");
844 }
845 #endif
846 count++;
847 }
848 #endif
849 #if !defined(CONFIG_USER_ONLY)
850 if (env->psret == 0) {
851 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
852 env->exception_index);
853 return;
854 }
855 #endif
856 env->psret = 0;
857 cwp = cpu_cwp_dec(env, env->cwp - 1);
858 cpu_set_cwp(env, cwp);
859 env->regwptr[9] = env->pc;
860 env->regwptr[10] = env->npc;
861 env->psrps = env->psrs;
862 env->psrs = 1;
863 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
864 env->pc = env->tbr;
865 env->npc = env->pc + 4;
866 env->exception_index = 0;
867 }
868 #endif
869
870 void memcpy32(target_ulong *dst, const target_ulong *src)
871 {
872 dst[0] = src[0];
873 dst[1] = src[1];
874 dst[2] = src[2];
875 dst[3] = src[3];
876 dst[4] = src[4];
877 dst[5] = src[5];
878 dst[6] = src[6];
879 dst[7] = src[7];
880 }
881
882 void cpu_reset(CPUSPARCState *env)
883 {
884 tlb_flush(env, 1);
885 env->cwp = 0;
886 env->wim = 1;
887 env->regwptr = env->regbase + (env->cwp * 16);
888 #if defined(CONFIG_USER_ONLY)
889 env->user_mode_only = 1;
890 #ifdef TARGET_SPARC64
891 env->cleanwin = env->nwindows - 2;
892 env->cansave = env->nwindows - 2;
893 env->pstate = PS_RMO | PS_PEF | PS_IE;
894 env->asi = 0x82; // Primary no-fault
895 #endif
896 #else
897 env->psret = 0;
898 env->psrs = 1;
899 env->psrps = 1;
900 #ifdef TARGET_SPARC64
901 env->pstate = PS_PRIV;
902 env->hpstate = HS_PRIV;
903 env->pc = 0x1fff0000000ULL;
904 env->tsptr = &env->ts[env->tl];
905 #else
906 env->pc = 0;
907 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
908 env->mmuregs[0] |= env->mmu_bm;
909 #endif
910 env->npc = env->pc + 4;
911 #endif
912 }
913
914 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
915 {
916 sparc_def_t def1, *def = &def1;
917
918 if (cpu_sparc_find_by_name(def, cpu_model) < 0)
919 return -1;
920
921 env->features = def->features;
922 env->cpu_model_str = cpu_model;
923 env->version = def->iu_version;
924 env->fsr = def->fpu_version;
925 env->nwindows = def->nwindows;
926 #if !defined(TARGET_SPARC64)
927 env->mmu_bm = def->mmu_bm;
928 env->mmu_ctpr_mask = def->mmu_ctpr_mask;
929 env->mmu_cxr_mask = def->mmu_cxr_mask;
930 env->mmu_sfsr_mask = def->mmu_sfsr_mask;
931 env->mmu_trcr_mask = def->mmu_trcr_mask;
932 env->mmuregs[0] |= def->mmu_version;
933 cpu_sparc_set_id(env, 0);
934 #else
935 env->version |= def->nwindows - 1;
936 #endif
937 return 0;
938 }
939
940 static void cpu_sparc_close(CPUSPARCState *env)
941 {
942 free(env);
943 }
944
945 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
946 {
947 CPUSPARCState *env;
948
949 env = qemu_mallocz(sizeof(CPUSPARCState));
950 if (!env)
951 return NULL;
952 cpu_exec_init(env);
953
954 gen_intermediate_code_init(env);
955
956 if (cpu_sparc_register(env, cpu_model) < 0) {
957 cpu_sparc_close(env);
958 return NULL;
959 }
960 cpu_reset(env);
961
962 return env;
963 }
964
965 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
966 {
967 #if !defined(TARGET_SPARC64)
968 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
969 #endif
970 }
971
972 static const sparc_def_t sparc_defs[] = {
973 #ifdef TARGET_SPARC64
974 {
975 .name = "Fujitsu Sparc64",
976 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
977 | (MAXTL << 8)),
978 .fpu_version = 0x00000000,
979 .mmu_version = 0,
980 .nwindows = 4,
981 .features = CPU_DEFAULT_FEATURES,
982 },
983 {
984 .name = "Fujitsu Sparc64 III",
985 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
986 | (MAXTL << 8)),
987 .fpu_version = 0x00000000,
988 .mmu_version = 0,
989 .nwindows = 5,
990 .features = CPU_DEFAULT_FEATURES,
991 },
992 {
993 .name = "Fujitsu Sparc64 IV",
994 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
995 | (MAXTL << 8)),
996 .fpu_version = 0x00000000,
997 .mmu_version = 0,
998 .nwindows = 8,
999 .features = CPU_DEFAULT_FEATURES,
1000 },
1001 {
1002 .name = "Fujitsu Sparc64 V",
1003 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
1004 | (MAXTL << 8)),
1005 .fpu_version = 0x00000000,
1006 .mmu_version = 0,
1007 .nwindows = 8,
1008 .features = CPU_DEFAULT_FEATURES,
1009 },
1010 {
1011 .name = "TI UltraSparc I",
1012 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
1013 | (MAXTL << 8)),
1014 .fpu_version = 0x00000000,
1015 .mmu_version = 0,
1016 .nwindows = 8,
1017 .features = CPU_DEFAULT_FEATURES,
1018 },
1019 {
1020 .name = "TI UltraSparc II",
1021 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
1022 | (MAXTL << 8)),
1023 .fpu_version = 0x00000000,
1024 .mmu_version = 0,
1025 .nwindows = 8,
1026 .features = CPU_DEFAULT_FEATURES,
1027 },
1028 {
1029 .name = "TI UltraSparc IIi",
1030 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
1031 | (MAXTL << 8)),
1032 .fpu_version = 0x00000000,
1033 .mmu_version = 0,
1034 .nwindows = 8,
1035 .features = CPU_DEFAULT_FEATURES,
1036 },
1037 {
1038 .name = "TI UltraSparc IIe",
1039 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
1040 | (MAXTL << 8)),
1041 .fpu_version = 0x00000000,
1042 .mmu_version = 0,
1043 .nwindows = 8,
1044 .features = CPU_DEFAULT_FEATURES,
1045 },
1046 {
1047 .name = "Sun UltraSparc III",
1048 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
1049 | (MAXTL << 8)),
1050 .fpu_version = 0x00000000,
1051 .mmu_version = 0,
1052 .nwindows = 8,
1053 .features = CPU_DEFAULT_FEATURES,
1054 },
1055 {
1056 .name = "Sun UltraSparc III Cu",
1057 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
1058 | (MAXTL << 8)),
1059 .fpu_version = 0x00000000,
1060 .mmu_version = 0,
1061 .nwindows = 8,
1062 .features = CPU_DEFAULT_FEATURES,
1063 },
1064 {
1065 .name = "Sun UltraSparc IIIi",
1066 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
1067 | (MAXTL << 8)),
1068 .fpu_version = 0x00000000,
1069 .mmu_version = 0,
1070 .nwindows = 8,
1071 .features = CPU_DEFAULT_FEATURES,
1072 },
1073 {
1074 .name = "Sun UltraSparc IV",
1075 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
1076 | (MAXTL << 8)),
1077 .fpu_version = 0x00000000,
1078 .mmu_version = 0,
1079 .nwindows = 8,
1080 .features = CPU_DEFAULT_FEATURES,
1081 },
1082 {
1083 .name = "Sun UltraSparc IV+",
1084 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
1085 | (MAXTL << 8)),
1086 .fpu_version = 0x00000000,
1087 .mmu_version = 0,
1088 .nwindows = 8,
1089 .features = CPU_DEFAULT_FEATURES,
1090 },
1091 {
1092 .name = "Sun UltraSparc IIIi+",
1093 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
1094 | (MAXTL << 8)),
1095 .fpu_version = 0x00000000,
1096 .mmu_version = 0,
1097 .nwindows = 8,
1098 .features = CPU_DEFAULT_FEATURES,
1099 },
1100 {
1101 .name = "NEC UltraSparc I",
1102 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
1103 | (MAXTL << 8)),
1104 .fpu_version = 0x00000000,
1105 .mmu_version = 0,
1106 .nwindows = 8,
1107 .features = CPU_DEFAULT_FEATURES,
1108 },
1109 #else
1110 {
1111 .name = "Fujitsu MB86900",
1112 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
1113 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1114 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
1115 .mmu_bm = 0x00004000,
1116 .mmu_ctpr_mask = 0x007ffff0,
1117 .mmu_cxr_mask = 0x0000003f,
1118 .mmu_sfsr_mask = 0xffffffff,
1119 .mmu_trcr_mask = 0xffffffff,
1120 .nwindows = 7,
1121 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
1122 },
1123 {
1124 .name = "Fujitsu MB86904",
1125 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
1126 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1127 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
1128 .mmu_bm = 0x00004000,
1129 .mmu_ctpr_mask = 0x00ffffc0,
1130 .mmu_cxr_mask = 0x000000ff,
1131 .mmu_sfsr_mask = 0x00016fff,
1132 .mmu_trcr_mask = 0x00ffffff,
1133 .nwindows = 8,
1134 .features = CPU_DEFAULT_FEATURES,
1135 },
1136 {
1137 .name = "Fujitsu MB86907",
1138 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
1139 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1140 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
1141 .mmu_bm = 0x00004000,
1142 .mmu_ctpr_mask = 0xffffffc0,
1143 .mmu_cxr_mask = 0x000000ff,
1144 .mmu_sfsr_mask = 0x00016fff,
1145 .mmu_trcr_mask = 0xffffffff,
1146 .nwindows = 8,
1147 .features = CPU_DEFAULT_FEATURES,
1148 },
1149 {
1150 .name = "LSI L64811",
1151 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
1152 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
1153 .mmu_version = 0x10 << 24,
1154 .mmu_bm = 0x00004000,
1155 .mmu_ctpr_mask = 0x007ffff0,
1156 .mmu_cxr_mask = 0x0000003f,
1157 .mmu_sfsr_mask = 0xffffffff,
1158 .mmu_trcr_mask = 0xffffffff,
1159 .nwindows = 8,
1160 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1161 CPU_FEATURE_FSMULD,
1162 },
1163 {
1164 .name = "Cypress CY7C601",
1165 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
1166 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1167 .mmu_version = 0x10 << 24,
1168 .mmu_bm = 0x00004000,
1169 .mmu_ctpr_mask = 0x007ffff0,
1170 .mmu_cxr_mask = 0x0000003f,
1171 .mmu_sfsr_mask = 0xffffffff,
1172 .mmu_trcr_mask = 0xffffffff,
1173 .nwindows = 8,
1174 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1175 CPU_FEATURE_FSMULD,
1176 },
1177 {
1178 .name = "Cypress CY7C611",
1179 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
1180 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1181 .mmu_version = 0x10 << 24,
1182 .mmu_bm = 0x00004000,
1183 .mmu_ctpr_mask = 0x007ffff0,
1184 .mmu_cxr_mask = 0x0000003f,
1185 .mmu_sfsr_mask = 0xffffffff,
1186 .mmu_trcr_mask = 0xffffffff,
1187 .nwindows = 8,
1188 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1189 CPU_FEATURE_FSMULD,
1190 },
1191 {
1192 .name = "TI SuperSparc II",
1193 .iu_version = 0x40000000,
1194 .fpu_version = 0 << 17,
1195 .mmu_version = 0x04000000,
1196 .mmu_bm = 0x00002000,
1197 .mmu_ctpr_mask = 0xffffffc0,
1198 .mmu_cxr_mask = 0x0000ffff,
1199 .mmu_sfsr_mask = 0xffffffff,
1200 .mmu_trcr_mask = 0xffffffff,
1201 .nwindows = 8,
1202 .features = CPU_DEFAULT_FEATURES,
1203 },
1204 {
1205 .name = "TI MicroSparc I",
1206 .iu_version = 0x41000000,
1207 .fpu_version = 4 << 17,
1208 .mmu_version = 0x41000000,
1209 .mmu_bm = 0x00004000,
1210 .mmu_ctpr_mask = 0x007ffff0,
1211 .mmu_cxr_mask = 0x0000003f,
1212 .mmu_sfsr_mask = 0x00016fff,
1213 .mmu_trcr_mask = 0x0000003f,
1214 .nwindows = 7,
1215 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
1216 CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
1217 CPU_FEATURE_FMUL,
1218 },
1219 {
1220 .name = "TI MicroSparc II",
1221 .iu_version = 0x42000000,
1222 .fpu_version = 4 << 17,
1223 .mmu_version = 0x02000000,
1224 .mmu_bm = 0x00004000,
1225 .mmu_ctpr_mask = 0x00ffffc0,
1226 .mmu_cxr_mask = 0x000000ff,
1227 .mmu_sfsr_mask = 0x00016fff,
1228 .mmu_trcr_mask = 0x00ffffff,
1229 .nwindows = 8,
1230 .features = CPU_DEFAULT_FEATURES,
1231 },
1232 {
1233 .name = "TI MicroSparc IIep",
1234 .iu_version = 0x42000000,
1235 .fpu_version = 4 << 17,
1236 .mmu_version = 0x04000000,
1237 .mmu_bm = 0x00004000,
1238 .mmu_ctpr_mask = 0x00ffffc0,
1239 .mmu_cxr_mask = 0x000000ff,
1240 .mmu_sfsr_mask = 0x00016bff,
1241 .mmu_trcr_mask = 0x00ffffff,
1242 .nwindows = 8,
1243 .features = CPU_DEFAULT_FEATURES,
1244 },
1245 {
1246 .name = "TI SuperSparc 40", // STP1020NPGA
1247 .iu_version = 0x41000000,
1248 .fpu_version = 0 << 17,
1249 .mmu_version = 0x00000000,
1250 .mmu_bm = 0x00002000,
1251 .mmu_ctpr_mask = 0xffffffc0,
1252 .mmu_cxr_mask = 0x0000ffff,
1253 .mmu_sfsr_mask = 0xffffffff,
1254 .mmu_trcr_mask = 0xffffffff,
1255 .nwindows = 8,
1256 .features = CPU_DEFAULT_FEATURES,
1257 },
1258 {
1259 .name = "TI SuperSparc 50", // STP1020PGA
1260 .iu_version = 0x40000000,
1261 .fpu_version = 0 << 17,
1262 .mmu_version = 0x04000000,
1263 .mmu_bm = 0x00002000,
1264 .mmu_ctpr_mask = 0xffffffc0,
1265 .mmu_cxr_mask = 0x0000ffff,
1266 .mmu_sfsr_mask = 0xffffffff,
1267 .mmu_trcr_mask = 0xffffffff,
1268 .nwindows = 8,
1269 .features = CPU_DEFAULT_FEATURES,
1270 },
1271 {
1272 .name = "TI SuperSparc 51",
1273 .iu_version = 0x43000000,
1274 .fpu_version = 0 << 17,
1275 .mmu_version = 0x04000000,
1276 .mmu_bm = 0x00002000,
1277 .mmu_ctpr_mask = 0xffffffc0,
1278 .mmu_cxr_mask = 0x0000ffff,
1279 .mmu_sfsr_mask = 0xffffffff,
1280 .mmu_trcr_mask = 0xffffffff,
1281 .nwindows = 8,
1282 .features = CPU_DEFAULT_FEATURES,
1283 },
1284 {
1285 .name = "TI SuperSparc 60", // STP1020APGA
1286 .iu_version = 0x40000000,
1287 .fpu_version = 0 << 17,
1288 .mmu_version = 0x03000000,
1289 .mmu_bm = 0x00002000,
1290 .mmu_ctpr_mask = 0xffffffc0,
1291 .mmu_cxr_mask = 0x0000ffff,
1292 .mmu_sfsr_mask = 0xffffffff,
1293 .mmu_trcr_mask = 0xffffffff,
1294 .nwindows = 8,
1295 .features = CPU_DEFAULT_FEATURES,
1296 },
1297 {
1298 .name = "TI SuperSparc 61",
1299 .iu_version = 0x44000000,
1300 .fpu_version = 0 << 17,
1301 .mmu_version = 0x04000000,
1302 .mmu_bm = 0x00002000,
1303 .mmu_ctpr_mask = 0xffffffc0,
1304 .mmu_cxr_mask = 0x0000ffff,
1305 .mmu_sfsr_mask = 0xffffffff,
1306 .mmu_trcr_mask = 0xffffffff,
1307 .nwindows = 8,
1308 .features = CPU_DEFAULT_FEATURES,
1309 },
1310 {
1311 .name = "Ross RT625",
1312 .iu_version = 0x1e000000,
1313 .fpu_version = 1 << 17,
1314 .mmu_version = 0x1e000000,
1315 .mmu_bm = 0x00004000,
1316 .mmu_ctpr_mask = 0x007ffff0,
1317 .mmu_cxr_mask = 0x0000003f,
1318 .mmu_sfsr_mask = 0xffffffff,
1319 .mmu_trcr_mask = 0xffffffff,
1320 .nwindows = 8,
1321 .features = CPU_DEFAULT_FEATURES,
1322 },
1323 {
1324 .name = "Ross RT620",
1325 .iu_version = 0x1f000000,
1326 .fpu_version = 1 << 17,
1327 .mmu_version = 0x1f000000,
1328 .mmu_bm = 0x00004000,
1329 .mmu_ctpr_mask = 0x007ffff0,
1330 .mmu_cxr_mask = 0x0000003f,
1331 .mmu_sfsr_mask = 0xffffffff,
1332 .mmu_trcr_mask = 0xffffffff,
1333 .nwindows = 8,
1334 .features = CPU_DEFAULT_FEATURES,
1335 },
1336 {
1337 .name = "BIT B5010",
1338 .iu_version = 0x20000000,
1339 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1340 .mmu_version = 0x20000000,
1341 .mmu_bm = 0x00004000,
1342 .mmu_ctpr_mask = 0x007ffff0,
1343 .mmu_cxr_mask = 0x0000003f,
1344 .mmu_sfsr_mask = 0xffffffff,
1345 .mmu_trcr_mask = 0xffffffff,
1346 .nwindows = 8,
1347 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1348 CPU_FEATURE_FSMULD,
1349 },
1350 {
1351 .name = "Matsushita MN10501",
1352 .iu_version = 0x50000000,
1353 .fpu_version = 0 << 17,
1354 .mmu_version = 0x50000000,
1355 .mmu_bm = 0x00004000,
1356 .mmu_ctpr_mask = 0x007ffff0,
1357 .mmu_cxr_mask = 0x0000003f,
1358 .mmu_sfsr_mask = 0xffffffff,
1359 .mmu_trcr_mask = 0xffffffff,
1360 .nwindows = 8,
1361 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
1362 CPU_FEATURE_FSMULD,
1363 },
1364 {
1365 .name = "Weitek W8601",
1366 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1367 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1368 .mmu_version = 0x10 << 24,
1369 .mmu_bm = 0x00004000,
1370 .mmu_ctpr_mask = 0x007ffff0,
1371 .mmu_cxr_mask = 0x0000003f,
1372 .mmu_sfsr_mask = 0xffffffff,
1373 .mmu_trcr_mask = 0xffffffff,
1374 .nwindows = 8,
1375 .features = CPU_DEFAULT_FEATURES,
1376 },
1377 {
1378 .name = "LEON2",
1379 .iu_version = 0xf2000000,
1380 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1381 .mmu_version = 0xf2000000,
1382 .mmu_bm = 0x00004000,
1383 .mmu_ctpr_mask = 0x007ffff0,
1384 .mmu_cxr_mask = 0x0000003f,
1385 .mmu_sfsr_mask = 0xffffffff,
1386 .mmu_trcr_mask = 0xffffffff,
1387 .nwindows = 8,
1388 .features = CPU_DEFAULT_FEATURES,
1389 },
1390 {
1391 .name = "LEON3",
1392 .iu_version = 0xf3000000,
1393 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1394 .mmu_version = 0xf3000000,
1395 .mmu_bm = 0x00004000,
1396 .mmu_ctpr_mask = 0x007ffff0,
1397 .mmu_cxr_mask = 0x0000003f,
1398 .mmu_sfsr_mask = 0xffffffff,
1399 .mmu_trcr_mask = 0xffffffff,
1400 .nwindows = 8,
1401 .features = CPU_DEFAULT_FEATURES,
1402 },
1403 #endif
1404 };
1405
1406 static const char * const feature_name[] = {
1407 "float",
1408 "float128",
1409 "swap",
1410 "mul",
1411 "div",
1412 "flush",
1413 "fsqrt",
1414 "fmul",
1415 "vis1",
1416 "vis2",
1417 "fsmuld",
1418 };
1419
1420 static void print_features(FILE *f,
1421 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1422 uint32_t features, const char *prefix)
1423 {
1424 unsigned int i;
1425
1426 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1427 if (feature_name[i] && (features & (1 << i))) {
1428 if (prefix)
1429 (*cpu_fprintf)(f, "%s", prefix);
1430 (*cpu_fprintf)(f, "%s ", feature_name[i]);
1431 }
1432 }
1433
1434 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1435 {
1436 unsigned int i;
1437
1438 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1439 if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1440 *features |= 1 << i;
1441 return;
1442 }
1443 fprintf(stderr, "CPU feature %s not found\n", flagname);
1444 }
1445
1446 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1447 {
1448 unsigned int i;
1449 const sparc_def_t *def = NULL;
1450 char *s = strdup(cpu_model);
1451 char *featurestr, *name = strtok(s, ",");
1452 uint32_t plus_features = 0;
1453 uint32_t minus_features = 0;
1454 long long iu_version;
1455 uint32_t fpu_version, mmu_version, nwindows;
1456
1457 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1458 if (strcasecmp(name, sparc_defs[i].name) == 0) {
1459 def = &sparc_defs[i];
1460 }
1461 }
1462 if (!def)
1463 goto error;
1464 memcpy(cpu_def, def, sizeof(*def));
1465
1466 featurestr = strtok(NULL, ",");
1467 while (featurestr) {
1468 char *val;
1469
1470 if (featurestr[0] == '+') {
1471 add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1472 } else if (featurestr[0] == '-') {
1473 add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1474 } else if ((val = strchr(featurestr, '='))) {
1475 *val = 0; val++;
1476 if (!strcmp(featurestr, "iu_version")) {
1477 char *err;
1478
1479 iu_version = strtoll(val, &err, 0);
1480 if (!*val || *err) {
1481 fprintf(stderr, "bad numerical value %s\n", val);
1482 goto error;
1483 }
1484 cpu_def->iu_version = iu_version;
1485 #ifdef DEBUG_FEATURES
1486 fprintf(stderr, "iu_version %llx\n", iu_version);
1487 #endif
1488 } else if (!strcmp(featurestr, "fpu_version")) {
1489 char *err;
1490
1491 fpu_version = strtol(val, &err, 0);
1492 if (!*val || *err) {
1493 fprintf(stderr, "bad numerical value %s\n", val);
1494 goto error;
1495 }
1496 cpu_def->fpu_version = fpu_version;
1497 #ifdef DEBUG_FEATURES
1498 fprintf(stderr, "fpu_version %llx\n", fpu_version);
1499 #endif
1500 } else if (!strcmp(featurestr, "mmu_version")) {
1501 char *err;
1502
1503 mmu_version = strtol(val, &err, 0);
1504 if (!*val || *err) {
1505 fprintf(stderr, "bad numerical value %s\n", val);
1506 goto error;
1507 }
1508 cpu_def->mmu_version = mmu_version;
1509 #ifdef DEBUG_FEATURES
1510 fprintf(stderr, "mmu_version %llx\n", mmu_version);
1511 #endif
1512 } else if (!strcmp(featurestr, "nwindows")) {
1513 char *err;
1514
1515 nwindows = strtol(val, &err, 0);
1516 if (!*val || *err || nwindows > MAX_NWINDOWS ||
1517 nwindows < MIN_NWINDOWS) {
1518 fprintf(stderr, "bad numerical value %s\n", val);
1519 goto error;
1520 }
1521 cpu_def->nwindows = nwindows;
1522 #ifdef DEBUG_FEATURES
1523 fprintf(stderr, "nwindows %d\n", nwindows);
1524 #endif
1525 } else {
1526 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1527 goto error;
1528 }
1529 } else {
1530 fprintf(stderr, "feature string `%s' not in format "
1531 "(+feature|-feature|feature=xyz)\n", featurestr);
1532 goto error;
1533 }
1534 featurestr = strtok(NULL, ",");
1535 }
1536 cpu_def->features |= plus_features;
1537 cpu_def->features &= ~minus_features;
1538 #ifdef DEBUG_FEATURES
1539 print_features(stderr, fprintf, cpu_def->features, NULL);
1540 #endif
1541 free(s);
1542 return 0;
1543
1544 error:
1545 free(s);
1546 return -1;
1547 }
1548
1549 void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1550 {
1551 unsigned int i;
1552
1553 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1554 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ",
1555 sparc_defs[i].name,
1556 sparc_defs[i].iu_version,
1557 sparc_defs[i].fpu_version,
1558 sparc_defs[i].mmu_version,
1559 sparc_defs[i].nwindows);
1560 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
1561 ~sparc_defs[i].features, "-");
1562 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
1563 sparc_defs[i].features, "+");
1564 (*cpu_fprintf)(f, "\n");
1565 }
1566 (*cpu_fprintf)(f, "CPU feature flags (+/-): ");
1567 print_features(f, cpu_fprintf, -1, NULL);
1568 (*cpu_fprintf)(f, "\n");
1569 (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version "
1570 "mmu_version nwindows\n");
1571 }
1572
1573 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1574
1575 void cpu_dump_state(CPUState *env, FILE *f,
1576 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1577 int flags)
1578 {
1579 int i, x;
1580
1581 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
1582 env->npc);
1583 cpu_fprintf(f, "General Registers:\n");
1584 for (i = 0; i < 4; i++)
1585 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1586 cpu_fprintf(f, "\n");
1587 for (; i < 8; i++)
1588 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1589 cpu_fprintf(f, "\nCurrent Register Window:\n");
1590 for (x = 0; x < 3; x++) {
1591 for (i = 0; i < 4; i++)
1592 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1593 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1594 env->regwptr[i + x * 8]);
1595 cpu_fprintf(f, "\n");
1596 for (; i < 8; i++)
1597 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1598 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1599 env->regwptr[i + x * 8]);
1600 cpu_fprintf(f, "\n");
1601 }
1602 cpu_fprintf(f, "\nFloating Point Registers:\n");
1603 for (i = 0; i < 32; i++) {
1604 if ((i & 3) == 0)
1605 cpu_fprintf(f, "%%f%02d:", i);
1606 cpu_fprintf(f, " %016lf", env->fpr[i]);
1607 if ((i & 3) == 3)
1608 cpu_fprintf(f, "\n");
1609 }
1610 #ifdef TARGET_SPARC64
1611 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1612 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
1613 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
1614 "cleanwin %d cwp %d\n",
1615 env->cansave, env->canrestore, env->otherwin, env->wstate,
1616 env->cleanwin, env->nwindows - 1 - env->cwp);
1617 #else
1618 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
1619 GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1620 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1621 env->psrs?'S':'-', env->psrps?'P':'-',
1622 env->psret?'E':'-', env->wim);
1623 #endif
1624 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
1625 }
1626
1627 #ifdef TARGET_SPARC64
1628 #if !defined(CONFIG_USER_ONLY)
1629 #include "qemu-common.h"
1630 #include "hw/irq.h"
1631 #include "qemu-timer.h"
1632 #endif
1633
1634 void helper_tick_set_count(void *opaque, uint64_t count)
1635 {
1636 #if !defined(CONFIG_USER_ONLY)
1637 ptimer_set_count(opaque, -count);
1638 #endif
1639 }
1640
1641 uint64_t helper_tick_get_count(void *opaque)
1642 {
1643 #if !defined(CONFIG_USER_ONLY)
1644 return -ptimer_get_count(opaque);
1645 #else
1646 return 0;
1647 #endif
1648 }
1649
1650 void helper_tick_set_limit(void *opaque, uint64_t limit)
1651 {
1652 #if !defined(CONFIG_USER_ONLY)
1653 ptimer_set_limit(opaque, -limit, 0);
1654 #endif
1655 }
1656 #endif
Patches shipped by Fedora