target-mips/exec.h

   1 #if !defined(__QEMU_MIPS_EXEC_H__)
   2 #define __QEMU_MIPS_EXEC_H__
   3
   4 //#define DEBUG_OP
   5
   6 #include "config.h"
   7 #include "mips-defs.h"
   8 #include "dyngen-exec.h"
   9 #include "cpu-defs.h"
  10
  11 register struct CPUMIPSState *env asm(AREG0);
  12
  13 #if TARGET_LONG_BITS > HOST_LONG_BITS
  14 #define T0 (env->t0)
  15 #define T1 (env->t1)
  16 #else
  17 register target_ulong T0 asm(AREG1);
  18 register target_ulong T1 asm(AREG2);
  19 #endif
  20
  21 #if defined (USE_HOST_FLOAT_REGS)
  22 #error "implement me."
  23 #else
  24 #define FDT0 (env->ft0.fd)
  25 #define FDT1 (env->ft1.fd)
  26 #define FDT2 (env->ft2.fd)
  27 #define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
  28 #define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
  29 #define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
  30 #define FSTH0 (env->ft0.fs[!FP_ENDIAN_IDX])
  31 #define FSTH1 (env->ft1.fs[!FP_ENDIAN_IDX])
  32 #define FSTH2 (env->ft2.fs[!FP_ENDIAN_IDX])
  33 #define DT0 (env->ft0.d)
  34 #define DT1 (env->ft1.d)
  35 #define DT2 (env->ft2.d)
  36 #define WT0 (env->ft0.w[FP_ENDIAN_IDX])
  37 #define WT1 (env->ft1.w[FP_ENDIAN_IDX])
  38 #define WT2 (env->ft2.w[FP_ENDIAN_IDX])
  39 #define WTH0 (env->ft0.w[!FP_ENDIAN_IDX])
  40 #define WTH1 (env->ft1.w[!FP_ENDIAN_IDX])
  41 #define WTH2 (env->ft2.w[!FP_ENDIAN_IDX])
  42 #endif
  43
  44 #include "cpu.h"
  45 #include "exec-all.h"
  46
  47 #if !defined(CONFIG_USER_ONLY)
  48 #include "softmmu_exec.h"
  49 #endif /* !defined(CONFIG_USER_ONLY) */
  50
  51 void do_mtc0_status_debug(uint32_t old, uint32_t val);
  52 void do_mtc0_status_irqraise_debug(void);
  53 void dump_fpu(CPUState *env);
  54 void fpu_dump_state(CPUState *env, FILE *f,
  55                     int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
  56                     int flags);
  57 void dump_sc (void);
  58
  59 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
  60                                int mmu_idx, int is_softmmu);
  61 void do_interrupt (CPUState *env);
  62 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
  63
  64 void cpu_loop_exit(void);
  65 void do_raise_exception_err (uint32_t exception, int error_code);
  66 void do_raise_exception (uint32_t exception);
  67
  68 void cpu_dump_state(CPUState *env, FILE *f,
  69                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
  70                     int flags);
  71 void cpu_mips_irqctrl_init (void);
  72 uint32_t cpu_mips_get_random (CPUState *env);
  73 uint32_t cpu_mips_get_count (CPUState *env);
  74 void cpu_mips_store_count (CPUState *env, uint32_t value);
  75 void cpu_mips_store_compare (CPUState *env, uint32_t value);
  76 void cpu_mips_start_count(CPUState *env);
  77 void cpu_mips_stop_count(CPUState *env);
  78 void cpu_mips_update_irq (CPUState *env);
  79 void cpu_mips_clock_init (CPUState *env);
  80 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
  81
  82 static always_inline void env_to_regs(void)
  83 {
  84 }
  85
  86 static always_inline void regs_to_env(void)
  87 {
  88 }
  89
  90 static always_inline int cpu_halted(CPUState *env)
  91 {
  92     if (!env->halted)
  93         return 0;
  94     if (env->interrupt_request &
  95         (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
  96         env->halted = 0;
  97         return 0;
  98     }
  99     return EXCP_HALTED;
 100 }
 101
 102 static always_inline void compute_hflags(CPUState *env)
 103 {
 104     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 105                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU);
 106     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 107         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 108         !(env->hflags & MIPS_HFLAG_DM)) {
 109         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 110     }
 111 #if defined(TARGET_MIPS64)
 112     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 113         (env->CP0_Status & (1 << CP0St_PX)) ||
 114         (env->CP0_Status & (1 << CP0St_UX)))
 115         env->hflags |= MIPS_HFLAG_64;
 116 #endif
 117     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
 118         !(env->hflags & MIPS_HFLAG_KSU))
 119         env->hflags |= MIPS_HFLAG_CP0;
 120     if (env->CP0_Status & (1 << CP0St_CU1))
 121         env->hflags |= MIPS_HFLAG_FPU;
 122     if (env->CP0_Status & (1 << CP0St_FR))
 123         env->hflags |= MIPS_HFLAG_F64;
 124     if (env->insn_flags & ISA_MIPS32R2) {
 125         if (env->fpu->fcr0 & (1 << FCR0_F64))
 126             env->hflags |= MIPS_HFLAG_COP1X;
 127     } else if (env->insn_flags & ISA_MIPS32) {
 128         if (env->hflags & MIPS_HFLAG_64)
 129             env->hflags |= MIPS_HFLAG_COP1X;
 130     } else if (env->insn_flags & ISA_MIPS4) {
 131         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 132            and disable the MIPS IV extensions to the MIPS III ISA.
 133            Some other MIPS IV CPUs ignore the bit, so the check here
 134            would be too restrictive for them.  */
 135         if (env->CP0_Status & (1 << CP0St_CU3))
 136             env->hflags |= MIPS_HFLAG_COP1X;
 137     }
 138 }
 139
 140 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */