qemu-kvm-x86.c

   1 /*
   2  * qemu/kvm integration, x86 specific code
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  *
   6  * Licensed under the terms of the GNU GPL version 2 or higher.
   7  */
   8
   9 #include "config.h"
  10 #include "config-host.h"
  11
  12 #include <string.h>
  13 #include "hw/hw.h"
  14 #include "gdbstub.h"
  15 #include <sys/io.h>
  16
  17 #include "qemu-kvm.h"
  18 #include <libkvm.h>
  19 #include <pthread.h>
  20 #include <sys/utsname.h>
  21 #include <linux/kvm_para.h>
  22
  23 #define MSR_IA32_TSC            0x10
  24
  25 static struct kvm_msr_list *kvm_msr_list;
  26 extern unsigned int kvm_shadow_memory;
  27 extern kvm_context_t kvm_context;
  28 static int kvm_has_msr_star;
  29
  30 static int lm_capable_kernel;
  31
  32 int kvm_qemu_create_memory_alias(uint64_t phys_start,
  33                                  uint64_t len,
  34                                  uint64_t target_phys)
  35 {
  36     return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
  37 }
  38
  39 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
  40 {
  41         return kvm_destroy_memory_alias(kvm_context, phys_start);
  42 }
  43
  44 int kvm_arch_qemu_create_context(void)
  45 {
  46     int i;
  47     struct utsname utsname;
  48
  49     uname(&utsname);
  50     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
  51
  52     if (kvm_shadow_memory)
  53         kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
  54
  55     kvm_msr_list = kvm_get_msr_list(kvm_context);
  56     if (!kvm_msr_list)
  57                 return -1;
  58     for (i = 0; i < kvm_msr_list->nmsrs; ++i)
  59         if (kvm_msr_list->indices[i] == MSR_STAR)
  60             kvm_has_msr_star = 1;
  61         return 0;
  62 }
  63
  64 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
  65                           uint64_t data)
  66 {
  67     entry->index = index;
  68     entry->data  = data;
  69 }
  70
  71 /* returns 0 on success, non-0 on failure */
  72 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
  73 {
  74         switch (entry->index) {
  75         case MSR_IA32_SYSENTER_CS:
  76             env->sysenter_cs  = entry->data;
  77             break;
  78         case MSR_IA32_SYSENTER_ESP:
  79             env->sysenter_esp = entry->data;
  80             break;
  81         case MSR_IA32_SYSENTER_EIP:
  82             env->sysenter_eip = entry->data;
  83             break;
  84         case MSR_STAR:
  85             env->star         = entry->data;
  86             break;
  87 #ifdef TARGET_X86_64
  88         case MSR_CSTAR:
  89             env->cstar        = entry->data;
  90             break;
  91         case MSR_KERNELGSBASE:
  92             env->kernelgsbase = entry->data;
  93             break;
  94         case MSR_FMASK:
  95             env->fmask        = entry->data;
  96             break;
  97         case MSR_LSTAR:
  98             env->lstar        = entry->data;
  99             break;
 100 #endif
 101         case MSR_IA32_TSC:
 102             env->tsc          = entry->data;
 103             break;
 104         case MSR_VM_HSAVE_PA:
 105             env->vm_hsave     = entry->data;
 106             break;
 107         default:
 108             printf("Warning unknown msr index 0x%x\n", entry->index);
 109             return 1;
 110         }
 111         return 0;
 112 }
 113
 114 #ifdef TARGET_X86_64
 115 #define MSR_COUNT 9
 116 #else
 117 #define MSR_COUNT 5
 118 #endif
 119
 120 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 121 {
 122     lhs->selector = rhs->selector;
 123     lhs->base = rhs->base;
 124     lhs->limit = rhs->limit;
 125     lhs->type = 3;
 126     lhs->present = 1;
 127     lhs->dpl = 3;
 128     lhs->db = 0;
 129     lhs->s = 1;
 130     lhs->l = 0;
 131     lhs->g = 0;
 132     lhs->avl = 0;
 133     lhs->unusable = 0;
 134 }
 135
 136 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 137 {
 138     unsigned flags = rhs->flags;
 139     lhs->selector = rhs->selector;
 140     lhs->base = rhs->base;
 141     lhs->limit = rhs->limit;
 142     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 143     lhs->present = (flags & DESC_P_MASK) != 0;
 144     lhs->dpl = rhs->selector & 3;
 145     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 146     lhs->s = (flags & DESC_S_MASK) != 0;
 147     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 148     lhs->g = (flags & DESC_G_MASK) != 0;
 149     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 150     lhs->unusable = 0;
 151 }
 152
 153 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 154 {
 155     lhs->selector = rhs->selector;
 156     lhs->base = rhs->base;
 157     lhs->limit = rhs->limit;
 158     lhs->flags =
 159         (rhs->type << DESC_TYPE_SHIFT)
 160         | (rhs->present * DESC_P_MASK)
 161         | (rhs->dpl << DESC_DPL_SHIFT)
 162         | (rhs->db << DESC_B_SHIFT)
 163         | (rhs->s * DESC_S_MASK)
 164         | (rhs->l << DESC_L_SHIFT)
 165         | (rhs->g * DESC_G_MASK)
 166         | (rhs->avl * DESC_AVL_MASK);
 167 }
 168
 169 void kvm_arch_load_regs(CPUState *env)
 170 {
 171     struct kvm_regs regs;
 172     struct kvm_fpu fpu;
 173     struct kvm_sregs sregs;
 174     struct kvm_msr_entry msrs[MSR_COUNT];
 175     int rc, n, i;
 176
 177     regs.rax = env->regs[R_EAX];
 178     regs.rbx = env->regs[R_EBX];
 179     regs.rcx = env->regs[R_ECX];
 180     regs.rdx = env->regs[R_EDX];
 181     regs.rsi = env->regs[R_ESI];
 182     regs.rdi = env->regs[R_EDI];
 183     regs.rsp = env->regs[R_ESP];
 184     regs.rbp = env->regs[R_EBP];
 185 #ifdef TARGET_X86_64
 186     regs.r8 = env->regs[8];
 187     regs.r9 = env->regs[9];
 188     regs.r10 = env->regs[10];
 189     regs.r11 = env->regs[11];
 190     regs.r12 = env->regs[12];
 191     regs.r13 = env->regs[13];
 192     regs.r14 = env->regs[14];
 193     regs.r15 = env->regs[15];
 194 #endif
 195
 196     regs.rflags = env->eflags;
 197     regs.rip = env->eip;
 198
 199     kvm_set_regs(kvm_context, env->cpu_index, &regs);
 200
 201     memset(&fpu, 0, sizeof fpu);
 202     fpu.fsw = env->fpus & ~(7 << 11);
 203     fpu.fsw |= (env->fpstt & 7) << 11;
 204     fpu.fcw = env->fpuc;
 205     for (i = 0; i < 8; ++i)
 206         fpu.ftwx |= (!env->fptags[i]) << i;
 207     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 208     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 209     fpu.mxcsr = env->mxcsr;
 210     kvm_set_fpu(kvm_context, env->cpu_index, &fpu);
 211
 212     memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
 213
 214     if ((env->eflags & VM_MASK)) {
 215             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 216             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 217             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 218             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 219             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 220             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 221     } else {
 222             set_seg(&sregs.cs, &env->segs[R_CS]);
 223             set_seg(&sregs.ds, &env->segs[R_DS]);
 224             set_seg(&sregs.es, &env->segs[R_ES]);
 225             set_seg(&sregs.fs, &env->segs[R_FS]);
 226             set_seg(&sregs.gs, &env->segs[R_GS]);
 227             set_seg(&sregs.ss, &env->segs[R_SS]);
 228
 229             if (env->cr[0] & CR0_PE_MASK) {
 230                 /* force ss cpl to cs cpl */
 231                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 232                         (sregs.cs.selector & 3);
 233                 sregs.ss.dpl = sregs.ss.selector & 3;
 234             }
 235     }
 236
 237     set_seg(&sregs.tr, &env->tr);
 238     set_seg(&sregs.ldt, &env->ldt);
 239
 240     sregs.idt.limit = env->idt.limit;
 241     sregs.idt.base = env->idt.base;
 242     sregs.gdt.limit = env->gdt.limit;
 243     sregs.gdt.base = env->gdt.base;
 244
 245     sregs.cr0 = env->cr[0];
 246     sregs.cr2 = env->cr[2];
 247     sregs.cr3 = env->cr[3];
 248     sregs.cr4 = env->cr[4];
 249
 250     sregs.cr8 = cpu_get_apic_tpr(env);
 251     sregs.apic_base = cpu_get_apic_base(env);
 252
 253     sregs.efer = env->efer;
 254
 255     kvm_set_sregs(kvm_context, env->cpu_index, &sregs);
 256
 257     /* msrs */
 258     n = 0;
 259     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS,  env->sysenter_cs);
 260     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 261     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 262     if (kvm_has_msr_star)
 263         set_msr_entry(&msrs[n++], MSR_STAR,              env->star);
 264     set_msr_entry(&msrs[n++], MSR_IA32_TSC, env->tsc);
 265     set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 266 #ifdef TARGET_X86_64
 267     if (lm_capable_kernel) {
 268         set_msr_entry(&msrs[n++], MSR_CSTAR,             env->cstar);
 269         set_msr_entry(&msrs[n++], MSR_KERNELGSBASE,      env->kernelgsbase);
 270         set_msr_entry(&msrs[n++], MSR_FMASK,             env->fmask);
 271         set_msr_entry(&msrs[n++], MSR_LSTAR  ,           env->lstar);
 272     }
 273 #endif
 274
 275     rc = kvm_set_msrs(kvm_context, env->cpu_index, msrs, n);
 276     if (rc == -1)
 277         perror("kvm_set_msrs FAILED");
 278 }
 279
 280 void kvm_save_mpstate(CPUState *env)
 281 {
 282 #ifdef KVM_CAP_MP_STATE
 283     int r;
 284     struct kvm_mp_state mp_state;
 285
 286     r = kvm_get_mpstate(kvm_context, env->cpu_index, &mp_state);
 287     if (r < 0)
 288         env->mp_state = -1;
 289     else
 290         env->mp_state = mp_state.mp_state;
 291 #endif
 292 }
 293
 294 void kvm_load_mpstate(CPUState *env)
 295 {
 296 #ifdef KVM_CAP_MP_STATE
 297     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 298
 299     /*
 300      * -1 indicates that the host did not support GET_MP_STATE ioctl,
 301      *  so don't touch it.
 302      */
 303     if (env->mp_state != -1)
 304         kvm_set_mpstate(kvm_context, env->cpu_index, &mp_state);
 305 #endif
 306 }
 307
 308 void kvm_arch_save_regs(CPUState *env)
 309 {
 310     struct kvm_regs regs;
 311     struct kvm_fpu fpu;
 312     struct kvm_sregs sregs;
 313     struct kvm_msr_entry msrs[MSR_COUNT];
 314     uint32_t hflags;
 315     uint32_t i, n, rc;
 316
 317     kvm_get_regs(kvm_context, env->cpu_index, &regs);
 318
 319     env->regs[R_EAX] = regs.rax;
 320     env->regs[R_EBX] = regs.rbx;
 321     env->regs[R_ECX] = regs.rcx;
 322     env->regs[R_EDX] = regs.rdx;
 323     env->regs[R_ESI] = regs.rsi;
 324     env->regs[R_EDI] = regs.rdi;
 325     env->regs[R_ESP] = regs.rsp;
 326     env->regs[R_EBP] = regs.rbp;
 327 #ifdef TARGET_X86_64
 328     env->regs[8] = regs.r8;
 329     env->regs[9] = regs.r9;
 330     env->regs[10] = regs.r10;
 331     env->regs[11] = regs.r11;
 332     env->regs[12] = regs.r12;
 333     env->regs[13] = regs.r13;
 334     env->regs[14] = regs.r14;
 335     env->regs[15] = regs.r15;
 336 #endif
 337
 338     env->eflags = regs.rflags;
 339     env->eip = regs.rip;
 340
 341     kvm_get_fpu(kvm_context, env->cpu_index, &fpu);
 342     env->fpstt = (fpu.fsw >> 11) & 7;
 343     env->fpus = fpu.fsw;
 344     env->fpuc = fpu.fcw;
 345     for (i = 0; i < 8; ++i)
 346         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 347     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 348     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 349     env->mxcsr = fpu.mxcsr;
 350
 351     kvm_get_sregs(kvm_context, env->cpu_index, &sregs);
 352
 353     memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
 354
 355     get_seg(&env->segs[R_CS], &sregs.cs);
 356     get_seg(&env->segs[R_DS], &sregs.ds);
 357     get_seg(&env->segs[R_ES], &sregs.es);
 358     get_seg(&env->segs[R_FS], &sregs.fs);
 359     get_seg(&env->segs[R_GS], &sregs.gs);
 360     get_seg(&env->segs[R_SS], &sregs.ss);
 361
 362     get_seg(&env->tr, &sregs.tr);
 363     get_seg(&env->ldt, &sregs.ldt);
 364
 365     env->idt.limit = sregs.idt.limit;
 366     env->idt.base = sregs.idt.base;
 367     env->gdt.limit = sregs.gdt.limit;
 368     env->gdt.base = sregs.gdt.base;
 369
 370     env->cr[0] = sregs.cr0;
 371     env->cr[2] = sregs.cr2;
 372     env->cr[3] = sregs.cr3;
 373     env->cr[4] = sregs.cr4;
 374
 375     cpu_set_apic_base(env, sregs.apic_base);
 376
 377     env->efer = sregs.efer;
 378     //cpu_set_apic_tpr(env, sregs.cr8);
 379
 380 #define HFLAG_COPY_MASK ~( \
 381                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 382                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 383                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 384                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 385
 386
 387
 388     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 389     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 390     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 391             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 392     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 393     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 394             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 395
 396     if (env->efer & MSR_EFER_LMA) {
 397         hflags |= HF_LMA_MASK;
 398     }
 399
 400     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 401         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 402     } else {
 403         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 404                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 405         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 406                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 407         if (!(env->cr[0] & CR0_PE_MASK) ||
 408                    (env->eflags & VM_MASK) ||
 409                    !(hflags & HF_CS32_MASK)) {
 410                 hflags |= HF_ADDSEG_MASK;
 411             } else {
 412                 hflags |= ((env->segs[R_DS].base |
 413                                 env->segs[R_ES].base |
 414                                 env->segs[R_SS].base) != 0) <<
 415                     HF_ADDSEG_SHIFT;
 416             }
 417     }
 418     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 419     env->cc_src = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 420     env->df = 1 - (2 * ((env->eflags >> 10) & 1));
 421     env->cc_op = CC_OP_EFLAGS;
 422     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 423
 424     /* msrs */
 425     n = 0;
 426     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 427     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 428     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 429     if (kvm_has_msr_star)
 430         msrs[n++].index = MSR_STAR;
 431     msrs[n++].index = MSR_IA32_TSC;
 432     msrs[n++].index = MSR_VM_HSAVE_PA;
 433 #ifdef TARGET_X86_64
 434     if (lm_capable_kernel) {
 435         msrs[n++].index = MSR_CSTAR;
 436         msrs[n++].index = MSR_KERNELGSBASE;
 437         msrs[n++].index = MSR_FMASK;
 438         msrs[n++].index = MSR_LSTAR;
 439     }
 440 #endif
 441     rc = kvm_get_msrs(kvm_context, env->cpu_index, msrs, n);
 442     if (rc == -1) {
 443         perror("kvm_get_msrs FAILED");
 444     }
 445     else {
 446         n = rc; /* actual number of MSRs */
 447         for (i=0 ; i<n; i++) {
 448             if (get_msr_entry(&msrs[i], env))
 449                 return;
 450         }
 451     }
 452 }
 453
 454 static void host_cpuid(uint32_t function, uint32_t *eax, uint32_t *ebx,
 455                        uint32_t *ecx, uint32_t *edx)
 456 {
 457     uint32_t vec[4];
 458
 459 #ifdef __x86_64__
 460     asm volatile("cpuid"
 461                  : "=a"(vec[0]), "=b"(vec[1]),
 462                    "=c"(vec[2]), "=d"(vec[3])
 463                  : "0"(function) : "cc");
 464 #else
 465     asm volatile("pusha \n\t"
 466                  "cpuid \n\t"
 467                  "mov %%eax, 0(%1) \n\t"
 468                  "mov %%ebx, 4(%1) \n\t"
 469                  "mov %%ecx, 8(%1) \n\t"
 470                  "mov %%edx, 12(%1) \n\t"
 471                  "popa"
 472                  : : "a"(function), "S"(vec)
 473                  : "memory", "cc");
 474 #endif
 475
 476     if (eax)
 477         *eax = vec[0];
 478     if (ebx)
 479         *ebx = vec[1];
 480     if (ecx)
 481         *ecx = vec[2];
 482     if (edx)
 483         *edx = vec[3];
 484 }
 485
 486
 487 static void do_cpuid_ent(struct kvm_cpuid_entry *e, uint32_t function,
 488                          CPUState *env)
 489 {
 490     env->regs[R_EAX] = function;
 491     qemu_kvm_cpuid_on_env(env);
 492     e->function = function;
 493     e->eax = env->regs[R_EAX];
 494     e->ebx = env->regs[R_EBX];
 495     e->ecx = env->regs[R_ECX];
 496     e->edx = env->regs[R_EDX];
 497     if (function == 0x80000001) {
 498         uint32_t h_eax, h_edx;
 499
 500         host_cpuid(function, &h_eax, NULL, NULL, &h_edx);
 501
 502         // long mode
 503         if ((h_edx & 0x20000000) == 0 || !lm_capable_kernel)
 504             e->edx &= ~0x20000000u;
 505         // syscall
 506         if ((h_edx & 0x00000800) == 0)
 507             e->edx &= ~0x00000800u;
 508         // nx
 509         if ((h_edx & 0x00100000) == 0)
 510             e->edx &= ~0x00100000u;
 511         // svm
 512         if (!kvm_nested && (e->ecx & 4))
 513             e->ecx &= ~4u;
 514     }
 515     // sysenter isn't supported on compatibility mode on AMD.  and syscall
 516     // isn't supported in compatibility mode on Intel.  so advertise the
 517     // actuall cpu, and say goodbye to migration between different vendors
 518     // is you use compatibility mode.
 519     if (function == 0) {
 520         uint32_t bcd[3];
 521
 522         host_cpuid(0, NULL, &bcd[0], &bcd[1], &bcd[2]);
 523         e->ebx = bcd[0];
 524         e->ecx = bcd[1];
 525         e->edx = bcd[2];
 526     }
 527     // "Hypervisor present" bit for Microsoft guests
 528     if (function == 1)
 529         e->ecx |= (1u << 31);
 530
 531     // 3dnow isn't properly emulated yet
 532     if (function == 0x80000001)
 533         e->edx &= ~0xc0000000;
 534 }
 535
 536 struct kvm_para_features {
 537         int cap;
 538         int feature;
 539 } para_features[] = {
 540 #ifdef KVM_CAP_CLOCKSOURCE
 541         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 542 #endif
 543 #ifdef KVM_CAP_NOP_IO_DELAY
 544         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 545 #endif
 546 #ifdef KVM_CAP_PV_MMU
 547         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 548 #endif
 549 #ifdef KVM_CAP_CR3_CACHE
 550         { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
 551 #endif
 552         { -1, -1 }
 553 };
 554
 555 static int get_para_features(kvm_context_t kvm_context)
 556 {
 557         int i, features = 0;
 558
 559         for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
 560                 if (kvm_check_extension(kvm_context, para_features[i].cap))
 561                         features |= (1 << para_features[i].feature);
 562         }
 563
 564         return features;
 565 }
 566
 567 int kvm_arch_qemu_init_env(CPUState *cenv)
 568 {
 569     struct kvm_cpuid_entry cpuid_ent[100];
 570 #ifdef KVM_CPUID_SIGNATURE
 571     struct kvm_cpuid_entry *pv_ent;
 572     uint32_t signature[3];
 573 #endif
 574     int cpuid_nent = 0;
 575     CPUState copy;
 576     uint32_t i, limit;
 577
 578     copy = *cenv;
 579
 580 #ifdef KVM_CPUID_SIGNATURE
 581     /* Paravirtualization CPUIDs */
 582     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 583     pv_ent = &cpuid_ent[cpuid_nent++];
 584     memset(pv_ent, 0, sizeof(*pv_ent));
 585     pv_ent->function = KVM_CPUID_SIGNATURE;
 586     pv_ent->eax = 0;
 587     pv_ent->ebx = signature[0];
 588     pv_ent->ecx = signature[1];
 589     pv_ent->edx = signature[2];
 590
 591     pv_ent = &cpuid_ent[cpuid_nent++];
 592     memset(pv_ent, 0, sizeof(*pv_ent));
 593     pv_ent->function = KVM_CPUID_FEATURES;
 594     pv_ent->eax = get_para_features(kvm_context);
 595 #endif
 596
 597     copy.regs[R_EAX] = 0;
 598     qemu_kvm_cpuid_on_env(&copy);
 599     limit = copy.regs[R_EAX];
 600
 601     for (i = 0; i <= limit; ++i)
 602         do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, &copy);
 603
 604     copy.regs[R_EAX] = 0x80000000;
 605     qemu_kvm_cpuid_on_env(&copy);
 606     limit = copy.regs[R_EAX];
 607
 608     for (i = 0x80000000; i <= limit; ++i)
 609         do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, &copy);
 610
 611     kvm_setup_cpuid(kvm_context, cenv->cpu_index, cpuid_nent, cpuid_ent);
 612     return 0;
 613 }
 614
 615 int kvm_arch_halt(void *opaque, int vcpu)
 616 {
 617     CPUState *env = cpu_single_env;
 618
 619     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 620           (env->eflags & IF_MASK)) &&
 621         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 622             env->halted = 1;
 623             env->exception_index = EXCP_HLT;
 624     }
 625     return 1;
 626 }
 627
 628 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
 629 {
 630     if (!kvm_irqchip_in_kernel(kvm_context))
 631         kvm_set_cr8(kvm_context, env->cpu_index, cpu_get_apic_tpr(env));
 632 }
 633
 634 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
 635 {
 636     int vcpu = env->cpu_index;
 637
 638     cpu_single_env = env;
 639
 640     env->eflags = kvm_get_interrupt_flag(kvm_context, vcpu)
 641         ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
 642
 643     cpu_set_apic_tpr(env, kvm_get_cr8(kvm_context, vcpu));
 644     cpu_set_apic_base(env, kvm_get_apic_base(kvm_context, vcpu));
 645 }
 646
 647 int kvm_arch_has_work(CPUState *env)
 648 {
 649     if (((env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT)) &&
 650          (env->eflags & IF_MASK)) ||
 651         (env->interrupt_request & CPU_INTERRUPT_NMI))
 652         return 1;
 653     return 0;
 654 }
 655
 656 int kvm_arch_try_push_interrupts(void *opaque)
 657 {
 658     CPUState *env = cpu_single_env;
 659     int r, irq;
 660
 661     if (kvm_is_ready_for_interrupt_injection(kvm_context, env->cpu_index) &&
 662         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 663         (env->eflags & IF_MASK)) {
 664             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 665             irq = cpu_get_pic_interrupt(env);
 666             if (irq >= 0) {
 667                 r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
 668                 if (r < 0)
 669                     printf("cpu %d fail inject %x\n", env->cpu_index, irq);
 670             }
 671     }
 672
 673     return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
 674 }
 675
 676 #ifdef KVM_CAP_USER_NMI
 677 void kvm_arch_push_nmi(void *opaque)
 678 {
 679     CPUState *env = cpu_single_env;
 680     int r;
 681
 682     if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
 683         return;
 684
 685     env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 686     r = kvm_inject_nmi(kvm_context, env->cpu_index);
 687     if (r < 0)
 688         printf("cpu %d fail inject NMI\n", env->cpu_index);
 689 }
 690 #endif /* KVM_CAP_USER_NMI */
 691
 692 void kvm_arch_update_regs_for_sipi(CPUState *env)
 693 {
 694     SegmentCache cs = env->segs[R_CS];
 695
 696     kvm_arch_save_regs(env);
 697     env->segs[R_CS] = cs;
 698     env->eip = 0;
 699     kvm_arch_load_regs(env);
 700 }
 701
 702 int handle_tpr_access(void *opaque, int vcpu,
 703                              uint64_t rip, int is_write)
 704 {
 705     kvm_tpr_access_report(cpu_single_env, rip, is_write);
 706     return 0;
 707 }
 708
 709 void kvm_arch_cpu_reset(CPUState *env)
 710 {
 711     kvm_arch_load_regs(env);
 712     if (env->cpu_index != 0) {
 713         if (kvm_irqchip_in_kernel(kvm_context)) {
 714 #ifdef KVM_CAP_MP_STATE
 715             kvm_reset_mpstate(kvm_context, env->cpu_index);
 716 #endif
 717         } else {
 718             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 719             env->halted = 1;
 720             env->exception_index = EXCP_HLT;
 721         }
 722     }
 723 }
 724
 725 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 726 {
 727     uint8_t int3 = 0xcc;
 728
 729     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 730         cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
 731         return -EINVAL;
 732     return 0;
 733 }
 734
 735 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 736 {
 737     uint8_t int3;
 738
 739     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 740         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 741         return -EINVAL;
 742     return 0;
 743 }
 744
 745 #ifdef KVM_CAP_SET_GUEST_DEBUG
 746 static struct {
 747     target_ulong addr;
 748     int len;
 749     int type;
 750 } hw_breakpoint[4];
 751
 752 static int nb_hw_breakpoint;
 753
 754 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 755 {
 756     int n;
 757
 758     for (n = 0; n < nb_hw_breakpoint; n++)
 759         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 760             (hw_breakpoint[n].len == len || len == -1))
 761             return n;
 762     return -1;
 763 }
 764
 765 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 766                                   target_ulong len, int type)
 767 {
 768     switch (type) {
 769     case GDB_BREAKPOINT_HW:
 770         len = 1;
 771         break;
 772     case GDB_WATCHPOINT_WRITE:
 773     case GDB_WATCHPOINT_ACCESS:
 774         switch (len) {
 775         case 1:
 776             break;
 777         case 2:
 778         case 4:
 779         case 8:
 780             if (addr & (len - 1))
 781                 return -EINVAL;
 782             break;
 783         default:
 784             return -EINVAL;
 785         }
 786         break;
 787     default:
 788         return -ENOSYS;
 789     }
 790
 791     if (nb_hw_breakpoint == 4)
 792         return -ENOBUFS;
 793
 794     if (find_hw_breakpoint(addr, len, type) >= 0)
 795         return -EEXIST;
 796
 797     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 798     hw_breakpoint[nb_hw_breakpoint].len = len;
 799     hw_breakpoint[nb_hw_breakpoint].type = type;
 800     nb_hw_breakpoint++;
 801
 802     return 0;
 803 }
 804
 805 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 806                                   target_ulong len, int type)
 807 {
 808     int n;
 809
 810     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
 811     if (n < 0)
 812         return -ENOENT;
 813
 814     nb_hw_breakpoint--;
 815     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
 816
 817     return 0;
 818 }
 819
 820 void kvm_arch_remove_all_hw_breakpoints(void)
 821 {
 822     nb_hw_breakpoint = 0;
 823 }
 824
 825 static CPUWatchpoint hw_watchpoint;
 826
 827 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
 828 {
 829     int handle = 0;
 830     int n;
 831
 832     if (arch_info->exception == 1) {
 833         if (arch_info->dr6 & (1 << 14)) {
 834             if (cpu_single_env->singlestep_enabled)
 835                 handle = 1;
 836         } else {
 837             for (n = 0; n < 4; n++)
 838                 if (arch_info->dr6 & (1 << n))
 839                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
 840                     case 0x0:
 841                         handle = 1;
 842                         break;
 843                     case 0x1:
 844                         handle = 1;
 845                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 846                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 847                         hw_watchpoint.flags = BP_MEM_WRITE;
 848                         break;
 849                     case 0x3:
 850                         handle = 1;
 851                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 852                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 853                         hw_watchpoint.flags = BP_MEM_ACCESS;
 854                         break;
 855                     }
 856         }
 857     } else if (kvm_find_sw_breakpoint(arch_info->pc))
 858         handle = 1;
 859
 860     if (!handle)
 861         kvm_update_guest_debug(cpu_single_env,
 862                         (arch_info->exception == 1) ?
 863                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
 864
 865     return handle;
 866 }
 867
 868 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
 869 {
 870     const uint8_t type_code[] = {
 871         [GDB_BREAKPOINT_HW] = 0x0,
 872         [GDB_WATCHPOINT_WRITE] = 0x1,
 873         [GDB_WATCHPOINT_ACCESS] = 0x3
 874     };
 875     const uint8_t len_code[] = {
 876         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
 877     };
 878     int n;
 879
 880     if (!TAILQ_EMPTY(&kvm_sw_breakpoints))
 881         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
 882
 883     if (nb_hw_breakpoint > 0) {
 884         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
 885         dbg->arch.debugreg[7] = 0x0600;
 886         for (n = 0; n < nb_hw_breakpoint; n++) {
 887             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
 888             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
 889                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
 890                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
 891         }
 892     }
 893 }
 894 #endif
 895
 896 void kvm_arch_do_ioperm(void *_data)
 897 {
 898     struct ioperm_data *data = _data;
 899     ioperm(data->start_port, data->num, data->turn_on);
 900 }