2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 #include "qemu-common.h"
35 //#define MIPS_DEBUG_DISAS
36 //#define MIPS_DEBUG_SIGN_EXTENSIONS
37 //#define MIPS_SINGLE_STEP
39 /* MIPS major opcodes */
40 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
43 /* indirect opcode tables */
44 OPC_SPECIAL
= (0x00 << 26),
45 OPC_REGIMM
= (0x01 << 26),
46 OPC_CP0
= (0x10 << 26),
47 OPC_CP1
= (0x11 << 26),
48 OPC_CP2
= (0x12 << 26),
49 OPC_CP3
= (0x13 << 26),
50 OPC_SPECIAL2
= (0x1C << 26),
51 OPC_SPECIAL3
= (0x1F << 26),
52 /* arithmetic with immediate */
53 OPC_ADDI
= (0x08 << 26),
54 OPC_ADDIU
= (0x09 << 26),
55 OPC_SLTI
= (0x0A << 26),
56 OPC_SLTIU
= (0x0B << 26),
57 OPC_ANDI
= (0x0C << 26),
58 OPC_ORI
= (0x0D << 26),
59 OPC_XORI
= (0x0E << 26),
60 OPC_LUI
= (0x0F << 26),
61 OPC_DADDI
= (0x18 << 26),
62 OPC_DADDIU
= (0x19 << 26),
63 /* Jump and branches */
65 OPC_JAL
= (0x03 << 26),
66 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
67 OPC_BEQL
= (0x14 << 26),
68 OPC_BNE
= (0x05 << 26),
69 OPC_BNEL
= (0x15 << 26),
70 OPC_BLEZ
= (0x06 << 26),
71 OPC_BLEZL
= (0x16 << 26),
72 OPC_BGTZ
= (0x07 << 26),
73 OPC_BGTZL
= (0x17 << 26),
74 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
76 OPC_LDL
= (0x1A << 26),
77 OPC_LDR
= (0x1B << 26),
78 OPC_LB
= (0x20 << 26),
79 OPC_LH
= (0x21 << 26),
80 OPC_LWL
= (0x22 << 26),
81 OPC_LW
= (0x23 << 26),
82 OPC_LBU
= (0x24 << 26),
83 OPC_LHU
= (0x25 << 26),
84 OPC_LWR
= (0x26 << 26),
85 OPC_LWU
= (0x27 << 26),
86 OPC_SB
= (0x28 << 26),
87 OPC_SH
= (0x29 << 26),
88 OPC_SWL
= (0x2A << 26),
89 OPC_SW
= (0x2B << 26),
90 OPC_SDL
= (0x2C << 26),
91 OPC_SDR
= (0x2D << 26),
92 OPC_SWR
= (0x2E << 26),
93 OPC_LL
= (0x30 << 26),
94 OPC_LLD
= (0x34 << 26),
95 OPC_LD
= (0x37 << 26),
96 OPC_SC
= (0x38 << 26),
97 OPC_SCD
= (0x3C << 26),
98 OPC_SD
= (0x3F << 26),
99 /* Floating point load/store */
100 OPC_LWC1
= (0x31 << 26),
101 OPC_LWC2
= (0x32 << 26),
102 OPC_LDC1
= (0x35 << 26),
103 OPC_LDC2
= (0x36 << 26),
104 OPC_SWC1
= (0x39 << 26),
105 OPC_SWC2
= (0x3A << 26),
106 OPC_SDC1
= (0x3D << 26),
107 OPC_SDC2
= (0x3E << 26),
108 /* MDMX ASE specific */
109 OPC_MDMX
= (0x1E << 26),
110 /* Cache and prefetch */
111 OPC_CACHE
= (0x2F << 26),
112 OPC_PREF
= (0x33 << 26),
113 /* Reserved major opcode */
114 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
117 /* MIPS special opcodes */
118 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
122 OPC_SLL
= 0x00 | OPC_SPECIAL
,
123 /* NOP is SLL r0, r0, 0 */
124 /* SSNOP is SLL r0, r0, 1 */
125 /* EHB is SLL r0, r0, 3 */
126 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
127 OPC_SRA
= 0x03 | OPC_SPECIAL
,
128 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
129 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
130 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
131 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
132 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
133 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
134 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
135 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
136 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
137 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
138 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
139 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
140 /* Multiplication / division */
141 OPC_MULT
= 0x18 | OPC_SPECIAL
,
142 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
143 OPC_DIV
= 0x1A | OPC_SPECIAL
,
144 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
145 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
146 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
147 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
148 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
149 /* 2 registers arithmetic / logic */
150 OPC_ADD
= 0x20 | OPC_SPECIAL
,
151 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
152 OPC_SUB
= 0x22 | OPC_SPECIAL
,
153 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
154 OPC_AND
= 0x24 | OPC_SPECIAL
,
155 OPC_OR
= 0x25 | OPC_SPECIAL
,
156 OPC_XOR
= 0x26 | OPC_SPECIAL
,
157 OPC_NOR
= 0x27 | OPC_SPECIAL
,
158 OPC_SLT
= 0x2A | OPC_SPECIAL
,
159 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
160 OPC_DADD
= 0x2C | OPC_SPECIAL
,
161 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
162 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
163 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
165 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
166 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
168 OPC_TGE
= 0x30 | OPC_SPECIAL
,
169 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
170 OPC_TLT
= 0x32 | OPC_SPECIAL
,
171 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
172 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
173 OPC_TNE
= 0x36 | OPC_SPECIAL
,
174 /* HI / LO registers load & stores */
175 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
176 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
177 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
178 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
179 /* Conditional moves */
180 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
181 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
183 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
186 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
187 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
188 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
189 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
190 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
192 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
193 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
194 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
195 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
196 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
197 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
198 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
201 /* Multiplication variants of the vr54xx. */
202 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
205 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
206 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
207 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
208 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
209 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
210 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
211 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
212 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
213 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
214 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
215 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
216 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
217 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
218 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
221 /* REGIMM (rt field) opcodes */
222 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
225 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
226 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
227 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
228 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
229 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
230 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
231 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
232 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
233 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
234 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
235 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
236 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
237 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
238 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
239 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
242 /* Special2 opcodes */
243 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
246 /* Multiply & xxx operations */
247 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
248 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
249 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
250 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
251 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
253 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
254 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
255 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
256 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
258 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
261 /* Special3 opcodes */
262 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
265 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
266 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
267 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
268 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
269 OPC_INS
= 0x04 | OPC_SPECIAL3
,
270 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
271 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
272 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
273 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
274 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
275 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
276 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
277 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
281 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
284 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
285 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
286 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
290 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
293 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
294 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
297 /* Coprocessor 0 (rs field) */
298 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
301 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
302 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
303 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
304 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
305 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
306 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
307 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
308 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
309 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
310 OPC_C0
= (0x10 << 21) | OPC_CP0
,
311 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
312 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
316 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
319 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
320 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
321 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
322 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
323 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
324 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
327 /* Coprocessor 0 (with rs == C0) */
328 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
331 OPC_TLBR
= 0x01 | OPC_C0
,
332 OPC_TLBWI
= 0x02 | OPC_C0
,
333 OPC_TLBWR
= 0x06 | OPC_C0
,
334 OPC_TLBP
= 0x08 | OPC_C0
,
335 OPC_RFE
= 0x10 | OPC_C0
,
336 OPC_ERET
= 0x18 | OPC_C0
,
337 OPC_DERET
= 0x1F | OPC_C0
,
338 OPC_WAIT
= 0x20 | OPC_C0
,
341 /* Coprocessor 1 (rs field) */
342 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
345 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
346 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
347 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
348 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
349 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
350 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
351 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
352 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
353 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
354 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
355 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
356 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
357 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
358 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
359 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
360 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
361 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
362 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
365 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
366 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
369 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
370 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
371 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
372 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
376 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
377 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
381 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
382 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
385 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
388 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
389 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
390 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
391 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
392 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
393 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
394 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
395 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
396 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
399 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
402 OPC_LWXC1
= 0x00 | OPC_CP3
,
403 OPC_LDXC1
= 0x01 | OPC_CP3
,
404 OPC_LUXC1
= 0x05 | OPC_CP3
,
405 OPC_SWXC1
= 0x08 | OPC_CP3
,
406 OPC_SDXC1
= 0x09 | OPC_CP3
,
407 OPC_SUXC1
= 0x0D | OPC_CP3
,
408 OPC_PREFX
= 0x0F | OPC_CP3
,
409 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
410 OPC_MADD_S
= 0x20 | OPC_CP3
,
411 OPC_MADD_D
= 0x21 | OPC_CP3
,
412 OPC_MADD_PS
= 0x26 | OPC_CP3
,
413 OPC_MSUB_S
= 0x28 | OPC_CP3
,
414 OPC_MSUB_D
= 0x29 | OPC_CP3
,
415 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
416 OPC_NMADD_S
= 0x30 | OPC_CP3
,
417 OPC_NMADD_D
= 0x31 | OPC_CP3
,
418 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
419 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
420 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
421 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
424 /* global register indices */
425 static TCGv cpu_env
, current_tc_gprs
, cpu_T
[2];
427 /* The code generator doesn't like lots of temporaries, so maintain our own
428 cache for reuse within a function. */
430 static int num_temps
;
431 static TCGv temps
[MAX_TEMPS
];
433 /* Allocate a temporary variable. */
434 static TCGv
new_tmp(void)
437 if (num_temps
== MAX_TEMPS
)
440 if (GET_TCGV(temps
[num_temps
]))
441 return temps
[num_temps
++];
443 tmp
= tcg_temp_new(TCG_TYPE_I32
);
444 temps
[num_temps
++] = tmp
;
448 /* Release a temporary variable. */
449 static void dead_tmp(TCGv tmp
)
454 if (GET_TCGV(temps
[i
]) == GET_TCGV(tmp
))
457 /* Shuffle this temp to the last slot. */
458 while (GET_TCGV(temps
[i
]) != GET_TCGV(tmp
))
460 while (i
< num_temps
) {
461 temps
[i
] = temps
[i
+ 1];
467 /* General purpose registers moves */
468 const unsigned char *regnames
[] =
469 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
470 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
472 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
474 static inline void gen_op_load_gpr_TN(int t_index
, int reg
)
476 tcg_gen_ld_tl(cpu_T
[t_index
], current_tc_gprs
, sizeof(target_ulong
) * reg
);
479 static inline void gen_op_load_gpr_T0(int reg
)
481 gen_op_load_gpr_TN(0, reg
);
484 static inline void gen_op_load_gpr_T1(int reg
)
486 gen_op_load_gpr_TN(1, reg
);
489 static inline void gen_op_store_gpr_TN(int t_index
, int reg
)
491 tcg_gen_st_tl(cpu_T
[t_index
], current_tc_gprs
, sizeof(target_ulong
) * reg
);
494 static inline void gen_op_store_gpr_T0(int reg
)
496 gen_op_store_gpr_TN(0, reg
);
499 static inline void gen_op_store_gpr_T1(int reg
)
501 gen_op_store_gpr_TN(1, reg
);
504 /* Moves to/from shadow registers */
505 static inline void gen_op_load_srsgpr_T0(int reg
)
507 int r_tmp
= new_tmp();
509 tcg_gen_ld_i32(r_tmp
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
510 tcg_gen_shri_i32(r_tmp
, r_tmp
, CP0SRSCtl_PSS
);
511 tcg_gen_andi_i32(r_tmp
, r_tmp
, 0xf);
512 tcg_gen_muli_i32(r_tmp
, r_tmp
, sizeof(target_ulong
) * 32);
513 tcg_gen_add_i32(r_tmp
, cpu_env
, r_tmp
);
515 tcg_gen_ld_tl(cpu_T
[0], r_tmp
, sizeof(target_ulong
) * reg
);
519 static inline void gen_op_store_srsgpr_T0(int reg
)
521 int r_tmp
= new_tmp();
523 tcg_gen_ld_i32(r_tmp
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
524 tcg_gen_shri_i32(r_tmp
, r_tmp
, CP0SRSCtl_PSS
);
525 tcg_gen_andi_i32(r_tmp
, r_tmp
, 0xf);
526 tcg_gen_muli_i32(r_tmp
, r_tmp
, sizeof(target_ulong
) * 32);
527 tcg_gen_add_i32(r_tmp
, cpu_env
, r_tmp
);
529 tcg_gen_st_tl(cpu_T
[0], r_tmp
, sizeof(target_ulong
) * reg
);
533 /* Load immediates, zero being a special case. */
534 static inline void gen_op_set_T0(target_ulong arg
)
536 tcg_gen_movi_tl(cpu_T
[0], arg
);
539 static inline void gen_op_set_T1(target_ulong arg
)
541 tcg_gen_movi_tl(cpu_T
[1], arg
);
544 static inline void gen_op_reset_T0(void)
546 tcg_gen_movi_tl(cpu_T
[0], 0);
549 static inline void gen_op_reset_T1(void)
551 tcg_gen_movi_tl(cpu_T
[1], 0);
554 /* Moves to/from HI/LO registers. */
555 static inline void gen_op_load_HI(int reg
)
557 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, HI
[reg
]));
560 static inline void gen_op_store_HI(int reg
)
562 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, HI
[reg
]));
565 static inline void gen_op_load_LO(int reg
)
567 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, LO
[reg
]));
570 static inline void gen_op_store_LO(int reg
)
572 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, LO
[reg
]));
576 /* Floating point register moves. */
577 static const char *fregnames
[] =
578 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
579 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
580 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
581 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
583 #define FGEN32(func, NAME) \
584 static GenOpFunc *NAME ## _table [32] = { \
585 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
586 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
587 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
588 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
589 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
590 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
591 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
592 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
594 static always_inline void func(int n) \
596 NAME ## _table[n](); \
599 FGEN32(gen_op_load_fpr_WT0
, gen_op_load_fpr_WT0_fpr
);
600 FGEN32(gen_op_store_fpr_WT0
, gen_op_store_fpr_WT0_fpr
);
602 FGEN32(gen_op_load_fpr_WT1
, gen_op_load_fpr_WT1_fpr
);
603 FGEN32(gen_op_store_fpr_WT1
, gen_op_store_fpr_WT1_fpr
);
605 FGEN32(gen_op_load_fpr_WT2
, gen_op_load_fpr_WT2_fpr
);
606 FGEN32(gen_op_store_fpr_WT2
, gen_op_store_fpr_WT2_fpr
);
608 FGEN32(gen_op_load_fpr_DT0
, gen_op_load_fpr_DT0_fpr
);
609 FGEN32(gen_op_store_fpr_DT0
, gen_op_store_fpr_DT0_fpr
);
611 FGEN32(gen_op_load_fpr_DT1
, gen_op_load_fpr_DT1_fpr
);
612 FGEN32(gen_op_store_fpr_DT1
, gen_op_store_fpr_DT1_fpr
);
614 FGEN32(gen_op_load_fpr_DT2
, gen_op_load_fpr_DT2_fpr
);
615 FGEN32(gen_op_store_fpr_DT2
, gen_op_store_fpr_DT2_fpr
);
617 FGEN32(gen_op_load_fpr_WTH0
, gen_op_load_fpr_WTH0_fpr
);
618 FGEN32(gen_op_store_fpr_WTH0
, gen_op_store_fpr_WTH0_fpr
);
620 FGEN32(gen_op_load_fpr_WTH1
, gen_op_load_fpr_WTH1_fpr
);
621 FGEN32(gen_op_store_fpr_WTH1
, gen_op_store_fpr_WTH1_fpr
);
623 FGEN32(gen_op_load_fpr_WTH2
, gen_op_load_fpr_WTH2_fpr
);
624 FGEN32(gen_op_store_fpr_WTH2
, gen_op_store_fpr_WTH2_fpr
);
626 #define FOP_CONDS(type, fmt) \
627 static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
628 gen_op_cmp ## type ## _ ## fmt ## _f, \
629 gen_op_cmp ## type ## _ ## fmt ## _un, \
630 gen_op_cmp ## type ## _ ## fmt ## _eq, \
631 gen_op_cmp ## type ## _ ## fmt ## _ueq, \
632 gen_op_cmp ## type ## _ ## fmt ## _olt, \
633 gen_op_cmp ## type ## _ ## fmt ## _ult, \
634 gen_op_cmp ## type ## _ ## fmt ## _ole, \
635 gen_op_cmp ## type ## _ ## fmt ## _ule, \
636 gen_op_cmp ## type ## _ ## fmt ## _sf, \
637 gen_op_cmp ## type ## _ ## fmt ## _ngle, \
638 gen_op_cmp ## type ## _ ## fmt ## _seq, \
639 gen_op_cmp ## type ## _ ## fmt ## _ngl, \
640 gen_op_cmp ## type ## _ ## fmt ## _lt, \
641 gen_op_cmp ## type ## _ ## fmt ## _nge, \
642 gen_op_cmp ## type ## _ ## fmt ## _le, \
643 gen_op_cmp ## type ## _ ## fmt ## _ngt, \
645 static always_inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
647 gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
657 typedef struct DisasContext
{
658 struct TranslationBlock
*tb
;
659 target_ulong pc
, saved_pc
;
662 /* Routine used to access memory */
664 uint32_t hflags
, saved_hflags
;
666 target_ulong btarget
;
672 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
673 * exception condition
675 BS_STOP
= 1, /* We want to stop translation for any reason */
676 BS_BRANCH
= 2, /* We reached a branch condition */
677 BS_EXCP
= 3, /* We reached an exception condition */
680 #ifdef MIPS_DEBUG_DISAS
681 #define MIPS_DEBUG(fmt, args...) \
683 if (loglevel & CPU_LOG_TB_IN_ASM) { \
684 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
685 ctx->pc, ctx->opcode , ##args); \
689 #define MIPS_DEBUG(fmt, args...) do { } while(0)
692 #define MIPS_INVAL(op) \
694 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
695 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
698 #define GEN_LOAD_REG_T0(Rn) \
703 if (ctx->glue(last_T0, _store) != gen_opc_ptr \
704 || ctx->glue(last_T0, _gpr) != Rn) { \
705 gen_op_load_gpr_T0(Rn); \
710 #define GEN_LOAD_REG_T1(Rn) \
715 gen_op_load_gpr_T1(Rn); \
719 #define GEN_LOAD_SRSREG_TN(Tn, Rn) \
722 glue(gen_op_reset_, Tn)(); \
724 glue(gen_op_load_srsgpr_, Tn)(Rn); \
728 #define GEN_LOAD_IMM_TN(Tn, Imm) \
731 glue(gen_op_reset_, Tn)(); \
733 glue(gen_op_set_, Tn)(Imm); \
737 #define GEN_STORE_T0_REG(Rn) \
740 gen_op_store_gpr_T0(Rn); \
741 ctx->glue(last_T0,_store) = gen_opc_ptr; \
742 ctx->glue(last_T0,_gpr) = Rn; \
746 #define GEN_STORE_T1_REG(Rn) \
749 gen_op_store_gpr_T1(Rn); \
752 #define GEN_STORE_TN_SRSREG(Rn, Tn) \
755 glue(gen_op_store_srsgpr_, Tn)(Rn); \
758 #define GEN_LOAD_FREG_FTN(FTn, Fn) \
760 glue(gen_op_load_fpr_, FTn)(Fn); \
763 #define GEN_STORE_FTN_FREG(Fn, FTn) \
765 glue(gen_op_store_fpr_, FTn)(Fn); \
768 static always_inline
void gen_save_pc(target_ulong pc
)
770 #if defined(TARGET_MIPS64)
771 if (pc
== (int32_t)pc
) {
774 gen_op_save_pc64(pc
>> 32, (uint32_t)pc
);
781 static always_inline
void gen_save_btarget(target_ulong btarget
)
783 #if defined(TARGET_MIPS64)
784 if (btarget
== (int32_t)btarget
) {
785 gen_op_save_btarget(btarget
);
787 gen_op_save_btarget64(btarget
>> 32, (uint32_t)btarget
);
790 gen_op_save_btarget(btarget
);
794 static always_inline
void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
796 #if defined MIPS_DEBUG_DISAS
797 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
798 fprintf(logfile
, "hflags %08x saved %08x\n",
799 ctx
->hflags
, ctx
->saved_hflags
);
802 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
803 gen_save_pc(ctx
->pc
);
804 ctx
->saved_pc
= ctx
->pc
;
806 if (ctx
->hflags
!= ctx
->saved_hflags
) {
807 gen_op_save_state(ctx
->hflags
);
808 ctx
->saved_hflags
= ctx
->hflags
;
809 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
815 gen_save_btarget(ctx
->btarget
);
821 static always_inline
void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
823 ctx
->saved_hflags
= ctx
->hflags
;
824 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
830 ctx
->btarget
= env
->btarget
;
835 static always_inline
void
836 generate_tcg_exception_err (DisasContext
*ctx
, int excp
, int err
)
838 save_cpu_state(ctx
, 1);
840 gen_op_raise_exception(excp
);
842 gen_op_raise_exception_err(excp
, err
);
843 gen_op_interrupt_restart();
847 static always_inline
void
848 generate_tcg_exception (DisasContext
*ctx
, int excp
)
850 generate_tcg_exception_err (ctx
, excp
, 0);
853 static always_inline
void generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
855 #if defined MIPS_DEBUG_DISAS
856 if (loglevel
& CPU_LOG_TB_IN_ASM
)
857 fprintf(logfile
, "%s: raise exception %d\n", __func__
, excp
);
859 save_cpu_state(ctx
, 1);
861 gen_op_raise_exception(excp
);
863 gen_op_raise_exception_err(excp
, err
);
864 ctx
->bstate
= BS_EXCP
;
867 static always_inline
void generate_exception (DisasContext
*ctx
, int excp
)
869 generate_exception_err (ctx
, excp
, 0);
872 static always_inline
void check_cp0_enabled(DisasContext
*ctx
)
874 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
875 generate_exception_err(ctx
, EXCP_CpU
, 1);
878 static always_inline
void check_cp1_enabled(DisasContext
*ctx
)
880 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
881 generate_exception_err(ctx
, EXCP_CpU
, 1);
884 /* Verify that the processor is running with COP1X instructions enabled.
885 This is associated with the nabla symbol in the MIPS32 and MIPS64
888 static always_inline
void check_cop1x(DisasContext
*ctx
)
890 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
891 generate_exception(ctx
, EXCP_RI
);
894 /* Verify that the processor is running with 64-bit floating-point
895 operations enabled. */
897 static always_inline
void check_cp1_64bitmode(DisasContext
*ctx
)
899 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
900 generate_exception(ctx
, EXCP_RI
);
904 * Verify if floating point register is valid; an operation is not defined
905 * if bit 0 of any register specification is set and the FR bit in the
906 * Status register equals zero, since the register numbers specify an
907 * even-odd pair of adjacent coprocessor general registers. When the FR bit
908 * in the Status register equals one, both even and odd register numbers
909 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
911 * Multiple 64 bit wide registers can be checked by calling
912 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
914 void check_cp1_registers(DisasContext
*ctx
, int regs
)
916 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
917 generate_exception(ctx
, EXCP_RI
);
920 /* This code generates a "reserved instruction" exception if the
921 CPU does not support the instruction set corresponding to flags. */
922 static always_inline
void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
924 if (unlikely(!(env
->insn_flags
& flags
)))
925 generate_exception(ctx
, EXCP_RI
);
928 /* This code generates a "reserved instruction" exception if 64-bit
929 instructions are not enabled. */
930 static always_inline
void check_mips_64(DisasContext
*ctx
)
932 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
933 generate_exception(ctx
, EXCP_RI
);
936 /* load/store instructions. */
937 #if defined(CONFIG_USER_ONLY)
938 #define op_ldst(name) gen_op_##name##_raw()
939 #define OP_LD_TABLE(width)
940 #define OP_ST_TABLE(width)
942 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
943 #define OP_LD_TABLE(width) \
944 static GenOpFunc *gen_op_l##width[] = { \
945 &gen_op_l##width##_kernel, \
946 &gen_op_l##width##_super, \
947 &gen_op_l##width##_user, \
949 #define OP_ST_TABLE(width) \
950 static GenOpFunc *gen_op_s##width[] = { \
951 &gen_op_s##width##_kernel, \
952 &gen_op_s##width##_super, \
953 &gen_op_s##width##_user, \
957 #if defined(TARGET_MIPS64)
974 #define OP_LD(insn,fname) \
975 void inline op_ldst_##insn(DisasContext *ctx) \
977 tcg_gen_qemu_##fname(cpu_T[0], cpu_T[0], ctx->mem_idx); \
984 #if defined(TARGET_MIPS64)
990 #define OP_ST(insn,fname) \
991 void inline op_ldst_##insn(DisasContext *ctx) \
993 tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx); \
998 #if defined(TARGET_MIPS64)
1003 #define OP_LD_ATOMIC(insn,fname) \
1004 void inline op_ldst_##insn(DisasContext *ctx) \
1006 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); \
1007 tcg_gen_qemu_##fname(cpu_T[0], cpu_T[0], ctx->mem_idx); \
1008 tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1010 OP_LD_ATOMIC(ll
,ld32s
);
1011 #if defined(TARGET_MIPS64)
1012 OP_LD_ATOMIC(lld
,ld64
);
1016 #define OP_ST_ATOMIC(insn,fname,almask) \
1017 void inline op_ldst_##insn(DisasContext *ctx) \
1019 int r_tmp = tcg_temp_new(TCG_TYPE_TL); \
1020 int l1 = gen_new_label(); \
1021 int l2 = gen_new_label(); \
1022 int l3 = gen_new_label(); \
1024 tcg_gen_andi_tl(r_tmp, cpu_T[0], almask); \
1025 tcg_gen_brcond_tl(TCG_COND_EQ, r_tmp, tcg_const_tl(0), l1); \
1026 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
1027 generate_tcg_exception(ctx, EXCP_AdES); \
1028 gen_set_label(l1); \
1029 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1030 tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], r_tmp, l2); \
1031 tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx); \
1032 tcg_gen_movi_tl(cpu_T[0], 1); \
1034 gen_set_label(l2); \
1035 tcg_gen_movi_tl(cpu_T[0], 0); \
1036 gen_set_label(l3); \
1038 OP_ST_ATOMIC(sc
,st32
,0x3);
1039 #if defined(TARGET_MIPS64)
1040 OP_ST_ATOMIC(scd
,st64
,0x7);
1044 void inline op_ldst_lwc1(DisasContext
*ctx
)
1049 void inline op_ldst_ldc1(DisasContext
*ctx
)
1054 void inline op_ldst_swc1(DisasContext
*ctx
)
1059 void inline op_ldst_sdc1(DisasContext
*ctx
)
1064 /* Load and store */
1065 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
1066 int base
, int16_t offset
)
1068 const char *opn
= "ldst";
1071 GEN_LOAD_IMM_TN(T0
, offset
);
1072 } else if (offset
== 0) {
1073 gen_op_load_gpr_T0(base
);
1075 gen_op_load_gpr_T0(base
);
1076 gen_op_set_T1(offset
);
1079 /* Don't do NOP if destination is zero: we must perform the actual
1082 #if defined(TARGET_MIPS64)
1085 GEN_STORE_T0_REG(rt
);
1090 GEN_STORE_T0_REG(rt
);
1095 GEN_STORE_T0_REG(rt
);
1099 GEN_LOAD_REG_T1(rt
);
1104 save_cpu_state(ctx
, 1);
1105 GEN_LOAD_REG_T1(rt
);
1107 GEN_STORE_T0_REG(rt
);
1111 GEN_LOAD_REG_T1(rt
);
1113 GEN_STORE_T1_REG(rt
);
1117 GEN_LOAD_REG_T1(rt
);
1122 GEN_LOAD_REG_T1(rt
);
1124 GEN_STORE_T1_REG(rt
);
1128 GEN_LOAD_REG_T1(rt
);
1135 GEN_STORE_T0_REG(rt
);
1139 GEN_LOAD_REG_T1(rt
);
1145 GEN_STORE_T0_REG(rt
);
1149 GEN_LOAD_REG_T1(rt
);
1155 GEN_STORE_T0_REG(rt
);
1160 GEN_STORE_T0_REG(rt
);
1164 GEN_LOAD_REG_T1(rt
);
1170 GEN_STORE_T0_REG(rt
);
1174 GEN_LOAD_REG_T1(rt
);
1176 GEN_STORE_T1_REG(rt
);
1180 GEN_LOAD_REG_T1(rt
);
1185 GEN_LOAD_REG_T1(rt
);
1187 GEN_STORE_T1_REG(rt
);
1191 GEN_LOAD_REG_T1(rt
);
1197 GEN_STORE_T0_REG(rt
);
1201 save_cpu_state(ctx
, 1);
1202 GEN_LOAD_REG_T1(rt
);
1204 GEN_STORE_T0_REG(rt
);
1209 generate_exception(ctx
, EXCP_RI
);
1212 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1215 /* Load and store */
1216 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1217 int base
, int16_t offset
)
1219 const char *opn
= "flt_ldst";
1222 GEN_LOAD_IMM_TN(T0
, offset
);
1223 } else if (offset
== 0) {
1224 gen_op_load_gpr_T0(base
);
1226 gen_op_load_gpr_T0(base
);
1227 gen_op_set_T1(offset
);
1230 /* Don't do NOP if destination is zero: we must perform the actual
1235 GEN_STORE_FTN_FREG(ft
, WT0
);
1239 GEN_LOAD_FREG_FTN(WT0
, ft
);
1245 GEN_STORE_FTN_FREG(ft
, DT0
);
1249 GEN_LOAD_FREG_FTN(DT0
, ft
);
1255 generate_exception(ctx
, EXCP_RI
);
1258 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1261 /* Arithmetic with immediate operand */
1262 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1263 int rt
, int rs
, int16_t imm
)
1266 const char *opn
= "imm arith";
1268 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1269 /* If no destination, treat it as a NOP.
1270 For addi, we must generate the overflow exception when needed. */
1274 uimm
= (uint16_t)imm
;
1278 #if defined(TARGET_MIPS64)
1284 uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1289 GEN_LOAD_REG_T0(rs
);
1290 GEN_LOAD_IMM_TN(T1
, uimm
);
1293 GEN_LOAD_IMM_TN(T0
, imm
<< 16);
1298 #if defined(TARGET_MIPS64)
1307 GEN_LOAD_REG_T0(rs
);
1308 GEN_LOAD_IMM_TN(T1
, uimm
);
1313 save_cpu_state(ctx
, 1);
1321 #if defined(TARGET_MIPS64)
1323 save_cpu_state(ctx
, 1);
1364 switch ((ctx
->opcode
>> 21) & 0x1f) {
1370 /* rotr is decoded as srl on non-R2 CPUs */
1371 if (env
->insn_flags
& ISA_MIPS32R2
) {
1380 MIPS_INVAL("invalid srl flag");
1381 generate_exception(ctx
, EXCP_RI
);
1385 #if defined(TARGET_MIPS64)
1395 switch ((ctx
->opcode
>> 21) & 0x1f) {
1401 /* drotr is decoded as dsrl on non-R2 CPUs */
1402 if (env
->insn_flags
& ISA_MIPS32R2
) {
1411 MIPS_INVAL("invalid dsrl flag");
1412 generate_exception(ctx
, EXCP_RI
);
1425 switch ((ctx
->opcode
>> 21) & 0x1f) {
1431 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1432 if (env
->insn_flags
& ISA_MIPS32R2
) {
1441 MIPS_INVAL("invalid dsrl32 flag");
1442 generate_exception(ctx
, EXCP_RI
);
1449 generate_exception(ctx
, EXCP_RI
);
1452 GEN_STORE_T0_REG(rt
);
1453 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1457 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1458 int rd
, int rs
, int rt
)
1460 const char *opn
= "arith";
1462 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1463 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1464 /* If no destination, treat it as a NOP.
1465 For add & sub, we must generate the overflow exception when needed. */
1469 GEN_LOAD_REG_T0(rs
);
1470 /* Specialcase the conventional move operation. */
1471 if (rt
== 0 && (opc
== OPC_ADDU
|| opc
== OPC_DADDU
1472 || opc
== OPC_SUBU
|| opc
== OPC_DSUBU
)) {
1473 GEN_STORE_T0_REG(rd
);
1476 GEN_LOAD_REG_T1(rt
);
1479 save_cpu_state(ctx
, 1);
1488 save_cpu_state(ctx
, 1);
1496 #if defined(TARGET_MIPS64)
1498 save_cpu_state(ctx
, 1);
1507 save_cpu_state(ctx
, 1);
1561 switch ((ctx
->opcode
>> 6) & 0x1f) {
1567 /* rotrv is decoded as srlv on non-R2 CPUs */
1568 if (env
->insn_flags
& ISA_MIPS32R2
) {
1577 MIPS_INVAL("invalid srlv flag");
1578 generate_exception(ctx
, EXCP_RI
);
1582 #if defined(TARGET_MIPS64)
1592 switch ((ctx
->opcode
>> 6) & 0x1f) {
1598 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1599 if (env
->insn_flags
& ISA_MIPS32R2
) {
1608 MIPS_INVAL("invalid dsrlv flag");
1609 generate_exception(ctx
, EXCP_RI
);
1616 generate_exception(ctx
, EXCP_RI
);
1619 GEN_STORE_T0_REG(rd
);
1621 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1624 /* Arithmetic on HI/LO registers */
1625 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1627 const char *opn
= "hilo";
1629 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1637 GEN_STORE_T0_REG(reg
);
1642 GEN_STORE_T0_REG(reg
);
1646 GEN_LOAD_REG_T0(reg
);
1651 GEN_LOAD_REG_T0(reg
);
1657 generate_exception(ctx
, EXCP_RI
);
1660 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1663 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1666 const char *opn
= "mul/div";
1668 GEN_LOAD_REG_T0(rs
);
1669 GEN_LOAD_REG_T1(rt
);
1687 #if defined(TARGET_MIPS64)
1723 generate_exception(ctx
, EXCP_RI
);
1726 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
1729 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
1730 int rd
, int rs
, int rt
)
1732 const char *opn
= "mul vr54xx";
1734 GEN_LOAD_REG_T0(rs
);
1735 GEN_LOAD_REG_T1(rt
);
1738 case OPC_VR54XX_MULS
:
1742 case OPC_VR54XX_MULSU
:
1746 case OPC_VR54XX_MACC
:
1750 case OPC_VR54XX_MACCU
:
1754 case OPC_VR54XX_MSAC
:
1758 case OPC_VR54XX_MSACU
:
1762 case OPC_VR54XX_MULHI
:
1766 case OPC_VR54XX_MULHIU
:
1770 case OPC_VR54XX_MULSHI
:
1774 case OPC_VR54XX_MULSHIU
:
1778 case OPC_VR54XX_MACCHI
:
1782 case OPC_VR54XX_MACCHIU
:
1786 case OPC_VR54XX_MSACHI
:
1790 case OPC_VR54XX_MSACHIU
:
1795 MIPS_INVAL("mul vr54xx");
1796 generate_exception(ctx
, EXCP_RI
);
1799 GEN_STORE_T0_REG(rd
);
1800 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1803 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
1806 const char *opn
= "CLx";
1812 GEN_LOAD_REG_T0(rs
);
1822 #if defined(TARGET_MIPS64)
1834 generate_exception(ctx
, EXCP_RI
);
1837 gen_op_store_gpr_T0(rd
);
1838 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
1842 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
1843 int rs
, int rt
, int16_t imm
)
1848 /* Load needed operands */
1856 /* Compare two registers */
1858 GEN_LOAD_REG_T0(rs
);
1859 GEN_LOAD_REG_T1(rt
);
1869 /* Compare register to immediate */
1870 if (rs
!= 0 || imm
!= 0) {
1871 GEN_LOAD_REG_T0(rs
);
1872 GEN_LOAD_IMM_TN(T1
, (int32_t)imm
);
1879 case OPC_TEQ
: /* rs == rs */
1880 case OPC_TEQI
: /* r0 == 0 */
1881 case OPC_TGE
: /* rs >= rs */
1882 case OPC_TGEI
: /* r0 >= 0 */
1883 case OPC_TGEU
: /* rs >= rs unsigned */
1884 case OPC_TGEIU
: /* r0 >= 0 unsigned */
1888 case OPC_TLT
: /* rs < rs */
1889 case OPC_TLTI
: /* r0 < 0 */
1890 case OPC_TLTU
: /* rs < rs unsigned */
1891 case OPC_TLTIU
: /* r0 < 0 unsigned */
1892 case OPC_TNE
: /* rs != rs */
1893 case OPC_TNEI
: /* r0 != 0 */
1894 /* Never trap: treat as NOP. */
1898 generate_exception(ctx
, EXCP_RI
);
1929 generate_exception(ctx
, EXCP_RI
);
1933 save_cpu_state(ctx
, 1);
1935 ctx
->bstate
= BS_STOP
;
1938 static always_inline
void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
1940 TranslationBlock
*tb
;
1942 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
1945 tcg_gen_exit_tb((long)tb
+ n
);
1952 static inline void tcg_gen_set_bcond(void)
1954 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, bcond
));
1957 static inline void tcg_gen_jnz_bcond(int label
)
1959 int r_tmp
= tcg_temp_new(TCG_TYPE_TL
);
1961 tcg_gen_ld_tl(r_tmp
, cpu_env
, offsetof(CPUState
, bcond
));
1962 tcg_gen_brcond_tl(TCG_COND_NE
, r_tmp
, tcg_const_tl(0), label
);
1965 /* Branches (before delay slot) */
1966 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
1967 int rs
, int rt
, int32_t offset
)
1969 target_ulong btarget
= -1;
1973 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
1974 #ifdef MIPS_DEBUG_DISAS
1975 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1977 "Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n",
1981 generate_exception(ctx
, EXCP_RI
);
1985 /* Load needed operands */
1991 /* Compare two registers */
1993 GEN_LOAD_REG_T0(rs
);
1994 GEN_LOAD_REG_T1(rt
);
1997 btarget
= ctx
->pc
+ 4 + offset
;
2011 /* Compare to zero */
2013 gen_op_load_gpr_T0(rs
);
2016 btarget
= ctx
->pc
+ 4 + offset
;
2020 /* Jump to immediate */
2021 btarget
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
2025 /* Jump to register */
2026 if (offset
!= 0 && offset
!= 16) {
2027 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2028 others are reserved. */
2029 MIPS_INVAL("jump hint");
2030 generate_exception(ctx
, EXCP_RI
);
2033 GEN_LOAD_REG_T1(rs
);
2034 gen_op_save_breg_target();
2037 MIPS_INVAL("branch/jump");
2038 generate_exception(ctx
, EXCP_RI
);
2042 /* No condition to be computed */
2044 case OPC_BEQ
: /* rx == rx */
2045 case OPC_BEQL
: /* rx == rx likely */
2046 case OPC_BGEZ
: /* 0 >= 0 */
2047 case OPC_BGEZL
: /* 0 >= 0 likely */
2048 case OPC_BLEZ
: /* 0 <= 0 */
2049 case OPC_BLEZL
: /* 0 <= 0 likely */
2051 ctx
->hflags
|= MIPS_HFLAG_B
;
2052 MIPS_DEBUG("balways");
2054 case OPC_BGEZAL
: /* 0 >= 0 */
2055 case OPC_BGEZALL
: /* 0 >= 0 likely */
2056 /* Always take and link */
2058 ctx
->hflags
|= MIPS_HFLAG_B
;
2059 MIPS_DEBUG("balways and link");
2061 case OPC_BNE
: /* rx != rx */
2062 case OPC_BGTZ
: /* 0 > 0 */
2063 case OPC_BLTZ
: /* 0 < 0 */
2065 MIPS_DEBUG("bnever (NOP)");
2067 case OPC_BLTZAL
: /* 0 < 0 */
2068 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
2069 gen_op_store_gpr_T0(31);
2070 MIPS_DEBUG("bnever and link");
2072 case OPC_BLTZALL
: /* 0 < 0 likely */
2073 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
2074 gen_op_store_gpr_T0(31);
2075 /* Skip the instruction in the delay slot */
2076 MIPS_DEBUG("bnever, link and skip");
2079 case OPC_BNEL
: /* rx != rx likely */
2080 case OPC_BGTZL
: /* 0 > 0 likely */
2081 case OPC_BLTZL
: /* 0 < 0 likely */
2082 /* Skip the instruction in the delay slot */
2083 MIPS_DEBUG("bnever and skip");
2087 ctx
->hflags
|= MIPS_HFLAG_B
;
2088 MIPS_DEBUG("j " TARGET_FMT_lx
, btarget
);
2092 ctx
->hflags
|= MIPS_HFLAG_B
;
2093 MIPS_DEBUG("jal " TARGET_FMT_lx
, btarget
);
2096 ctx
->hflags
|= MIPS_HFLAG_BR
;
2097 MIPS_DEBUG("jr %s", regnames
[rs
]);
2101 ctx
->hflags
|= MIPS_HFLAG_BR
;
2102 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2105 MIPS_INVAL("branch/jump");
2106 generate_exception(ctx
, EXCP_RI
);
2113 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2114 regnames
[rs
], regnames
[rt
], btarget
);
2118 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2119 regnames
[rs
], regnames
[rt
], btarget
);
2123 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2124 regnames
[rs
], regnames
[rt
], btarget
);
2128 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2129 regnames
[rs
], regnames
[rt
], btarget
);
2133 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2137 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2141 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2147 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2151 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2155 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2159 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2163 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2167 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2171 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2176 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2178 ctx
->hflags
|= MIPS_HFLAG_BC
;
2179 tcg_gen_set_bcond();
2184 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2186 ctx
->hflags
|= MIPS_HFLAG_BL
;
2187 tcg_gen_set_bcond();
2190 MIPS_INVAL("conditional branch/jump");
2191 generate_exception(ctx
, EXCP_RI
);
2195 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2196 blink
, ctx
->hflags
, btarget
);
2198 ctx
->btarget
= btarget
;
2200 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
2201 gen_op_store_gpr_T0(blink
);
2205 /* special3 bitfield operations */
2206 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2207 int rs
, int lsb
, int msb
)
2209 GEN_LOAD_REG_T1(rs
);
2214 gen_op_ext(lsb
, msb
+ 1);
2216 #if defined(TARGET_MIPS64)
2220 gen_op_dext(lsb
, msb
+ 1 + 32);
2225 gen_op_dext(lsb
+ 32, msb
+ 1);
2230 gen_op_dext(lsb
, msb
+ 1);
2236 GEN_LOAD_REG_T0(rt
);
2237 gen_op_ins(lsb
, msb
- lsb
+ 1);
2239 #if defined(TARGET_MIPS64)
2243 GEN_LOAD_REG_T0(rt
);
2244 gen_op_dins(lsb
, msb
- lsb
+ 1 + 32);
2249 GEN_LOAD_REG_T0(rt
);
2250 gen_op_dins(lsb
+ 32, msb
- lsb
+ 1);
2255 GEN_LOAD_REG_T0(rt
);
2256 gen_op_dins(lsb
, msb
- lsb
+ 1);
2261 MIPS_INVAL("bitops");
2262 generate_exception(ctx
, EXCP_RI
);
2265 GEN_STORE_T0_REG(rt
);
2268 /* CP0 (MMU and control) */
2269 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
2271 const char *rn
= "invalid";
2274 check_insn(env
, ctx
, ISA_MIPS32
);
2280 gen_op_mfc0_index();
2284 check_insn(env
, ctx
, ASE_MT
);
2285 gen_op_mfc0_mvpcontrol();
2289 check_insn(env
, ctx
, ASE_MT
);
2290 gen_op_mfc0_mvpconf0();
2294 check_insn(env
, ctx
, ASE_MT
);
2295 gen_op_mfc0_mvpconf1();
2305 gen_op_mfc0_random();
2309 check_insn(env
, ctx
, ASE_MT
);
2310 gen_op_mfc0_vpecontrol();
2314 check_insn(env
, ctx
, ASE_MT
);
2315 gen_op_mfc0_vpeconf0();
2319 check_insn(env
, ctx
, ASE_MT
);
2320 gen_op_mfc0_vpeconf1();
2324 check_insn(env
, ctx
, ASE_MT
);
2325 gen_op_mfc0_yqmask();
2329 check_insn(env
, ctx
, ASE_MT
);
2330 gen_op_mfc0_vpeschedule();
2334 check_insn(env
, ctx
, ASE_MT
);
2335 gen_op_mfc0_vpeschefback();
2336 rn
= "VPEScheFBack";
2339 check_insn(env
, ctx
, ASE_MT
);
2340 gen_op_mfc0_vpeopt();
2350 gen_op_mfc0_entrylo0();
2354 check_insn(env
, ctx
, ASE_MT
);
2355 gen_op_mfc0_tcstatus();
2359 check_insn(env
, ctx
, ASE_MT
);
2360 gen_op_mfc0_tcbind();
2364 check_insn(env
, ctx
, ASE_MT
);
2365 gen_op_mfc0_tcrestart();
2369 check_insn(env
, ctx
, ASE_MT
);
2370 gen_op_mfc0_tchalt();
2374 check_insn(env
, ctx
, ASE_MT
);
2375 gen_op_mfc0_tccontext();
2379 check_insn(env
, ctx
, ASE_MT
);
2380 gen_op_mfc0_tcschedule();
2384 check_insn(env
, ctx
, ASE_MT
);
2385 gen_op_mfc0_tcschefback();
2395 gen_op_mfc0_entrylo1();
2405 gen_op_mfc0_context();
2409 // gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
2410 rn
= "ContextConfig";
2419 gen_op_mfc0_pagemask();
2423 check_insn(env
, ctx
, ISA_MIPS32R2
);
2424 gen_op_mfc0_pagegrain();
2434 gen_op_mfc0_wired();
2438 check_insn(env
, ctx
, ISA_MIPS32R2
);
2439 gen_op_mfc0_srsconf0();
2443 check_insn(env
, ctx
, ISA_MIPS32R2
);
2444 gen_op_mfc0_srsconf1();
2448 check_insn(env
, ctx
, ISA_MIPS32R2
);
2449 gen_op_mfc0_srsconf2();
2453 check_insn(env
, ctx
, ISA_MIPS32R2
);
2454 gen_op_mfc0_srsconf3();
2458 check_insn(env
, ctx
, ISA_MIPS32R2
);
2459 gen_op_mfc0_srsconf4();
2469 check_insn(env
, ctx
, ISA_MIPS32R2
);
2470 gen_op_mfc0_hwrena();
2480 gen_op_mfc0_badvaddr();
2490 gen_op_mfc0_count();
2493 /* 6,7 are implementation dependent */
2501 gen_op_mfc0_entryhi();
2511 gen_op_mfc0_compare();
2514 /* 6,7 are implementation dependent */
2522 gen_op_mfc0_status();
2526 check_insn(env
, ctx
, ISA_MIPS32R2
);
2527 gen_op_mfc0_intctl();
2531 check_insn(env
, ctx
, ISA_MIPS32R2
);
2532 gen_op_mfc0_srsctl();
2536 check_insn(env
, ctx
, ISA_MIPS32R2
);
2537 gen_op_mfc0_srsmap();
2547 gen_op_mfc0_cause();
2571 check_insn(env
, ctx
, ISA_MIPS32R2
);
2572 gen_op_mfc0_ebase();
2582 gen_op_mfc0_config0();
2586 gen_op_mfc0_config1();
2590 gen_op_mfc0_config2();
2594 gen_op_mfc0_config3();
2597 /* 4,5 are reserved */
2598 /* 6,7 are implementation dependent */
2600 gen_op_mfc0_config6();
2604 gen_op_mfc0_config7();
2614 gen_op_mfc0_lladdr();
2624 gen_op_mfc0_watchlo(sel
);
2634 gen_op_mfc0_watchhi(sel
);
2644 #if defined(TARGET_MIPS64)
2645 check_insn(env
, ctx
, ISA_MIPS3
);
2646 gen_op_mfc0_xcontext();
2655 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2658 gen_op_mfc0_framemask();
2667 rn
= "'Diagnostic"; /* implementation dependent */
2672 gen_op_mfc0_debug(); /* EJTAG support */
2676 // gen_op_mfc0_tracecontrol(); /* PDtrace support */
2677 rn
= "TraceControl";
2680 // gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2681 rn
= "TraceControl2";
2684 // gen_op_mfc0_usertracedata(); /* PDtrace support */
2685 rn
= "UserTraceData";
2688 // gen_op_mfc0_debug(); /* PDtrace support */
2698 gen_op_mfc0_depc(); /* EJTAG support */
2708 gen_op_mfc0_performance0();
2709 rn
= "Performance0";
2712 // gen_op_mfc0_performance1();
2713 rn
= "Performance1";
2716 // gen_op_mfc0_performance2();
2717 rn
= "Performance2";
2720 // gen_op_mfc0_performance3();
2721 rn
= "Performance3";
2724 // gen_op_mfc0_performance4();
2725 rn
= "Performance4";
2728 // gen_op_mfc0_performance5();
2729 rn
= "Performance5";
2732 // gen_op_mfc0_performance6();
2733 rn
= "Performance6";
2736 // gen_op_mfc0_performance7();
2737 rn
= "Performance7";
2762 gen_op_mfc0_taglo();
2769 gen_op_mfc0_datalo();
2782 gen_op_mfc0_taghi();
2789 gen_op_mfc0_datahi();
2799 gen_op_mfc0_errorepc();
2809 gen_op_mfc0_desave(); /* EJTAG support */
2819 #if defined MIPS_DEBUG_DISAS
2820 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2821 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2828 #if defined MIPS_DEBUG_DISAS
2829 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2830 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2834 generate_exception(ctx
, EXCP_RI
);
2837 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
2839 const char *rn
= "invalid";
2842 check_insn(env
, ctx
, ISA_MIPS32
);
2848 gen_op_mtc0_index();
2852 check_insn(env
, ctx
, ASE_MT
);
2853 gen_op_mtc0_mvpcontrol();
2857 check_insn(env
, ctx
, ASE_MT
);
2862 check_insn(env
, ctx
, ASE_MT
);
2877 check_insn(env
, ctx
, ASE_MT
);
2878 gen_op_mtc0_vpecontrol();
2882 check_insn(env
, ctx
, ASE_MT
);
2883 gen_op_mtc0_vpeconf0();
2887 check_insn(env
, ctx
, ASE_MT
);
2888 gen_op_mtc0_vpeconf1();
2892 check_insn(env
, ctx
, ASE_MT
);
2893 gen_op_mtc0_yqmask();
2897 check_insn(env
, ctx
, ASE_MT
);
2898 gen_op_mtc0_vpeschedule();
2902 check_insn(env
, ctx
, ASE_MT
);
2903 gen_op_mtc0_vpeschefback();
2904 rn
= "VPEScheFBack";
2907 check_insn(env
, ctx
, ASE_MT
);
2908 gen_op_mtc0_vpeopt();
2918 gen_op_mtc0_entrylo0();
2922 check_insn(env
, ctx
, ASE_MT
);
2923 gen_op_mtc0_tcstatus();
2927 check_insn(env
, ctx
, ASE_MT
);
2928 gen_op_mtc0_tcbind();
2932 check_insn(env
, ctx
, ASE_MT
);
2933 gen_op_mtc0_tcrestart();
2937 check_insn(env
, ctx
, ASE_MT
);
2938 gen_op_mtc0_tchalt();
2942 check_insn(env
, ctx
, ASE_MT
);
2943 gen_op_mtc0_tccontext();
2947 check_insn(env
, ctx
, ASE_MT
);
2948 gen_op_mtc0_tcschedule();
2952 check_insn(env
, ctx
, ASE_MT
);
2953 gen_op_mtc0_tcschefback();
2963 gen_op_mtc0_entrylo1();
2973 gen_op_mtc0_context();
2977 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2978 rn
= "ContextConfig";
2987 gen_op_mtc0_pagemask();
2991 check_insn(env
, ctx
, ISA_MIPS32R2
);
2992 gen_op_mtc0_pagegrain();
3002 gen_op_mtc0_wired();
3006 check_insn(env
, ctx
, ISA_MIPS32R2
);
3007 gen_op_mtc0_srsconf0();
3011 check_insn(env
, ctx
, ISA_MIPS32R2
);
3012 gen_op_mtc0_srsconf1();
3016 check_insn(env
, ctx
, ISA_MIPS32R2
);
3017 gen_op_mtc0_srsconf2();
3021 check_insn(env
, ctx
, ISA_MIPS32R2
);
3022 gen_op_mtc0_srsconf3();
3026 check_insn(env
, ctx
, ISA_MIPS32R2
);
3027 gen_op_mtc0_srsconf4();
3037 check_insn(env
, ctx
, ISA_MIPS32R2
);
3038 gen_op_mtc0_hwrena();
3052 gen_op_mtc0_count();
3055 /* 6,7 are implementation dependent */
3059 /* Stop translation as we may have switched the execution mode */
3060 ctx
->bstate
= BS_STOP
;
3065 gen_op_mtc0_entryhi();
3075 gen_op_mtc0_compare();
3078 /* 6,7 are implementation dependent */
3082 /* Stop translation as we may have switched the execution mode */
3083 ctx
->bstate
= BS_STOP
;
3088 gen_op_mtc0_status();
3089 /* BS_STOP isn't good enough here, hflags may have changed. */
3090 gen_save_pc(ctx
->pc
+ 4);
3091 ctx
->bstate
= BS_EXCP
;
3095 check_insn(env
, ctx
, ISA_MIPS32R2
);
3096 gen_op_mtc0_intctl();
3097 /* Stop translation as we may have switched the execution mode */
3098 ctx
->bstate
= BS_STOP
;
3102 check_insn(env
, ctx
, ISA_MIPS32R2
);
3103 gen_op_mtc0_srsctl();
3104 /* Stop translation as we may have switched the execution mode */
3105 ctx
->bstate
= BS_STOP
;
3109 check_insn(env
, ctx
, ISA_MIPS32R2
);
3110 gen_op_mtc0_srsmap();
3111 /* Stop translation as we may have switched the execution mode */
3112 ctx
->bstate
= BS_STOP
;
3122 gen_op_mtc0_cause();
3128 /* Stop translation as we may have switched the execution mode */
3129 ctx
->bstate
= BS_STOP
;
3148 check_insn(env
, ctx
, ISA_MIPS32R2
);
3149 gen_op_mtc0_ebase();
3159 gen_op_mtc0_config0();
3161 /* Stop translation as we may have switched the execution mode */
3162 ctx
->bstate
= BS_STOP
;
3165 /* ignored, read only */
3169 gen_op_mtc0_config2();
3171 /* Stop translation as we may have switched the execution mode */
3172 ctx
->bstate
= BS_STOP
;
3175 /* ignored, read only */
3178 /* 4,5 are reserved */
3179 /* 6,7 are implementation dependent */
3189 rn
= "Invalid config selector";
3206 gen_op_mtc0_watchlo(sel
);
3216 gen_op_mtc0_watchhi(sel
);
3226 #if defined(TARGET_MIPS64)
3227 check_insn(env
, ctx
, ISA_MIPS3
);
3228 gen_op_mtc0_xcontext();
3237 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3240 gen_op_mtc0_framemask();
3249 rn
= "Diagnostic"; /* implementation dependent */
3254 gen_op_mtc0_debug(); /* EJTAG support */
3255 /* BS_STOP isn't good enough here, hflags may have changed. */
3256 gen_save_pc(ctx
->pc
+ 4);
3257 ctx
->bstate
= BS_EXCP
;
3261 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
3262 rn
= "TraceControl";
3263 /* Stop translation as we may have switched the execution mode */
3264 ctx
->bstate
= BS_STOP
;
3267 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
3268 rn
= "TraceControl2";
3269 /* Stop translation as we may have switched the execution mode */
3270 ctx
->bstate
= BS_STOP
;
3273 /* Stop translation as we may have switched the execution mode */
3274 ctx
->bstate
= BS_STOP
;
3275 // gen_op_mtc0_usertracedata(); /* PDtrace support */
3276 rn
= "UserTraceData";
3277 /* Stop translation as we may have switched the execution mode */
3278 ctx
->bstate
= BS_STOP
;
3281 // gen_op_mtc0_debug(); /* PDtrace support */
3282 /* Stop translation as we may have switched the execution mode */
3283 ctx
->bstate
= BS_STOP
;
3293 gen_op_mtc0_depc(); /* EJTAG support */
3303 gen_op_mtc0_performance0();
3304 rn
= "Performance0";
3307 // gen_op_mtc0_performance1();
3308 rn
= "Performance1";
3311 // gen_op_mtc0_performance2();
3312 rn
= "Performance2";
3315 // gen_op_mtc0_performance3();
3316 rn
= "Performance3";
3319 // gen_op_mtc0_performance4();
3320 rn
= "Performance4";
3323 // gen_op_mtc0_performance5();
3324 rn
= "Performance5";
3327 // gen_op_mtc0_performance6();
3328 rn
= "Performance6";
3331 // gen_op_mtc0_performance7();
3332 rn
= "Performance7";
3358 gen_op_mtc0_taglo();
3365 gen_op_mtc0_datalo();
3378 gen_op_mtc0_taghi();
3385 gen_op_mtc0_datahi();
3396 gen_op_mtc0_errorepc();
3406 gen_op_mtc0_desave(); /* EJTAG support */
3412 /* Stop translation as we may have switched the execution mode */
3413 ctx
->bstate
= BS_STOP
;
3418 #if defined MIPS_DEBUG_DISAS
3419 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3420 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3427 #if defined MIPS_DEBUG_DISAS
3428 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3429 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3433 generate_exception(ctx
, EXCP_RI
);
3436 #if defined(TARGET_MIPS64)
3437 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
3439 const char *rn
= "invalid";
3442 check_insn(env
, ctx
, ISA_MIPS64
);
3448 gen_op_mfc0_index();
3452 check_insn(env
, ctx
, ASE_MT
);
3453 gen_op_mfc0_mvpcontrol();
3457 check_insn(env
, ctx
, ASE_MT
);
3458 gen_op_mfc0_mvpconf0();
3462 check_insn(env
, ctx
, ASE_MT
);
3463 gen_op_mfc0_mvpconf1();
3473 gen_op_mfc0_random();
3477 check_insn(env
, ctx
, ASE_MT
);
3478 gen_op_mfc0_vpecontrol();
3482 check_insn(env
, ctx
, ASE_MT
);
3483 gen_op_mfc0_vpeconf0();
3487 check_insn(env
, ctx
, ASE_MT
);
3488 gen_op_mfc0_vpeconf1();
3492 check_insn(env
, ctx
, ASE_MT
);
3493 gen_op_dmfc0_yqmask();
3497 check_insn(env
, ctx
, ASE_MT
);
3498 gen_op_dmfc0_vpeschedule();
3502 check_insn(env
, ctx
, ASE_MT
);
3503 gen_op_dmfc0_vpeschefback();
3504 rn
= "VPEScheFBack";
3507 check_insn(env
, ctx
, ASE_MT
);
3508 gen_op_mfc0_vpeopt();
3518 gen_op_dmfc0_entrylo0();
3522 check_insn(env
, ctx
, ASE_MT
);
3523 gen_op_mfc0_tcstatus();
3527 check_insn(env
, ctx
, ASE_MT
);
3528 gen_op_mfc0_tcbind();
3532 check_insn(env
, ctx
, ASE_MT
);
3533 gen_op_dmfc0_tcrestart();
3537 check_insn(env
, ctx
, ASE_MT
);
3538 gen_op_dmfc0_tchalt();
3542 check_insn(env
, ctx
, ASE_MT
);
3543 gen_op_dmfc0_tccontext();
3547 check_insn(env
, ctx
, ASE_MT
);
3548 gen_op_dmfc0_tcschedule();
3552 check_insn(env
, ctx
, ASE_MT
);
3553 gen_op_dmfc0_tcschefback();
3563 gen_op_dmfc0_entrylo1();
3573 gen_op_dmfc0_context();
3577 // gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
3578 rn
= "ContextConfig";
3587 gen_op_mfc0_pagemask();
3591 check_insn(env
, ctx
, ISA_MIPS32R2
);
3592 gen_op_mfc0_pagegrain();
3602 gen_op_mfc0_wired();
3606 check_insn(env
, ctx
, ISA_MIPS32R2
);
3607 gen_op_mfc0_srsconf0();
3611 check_insn(env
, ctx
, ISA_MIPS32R2
);
3612 gen_op_mfc0_srsconf1();
3616 check_insn(env
, ctx
, ISA_MIPS32R2
);
3617 gen_op_mfc0_srsconf2();
3621 check_insn(env
, ctx
, ISA_MIPS32R2
);
3622 gen_op_mfc0_srsconf3();
3626 check_insn(env
, ctx
, ISA_MIPS32R2
);
3627 gen_op_mfc0_srsconf4();
3637 check_insn(env
, ctx
, ISA_MIPS32R2
);
3638 gen_op_mfc0_hwrena();
3648 gen_op_dmfc0_badvaddr();
3658 gen_op_mfc0_count();
3661 /* 6,7 are implementation dependent */
3669 gen_op_dmfc0_entryhi();
3679 gen_op_mfc0_compare();
3682 /* 6,7 are implementation dependent */
3690 gen_op_mfc0_status();
3694 check_insn(env
, ctx
, ISA_MIPS32R2
);
3695 gen_op_mfc0_intctl();
3699 check_insn(env
, ctx
, ISA_MIPS32R2
);
3700 gen_op_mfc0_srsctl();
3704 check_insn(env
, ctx
, ISA_MIPS32R2
);
3705 gen_op_mfc0_srsmap();
3715 gen_op_mfc0_cause();
3739 check_insn(env
, ctx
, ISA_MIPS32R2
);
3740 gen_op_mfc0_ebase();
3750 gen_op_mfc0_config0();
3754 gen_op_mfc0_config1();
3758 gen_op_mfc0_config2();
3762 gen_op_mfc0_config3();
3765 /* 6,7 are implementation dependent */
3773 gen_op_dmfc0_lladdr();
3783 gen_op_dmfc0_watchlo(sel
);
3793 gen_op_mfc0_watchhi(sel
);
3803 check_insn(env
, ctx
, ISA_MIPS3
);
3804 gen_op_dmfc0_xcontext();
3812 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3815 gen_op_mfc0_framemask();
3824 rn
= "'Diagnostic"; /* implementation dependent */
3829 gen_op_mfc0_debug(); /* EJTAG support */
3833 // gen_op_dmfc0_tracecontrol(); /* PDtrace support */
3834 rn
= "TraceControl";
3837 // gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
3838 rn
= "TraceControl2";
3841 // gen_op_dmfc0_usertracedata(); /* PDtrace support */
3842 rn
= "UserTraceData";
3845 // gen_op_dmfc0_debug(); /* PDtrace support */
3855 gen_op_dmfc0_depc(); /* EJTAG support */
3865 gen_op_mfc0_performance0();
3866 rn
= "Performance0";
3869 // gen_op_dmfc0_performance1();
3870 rn
= "Performance1";
3873 // gen_op_dmfc0_performance2();
3874 rn
= "Performance2";
3877 // gen_op_dmfc0_performance3();
3878 rn
= "Performance3";
3881 // gen_op_dmfc0_performance4();
3882 rn
= "Performance4";
3885 // gen_op_dmfc0_performance5();
3886 rn
= "Performance5";
3889 // gen_op_dmfc0_performance6();
3890 rn
= "Performance6";
3893 // gen_op_dmfc0_performance7();
3894 rn
= "Performance7";
3919 gen_op_mfc0_taglo();
3926 gen_op_mfc0_datalo();
3939 gen_op_mfc0_taghi();
3946 gen_op_mfc0_datahi();
3956 gen_op_dmfc0_errorepc();
3966 gen_op_mfc0_desave(); /* EJTAG support */
3976 #if defined MIPS_DEBUG_DISAS
3977 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3978 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3985 #if defined MIPS_DEBUG_DISAS
3986 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3987 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3991 generate_exception(ctx
, EXCP_RI
);
3994 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
3996 const char *rn
= "invalid";
3999 check_insn(env
, ctx
, ISA_MIPS64
);
4005 gen_op_mtc0_index();
4009 check_insn(env
, ctx
, ASE_MT
);
4010 gen_op_mtc0_mvpcontrol();
4014 check_insn(env
, ctx
, ASE_MT
);
4019 check_insn(env
, ctx
, ASE_MT
);
4034 check_insn(env
, ctx
, ASE_MT
);
4035 gen_op_mtc0_vpecontrol();
4039 check_insn(env
, ctx
, ASE_MT
);
4040 gen_op_mtc0_vpeconf0();
4044 check_insn(env
, ctx
, ASE_MT
);
4045 gen_op_mtc0_vpeconf1();
4049 check_insn(env
, ctx
, ASE_MT
);
4050 gen_op_mtc0_yqmask();
4054 check_insn(env
, ctx
, ASE_MT
);
4055 gen_op_mtc0_vpeschedule();
4059 check_insn(env
, ctx
, ASE_MT
);
4060 gen_op_mtc0_vpeschefback();
4061 rn
= "VPEScheFBack";
4064 check_insn(env
, ctx
, ASE_MT
);
4065 gen_op_mtc0_vpeopt();
4075 gen_op_mtc0_entrylo0();
4079 check_insn(env
, ctx
, ASE_MT
);
4080 gen_op_mtc0_tcstatus();
4084 check_insn(env
, ctx
, ASE_MT
);
4085 gen_op_mtc0_tcbind();
4089 check_insn(env
, ctx
, ASE_MT
);
4090 gen_op_mtc0_tcrestart();
4094 check_insn(env
, ctx
, ASE_MT
);
4095 gen_op_mtc0_tchalt();
4099 check_insn(env
, ctx
, ASE_MT
);
4100 gen_op_mtc0_tccontext();
4104 check_insn(env
, ctx
, ASE_MT
);
4105 gen_op_mtc0_tcschedule();
4109 check_insn(env
, ctx
, ASE_MT
);
4110 gen_op_mtc0_tcschefback();
4120 gen_op_mtc0_entrylo1();
4130 gen_op_mtc0_context();
4134 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
4135 rn
= "ContextConfig";
4144 gen_op_mtc0_pagemask();
4148 check_insn(env
, ctx
, ISA_MIPS32R2
);
4149 gen_op_mtc0_pagegrain();
4159 gen_op_mtc0_wired();
4163 check_insn(env
, ctx
, ISA_MIPS32R2
);
4164 gen_op_mtc0_srsconf0();
4168 check_insn(env
, ctx
, ISA_MIPS32R2
);
4169 gen_op_mtc0_srsconf1();
4173 check_insn(env
, ctx
, ISA_MIPS32R2
);
4174 gen_op_mtc0_srsconf2();
4178 check_insn(env
, ctx
, ISA_MIPS32R2
);
4179 gen_op_mtc0_srsconf3();
4183 check_insn(env
, ctx
, ISA_MIPS32R2
);
4184 gen_op_mtc0_srsconf4();
4194 check_insn(env
, ctx
, ISA_MIPS32R2
);
4195 gen_op_mtc0_hwrena();
4209 gen_op_mtc0_count();
4212 /* 6,7 are implementation dependent */
4216 /* Stop translation as we may have switched the execution mode */
4217 ctx
->bstate
= BS_STOP
;
4222 gen_op_mtc0_entryhi();
4232 gen_op_mtc0_compare();
4235 /* 6,7 are implementation dependent */
4239 /* Stop translation as we may have switched the execution mode */
4240 ctx
->bstate
= BS_STOP
;
4245 gen_op_mtc0_status();
4246 /* BS_STOP isn't good enough here, hflags may have changed. */
4247 gen_save_pc(ctx
->pc
+ 4);
4248 ctx
->bstate
= BS_EXCP
;
4252 check_insn(env
, ctx
, ISA_MIPS32R2
);
4253 gen_op_mtc0_intctl();
4254 /* Stop translation as we may have switched the execution mode */
4255 ctx
->bstate
= BS_STOP
;
4259 check_insn(env
, ctx
, ISA_MIPS32R2
);
4260 gen_op_mtc0_srsctl();
4261 /* Stop translation as we may have switched the execution mode */
4262 ctx
->bstate
= BS_STOP
;
4266 check_insn(env
, ctx
, ISA_MIPS32R2
);
4267 gen_op_mtc0_srsmap();
4268 /* Stop translation as we may have switched the execution mode */
4269 ctx
->bstate
= BS_STOP
;
4279 gen_op_mtc0_cause();
4285 /* Stop translation as we may have switched the execution mode */
4286 ctx
->bstate
= BS_STOP
;
4305 check_insn(env
, ctx
, ISA_MIPS32R2
);
4306 gen_op_mtc0_ebase();
4316 gen_op_mtc0_config0();
4318 /* Stop translation as we may have switched the execution mode */
4319 ctx
->bstate
= BS_STOP
;
4326 gen_op_mtc0_config2();
4328 /* Stop translation as we may have switched the execution mode */
4329 ctx
->bstate
= BS_STOP
;
4335 /* 6,7 are implementation dependent */
4337 rn
= "Invalid config selector";
4354 gen_op_mtc0_watchlo(sel
);
4364 gen_op_mtc0_watchhi(sel
);
4374 check_insn(env
, ctx
, ISA_MIPS3
);
4375 gen_op_mtc0_xcontext();
4383 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4386 gen_op_mtc0_framemask();
4395 rn
= "Diagnostic"; /* implementation dependent */
4400 gen_op_mtc0_debug(); /* EJTAG support */
4401 /* BS_STOP isn't good enough here, hflags may have changed. */
4402 gen_save_pc(ctx
->pc
+ 4);
4403 ctx
->bstate
= BS_EXCP
;
4407 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
4408 /* Stop translation as we may have switched the execution mode */
4409 ctx
->bstate
= BS_STOP
;
4410 rn
= "TraceControl";
4413 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
4414 /* Stop translation as we may have switched the execution mode */
4415 ctx
->bstate
= BS_STOP
;
4416 rn
= "TraceControl2";
4419 // gen_op_mtc0_usertracedata(); /* PDtrace support */
4420 /* Stop translation as we may have switched the execution mode */
4421 ctx
->bstate
= BS_STOP
;
4422 rn
= "UserTraceData";
4425 // gen_op_mtc0_debug(); /* PDtrace support */
4426 /* Stop translation as we may have switched the execution mode */
4427 ctx
->bstate
= BS_STOP
;
4437 gen_op_mtc0_depc(); /* EJTAG support */
4447 gen_op_mtc0_performance0();
4448 rn
= "Performance0";
4451 // gen_op_mtc0_performance1();
4452 rn
= "Performance1";
4455 // gen_op_mtc0_performance2();
4456 rn
= "Performance2";
4459 // gen_op_mtc0_performance3();
4460 rn
= "Performance3";
4463 // gen_op_mtc0_performance4();
4464 rn
= "Performance4";
4467 // gen_op_mtc0_performance5();
4468 rn
= "Performance5";
4471 // gen_op_mtc0_performance6();
4472 rn
= "Performance6";
4475 // gen_op_mtc0_performance7();
4476 rn
= "Performance7";
4502 gen_op_mtc0_taglo();
4509 gen_op_mtc0_datalo();
4522 gen_op_mtc0_taghi();
4529 gen_op_mtc0_datahi();
4540 gen_op_mtc0_errorepc();
4550 gen_op_mtc0_desave(); /* EJTAG support */
4556 /* Stop translation as we may have switched the execution mode */
4557 ctx
->bstate
= BS_STOP
;
4562 #if defined MIPS_DEBUG_DISAS
4563 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4564 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
4571 #if defined MIPS_DEBUG_DISAS
4572 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4573 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
4577 generate_exception(ctx
, EXCP_RI
);
4579 #endif /* TARGET_MIPS64 */
4581 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
,
4582 int u
, int sel
, int h
)
4584 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
4586 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
4587 ((env
->CP0_TCBind
[other_tc
] & (0xf << CP0TCBd_CurVPE
)) !=
4588 (env
->CP0_TCBind
[env
->current_tc
] & (0xf << CP0TCBd_CurVPE
))))
4590 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
4591 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
4598 gen_op_mftc0_tcstatus();
4601 gen_op_mftc0_tcbind();
4604 gen_op_mftc0_tcrestart();
4607 gen_op_mftc0_tchalt();
4610 gen_op_mftc0_tccontext();
4613 gen_op_mftc0_tcschedule();
4616 gen_op_mftc0_tcschefback();
4619 gen_mfc0(env
, ctx
, rt
, sel
);
4626 gen_op_mftc0_entryhi();
4629 gen_mfc0(env
, ctx
, rt
, sel
);
4635 gen_op_mftc0_status();
4638 gen_mfc0(env
, ctx
, rt
, sel
);
4644 gen_op_mftc0_debug();
4647 gen_mfc0(env
, ctx
, rt
, sel
);
4652 gen_mfc0(env
, ctx
, rt
, sel
);
4654 } else switch (sel
) {
4655 /* GPR registers. */
4659 /* Auxiliary CPU registers */
4705 /* Floating point (COP1). */
4707 /* XXX: For now we support only a single FPU context. */
4709 GEN_LOAD_FREG_FTN(WT0
, rt
);
4712 GEN_LOAD_FREG_FTN(WTH0
, rt
);
4717 /* XXX: For now we support only a single FPU context. */
4720 /* COP2: Not implemented. */
4727 #if defined MIPS_DEBUG_DISAS
4728 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4729 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
4736 #if defined MIPS_DEBUG_DISAS
4737 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4738 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
4742 generate_exception(ctx
, EXCP_RI
);
4745 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
,
4746 int u
, int sel
, int h
)
4748 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
4750 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
4751 ((env
->CP0_TCBind
[other_tc
] & (0xf << CP0TCBd_CurVPE
)) !=
4752 (env
->CP0_TCBind
[env
->current_tc
] & (0xf << CP0TCBd_CurVPE
))))
4754 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
4755 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
4762 gen_op_mttc0_tcstatus();
4765 gen_op_mttc0_tcbind();
4768 gen_op_mttc0_tcrestart();
4771 gen_op_mttc0_tchalt();
4774 gen_op_mttc0_tccontext();
4777 gen_op_mttc0_tcschedule();
4780 gen_op_mttc0_tcschefback();
4783 gen_mtc0(env
, ctx
, rd
, sel
);
4790 gen_op_mttc0_entryhi();
4793 gen_mtc0(env
, ctx
, rd
, sel
);
4799 gen_op_mttc0_status();
4802 gen_mtc0(env
, ctx
, rd
, sel
);
4808 gen_op_mttc0_debug();
4811 gen_mtc0(env
, ctx
, rd
, sel
);
4816 gen_mtc0(env
, ctx
, rd
, sel
);
4818 } else switch (sel
) {
4819 /* GPR registers. */
4823 /* Auxiliary CPU registers */
4869 /* Floating point (COP1). */
4871 /* XXX: For now we support only a single FPU context. */
4874 GEN_STORE_FTN_FREG(rd
, WT0
);
4877 GEN_STORE_FTN_FREG(rd
, WTH0
);
4881 /* XXX: For now we support only a single FPU context. */
4884 /* COP2: Not implemented. */
4891 #if defined MIPS_DEBUG_DISAS
4892 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4893 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
4900 #if defined MIPS_DEBUG_DISAS
4901 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4902 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
4906 generate_exception(ctx
, EXCP_RI
);
4909 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
4911 const char *opn
= "ldst";
4919 gen_mfc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4920 gen_op_store_gpr_T0(rt
);
4924 GEN_LOAD_REG_T0(rt
);
4925 save_cpu_state(ctx
, 1);
4926 gen_mtc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4929 #if defined(TARGET_MIPS64)
4931 check_insn(env
, ctx
, ISA_MIPS3
);
4936 gen_dmfc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4937 gen_op_store_gpr_T0(rt
);
4941 check_insn(env
, ctx
, ISA_MIPS3
);
4942 GEN_LOAD_REG_T0(rt
);
4943 save_cpu_state(ctx
, 1);
4944 gen_dmtc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4949 check_insn(env
, ctx
, ASE_MT
);
4954 gen_mftr(env
, ctx
, rt
, (ctx
->opcode
>> 5) & 1,
4955 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
4956 gen_op_store_gpr_T0(rd
);
4960 check_insn(env
, ctx
, ASE_MT
);
4961 GEN_LOAD_REG_T0(rt
);
4962 gen_mttr(env
, ctx
, rd
, (ctx
->opcode
>> 5) & 1,
4963 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
4968 if (!env
->tlb
->do_tlbwi
)
4974 if (!env
->tlb
->do_tlbwr
)
4980 if (!env
->tlb
->do_tlbp
)
4986 if (!env
->tlb
->do_tlbr
)
4992 check_insn(env
, ctx
, ISA_MIPS2
);
4993 save_cpu_state(ctx
, 1);
4995 ctx
->bstate
= BS_EXCP
;
4999 check_insn(env
, ctx
, ISA_MIPS32
);
5000 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5002 generate_exception(ctx
, EXCP_RI
);
5004 save_cpu_state(ctx
, 1);
5006 ctx
->bstate
= BS_EXCP
;
5011 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5012 /* If we get an exception, we want to restart at next instruction */
5014 save_cpu_state(ctx
, 1);
5017 ctx
->bstate
= BS_EXCP
;
5022 generate_exception(ctx
, EXCP_RI
);
5025 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5028 /* CP1 Branches (before delay slot) */
5029 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5030 int32_t cc
, int32_t offset
)
5032 target_ulong btarget
;
5033 const char *opn
= "cp1 cond branch";
5036 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5038 btarget
= ctx
->pc
+ 4 + offset
;
5057 ctx
->hflags
|= MIPS_HFLAG_BL
;
5058 tcg_gen_set_bcond();
5061 gen_op_bc1any2f(cc
);
5065 gen_op_bc1any2t(cc
);
5069 gen_op_bc1any4f(cc
);
5073 gen_op_bc1any4t(cc
);
5076 ctx
->hflags
|= MIPS_HFLAG_BC
;
5077 tcg_gen_set_bcond();
5081 generate_exception (ctx
, EXCP_RI
);
5084 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5085 ctx
->hflags
, btarget
);
5086 ctx
->btarget
= btarget
;
5089 /* Coprocessor 1 (FPU) */
5091 #define FOP(func, fmt) (((fmt) << 21) | (func))
5093 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5095 const char *opn
= "cp1 move";
5099 GEN_LOAD_FREG_FTN(WT0
, fs
);
5101 GEN_STORE_T0_REG(rt
);
5105 GEN_LOAD_REG_T0(rt
);
5107 GEN_STORE_FTN_FREG(fs
, WT0
);
5112 GEN_STORE_T0_REG(rt
);
5116 GEN_LOAD_REG_T0(rt
);
5121 GEN_LOAD_FREG_FTN(DT0
, fs
);
5123 GEN_STORE_T0_REG(rt
);
5127 GEN_LOAD_REG_T0(rt
);
5129 GEN_STORE_FTN_FREG(fs
, DT0
);
5133 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5135 GEN_STORE_T0_REG(rt
);
5139 GEN_LOAD_REG_T0(rt
);
5141 GEN_STORE_FTN_FREG(fs
, WTH0
);
5146 generate_exception (ctx
, EXCP_RI
);
5149 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
5152 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
5156 GEN_LOAD_REG_T0(rd
);
5157 GEN_LOAD_REG_T1(rs
);
5159 ccbit
= 1 << (24 + cc
);
5166 GEN_STORE_T0_REG(rd
);
5169 #define GEN_MOVCF(fmt) \
5170 static void glue(gen_movcf_, fmt) (DisasContext *ctx, int cc, int tf) \
5175 ccbit = 1 << (24 + cc); \
5179 glue(gen_op_float_movf_, fmt)(ccbit); \
5181 glue(gen_op_float_movt_, fmt)(ccbit); \
5188 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
5189 int ft
, int fs
, int fd
, int cc
)
5191 const char *opn
= "farith";
5192 const char *condnames
[] = {
5210 const char *condnames_abs
[] = {
5228 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
5229 uint32_t func
= ctx
->opcode
& 0x3f;
5231 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
5233 GEN_LOAD_FREG_FTN(WT0
, fs
);
5234 GEN_LOAD_FREG_FTN(WT1
, ft
);
5235 gen_op_float_add_s();
5236 GEN_STORE_FTN_FREG(fd
, WT2
);
5241 GEN_LOAD_FREG_FTN(WT0
, fs
);
5242 GEN_LOAD_FREG_FTN(WT1
, ft
);
5243 gen_op_float_sub_s();
5244 GEN_STORE_FTN_FREG(fd
, WT2
);
5249 GEN_LOAD_FREG_FTN(WT0
, fs
);
5250 GEN_LOAD_FREG_FTN(WT1
, ft
);
5251 gen_op_float_mul_s();
5252 GEN_STORE_FTN_FREG(fd
, WT2
);
5257 GEN_LOAD_FREG_FTN(WT0
, fs
);
5258 GEN_LOAD_FREG_FTN(WT1
, ft
);
5259 gen_op_float_div_s();
5260 GEN_STORE_FTN_FREG(fd
, WT2
);
5265 GEN_LOAD_FREG_FTN(WT0
, fs
);
5266 gen_op_float_sqrt_s();
5267 GEN_STORE_FTN_FREG(fd
, WT2
);
5271 GEN_LOAD_FREG_FTN(WT0
, fs
);
5272 gen_op_float_abs_s();
5273 GEN_STORE_FTN_FREG(fd
, WT2
);
5277 GEN_LOAD_FREG_FTN(WT0
, fs
);
5278 gen_op_float_mov_s();
5279 GEN_STORE_FTN_FREG(fd
, WT2
);
5283 GEN_LOAD_FREG_FTN(WT0
, fs
);
5284 gen_op_float_chs_s();
5285 GEN_STORE_FTN_FREG(fd
, WT2
);
5289 check_cp1_64bitmode(ctx
);
5290 GEN_LOAD_FREG_FTN(WT0
, fs
);
5291 gen_op_float_roundl_s();
5292 GEN_STORE_FTN_FREG(fd
, DT2
);
5296 check_cp1_64bitmode(ctx
);
5297 GEN_LOAD_FREG_FTN(WT0
, fs
);
5298 gen_op_float_truncl_s();
5299 GEN_STORE_FTN_FREG(fd
, DT2
);
5303 check_cp1_64bitmode(ctx
);
5304 GEN_LOAD_FREG_FTN(WT0
, fs
);
5305 gen_op_float_ceill_s();
5306 GEN_STORE_FTN_FREG(fd
, DT2
);
5310 check_cp1_64bitmode(ctx
);
5311 GEN_LOAD_FREG_FTN(WT0
, fs
);
5312 gen_op_float_floorl_s();
5313 GEN_STORE_FTN_FREG(fd
, DT2
);
5317 GEN_LOAD_FREG_FTN(WT0
, fs
);
5318 gen_op_float_roundw_s();
5319 GEN_STORE_FTN_FREG(fd
, WT2
);
5323 GEN_LOAD_FREG_FTN(WT0
, fs
);
5324 gen_op_float_truncw_s();
5325 GEN_STORE_FTN_FREG(fd
, WT2
);
5329 GEN_LOAD_FREG_FTN(WT0
, fs
);
5330 gen_op_float_ceilw_s();
5331 GEN_STORE_FTN_FREG(fd
, WT2
);
5335 GEN_LOAD_FREG_FTN(WT0
, fs
);
5336 gen_op_float_floorw_s();
5337 GEN_STORE_FTN_FREG(fd
, WT2
);
5341 GEN_LOAD_REG_T0(ft
);
5342 GEN_LOAD_FREG_FTN(WT0
, fs
);
5343 GEN_LOAD_FREG_FTN(WT2
, fd
);
5344 gen_movcf_s(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5345 GEN_STORE_FTN_FREG(fd
, WT2
);
5349 GEN_LOAD_REG_T0(ft
);
5350 GEN_LOAD_FREG_FTN(WT0
, fs
);
5351 GEN_LOAD_FREG_FTN(WT2
, fd
);
5352 gen_op_float_movz_s();
5353 GEN_STORE_FTN_FREG(fd
, WT2
);
5357 GEN_LOAD_REG_T0(ft
);
5358 GEN_LOAD_FREG_FTN(WT0
, fs
);
5359 GEN_LOAD_FREG_FTN(WT2
, fd
);
5360 gen_op_float_movn_s();
5361 GEN_STORE_FTN_FREG(fd
, WT2
);
5366 GEN_LOAD_FREG_FTN(WT0
, fs
);
5367 gen_op_float_recip_s();
5368 GEN_STORE_FTN_FREG(fd
, WT2
);
5373 GEN_LOAD_FREG_FTN(WT0
, fs
);
5374 gen_op_float_rsqrt_s();
5375 GEN_STORE_FTN_FREG(fd
, WT2
);
5379 check_cp1_64bitmode(ctx
);
5380 GEN_LOAD_FREG_FTN(WT0
, fs
);
5381 GEN_LOAD_FREG_FTN(WT2
, fd
);
5382 gen_op_float_recip2_s();
5383 GEN_STORE_FTN_FREG(fd
, WT2
);
5387 check_cp1_64bitmode(ctx
);
5388 GEN_LOAD_FREG_FTN(WT0
, fs
);
5389 gen_op_float_recip1_s();
5390 GEN_STORE_FTN_FREG(fd
, WT2
);
5394 check_cp1_64bitmode(ctx
);
5395 GEN_LOAD_FREG_FTN(WT0
, fs
);
5396 gen_op_float_rsqrt1_s();
5397 GEN_STORE_FTN_FREG(fd
, WT2
);
5401 check_cp1_64bitmode(ctx
);
5402 GEN_LOAD_FREG_FTN(WT0
, fs
);
5403 GEN_LOAD_FREG_FTN(WT2
, ft
);
5404 gen_op_float_rsqrt2_s();
5405 GEN_STORE_FTN_FREG(fd
, WT2
);
5409 check_cp1_registers(ctx
, fd
);
5410 GEN_LOAD_FREG_FTN(WT0
, fs
);
5411 gen_op_float_cvtd_s();
5412 GEN_STORE_FTN_FREG(fd
, DT2
);
5416 GEN_LOAD_FREG_FTN(WT0
, fs
);
5417 gen_op_float_cvtw_s();
5418 GEN_STORE_FTN_FREG(fd
, WT2
);
5422 check_cp1_64bitmode(ctx
);
5423 GEN_LOAD_FREG_FTN(WT0
, fs
);
5424 gen_op_float_cvtl_s();
5425 GEN_STORE_FTN_FREG(fd
, DT2
);
5429 check_cp1_64bitmode(ctx
);
5430 GEN_LOAD_FREG_FTN(WT1
, fs
);
5431 GEN_LOAD_FREG_FTN(WT0
, ft
);
5432 gen_op_float_cvtps_s();
5433 GEN_STORE_FTN_FREG(fd
, DT2
);
5452 GEN_LOAD_FREG_FTN(WT0
, fs
);
5453 GEN_LOAD_FREG_FTN(WT1
, ft
);
5454 if (ctx
->opcode
& (1 << 6)) {
5456 gen_cmpabs_s(func
-48, cc
);
5457 opn
= condnames_abs
[func
-48];
5459 gen_cmp_s(func
-48, cc
);
5460 opn
= condnames
[func
-48];
5464 check_cp1_registers(ctx
, fs
| ft
| fd
);
5465 GEN_LOAD_FREG_FTN(DT0
, fs
);
5466 GEN_LOAD_FREG_FTN(DT1
, ft
);
5467 gen_op_float_add_d();
5468 GEN_STORE_FTN_FREG(fd
, DT2
);
5473 check_cp1_registers(ctx
, fs
| ft
| fd
);
5474 GEN_LOAD_FREG_FTN(DT0
, fs
);
5475 GEN_LOAD_FREG_FTN(DT1
, ft
);
5476 gen_op_float_sub_d();
5477 GEN_STORE_FTN_FREG(fd
, DT2
);
5482 check_cp1_registers(ctx
, fs
| ft
| fd
);
5483 GEN_LOAD_FREG_FTN(DT0
, fs
);
5484 GEN_LOAD_FREG_FTN(DT1
, ft
);
5485 gen_op_float_mul_d();
5486 GEN_STORE_FTN_FREG(fd
, DT2
);
5491 check_cp1_registers(ctx
, fs
| ft
| fd
);
5492 GEN_LOAD_FREG_FTN(DT0
, fs
);
5493 GEN_LOAD_FREG_FTN(DT1
, ft
);
5494 gen_op_float_div_d();
5495 GEN_STORE_FTN_FREG(fd
, DT2
);
5500 check_cp1_registers(ctx
, fs
| fd
);
5501 GEN_LOAD_FREG_FTN(DT0
, fs
);
5502 gen_op_float_sqrt_d();
5503 GEN_STORE_FTN_FREG(fd
, DT2
);
5507 check_cp1_registers(ctx
, fs
| fd
);
5508 GEN_LOAD_FREG_FTN(DT0
, fs
);
5509 gen_op_float_abs_d();
5510 GEN_STORE_FTN_FREG(fd
, DT2
);
5514 check_cp1_registers(ctx
, fs
| fd
);
5515 GEN_LOAD_FREG_FTN(DT0
, fs
);
5516 gen_op_float_mov_d();
5517 GEN_STORE_FTN_FREG(fd
, DT2
);
5521 check_cp1_registers(ctx
, fs
| fd
);
5522 GEN_LOAD_FREG_FTN(DT0
, fs
);
5523 gen_op_float_chs_d();
5524 GEN_STORE_FTN_FREG(fd
, DT2
);
5528 check_cp1_64bitmode(ctx
);
5529 GEN_LOAD_FREG_FTN(DT0
, fs
);
5530 gen_op_float_roundl_d();
5531 GEN_STORE_FTN_FREG(fd
, DT2
);
5535 check_cp1_64bitmode(ctx
);
5536 GEN_LOAD_FREG_FTN(DT0
, fs
);
5537 gen_op_float_truncl_d();
5538 GEN_STORE_FTN_FREG(fd
, DT2
);
5542 check_cp1_64bitmode(ctx
);
5543 GEN_LOAD_FREG_FTN(DT0
, fs
);
5544 gen_op_float_ceill_d();
5545 GEN_STORE_FTN_FREG(fd
, DT2
);
5549 check_cp1_64bitmode(ctx
);
5550 GEN_LOAD_FREG_FTN(DT0
, fs
);
5551 gen_op_float_floorl_d();
5552 GEN_STORE_FTN_FREG(fd
, DT2
);
5556 check_cp1_registers(ctx
, fs
);
5557 GEN_LOAD_FREG_FTN(DT0
, fs
);
5558 gen_op_float_roundw_d();
5559 GEN_STORE_FTN_FREG(fd
, WT2
);
5563 check_cp1_registers(ctx
, fs
);
5564 GEN_LOAD_FREG_FTN(DT0
, fs
);
5565 gen_op_float_truncw_d();
5566 GEN_STORE_FTN_FREG(fd
, WT2
);
5570 check_cp1_registers(ctx
, fs
);
5571 GEN_LOAD_FREG_FTN(DT0
, fs
);
5572 gen_op_float_ceilw_d();
5573 GEN_STORE_FTN_FREG(fd
, WT2
);
5577 check_cp1_registers(ctx
, fs
);
5578 GEN_LOAD_FREG_FTN(DT0
, fs
);
5579 gen_op_float_floorw_d();
5580 GEN_STORE_FTN_FREG(fd
, WT2
);
5584 GEN_LOAD_REG_T0(ft
);
5585 GEN_LOAD_FREG_FTN(DT0
, fs
);
5586 GEN_LOAD_FREG_FTN(DT2
, fd
);
5587 gen_movcf_d(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5588 GEN_STORE_FTN_FREG(fd
, DT2
);
5592 GEN_LOAD_REG_T0(ft
);
5593 GEN_LOAD_FREG_FTN(DT0
, fs
);
5594 GEN_LOAD_FREG_FTN(DT2
, fd
);
5595 gen_op_float_movz_d();
5596 GEN_STORE_FTN_FREG(fd
, DT2
);
5600 GEN_LOAD_REG_T0(ft
);
5601 GEN_LOAD_FREG_FTN(DT0
, fs
);
5602 GEN_LOAD_FREG_FTN(DT2
, fd
);
5603 gen_op_float_movn_d();
5604 GEN_STORE_FTN_FREG(fd
, DT2
);
5608 check_cp1_64bitmode(ctx
);
5609 GEN_LOAD_FREG_FTN(DT0
, fs
);
5610 gen_op_float_recip_d();
5611 GEN_STORE_FTN_FREG(fd
, DT2
);
5615 check_cp1_64bitmode(ctx
);
5616 GEN_LOAD_FREG_FTN(DT0
, fs
);
5617 gen_op_float_rsqrt_d();
5618 GEN_STORE_FTN_FREG(fd
, DT2
);
5622 check_cp1_64bitmode(ctx
);
5623 GEN_LOAD_FREG_FTN(DT0
, fs
);
5624 GEN_LOAD_FREG_FTN(DT2
, ft
);
5625 gen_op_float_recip2_d();
5626 GEN_STORE_FTN_FREG(fd
, DT2
);
5630 check_cp1_64bitmode(ctx
);
5631 GEN_LOAD_FREG_FTN(DT0
, fs
);
5632 gen_op_float_recip1_d();
5633 GEN_STORE_FTN_FREG(fd
, DT2
);
5637 check_cp1_64bitmode(ctx
);
5638 GEN_LOAD_FREG_FTN(DT0
, fs
);
5639 gen_op_float_rsqrt1_d();
5640 GEN_STORE_FTN_FREG(fd
, DT2
);
5644 check_cp1_64bitmode(ctx
);
5645 GEN_LOAD_FREG_FTN(DT0
, fs
);
5646 GEN_LOAD_FREG_FTN(DT2
, ft
);
5647 gen_op_float_rsqrt2_d();
5648 GEN_STORE_FTN_FREG(fd
, DT2
);
5667 GEN_LOAD_FREG_FTN(DT0
, fs
);
5668 GEN_LOAD_FREG_FTN(DT1
, ft
);
5669 if (ctx
->opcode
& (1 << 6)) {
5671 check_cp1_registers(ctx
, fs
| ft
);
5672 gen_cmpabs_d(func
-48, cc
);
5673 opn
= condnames_abs
[func
-48];
5675 check_cp1_registers(ctx
, fs
| ft
);
5676 gen_cmp_d(func
-48, cc
);
5677 opn
= condnames
[func
-48];
5681 check_cp1_registers(ctx
, fs
);
5682 GEN_LOAD_FREG_FTN(DT0
, fs
);
5683 gen_op_float_cvts_d();
5684 GEN_STORE_FTN_FREG(fd
, WT2
);
5688 check_cp1_registers(ctx
, fs
);
5689 GEN_LOAD_FREG_FTN(DT0
, fs
);
5690 gen_op_float_cvtw_d();
5691 GEN_STORE_FTN_FREG(fd
, WT2
);
5695 check_cp1_64bitmode(ctx
);
5696 GEN_LOAD_FREG_FTN(DT0
, fs
);
5697 gen_op_float_cvtl_d();
5698 GEN_STORE_FTN_FREG(fd
, DT2
);
5702 GEN_LOAD_FREG_FTN(WT0
, fs
);
5703 gen_op_float_cvts_w();
5704 GEN_STORE_FTN_FREG(fd
, WT2
);
5708 check_cp1_registers(ctx
, fd
);
5709 GEN_LOAD_FREG_FTN(WT0
, fs
);
5710 gen_op_float_cvtd_w();
5711 GEN_STORE_FTN_FREG(fd
, DT2
);
5715 check_cp1_64bitmode(ctx
);
5716 GEN_LOAD_FREG_FTN(DT0
, fs
);
5717 gen_op_float_cvts_l();
5718 GEN_STORE_FTN_FREG(fd
, WT2
);
5722 check_cp1_64bitmode(ctx
);
5723 GEN_LOAD_FREG_FTN(DT0
, fs
);
5724 gen_op_float_cvtd_l();
5725 GEN_STORE_FTN_FREG(fd
, DT2
);
5729 check_cp1_64bitmode(ctx
);
5730 GEN_LOAD_FREG_FTN(WT0
, fs
);
5731 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5732 gen_op_float_cvtps_pw();
5733 GEN_STORE_FTN_FREG(fd
, WT2
);
5734 GEN_STORE_FTN_FREG(fd
, WTH2
);
5738 check_cp1_64bitmode(ctx
);
5739 GEN_LOAD_FREG_FTN(WT0
, fs
);
5740 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5741 GEN_LOAD_FREG_FTN(WT1
, ft
);
5742 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5743 gen_op_float_add_ps();
5744 GEN_STORE_FTN_FREG(fd
, WT2
);
5745 GEN_STORE_FTN_FREG(fd
, WTH2
);
5749 check_cp1_64bitmode(ctx
);
5750 GEN_LOAD_FREG_FTN(WT0
, fs
);
5751 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5752 GEN_LOAD_FREG_FTN(WT1
, ft
);
5753 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5754 gen_op_float_sub_ps();
5755 GEN_STORE_FTN_FREG(fd
, WT2
);
5756 GEN_STORE_FTN_FREG(fd
, WTH2
);
5760 check_cp1_64bitmode(ctx
);
5761 GEN_LOAD_FREG_FTN(WT0
, fs
);
5762 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5763 GEN_LOAD_FREG_FTN(WT1
, ft
);
5764 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5765 gen_op_float_mul_ps();
5766 GEN_STORE_FTN_FREG(fd
, WT2
);
5767 GEN_STORE_FTN_FREG(fd
, WTH2
);
5771 check_cp1_64bitmode(ctx
);
5772 GEN_LOAD_FREG_FTN(WT0
, fs
);
5773 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5774 gen_op_float_abs_ps();
5775 GEN_STORE_FTN_FREG(fd
, WT2
);
5776 GEN_STORE_FTN_FREG(fd
, WTH2
);
5780 check_cp1_64bitmode(ctx
);
5781 GEN_LOAD_FREG_FTN(WT0
, fs
);
5782 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5783 gen_op_float_mov_ps();
5784 GEN_STORE_FTN_FREG(fd
, WT2
);
5785 GEN_STORE_FTN_FREG(fd
, WTH2
);
5789 check_cp1_64bitmode(ctx
);
5790 GEN_LOAD_FREG_FTN(WT0
, fs
);
5791 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5792 gen_op_float_chs_ps();
5793 GEN_STORE_FTN_FREG(fd
, WT2
);
5794 GEN_STORE_FTN_FREG(fd
, WTH2
);
5798 check_cp1_64bitmode(ctx
);
5799 GEN_LOAD_REG_T0(ft
);
5800 GEN_LOAD_FREG_FTN(WT0
, fs
);
5801 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5802 GEN_LOAD_FREG_FTN(WT2
, fd
);
5803 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5804 gen_movcf_ps(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5805 GEN_STORE_FTN_FREG(fd
, WT2
);
5806 GEN_STORE_FTN_FREG(fd
, WTH2
);
5810 check_cp1_64bitmode(ctx
);
5811 GEN_LOAD_REG_T0(ft
);
5812 GEN_LOAD_FREG_FTN(WT0
, fs
);
5813 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5814 GEN_LOAD_FREG_FTN(WT2
, fd
);
5815 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5816 gen_op_float_movz_ps();
5817 GEN_STORE_FTN_FREG(fd
, WT2
);
5818 GEN_STORE_FTN_FREG(fd
, WTH2
);
5822 check_cp1_64bitmode(ctx
);
5823 GEN_LOAD_REG_T0(ft
);
5824 GEN_LOAD_FREG_FTN(WT0
, fs
);
5825 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5826 GEN_LOAD_FREG_FTN(WT2
, fd
);
5827 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5828 gen_op_float_movn_ps();
5829 GEN_STORE_FTN_FREG(fd
, WT2
);
5830 GEN_STORE_FTN_FREG(fd
, WTH2
);
5834 check_cp1_64bitmode(ctx
);
5835 GEN_LOAD_FREG_FTN(WT0
, ft
);
5836 GEN_LOAD_FREG_FTN(WTH0
, ft
);
5837 GEN_LOAD_FREG_FTN(WT1
, fs
);
5838 GEN_LOAD_FREG_FTN(WTH1
, fs
);
5839 gen_op_float_addr_ps();
5840 GEN_STORE_FTN_FREG(fd
, WT2
);
5841 GEN_STORE_FTN_FREG(fd
, WTH2
);
5845 check_cp1_64bitmode(ctx
);
5846 GEN_LOAD_FREG_FTN(WT0
, ft
);
5847 GEN_LOAD_FREG_FTN(WTH0
, ft
);
5848 GEN_LOAD_FREG_FTN(WT1
, fs
);
5849 GEN_LOAD_FREG_FTN(WTH1
, fs
);
5850 gen_op_float_mulr_ps();
5851 GEN_STORE_FTN_FREG(fd
, WT2
);
5852 GEN_STORE_FTN_FREG(fd
, WTH2
);
5856 check_cp1_64bitmode(ctx
);
5857 GEN_LOAD_FREG_FTN(WT0
, fs
);
5858 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5859 GEN_LOAD_FREG_FTN(WT2
, fd
);
5860 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5861 gen_op_float_recip2_ps();
5862 GEN_STORE_FTN_FREG(fd
, WT2
);
5863 GEN_STORE_FTN_FREG(fd
, WTH2
);
5867 check_cp1_64bitmode(ctx
);
5868 GEN_LOAD_FREG_FTN(WT0
, fs
);
5869 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5870 gen_op_float_recip1_ps();
5871 GEN_STORE_FTN_FREG(fd
, WT2
);
5872 GEN_STORE_FTN_FREG(fd
, WTH2
);
5876 check_cp1_64bitmode(ctx
);
5877 GEN_LOAD_FREG_FTN(WT0
, fs
);
5878 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5879 gen_op_float_rsqrt1_ps();
5880 GEN_STORE_FTN_FREG(fd
, WT2
);
5881 GEN_STORE_FTN_FREG(fd
, WTH2
);
5885 check_cp1_64bitmode(ctx
);
5886 GEN_LOAD_FREG_FTN(WT0
, fs
);
5887 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5888 GEN_LOAD_FREG_FTN(WT2
, ft
);
5889 GEN_LOAD_FREG_FTN(WTH2
, ft
);
5890 gen_op_float_rsqrt2_ps();
5891 GEN_STORE_FTN_FREG(fd
, WT2
);
5892 GEN_STORE_FTN_FREG(fd
, WTH2
);
5896 check_cp1_64bitmode(ctx
);
5897 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5898 gen_op_float_cvts_pu();
5899 GEN_STORE_FTN_FREG(fd
, WT2
);
5903 check_cp1_64bitmode(ctx
);
5904 GEN_LOAD_FREG_FTN(WT0
, fs
);
5905 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5906 gen_op_float_cvtpw_ps();
5907 GEN_STORE_FTN_FREG(fd
, WT2
);
5908 GEN_STORE_FTN_FREG(fd
, WTH2
);
5912 check_cp1_64bitmode(ctx
);
5913 GEN_LOAD_FREG_FTN(WT0
, fs
);
5914 gen_op_float_cvts_pl();
5915 GEN_STORE_FTN_FREG(fd
, WT2
);
5919 check_cp1_64bitmode(ctx
);
5920 GEN_LOAD_FREG_FTN(WT0
, fs
);
5921 GEN_LOAD_FREG_FTN(WT1
, ft
);
5922 gen_op_float_pll_ps();
5923 GEN_STORE_FTN_FREG(fd
, DT2
);
5927 check_cp1_64bitmode(ctx
);
5928 GEN_LOAD_FREG_FTN(WT0
, fs
);
5929 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5930 gen_op_float_plu_ps();
5931 GEN_STORE_FTN_FREG(fd
, DT2
);
5935 check_cp1_64bitmode(ctx
);
5936 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5937 GEN_LOAD_FREG_FTN(WT1
, ft
);
5938 gen_op_float_pul_ps();
5939 GEN_STORE_FTN_FREG(fd
, DT2
);
5943 check_cp1_64bitmode(ctx
);
5944 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5945 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5946 gen_op_float_puu_ps();
5947 GEN_STORE_FTN_FREG(fd
, DT2
);
5966 check_cp1_64bitmode(ctx
);
5967 GEN_LOAD_FREG_FTN(WT0
, fs
);
5968 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5969 GEN_LOAD_FREG_FTN(WT1
, ft
);
5970 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5971 if (ctx
->opcode
& (1 << 6)) {
5972 gen_cmpabs_ps(func
-48, cc
);
5973 opn
= condnames_abs
[func
-48];
5975 gen_cmp_ps(func
-48, cc
);
5976 opn
= condnames
[func
-48];
5981 generate_exception (ctx
, EXCP_RI
);
5986 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
5989 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
5992 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
5997 /* Coprocessor 3 (FPU) */
5998 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
5999 int fd
, int fs
, int base
, int index
)
6001 const char *opn
= "extended float load/store";
6008 GEN_LOAD_REG_T0(index
);
6009 } else if (index
== 0) {
6010 GEN_LOAD_REG_T0(base
);
6012 GEN_LOAD_REG_T0(base
);
6013 GEN_LOAD_REG_T1(index
);
6016 /* Don't do NOP if destination is zero: we must perform the actual
6022 GEN_STORE_FTN_FREG(fd
, WT0
);
6027 check_cp1_registers(ctx
, fd
);
6029 GEN_STORE_FTN_FREG(fd
, DT0
);
6033 check_cp1_64bitmode(ctx
);
6035 GEN_STORE_FTN_FREG(fd
, DT0
);
6040 GEN_LOAD_FREG_FTN(WT0
, fs
);
6047 check_cp1_registers(ctx
, fs
);
6048 GEN_LOAD_FREG_FTN(DT0
, fs
);
6054 check_cp1_64bitmode(ctx
);
6055 GEN_LOAD_FREG_FTN(DT0
, fs
);
6062 generate_exception(ctx
, EXCP_RI
);
6065 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
6066 regnames
[index
], regnames
[base
]);
6069 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
6070 int fd
, int fr
, int fs
, int ft
)
6072 const char *opn
= "flt3_arith";
6076 check_cp1_64bitmode(ctx
);
6077 GEN_LOAD_REG_T0(fr
);
6078 GEN_LOAD_FREG_FTN(DT0
, fs
);
6079 GEN_LOAD_FREG_FTN(DT1
, ft
);
6080 gen_op_float_alnv_ps();
6081 GEN_STORE_FTN_FREG(fd
, DT2
);
6086 GEN_LOAD_FREG_FTN(WT0
, fs
);
6087 GEN_LOAD_FREG_FTN(WT1
, ft
);
6088 GEN_LOAD_FREG_FTN(WT2
, fr
);
6089 gen_op_float_muladd_s();
6090 GEN_STORE_FTN_FREG(fd
, WT2
);
6095 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
6096 GEN_LOAD_FREG_FTN(DT0
, fs
);
6097 GEN_LOAD_FREG_FTN(DT1
, ft
);
6098 GEN_LOAD_FREG_FTN(DT2
, fr
);
6099 gen_op_float_muladd_d();
6100 GEN_STORE_FTN_FREG(fd
, DT2
);
6104 check_cp1_64bitmode(ctx
);
6105 GEN_LOAD_FREG_FTN(WT0
, fs
);
6106 GEN_LOAD_FREG_FTN(WTH0
, fs
);
6107 GEN_LOAD_FREG_FTN(WT1
, ft
);
6108 GEN_LOAD_FREG_FTN(WTH1
, ft
);
6109 GEN_LOAD_FREG_FTN(WT2
, fr
);
6110 GEN_LOAD_FREG_FTN(WTH2
, fr
);
6111 gen_op_float_muladd_ps();
6112 GEN_STORE_FTN_FREG(fd
, WT2
);
6113 GEN_STORE_FTN_FREG(fd
, WTH2
);
6118 GEN_LOAD_FREG_FTN(WT0
, fs
);
6119 GEN_LOAD_FREG_FTN(WT1
, ft
);
6120 GEN_LOAD_FREG_FTN(WT2
, fr
);
6121 gen_op_float_mulsub_s();
6122 GEN_STORE_FTN_FREG(fd
, WT2
);
6127 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
6128 GEN_LOAD_FREG_FTN(DT0
, fs
);
6129 GEN_LOAD_FREG_FTN(DT1
, ft
);
6130 GEN_LOAD_FREG_FTN(DT2
, fr
);
6131 gen_op_float_mulsub_d();
6132 GEN_STORE_FTN_FREG(fd
, DT2
);
6136 check_cp1_64bitmode(ctx
);
6137 GEN_LOAD_FREG_FTN(WT0
, fs
);
6138 GEN_LOAD_FREG_FTN(WTH0
, fs
);
6139 GEN_LOAD_FREG_FTN(WT1
, ft
);
6140 GEN_LOAD_FREG_FTN(WTH1
, ft
);
6141 GEN_LOAD_FREG_FTN(WT2
, fr
);
6142 GEN_LOAD_FREG_FTN(WTH2
, fr
);
6143 gen_op_float_mulsub_ps();
6144 GEN_STORE_FTN_FREG(fd
, WT2
);
6145 GEN_STORE_FTN_FREG(fd
, WTH2
);
6150 GEN_LOAD_FREG_FTN(WT0
, fs
);
6151 GEN_LOAD_FREG_FTN(WT1
, ft
);
6152 GEN_LOAD_FREG_FTN(WT2
, fr
);
6153 gen_op_float_nmuladd_s();
6154 GEN_STORE_FTN_FREG(fd
, WT2
);
6159 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
6160 GEN_LOAD_FREG_FTN(DT0
, fs
);
6161 GEN_LOAD_FREG_FTN(DT1
, ft
);
6162 GEN_LOAD_FREG_FTN(DT2
, fr
);
6163 gen_op_float_nmuladd_d();
6164 GEN_STORE_FTN_FREG(fd
, DT2
);
6168 check_cp1_64bitmode(ctx
);
6169 GEN_LOAD_FREG_FTN(WT0
, fs
);
6170 GEN_LOAD_FREG_FTN(WTH0
, fs
);
6171 GEN_LOAD_FREG_FTN(WT1
, ft
);
6172 GEN_LOAD_FREG_FTN(WTH1
, ft
);
6173 GEN_LOAD_FREG_FTN(WT2
, fr
);
6174 GEN_LOAD_FREG_FTN(WTH2
, fr
);
6175 gen_op_float_nmuladd_ps();
6176 GEN_STORE_FTN_FREG(fd
, WT2
);
6177 GEN_STORE_FTN_FREG(fd
, WTH2
);
6182 GEN_LOAD_FREG_FTN(WT0
, fs
);
6183 GEN_LOAD_FREG_FTN(WT1
, ft
);
6184 GEN_LOAD_FREG_FTN(WT2
, fr
);
6185 gen_op_float_nmulsub_s();
6186 GEN_STORE_FTN_FREG(fd
, WT2
);
6191 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
6192 GEN_LOAD_FREG_FTN(DT0
, fs
);
6193 GEN_LOAD_FREG_FTN(DT1
, ft
);
6194 GEN_LOAD_FREG_FTN(DT2
, fr
);
6195 gen_op_float_nmulsub_d();
6196 GEN_STORE_FTN_FREG(fd
, DT2
);
6200 check_cp1_64bitmode(ctx
);
6201 GEN_LOAD_FREG_FTN(WT0
, fs
);
6202 GEN_LOAD_FREG_FTN(WTH0
, fs
);
6203 GEN_LOAD_FREG_FTN(WT1
, ft
);
6204 GEN_LOAD_FREG_FTN(WTH1
, ft
);
6205 GEN_LOAD_FREG_FTN(WT2
, fr
);
6206 GEN_LOAD_FREG_FTN(WTH2
, fr
);
6207 gen_op_float_nmulsub_ps();
6208 GEN_STORE_FTN_FREG(fd
, WT2
);
6209 GEN_STORE_FTN_FREG(fd
, WTH2
);
6214 generate_exception (ctx
, EXCP_RI
);
6217 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
6218 fregnames
[fs
], fregnames
[ft
]);
6221 /* ISA extensions (ASEs) */
6222 /* MIPS16 extension to MIPS32 */
6223 /* SmartMIPS extension to MIPS32 */
6225 #if defined(TARGET_MIPS64)
6227 /* MDMX extension to MIPS64 */
6231 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
6235 uint32_t op
, op1
, op2
;
6238 /* make sure instructions are on a word boundary */
6239 if (ctx
->pc
& 0x3) {
6240 env
->CP0_BadVAddr
= ctx
->pc
;
6241 generate_exception(ctx
, EXCP_AdEL
);
6245 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
6247 /* Handle blikely not taken case */
6248 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
6249 l1
= gen_new_label();
6250 tcg_gen_jnz_bcond(l1
);
6251 gen_op_save_state(ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
6252 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
6255 op
= MASK_OP_MAJOR(ctx
->opcode
);
6256 rs
= (ctx
->opcode
>> 21) & 0x1f;
6257 rt
= (ctx
->opcode
>> 16) & 0x1f;
6258 rd
= (ctx
->opcode
>> 11) & 0x1f;
6259 sa
= (ctx
->opcode
>> 6) & 0x1f;
6260 imm
= (int16_t)ctx
->opcode
;
6263 op1
= MASK_SPECIAL(ctx
->opcode
);
6265 case OPC_SLL
: /* Arithmetic with immediate */
6266 case OPC_SRL
... OPC_SRA
:
6267 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
6269 case OPC_MOVZ
... OPC_MOVN
:
6270 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
6271 case OPC_SLLV
: /* Arithmetic */
6272 case OPC_SRLV
... OPC_SRAV
:
6273 case OPC_ADD
... OPC_NOR
:
6274 case OPC_SLT
... OPC_SLTU
:
6275 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
6277 case OPC_MULT
... OPC_DIVU
:
6279 check_insn(env
, ctx
, INSN_VR54XX
);
6280 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
6281 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
6283 gen_muldiv(ctx
, op1
, rs
, rt
);
6285 case OPC_JR
... OPC_JALR
:
6286 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
6288 case OPC_TGE
... OPC_TEQ
: /* Traps */
6290 gen_trap(ctx
, op1
, rs
, rt
, -1);
6292 case OPC_MFHI
: /* Move from HI/LO */
6294 gen_HILO(ctx
, op1
, rd
);
6297 case OPC_MTLO
: /* Move to HI/LO */
6298 gen_HILO(ctx
, op1
, rs
);
6300 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
6301 #ifdef MIPS_STRICT_STANDARD
6302 MIPS_INVAL("PMON / selsl");
6303 generate_exception(ctx
, EXCP_RI
);
6309 generate_exception(ctx
, EXCP_SYSCALL
);
6312 generate_exception(ctx
, EXCP_BREAK
);
6315 #ifdef MIPS_STRICT_STANDARD
6317 generate_exception(ctx
, EXCP_RI
);
6319 /* Implemented as RI exception for now. */
6320 MIPS_INVAL("spim (unofficial)");
6321 generate_exception(ctx
, EXCP_RI
);
6329 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
6330 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6331 save_cpu_state(ctx
, 1);
6332 check_cp1_enabled(ctx
);
6333 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
6334 (ctx
->opcode
>> 16) & 1);
6336 generate_exception_err(ctx
, EXCP_CpU
, 1);
6340 #if defined(TARGET_MIPS64)
6341 /* MIPS64 specific opcodes */
6343 case OPC_DSRL
... OPC_DSRA
:
6345 case OPC_DSRL32
... OPC_DSRA32
:
6346 check_insn(env
, ctx
, ISA_MIPS3
);
6348 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
6351 case OPC_DSRLV
... OPC_DSRAV
:
6352 case OPC_DADD
... OPC_DSUBU
:
6353 check_insn(env
, ctx
, ISA_MIPS3
);
6355 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
6357 case OPC_DMULT
... OPC_DDIVU
:
6358 check_insn(env
, ctx
, ISA_MIPS3
);
6360 gen_muldiv(ctx
, op1
, rs
, rt
);
6363 default: /* Invalid */
6364 MIPS_INVAL("special");
6365 generate_exception(ctx
, EXCP_RI
);
6370 op1
= MASK_SPECIAL2(ctx
->opcode
);
6372 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
6373 case OPC_MSUB
... OPC_MSUBU
:
6374 check_insn(env
, ctx
, ISA_MIPS32
);
6375 gen_muldiv(ctx
, op1
, rs
, rt
);
6378 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
6380 case OPC_CLZ
... OPC_CLO
:
6381 check_insn(env
, ctx
, ISA_MIPS32
);
6382 gen_cl(ctx
, op1
, rd
, rs
);
6385 /* XXX: not clear which exception should be raised
6386 * when in debug mode...
6388 check_insn(env
, ctx
, ISA_MIPS32
);
6389 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
6390 generate_exception(ctx
, EXCP_DBp
);
6392 generate_exception(ctx
, EXCP_DBp
);
6396 #if defined(TARGET_MIPS64)
6397 case OPC_DCLZ
... OPC_DCLO
:
6398 check_insn(env
, ctx
, ISA_MIPS64
);
6400 gen_cl(ctx
, op1
, rd
, rs
);
6403 default: /* Invalid */
6404 MIPS_INVAL("special2");
6405 generate_exception(ctx
, EXCP_RI
);
6410 op1
= MASK_SPECIAL3(ctx
->opcode
);
6414 check_insn(env
, ctx
, ISA_MIPS32R2
);
6415 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
6418 check_insn(env
, ctx
, ISA_MIPS32R2
);
6419 op2
= MASK_BSHFL(ctx
->opcode
);
6422 GEN_LOAD_REG_T1(rt
);
6426 GEN_LOAD_REG_T1(rt
);
6430 GEN_LOAD_REG_T1(rt
);
6433 default: /* Invalid */
6434 MIPS_INVAL("bshfl");
6435 generate_exception(ctx
, EXCP_RI
);
6438 GEN_STORE_T0_REG(rd
);
6441 check_insn(env
, ctx
, ISA_MIPS32R2
);
6444 save_cpu_state(ctx
, 1);
6445 gen_op_rdhwr_cpunum();
6448 save_cpu_state(ctx
, 1);
6449 gen_op_rdhwr_synci_step();
6452 save_cpu_state(ctx
, 1);
6456 save_cpu_state(ctx
, 1);
6457 gen_op_rdhwr_ccres();
6460 #if defined (CONFIG_USER_ONLY)
6464 default: /* Invalid */
6465 MIPS_INVAL("rdhwr");
6466 generate_exception(ctx
, EXCP_RI
);
6469 GEN_STORE_T0_REG(rt
);
6472 check_insn(env
, ctx
, ASE_MT
);
6473 GEN_LOAD_REG_T0(rt
);
6474 GEN_LOAD_REG_T1(rs
);
6478 check_insn(env
, ctx
, ASE_MT
);
6479 GEN_LOAD_REG_T0(rs
);
6481 GEN_STORE_T0_REG(rd
);
6483 #if defined(TARGET_MIPS64)
6484 case OPC_DEXTM
... OPC_DEXT
:
6485 case OPC_DINSM
... OPC_DINS
:
6486 check_insn(env
, ctx
, ISA_MIPS64R2
);
6488 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
6491 check_insn(env
, ctx
, ISA_MIPS64R2
);
6493 op2
= MASK_DBSHFL(ctx
->opcode
);
6496 GEN_LOAD_REG_T1(rt
);
6500 GEN_LOAD_REG_T1(rt
);
6503 default: /* Invalid */
6504 MIPS_INVAL("dbshfl");
6505 generate_exception(ctx
, EXCP_RI
);
6508 GEN_STORE_T0_REG(rd
);
6511 default: /* Invalid */
6512 MIPS_INVAL("special3");
6513 generate_exception(ctx
, EXCP_RI
);
6518 op1
= MASK_REGIMM(ctx
->opcode
);
6520 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
6521 case OPC_BLTZAL
... OPC_BGEZALL
:
6522 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
6524 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
6526 gen_trap(ctx
, op1
, rs
, -1, imm
);
6529 check_insn(env
, ctx
, ISA_MIPS32R2
);
6532 default: /* Invalid */
6533 MIPS_INVAL("regimm");
6534 generate_exception(ctx
, EXCP_RI
);
6539 check_cp0_enabled(ctx
);
6540 op1
= MASK_CP0(ctx
->opcode
);
6546 #if defined(TARGET_MIPS64)
6550 gen_cp0(env
, ctx
, op1
, rt
, rd
);
6552 case OPC_C0_FIRST
... OPC_C0_LAST
:
6553 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
6556 op2
= MASK_MFMC0(ctx
->opcode
);
6559 check_insn(env
, ctx
, ASE_MT
);
6563 check_insn(env
, ctx
, ASE_MT
);
6567 check_insn(env
, ctx
, ASE_MT
);
6571 check_insn(env
, ctx
, ASE_MT
);
6575 check_insn(env
, ctx
, ISA_MIPS32R2
);
6576 save_cpu_state(ctx
, 1);
6578 /* Stop translation as we may have switched the execution mode */
6579 ctx
->bstate
= BS_STOP
;
6582 check_insn(env
, ctx
, ISA_MIPS32R2
);
6583 save_cpu_state(ctx
, 1);
6585 /* Stop translation as we may have switched the execution mode */
6586 ctx
->bstate
= BS_STOP
;
6588 default: /* Invalid */
6589 MIPS_INVAL("mfmc0");
6590 generate_exception(ctx
, EXCP_RI
);
6593 GEN_STORE_T0_REG(rt
);
6596 check_insn(env
, ctx
, ISA_MIPS32R2
);
6597 GEN_LOAD_SRSREG_TN(T0
, rt
);
6598 GEN_STORE_T0_REG(rd
);
6601 check_insn(env
, ctx
, ISA_MIPS32R2
);
6602 GEN_LOAD_REG_T0(rt
);
6603 GEN_STORE_TN_SRSREG(rd
, T0
);
6607 generate_exception(ctx
, EXCP_RI
);
6611 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
6612 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
6614 case OPC_J
... OPC_JAL
: /* Jump */
6615 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
6616 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
6618 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
6619 case OPC_BEQL
... OPC_BGTZL
:
6620 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
6622 case OPC_LB
... OPC_LWR
: /* Load and stores */
6623 case OPC_SB
... OPC_SW
:
6627 gen_ldst(ctx
, op
, rt
, rs
, imm
);
6630 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
6634 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
6638 /* Floating point (COP1). */
6643 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6644 save_cpu_state(ctx
, 1);
6645 check_cp1_enabled(ctx
);
6646 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
6648 generate_exception_err(ctx
, EXCP_CpU
, 1);
6653 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6654 save_cpu_state(ctx
, 1);
6655 check_cp1_enabled(ctx
);
6656 op1
= MASK_CP1(ctx
->opcode
);
6660 check_insn(env
, ctx
, ISA_MIPS32R2
);
6665 gen_cp1(ctx
, op1
, rt
, rd
);
6667 #if defined(TARGET_MIPS64)
6670 check_insn(env
, ctx
, ISA_MIPS3
);
6671 gen_cp1(ctx
, op1
, rt
, rd
);
6677 check_insn(env
, ctx
, ASE_MIPS3D
);
6680 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
6681 (rt
>> 2) & 0x7, imm
<< 2);
6688 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
6693 generate_exception (ctx
, EXCP_RI
);
6697 generate_exception_err(ctx
, EXCP_CpU
, 1);
6707 /* COP2: Not implemented. */
6708 generate_exception_err(ctx
, EXCP_CpU
, 2);
6712 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6713 save_cpu_state(ctx
, 1);
6714 check_cp1_enabled(ctx
);
6715 op1
= MASK_CP3(ctx
->opcode
);
6723 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
6741 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
6745 generate_exception (ctx
, EXCP_RI
);
6749 generate_exception_err(ctx
, EXCP_CpU
, 1);
6753 #if defined(TARGET_MIPS64)
6754 /* MIPS64 opcodes */
6756 case OPC_LDL
... OPC_LDR
:
6757 case OPC_SDL
... OPC_SDR
:
6762 check_insn(env
, ctx
, ISA_MIPS3
);
6764 gen_ldst(ctx
, op
, rt
, rs
, imm
);
6766 case OPC_DADDI
... OPC_DADDIU
:
6767 check_insn(env
, ctx
, ISA_MIPS3
);
6769 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
6773 check_insn(env
, ctx
, ASE_MIPS16
);
6774 /* MIPS16: Not implemented. */
6776 check_insn(env
, ctx
, ASE_MDMX
);
6777 /* MDMX: Not implemented. */
6778 default: /* Invalid */
6779 MIPS_INVAL("major opcode");
6780 generate_exception(ctx
, EXCP_RI
);
6783 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
6784 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
6785 /* Branches completion */
6786 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
6787 ctx
->bstate
= BS_BRANCH
;
6788 save_cpu_state(ctx
, 0);
6791 /* unconditional branch */
6792 MIPS_DEBUG("unconditional branch");
6793 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6796 /* blikely taken case */
6797 MIPS_DEBUG("blikely branch taken");
6798 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6801 /* Conditional branch */
6802 MIPS_DEBUG("conditional branch");
6805 l1
= gen_new_label();
6806 tcg_gen_jnz_bcond(l1
);
6807 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
6809 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6813 /* unconditional branch to register */
6814 MIPS_DEBUG("branch to register");
6819 MIPS_DEBUG("unknown branch");
6825 static always_inline
int
6826 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
6830 target_ulong pc_start
;
6831 uint16_t *gen_opc_end
;
6834 if (search_pc
&& loglevel
)
6835 fprintf (logfile
, "search pc %d\n", search_pc
);
6838 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
6842 ctx
.bstate
= BS_NONE
;
6843 /* Restore delay slot state from the tb context. */
6844 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
6845 restore_cpu_state(env
, &ctx
);
6846 #if defined(CONFIG_USER_ONLY)
6847 ctx
.mem_idx
= MIPS_HFLAG_UM
;
6849 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
6852 if (loglevel
& CPU_LOG_TB_CPU
) {
6853 fprintf(logfile
, "------------------------------------------------\n");
6854 /* FIXME: This may print out stale hflags from env... */
6855 cpu_dump_state(env
, logfile
, fprintf
, 0);
6858 #ifdef MIPS_DEBUG_DISAS
6859 if (loglevel
& CPU_LOG_TB_IN_ASM
)
6860 fprintf(logfile
, "\ntb %p idx %d hflags %04x\n",
6861 tb
, ctx
.mem_idx
, ctx
.hflags
);
6863 while (ctx
.bstate
== BS_NONE
&& gen_opc_ptr
< gen_opc_end
) {
6864 if (env
->nb_breakpoints
> 0) {
6865 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
6866 if (env
->breakpoints
[j
] == ctx
.pc
) {
6867 save_cpu_state(&ctx
, 1);
6868 ctx
.bstate
= BS_BRANCH
;
6870 /* Include the breakpoint location or the tb won't
6871 * be flushed when it must be. */
6873 goto done_generating
;
6879 j
= gen_opc_ptr
- gen_opc_buf
;
6883 gen_opc_instr_start
[lj
++] = 0;
6885 gen_opc_pc
[lj
] = ctx
.pc
;
6886 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
6887 gen_opc_instr_start
[lj
] = 1;
6889 ctx
.opcode
= ldl_code(ctx
.pc
);
6890 decode_opc(env
, &ctx
);
6893 if (env
->singlestep_enabled
)
6896 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
6899 #if defined (MIPS_SINGLE_STEP)
6903 if (env
->singlestep_enabled
) {
6904 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
6907 switch (ctx
.bstate
) {
6909 gen_op_interrupt_restart();
6910 gen_goto_tb(&ctx
, 0, ctx
.pc
);
6913 save_cpu_state(&ctx
, 0);
6914 gen_goto_tb(&ctx
, 0, ctx
.pc
);
6917 gen_op_interrupt_restart();
6926 ctx
.last_T0_store
= NULL
;
6927 *gen_opc_ptr
= INDEX_op_end
;
6929 j
= gen_opc_ptr
- gen_opc_buf
;
6932 gen_opc_instr_start
[lj
++] = 0;
6934 tb
->size
= ctx
.pc
- pc_start
;
6937 #if defined MIPS_DEBUG_DISAS
6938 if (loglevel
& CPU_LOG_TB_IN_ASM
)
6939 fprintf(logfile
, "\n");
6941 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6942 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
6943 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
6944 fprintf(logfile
, "\n");
6946 if (loglevel
& CPU_LOG_TB_CPU
) {
6947 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
6954 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
6956 return gen_intermediate_code_internal(env
, tb
, 0);
6959 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
6961 return gen_intermediate_code_internal(env
, tb
, 1);
6964 void fpu_dump_state(CPUState
*env
, FILE *f
,
6965 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6969 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
6971 #define printfpr(fp) \
6974 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
6975 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
6976 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
6979 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
6980 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
6981 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
6982 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
6983 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
6988 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
6989 env
->fpu
->fcr0
, env
->fpu
->fcr31
, is_fpu64
, env
->fpu
->fp_status
,
6990 get_float_exception_flags(&env
->fpu
->fp_status
));
6991 fpu_fprintf(f
, "FT0: "); printfpr(&env
->fpu
->ft0
);
6992 fpu_fprintf(f
, "FT1: "); printfpr(&env
->fpu
->ft1
);
6993 fpu_fprintf(f
, "FT2: "); printfpr(&env
->fpu
->ft2
);
6994 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
6995 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
6996 printfpr(&env
->fpu
->fpr
[i
]);
7002 void dump_fpu (CPUState
*env
)
7006 "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
7007 " LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
7009 env
->PC
[env
->current_tc
], env
->HI
[env
->current_tc
][0],
7010 env
->LO
[env
->current_tc
][0], env
->hflags
, env
->btarget
,
7012 fpu_dump_state(env
, logfile
, fprintf
, 0);
7016 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
7017 /* Debug help: The architecture requires 32bit code to maintain proper
7018 sign-extened values on 64bit machines. */
7020 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
7022 void cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
7023 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
7028 if (!SIGN_EXT_P(env
->PC
[env
->current_tc
]))
7029 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->PC
[env
->current_tc
]);
7030 if (!SIGN_EXT_P(env
->HI
[env
->current_tc
][0]))
7031 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->HI
[env
->current_tc
][0]);
7032 if (!SIGN_EXT_P(env
->LO
[env
->current_tc
][0]))
7033 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->LO
[env
->current_tc
][0]);
7034 if (!SIGN_EXT_P(env
->btarget
))
7035 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
7037 for (i
= 0; i
< 32; i
++) {
7038 if (!SIGN_EXT_P(env
->gpr
[env
->current_tc
][i
]))
7039 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->gpr
[env
->current_tc
][i
]);
7042 if (!SIGN_EXT_P(env
->CP0_EPC
))
7043 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
7044 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
7045 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
7049 void cpu_dump_state (CPUState
*env
, FILE *f
,
7050 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
7055 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
7056 env
->PC
[env
->current_tc
], env
->HI
[env
->current_tc
], env
->LO
[env
->current_tc
], env
->hflags
, env
->btarget
, env
->bcond
);
7057 for (i
= 0; i
< 32; i
++) {
7059 cpu_fprintf(f
, "GPR%02d:", i
);
7060 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->gpr
[env
->current_tc
][i
]);
7062 cpu_fprintf(f
, "\n");
7065 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
7066 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
7067 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
7068 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
7069 if (env
->hflags
& MIPS_HFLAG_FPU
)
7070 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
7071 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
7072 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
7076 static void mips_tcg_init(void)
7080 /* Initialize various static tables. */
7084 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
7085 current_tc_gprs
= tcg_global_mem_new(TCG_TYPE_PTR
,
7087 offsetof(CPUState
, current_tc_gprs
),
7089 #if TARGET_LONG_BITS > HOST_LONG_BITS
7090 cpu_T
[0] = tcg_global_mem_new(TCG_TYPE_TL
,
7091 TCG_AREG0
, offsetof(CPUState
, t0
), "T0");
7092 cpu_T
[1] = tcg_global_mem_new(TCG_TYPE_TL
,
7093 TCG_AREG0
, offsetof(CPUState
, t1
), "T1");
7095 cpu_T
[0] = tcg_global_reg_new(TCG_TYPE_TL
, TCG_AREG1
, "T0");
7096 cpu_T
[1] = tcg_global_reg_new(TCG_TYPE_TL
, TCG_AREG2
, "T1");
7102 #include "translate_init.c"
7104 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
7107 const mips_def_t
*def
;
7109 def
= cpu_mips_find_by_name(cpu_model
);
7112 env
= qemu_mallocz(sizeof(CPUMIPSState
));
7115 env
->cpu_model
= def
;
7118 env
->cpu_model_str
= cpu_model
;
7124 void cpu_reset (CPUMIPSState
*env
)
7126 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
7131 #if !defined(CONFIG_USER_ONLY)
7132 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
7133 /* If the exception was raised from a delay slot,
7134 * come back to the jump. */
7135 env
->CP0_ErrorEPC
= env
->PC
[env
->current_tc
] - 4;
7137 env
->CP0_ErrorEPC
= env
->PC
[env
->current_tc
];
7139 env
->PC
[env
->current_tc
] = (int32_t)0xBFC00000;
7141 /* SMP not implemented */
7142 env
->CP0_EBase
= 0x80000000;
7143 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
7144 /* vectored interrupts not implemented, timer on int 7,
7145 no performance counters. */
7146 env
->CP0_IntCtl
= 0xe0000000;
7150 for (i
= 0; i
< 7; i
++) {
7151 env
->CP0_WatchLo
[i
] = 0;
7152 env
->CP0_WatchHi
[i
] = 0x80000000;
7154 env
->CP0_WatchLo
[7] = 0;
7155 env
->CP0_WatchHi
[7] = 0;
7157 /* Count register increments in debug mode, EJTAG version 1 */
7158 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
7160 env
->exception_index
= EXCP_NONE
;
7161 #if defined(CONFIG_USER_ONLY)
7162 env
->hflags
= MIPS_HFLAG_UM
;
7163 env
->user_mode_only
= 1;
7165 env
->hflags
= MIPS_HFLAG_CP0
;
7167 cpu_mips_register(env
, env
->cpu_model
);
7170 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
7171 unsigned long searched_pc
, int pc_pos
, void *puc
)
7173 env
->PC
[env
->current_tc
] = gen_opc_pc
[pc_pos
];
7174 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
7175 env
->hflags
|= gen_opc_hflags
[pc_pos
];