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Stop dirty logging while updating cirrus bank memory
[qemu-kvm/fedora.git] / hw / cirrus_vga.c
blob4c99d0dab9c1577dc0ac98d6d2b387b4d9ecf431
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "kvm.h"
35 #include "qemu-kvm.h"
36
37 /*
38 * TODO:
39 * - destination write mask support not complete (bits 5..7)
40 * - optimize linear mappings
41 * - optimize bitblt functions
42 */
43
44 //#define DEBUG_CIRRUS
45 //#define DEBUG_BITBLT
46
47 /***************************************
48 *
49 * definitions
50 *
51 ***************************************/
52
53 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
54
55 // ID
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64
65 // sequencer 0x07
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75
76 // sequencer 0x0f
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81
82 // sequencer 0x12
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86
87 // sequencer 0x17
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95
96 // control 0x0b
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99
100 // control 0x30
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112
113 // control 0x31
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
119
120 // control 0x32
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
137
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
140
141 // control 0x33
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145
146 // memory-mapped IO
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
176
177 // PCI 0x00: vendor, 0x02: device
178 #define PCI_VENDOR_CIRRUS 0x1013
179 #define PCI_DEVICE_CLGD5462 0x00d0
180 #define PCI_DEVICE_CLGD5465 0x00d6
181
182 // PCI 0x04: command(word), 0x06(word): status
183 #define PCI_COMMAND_IOACCESS 0x0001
184 #define PCI_COMMAND_MEMACCESS 0x0002
185 #define PCI_COMMAND_BUSMASTER 0x0004
186 #define PCI_COMMAND_SPECIALCYCLE 0x0008
187 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
188 #define PCI_COMMAND_PALETTESNOOPING 0x0020
189 #define PCI_COMMAND_PARITYDETECTION 0x0040
190 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
191 #define PCI_COMMAND_SERR 0x0100
192 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
193 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
194 #define PCI_CLASS_BASE_DISPLAY 0x03
195 // PCI 0x08, 0x00ff0000
196 #define PCI_CLASS_SUB_VGA 0x00
197 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
198 #define PCI_CLASS_HEADERTYPE_00h 0x00
199 // 0x10-0x3f (headertype 00h)
200 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
201 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
202 #define PCI_MAP_MEM 0x0
203 #define PCI_MAP_IO 0x1
204 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
205 #define PCI_MAP_IO_ADDR_MASK (~0x3)
206 #define PCI_MAP_MEMFLAGS_32BIT 0x0
207 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
208 #define PCI_MAP_MEMFLAGS_64BIT 0x4
209 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
210 // PCI 0x28: cardbus CIS pointer
211 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
212 // PCI 0x30: expansion ROM base address
213 #define PCI_ROMBIOS_ENABLED 0x1
214 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
215 // PCI 0x38: reserved
216 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
217
218 #define CIRRUS_PNPMMIO_SIZE 0x1000
219
220
221 /* I/O and memory hook */
222 #define CIRRUS_HOOK_NOT_HANDLED 0
223 #define CIRRUS_HOOK_HANDLED 1
224
225 #define BLTUNSAFE(s) \
226 ( \
227 ( /* check dst is within bounds */ \
228 (s)->cirrus_blt_height * (s)->cirrus_blt_dstpitch \
229 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
230 (s)->vram_size \
231 ) || \
232 ( /* check src is within bounds */ \
233 (s)->cirrus_blt_height * (s)->cirrus_blt_srcpitch \
234 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
235 (s)->vram_size \
236 ) \
237 )
238
239 struct CirrusVGAState;
240 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
241 uint8_t * dst, const uint8_t * src,
242 int dstpitch, int srcpitch,
243 int bltwidth, int bltheight);
244 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
245 uint8_t *dst, int dst_pitch, int width, int height);
246
247 typedef struct CirrusVGAState {
248 VGA_STATE_COMMON
249
250 int cirrus_linear_io_addr;
251 int cirrus_linear_bitblt_io_addr;
252 int cirrus_mmio_io_addr;
253 uint32_t cirrus_addr_mask;
254 uint32_t linear_mmio_mask;
255 uint8_t cirrus_shadow_gr0;
256 uint8_t cirrus_shadow_gr1;
257 uint8_t cirrus_hidden_dac_lockindex;
258 uint8_t cirrus_hidden_dac_data;
259 uint32_t cirrus_bank_base[2];
260 uint32_t cirrus_bank_limit[2];
261 uint8_t cirrus_hidden_palette[48];
262 uint32_t hw_cursor_x;
263 uint32_t hw_cursor_y;
264 int cirrus_blt_pixelwidth;
265 int cirrus_blt_width;
266 int cirrus_blt_height;
267 int cirrus_blt_dstpitch;
268 int cirrus_blt_srcpitch;
269 uint32_t cirrus_blt_fgcol;
270 uint32_t cirrus_blt_bgcol;
271 uint32_t cirrus_blt_dstaddr;
272 uint32_t cirrus_blt_srcaddr;
273 uint8_t cirrus_blt_mode;
274 uint8_t cirrus_blt_modeext;
275 cirrus_bitblt_rop_t cirrus_rop;
276 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
277 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
278 uint8_t *cirrus_srcptr;
279 uint8_t *cirrus_srcptr_end;
280 uint32_t cirrus_srccounter;
281 /* hwcursor display state */
282 int last_hw_cursor_size;
283 int last_hw_cursor_x;
284 int last_hw_cursor_y;
285 int last_hw_cursor_y_start;
286 int last_hw_cursor_y_end;
287 int real_vram_size; /* XXX: suppress that */
288 CPUWriteMemoryFunc **cirrus_linear_write;
289 } CirrusVGAState;
290
291 typedef struct PCICirrusVGAState {
292 PCIDevice dev;
293 CirrusVGAState cirrus_vga;
294 } PCICirrusVGAState;
295
296 static uint8_t rop_to_index[256];
297
298 /***************************************
299 *
300 * prototypes.
301 *
302 ***************************************/
303
304
305 static void cirrus_bitblt_reset(CirrusVGAState *s);
306 static void cirrus_update_memory_access(CirrusVGAState *s);
307
308 /***************************************
309 *
310 * raster operations
311 *
312 ***************************************/
313
314 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
315 uint8_t *dst,const uint8_t *src,
316 int dstpitch,int srcpitch,
317 int bltwidth,int bltheight)
318 {
319 }
320
321 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
322 uint8_t *dst,
323 int dstpitch, int bltwidth,int bltheight)
324 {
325 }
326
327 #define ROP_NAME 0
328 #define ROP_OP(d, s) d = 0
329 #include "cirrus_vga_rop.h"
330
331 #define ROP_NAME src_and_dst
332 #define ROP_OP(d, s) d = (s) & (d)
333 #include "cirrus_vga_rop.h"
334
335 #define ROP_NAME src_and_notdst
336 #define ROP_OP(d, s) d = (s) & (~(d))
337 #include "cirrus_vga_rop.h"
338
339 #define ROP_NAME notdst
340 #define ROP_OP(d, s) d = ~(d)
341 #include "cirrus_vga_rop.h"
342
343 #define ROP_NAME src
344 #define ROP_OP(d, s) d = s
345 #include "cirrus_vga_rop.h"
346
347 #define ROP_NAME 1
348 #define ROP_OP(d, s) d = ~0
349 #include "cirrus_vga_rop.h"
350
351 #define ROP_NAME notsrc_and_dst
352 #define ROP_OP(d, s) d = (~(s)) & (d)
353 #include "cirrus_vga_rop.h"
354
355 #define ROP_NAME src_xor_dst
356 #define ROP_OP(d, s) d = (s) ^ (d)
357 #include "cirrus_vga_rop.h"
358
359 #define ROP_NAME src_or_dst
360 #define ROP_OP(d, s) d = (s) | (d)
361 #include "cirrus_vga_rop.h"
362
363 #define ROP_NAME notsrc_or_notdst
364 #define ROP_OP(d, s) d = (~(s)) | (~(d))
365 #include "cirrus_vga_rop.h"
366
367 #define ROP_NAME src_notxor_dst
368 #define ROP_OP(d, s) d = ~((s) ^ (d))
369 #include "cirrus_vga_rop.h"
370
371 #define ROP_NAME src_or_notdst
372 #define ROP_OP(d, s) d = (s) | (~(d))
373 #include "cirrus_vga_rop.h"
374
375 #define ROP_NAME notsrc
376 #define ROP_OP(d, s) d = (~(s))
377 #include "cirrus_vga_rop.h"
378
379 #define ROP_NAME notsrc_or_dst
380 #define ROP_OP(d, s) d = (~(s)) | (d)
381 #include "cirrus_vga_rop.h"
382
383 #define ROP_NAME notsrc_and_notdst
384 #define ROP_OP(d, s) d = (~(s)) & (~(d))
385 #include "cirrus_vga_rop.h"
386
387 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
388 cirrus_bitblt_rop_fwd_0,
389 cirrus_bitblt_rop_fwd_src_and_dst,
390 cirrus_bitblt_rop_nop,
391 cirrus_bitblt_rop_fwd_src_and_notdst,
392 cirrus_bitblt_rop_fwd_notdst,
393 cirrus_bitblt_rop_fwd_src,
394 cirrus_bitblt_rop_fwd_1,
395 cirrus_bitblt_rop_fwd_notsrc_and_dst,
396 cirrus_bitblt_rop_fwd_src_xor_dst,
397 cirrus_bitblt_rop_fwd_src_or_dst,
398 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
399 cirrus_bitblt_rop_fwd_src_notxor_dst,
400 cirrus_bitblt_rop_fwd_src_or_notdst,
401 cirrus_bitblt_rop_fwd_notsrc,
402 cirrus_bitblt_rop_fwd_notsrc_or_dst,
403 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
404 };
405
406 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
407 cirrus_bitblt_rop_bkwd_0,
408 cirrus_bitblt_rop_bkwd_src_and_dst,
409 cirrus_bitblt_rop_nop,
410 cirrus_bitblt_rop_bkwd_src_and_notdst,
411 cirrus_bitblt_rop_bkwd_notdst,
412 cirrus_bitblt_rop_bkwd_src,
413 cirrus_bitblt_rop_bkwd_1,
414 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
415 cirrus_bitblt_rop_bkwd_src_xor_dst,
416 cirrus_bitblt_rop_bkwd_src_or_dst,
417 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
418 cirrus_bitblt_rop_bkwd_src_notxor_dst,
419 cirrus_bitblt_rop_bkwd_src_or_notdst,
420 cirrus_bitblt_rop_bkwd_notsrc,
421 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
422 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
423 };
424
425 #define TRANSP_ROP(name) {\
426 name ## _8,\
427 name ## _16,\
428 }
429 #define TRANSP_NOP(func) {\
430 func,\
431 func,\
432 }
433
434 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
435 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
437 TRANSP_NOP(cirrus_bitblt_rop_nop),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
451 };
452
453 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
454 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
456 TRANSP_NOP(cirrus_bitblt_rop_nop),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
470 };
471
472 #define ROP2(name) {\
473 name ## _8,\
474 name ## _16,\
475 name ## _24,\
476 name ## _32,\
477 }
478
479 #define ROP_NOP2(func) {\
480 func,\
481 func,\
482 func,\
483 func,\
484 }
485
486 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
487 ROP2(cirrus_patternfill_0),
488 ROP2(cirrus_patternfill_src_and_dst),
489 ROP_NOP2(cirrus_bitblt_rop_nop),
490 ROP2(cirrus_patternfill_src_and_notdst),
491 ROP2(cirrus_patternfill_notdst),
492 ROP2(cirrus_patternfill_src),
493 ROP2(cirrus_patternfill_1),
494 ROP2(cirrus_patternfill_notsrc_and_dst),
495 ROP2(cirrus_patternfill_src_xor_dst),
496 ROP2(cirrus_patternfill_src_or_dst),
497 ROP2(cirrus_patternfill_notsrc_or_notdst),
498 ROP2(cirrus_patternfill_src_notxor_dst),
499 ROP2(cirrus_patternfill_src_or_notdst),
500 ROP2(cirrus_patternfill_notsrc),
501 ROP2(cirrus_patternfill_notsrc_or_dst),
502 ROP2(cirrus_patternfill_notsrc_and_notdst),
503 };
504
505 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
506 ROP2(cirrus_colorexpand_transp_0),
507 ROP2(cirrus_colorexpand_transp_src_and_dst),
508 ROP_NOP2(cirrus_bitblt_rop_nop),
509 ROP2(cirrus_colorexpand_transp_src_and_notdst),
510 ROP2(cirrus_colorexpand_transp_notdst),
511 ROP2(cirrus_colorexpand_transp_src),
512 ROP2(cirrus_colorexpand_transp_1),
513 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
514 ROP2(cirrus_colorexpand_transp_src_xor_dst),
515 ROP2(cirrus_colorexpand_transp_src_or_dst),
516 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
517 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
518 ROP2(cirrus_colorexpand_transp_src_or_notdst),
519 ROP2(cirrus_colorexpand_transp_notsrc),
520 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
521 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
522 };
523
524 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
525 ROP2(cirrus_colorexpand_0),
526 ROP2(cirrus_colorexpand_src_and_dst),
527 ROP_NOP2(cirrus_bitblt_rop_nop),
528 ROP2(cirrus_colorexpand_src_and_notdst),
529 ROP2(cirrus_colorexpand_notdst),
530 ROP2(cirrus_colorexpand_src),
531 ROP2(cirrus_colorexpand_1),
532 ROP2(cirrus_colorexpand_notsrc_and_dst),
533 ROP2(cirrus_colorexpand_src_xor_dst),
534 ROP2(cirrus_colorexpand_src_or_dst),
535 ROP2(cirrus_colorexpand_notsrc_or_notdst),
536 ROP2(cirrus_colorexpand_src_notxor_dst),
537 ROP2(cirrus_colorexpand_src_or_notdst),
538 ROP2(cirrus_colorexpand_notsrc),
539 ROP2(cirrus_colorexpand_notsrc_or_dst),
540 ROP2(cirrus_colorexpand_notsrc_and_notdst),
541 };
542
543 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
544 ROP2(cirrus_colorexpand_pattern_transp_0),
545 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
546 ROP_NOP2(cirrus_bitblt_rop_nop),
547 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
548 ROP2(cirrus_colorexpand_pattern_transp_notdst),
549 ROP2(cirrus_colorexpand_pattern_transp_src),
550 ROP2(cirrus_colorexpand_pattern_transp_1),
551 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
552 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
553 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
554 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
555 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
556 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
557 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
558 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
559 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
560 };
561
562 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
563 ROP2(cirrus_colorexpand_pattern_0),
564 ROP2(cirrus_colorexpand_pattern_src_and_dst),
565 ROP_NOP2(cirrus_bitblt_rop_nop),
566 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
567 ROP2(cirrus_colorexpand_pattern_notdst),
568 ROP2(cirrus_colorexpand_pattern_src),
569 ROP2(cirrus_colorexpand_pattern_1),
570 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
571 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
572 ROP2(cirrus_colorexpand_pattern_src_or_dst),
573 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
574 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
575 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
576 ROP2(cirrus_colorexpand_pattern_notsrc),
577 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
578 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
579 };
580
581 static const cirrus_fill_t cirrus_fill[16][4] = {
582 ROP2(cirrus_fill_0),
583 ROP2(cirrus_fill_src_and_dst),
584 ROP_NOP2(cirrus_bitblt_fill_nop),
585 ROP2(cirrus_fill_src_and_notdst),
586 ROP2(cirrus_fill_notdst),
587 ROP2(cirrus_fill_src),
588 ROP2(cirrus_fill_1),
589 ROP2(cirrus_fill_notsrc_and_dst),
590 ROP2(cirrus_fill_src_xor_dst),
591 ROP2(cirrus_fill_src_or_dst),
592 ROP2(cirrus_fill_notsrc_or_notdst),
593 ROP2(cirrus_fill_src_notxor_dst),
594 ROP2(cirrus_fill_src_or_notdst),
595 ROP2(cirrus_fill_notsrc),
596 ROP2(cirrus_fill_notsrc_or_dst),
597 ROP2(cirrus_fill_notsrc_and_notdst),
598 };
599
600 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
601 {
602 unsigned int color;
603 switch (s->cirrus_blt_pixelwidth) {
604 case 1:
605 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
606 break;
607 case 2:
608 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
609 s->cirrus_blt_fgcol = le16_to_cpu(color);
610 break;
611 case 3:
612 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
613 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
614 break;
615 default:
616 case 4:
617 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
618 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
619 s->cirrus_blt_fgcol = le32_to_cpu(color);
620 break;
621 }
622 }
623
624 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
625 {
626 unsigned int color;
627 switch (s->cirrus_blt_pixelwidth) {
628 case 1:
629 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
630 break;
631 case 2:
632 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
633 s->cirrus_blt_bgcol = le16_to_cpu(color);
634 break;
635 case 3:
636 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
637 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
638 break;
639 default:
640 case 4:
641 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
642 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
643 s->cirrus_blt_bgcol = le32_to_cpu(color);
644 break;
645 }
646 }
647
648 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
649 int off_pitch, int bytesperline,
650 int lines)
651 {
652 int y;
653 int off_cur;
654 int off_cur_end;
655
656 for (y = 0; y < lines; y++) {
657 off_cur = off_begin;
658 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
659 off_cur &= TARGET_PAGE_MASK;
660 while (off_cur < off_cur_end) {
661 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
662 off_cur += TARGET_PAGE_SIZE;
663 }
664 off_begin += off_pitch;
665 }
666 }
667
668 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
669 const uint8_t * src)
670 {
671 uint8_t *dst;
672
673 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
674
675 if (BLTUNSAFE(s))
676 return 0;
677
678 (*s->cirrus_rop) (s, dst, src,
679 s->cirrus_blt_dstpitch, 0,
680 s->cirrus_blt_width, s->cirrus_blt_height);
681 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
682 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
683 s->cirrus_blt_height);
684 return 1;
685 }
686
687 /* fill */
688
689 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
690 {
691 cirrus_fill_t rop_func;
692
693 if (BLTUNSAFE(s))
694 return 0;
695 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
696 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
697 s->cirrus_blt_dstpitch,
698 s->cirrus_blt_width, s->cirrus_blt_height);
699 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
700 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
701 s->cirrus_blt_height);
702 cirrus_bitblt_reset(s);
703 return 1;
704 }
705
706 /***************************************
707 *
708 * bitblt (video-to-video)
709 *
710 ***************************************/
711
712 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
713 {
714 return cirrus_bitblt_common_patterncopy(s,
715 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
716 s->cirrus_addr_mask));
717 }
718
719 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
720 {
721 int sx, sy;
722 int dx, dy;
723 int width, height;
724 int depth;
725 int notify = 0;
726
727 depth = s->get_bpp((VGAState *)s) / 8;
728 s->get_resolution((VGAState *)s, &width, &height);
729
730 /* extra x, y */
731 sx = (src % (width * depth)) / depth;
732 sy = (src / (width * depth));
733 dx = (dst % (width *depth)) / depth;
734 dy = (dst / (width * depth));
735
736 /* normalize width */
737 w /= depth;
738
739 /* if we're doing a backward copy, we have to adjust
740 our x/y to be the upper left corner (instead of the lower
741 right corner) */
742 if (s->cirrus_blt_dstpitch < 0) {
743 sx -= (s->cirrus_blt_width / depth) - 1;
744 dx -= (s->cirrus_blt_width / depth) - 1;
745 sy -= s->cirrus_blt_height - 1;
746 dy -= s->cirrus_blt_height - 1;
747 }
748
749 /* are we in the visible portion of memory? */
750 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
751 (sx + w) <= width && (sy + h) <= height &&
752 (dx + w) <= width && (dy + h) <= height) {
753 notify = 1;
754 }
755
756 /* make to sure only copy if it's a plain copy ROP */
757 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
758 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
759 notify = 0;
760
761 /* we have to flush all pending changes so that the copy
762 is generated at the appropriate moment in time */
763 if (notify)
764 vga_hw_update();
765
766 (*s->cirrus_rop) (s, s->vram_ptr +
767 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
768 s->vram_ptr +
769 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
770 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
771 s->cirrus_blt_width, s->cirrus_blt_height);
772
773 if (notify)
774 qemu_console_copy(s->console,
775 sx, sy, dx, dy,
776 s->cirrus_blt_width / depth,
777 s->cirrus_blt_height);
778
779 /* we don't have to notify the display that this portion has
780 changed since qemu_console_copy implies this */
781
782 if (!notify)
783 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
784 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
785 s->cirrus_blt_height);
786 }
787
788 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
789 {
790 if (BLTUNSAFE(s))
791 return 0;
792
793 if (s->ds->dpy_copy) {
794 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
795 s->cirrus_blt_srcaddr - s->start_addr,
796 s->cirrus_blt_width, s->cirrus_blt_height);
797 } else {
798 (*s->cirrus_rop) (s, s->vram_ptr +
799 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
800 s->vram_ptr +
801 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
802 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
803 s->cirrus_blt_width, s->cirrus_blt_height);
804
805 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
806 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
807 s->cirrus_blt_height);
808 }
809
810 return 1;
811 }
812
813 /***************************************
814 *
815 * bitblt (cpu-to-video)
816 *
817 ***************************************/
818
819 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
820 {
821 int copy_count;
822 uint8_t *end_ptr;
823
824 if (s->cirrus_srccounter > 0) {
825 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
826 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
827 the_end:
828 s->cirrus_srccounter = 0;
829 cirrus_bitblt_reset(s);
830 } else {
831 /* at least one scan line */
832 do {
833 (*s->cirrus_rop)(s, s->vram_ptr +
834 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
835 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
836 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
837 s->cirrus_blt_width, 1);
838 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
839 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
840 if (s->cirrus_srccounter <= 0)
841 goto the_end;
842 /* more bytes than needed can be transfered because of
843 word alignment, so we keep them for the next line */
844 /* XXX: keep alignment to speed up transfer */
845 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
846 copy_count = s->cirrus_srcptr_end - end_ptr;
847 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
848 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
849 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
850 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
851 }
852 }
853 }
854
855 /***************************************
856 *
857 * bitblt wrapper
858 *
859 ***************************************/
860
861 static void cirrus_bitblt_reset(CirrusVGAState * s)
862 {
863 s->gr[0x31] &=
864 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
865 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
866 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
867 s->cirrus_srccounter = 0;
868 cirrus_update_memory_access(s);
869 }
870
871 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
872 {
873 int w;
874
875 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
876 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
877 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
878
879 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
880 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
881 s->cirrus_blt_srcpitch = 8;
882 } else {
883 /* XXX: check for 24 bpp */
884 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
885 }
886 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
887 } else {
888 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
889 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
890 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
891 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
892 else
893 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
894 } else {
895 /* always align input size to 32 bits */
896 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
897 }
898 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
899 }
900 s->cirrus_srcptr = s->cirrus_bltbuf;
901 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
902 cirrus_update_memory_access(s);
903 return 1;
904 }
905
906 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
907 {
908 /* XXX */
909 #ifdef DEBUG_BITBLT
910 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
911 #endif
912 return 0;
913 }
914
915 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
916 {
917 int ret;
918
919 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
920 ret = cirrus_bitblt_videotovideo_patterncopy(s);
921 } else {
922 ret = cirrus_bitblt_videotovideo_copy(s);
923 }
924 if (ret)
925 cirrus_bitblt_reset(s);
926 return ret;
927 }
928
929 static void cirrus_bitblt_start(CirrusVGAState * s)
930 {
931 uint8_t blt_rop;
932
933 s->gr[0x31] |= CIRRUS_BLT_BUSY;
934
935 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
936 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
937 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
938 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
939 s->cirrus_blt_dstaddr =
940 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
941 s->cirrus_blt_srcaddr =
942 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
943 s->cirrus_blt_mode = s->gr[0x30];
944 s->cirrus_blt_modeext = s->gr[0x33];
945 blt_rop = s->gr[0x32];
946
947 #ifdef DEBUG_BITBLT
948 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
949 blt_rop,
950 s->cirrus_blt_mode,
951 s->cirrus_blt_modeext,
952 s->cirrus_blt_width,
953 s->cirrus_blt_height,
954 s->cirrus_blt_dstpitch,
955 s->cirrus_blt_srcpitch,
956 s->cirrus_blt_dstaddr,
957 s->cirrus_blt_srcaddr,
958 s->gr[0x2f]);
959 #endif
960
961 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
962 case CIRRUS_BLTMODE_PIXELWIDTH8:
963 s->cirrus_blt_pixelwidth = 1;
964 break;
965 case CIRRUS_BLTMODE_PIXELWIDTH16:
966 s->cirrus_blt_pixelwidth = 2;
967 break;
968 case CIRRUS_BLTMODE_PIXELWIDTH24:
969 s->cirrus_blt_pixelwidth = 3;
970 break;
971 case CIRRUS_BLTMODE_PIXELWIDTH32:
972 s->cirrus_blt_pixelwidth = 4;
973 break;
974 default:
975 #ifdef DEBUG_BITBLT
976 printf("cirrus: bitblt - pixel width is unknown\n");
977 #endif
978 goto bitblt_ignore;
979 }
980 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
981
982 if ((s->
983 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
984 CIRRUS_BLTMODE_MEMSYSDEST))
985 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
986 #ifdef DEBUG_BITBLT
987 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
988 #endif
989 goto bitblt_ignore;
990 }
991
992 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
993 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
994 CIRRUS_BLTMODE_TRANSPARENTCOMP |
995 CIRRUS_BLTMODE_PATTERNCOPY |
996 CIRRUS_BLTMODE_COLOREXPAND)) ==
997 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
998 cirrus_bitblt_fgcol(s);
999 cirrus_bitblt_solidfill(s, blt_rop);
1000 } else {
1001 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1002 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1003 CIRRUS_BLTMODE_COLOREXPAND) {
1004
1005 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1006 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1007 cirrus_bitblt_bgcol(s);
1008 else
1009 cirrus_bitblt_fgcol(s);
1010 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1011 } else {
1012 cirrus_bitblt_fgcol(s);
1013 cirrus_bitblt_bgcol(s);
1014 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1015 }
1016 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1017 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1018 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1019 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1020 cirrus_bitblt_bgcol(s);
1021 else
1022 cirrus_bitblt_fgcol(s);
1023 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1024 } else {
1025 cirrus_bitblt_fgcol(s);
1026 cirrus_bitblt_bgcol(s);
1027 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1028 }
1029 } else {
1030 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1031 }
1032 } else {
1033 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1034 if (s->cirrus_blt_pixelwidth > 2) {
1035 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1036 goto bitblt_ignore;
1037 }
1038 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1039 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1040 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1041 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1042 } else {
1043 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1044 }
1045 } else {
1046 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1047 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1048 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1049 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1050 } else {
1051 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1052 }
1053 }
1054 }
1055 // setup bitblt engine.
1056 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1057 if (!cirrus_bitblt_cputovideo(s))
1058 goto bitblt_ignore;
1059 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1060 if (!cirrus_bitblt_videotocpu(s))
1061 goto bitblt_ignore;
1062 } else {
1063 if (!cirrus_bitblt_videotovideo(s))
1064 goto bitblt_ignore;
1065 }
1066 }
1067 return;
1068 bitblt_ignore:;
1069 cirrus_bitblt_reset(s);
1070 }
1071
1072 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1073 {
1074 unsigned old_value;
1075
1076 old_value = s->gr[0x31];
1077 s->gr[0x31] = reg_value;
1078
1079 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1080 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1081 cirrus_bitblt_reset(s);
1082 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1083 ((reg_value & CIRRUS_BLT_START) != 0)) {
1084 cirrus_bitblt_start(s);
1085 }
1086 }
1087
1088
1089 /***************************************
1090 *
1091 * basic parameters
1092 *
1093 ***************************************/
1094
1095 static void cirrus_get_offsets(VGAState *s1,
1096 uint32_t *pline_offset,
1097 uint32_t *pstart_addr,
1098 uint32_t *pline_compare)
1099 {
1100 CirrusVGAState * s = (CirrusVGAState *)s1;
1101 uint32_t start_addr, line_offset, line_compare;
1102
1103 line_offset = s->cr[0x13]
1104 | ((s->cr[0x1b] & 0x10) << 4);
1105 line_offset <<= 3;
1106 *pline_offset = line_offset;
1107
1108 start_addr = (s->cr[0x0c] << 8)
1109 | s->cr[0x0d]
1110 | ((s->cr[0x1b] & 0x01) << 16)
1111 | ((s->cr[0x1b] & 0x0c) << 15)
1112 | ((s->cr[0x1d] & 0x80) << 12);
1113 *pstart_addr = start_addr;
1114
1115 line_compare = s->cr[0x18] |
1116 ((s->cr[0x07] & 0x10) << 4) |
1117 ((s->cr[0x09] & 0x40) << 3);
1118 *pline_compare = line_compare;
1119 }
1120
1121 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1122 {
1123 uint32_t ret = 16;
1124
1125 switch (s->cirrus_hidden_dac_data & 0xf) {
1126 case 0:
1127 ret = 15;
1128 break; /* Sierra HiColor */
1129 case 1:
1130 ret = 16;
1131 break; /* XGA HiColor */
1132 default:
1133 #ifdef DEBUG_CIRRUS
1134 printf("cirrus: invalid DAC value %x in 16bpp\n",
1135 (s->cirrus_hidden_dac_data & 0xf));
1136 #endif
1137 ret = 15; /* XXX */
1138 break;
1139 }
1140 return ret;
1141 }
1142
1143 static int cirrus_get_bpp(VGAState *s1)
1144 {
1145 CirrusVGAState * s = (CirrusVGAState *)s1;
1146 uint32_t ret = 8;
1147
1148 if ((s->sr[0x07] & 0x01) != 0) {
1149 /* Cirrus SVGA */
1150 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1151 case CIRRUS_SR7_BPP_8:
1152 ret = 8;
1153 break;
1154 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1155 ret = cirrus_get_bpp16_depth(s);
1156 break;
1157 case CIRRUS_SR7_BPP_24:
1158 ret = 24;
1159 break;
1160 case CIRRUS_SR7_BPP_16:
1161 ret = cirrus_get_bpp16_depth(s);
1162 break;
1163 case CIRRUS_SR7_BPP_32:
1164 ret = 32;
1165 break;
1166 default:
1167 #ifdef DEBUG_CIRRUS
1168 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1169 #endif
1170 ret = 8;
1171 break;
1172 }
1173 } else {
1174 /* VGA */
1175 ret = 0;
1176 }
1177
1178 return ret;
1179 }
1180
1181 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1182 {
1183 int width, height;
1184
1185 width = (s->cr[0x01] + 1) * 8;
1186 height = s->cr[0x12] |
1187 ((s->cr[0x07] & 0x02) << 7) |
1188 ((s->cr[0x07] & 0x40) << 3);
1189 height = (height + 1);
1190 /* interlace support */
1191 if (s->cr[0x1a] & 0x01)
1192 height = height * 2;
1193 *pwidth = width;
1194 *pheight = height;
1195 }
1196
1197 /***************************************
1198 *
1199 * bank memory
1200 *
1201 ***************************************/
1202
1203 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1204 {
1205 unsigned offset;
1206 unsigned limit;
1207
1208 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1209 offset = s->gr[0x09 + bank_index];
1210 else /* single bank */
1211 offset = s->gr[0x09];
1212
1213 if ((s->gr[0x0b] & 0x20) != 0)
1214 offset <<= 14;
1215 else
1216 offset <<= 12;
1217
1218 if (s->real_vram_size <= offset)
1219 limit = 0;
1220 else
1221 limit = s->real_vram_size - offset;
1222
1223 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1224 if (limit > 0x8000) {
1225 offset += 0x8000;
1226 limit -= 0x8000;
1227 } else {
1228 limit = 0;
1229 }
1230 }
1231
1232 if (limit > 0) {
1233 /* Thinking about changing bank base? First, drop the dirty bitmap information
1234 * on the current location, otherwise we lose this pointer forever */
1235 if (s->lfb_vram_mapped) {
1236 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1237 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1238 }
1239 s->cirrus_bank_base[bank_index] = offset;
1240 s->cirrus_bank_limit[bank_index] = limit;
1241 } else {
1242 s->cirrus_bank_base[bank_index] = 0;
1243 s->cirrus_bank_limit[bank_index] = 0;
1244 }
1245 }
1246
1247 /***************************************
1248 *
1249 * I/O access between 0x3c4-0x3c5
1250 *
1251 ***************************************/
1252
1253 static int
1254 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1255 {
1256 switch (reg_index) {
1257 case 0x00: // Standard VGA
1258 case 0x01: // Standard VGA
1259 case 0x02: // Standard VGA
1260 case 0x03: // Standard VGA
1261 case 0x04: // Standard VGA
1262 return CIRRUS_HOOK_NOT_HANDLED;
1263 case 0x06: // Unlock Cirrus extensions
1264 *reg_value = s->sr[reg_index];
1265 break;
1266 case 0x10:
1267 case 0x30:
1268 case 0x50:
1269 case 0x70: // Graphics Cursor X
1270 case 0x90:
1271 case 0xb0:
1272 case 0xd0:
1273 case 0xf0: // Graphics Cursor X
1274 *reg_value = s->sr[0x10];
1275 break;
1276 case 0x11:
1277 case 0x31:
1278 case 0x51:
1279 case 0x71: // Graphics Cursor Y
1280 case 0x91:
1281 case 0xb1:
1282 case 0xd1:
1283 case 0xf1: // Graphics Cursor Y
1284 *reg_value = s->sr[0x11];
1285 break;
1286 case 0x05: // ???
1287 case 0x07: // Extended Sequencer Mode
1288 case 0x08: // EEPROM Control
1289 case 0x09: // Scratch Register 0
1290 case 0x0a: // Scratch Register 1
1291 case 0x0b: // VCLK 0
1292 case 0x0c: // VCLK 1
1293 case 0x0d: // VCLK 2
1294 case 0x0e: // VCLK 3
1295 case 0x0f: // DRAM Control
1296 case 0x12: // Graphics Cursor Attribute
1297 case 0x13: // Graphics Cursor Pattern Address
1298 case 0x14: // Scratch Register 2
1299 case 0x15: // Scratch Register 3
1300 case 0x16: // Performance Tuning Register
1301 case 0x17: // Configuration Readback and Extended Control
1302 case 0x18: // Signature Generator Control
1303 case 0x19: // Signal Generator Result
1304 case 0x1a: // Signal Generator Result
1305 case 0x1b: // VCLK 0 Denominator & Post
1306 case 0x1c: // VCLK 1 Denominator & Post
1307 case 0x1d: // VCLK 2 Denominator & Post
1308 case 0x1e: // VCLK 3 Denominator & Post
1309 case 0x1f: // BIOS Write Enable and MCLK select
1310 #ifdef DEBUG_CIRRUS
1311 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1312 #endif
1313 *reg_value = s->sr[reg_index];
1314 break;
1315 default:
1316 #ifdef DEBUG_CIRRUS
1317 printf("cirrus: inport sr_index %02x\n", reg_index);
1318 #endif
1319 *reg_value = 0xff;
1320 break;
1321 }
1322
1323 return CIRRUS_HOOK_HANDLED;
1324 }
1325
1326 static int
1327 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1328 {
1329 switch (reg_index) {
1330 case 0x00: // Standard VGA
1331 case 0x01: // Standard VGA
1332 case 0x02: // Standard VGA
1333 case 0x03: // Standard VGA
1334 case 0x04: // Standard VGA
1335 return CIRRUS_HOOK_NOT_HANDLED;
1336 case 0x06: // Unlock Cirrus extensions
1337 reg_value &= 0x17;
1338 if (reg_value == 0x12) {
1339 s->sr[reg_index] = 0x12;
1340 } else {
1341 s->sr[reg_index] = 0x0f;
1342 }
1343 break;
1344 case 0x10:
1345 case 0x30:
1346 case 0x50:
1347 case 0x70: // Graphics Cursor X
1348 case 0x90:
1349 case 0xb0:
1350 case 0xd0:
1351 case 0xf0: // Graphics Cursor X
1352 s->sr[0x10] = reg_value;
1353 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1354 break;
1355 case 0x11:
1356 case 0x31:
1357 case 0x51:
1358 case 0x71: // Graphics Cursor Y
1359 case 0x91:
1360 case 0xb1:
1361 case 0xd1:
1362 case 0xf1: // Graphics Cursor Y
1363 s->sr[0x11] = reg_value;
1364 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1365 break;
1366 case 0x07: // Extended Sequencer Mode
1367 cirrus_update_memory_access(s);
1368 case 0x08: // EEPROM Control
1369 case 0x09: // Scratch Register 0
1370 case 0x0a: // Scratch Register 1
1371 case 0x0b: // VCLK 0
1372 case 0x0c: // VCLK 1
1373 case 0x0d: // VCLK 2
1374 case 0x0e: // VCLK 3
1375 case 0x0f: // DRAM Control
1376 case 0x12: // Graphics Cursor Attribute
1377 case 0x13: // Graphics Cursor Pattern Address
1378 case 0x14: // Scratch Register 2
1379 case 0x15: // Scratch Register 3
1380 case 0x16: // Performance Tuning Register
1381 case 0x18: // Signature Generator Control
1382 case 0x19: // Signature Generator Result
1383 case 0x1a: // Signature Generator Result
1384 case 0x1b: // VCLK 0 Denominator & Post
1385 case 0x1c: // VCLK 1 Denominator & Post
1386 case 0x1d: // VCLK 2 Denominator & Post
1387 case 0x1e: // VCLK 3 Denominator & Post
1388 case 0x1f: // BIOS Write Enable and MCLK select
1389 s->sr[reg_index] = reg_value;
1390 #ifdef DEBUG_CIRRUS
1391 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1392 reg_index, reg_value);
1393 #endif
1394 if (reg_index == 0x07)
1395 cirrus_update_memory_access(s);
1396 break;
1397 case 0x17: // Configuration Readback and Extended Control
1398 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1399 cirrus_update_memory_access(s);
1400 break;
1401 default:
1402 #ifdef DEBUG_CIRRUS
1403 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1404 reg_value);
1405 #endif
1406 break;
1407 }
1408
1409 return CIRRUS_HOOK_HANDLED;
1410 }
1411
1412 /***************************************
1413 *
1414 * I/O access at 0x3c6
1415 *
1416 ***************************************/
1417
1418 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1419 {
1420 *reg_value = 0xff;
1421 if (++s->cirrus_hidden_dac_lockindex == 5) {
1422 *reg_value = s->cirrus_hidden_dac_data;
1423 s->cirrus_hidden_dac_lockindex = 0;
1424 }
1425 }
1426
1427 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1428 {
1429 if (s->cirrus_hidden_dac_lockindex == 4) {
1430 s->cirrus_hidden_dac_data = reg_value;
1431 #if defined(DEBUG_CIRRUS)
1432 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1433 #endif
1434 }
1435 s->cirrus_hidden_dac_lockindex = 0;
1436 }
1437
1438 /***************************************
1439 *
1440 * I/O access at 0x3c9
1441 *
1442 ***************************************/
1443
1444 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1445 {
1446 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1447 return CIRRUS_HOOK_NOT_HANDLED;
1448 *reg_value =
1449 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1450 s->dac_sub_index];
1451 if (++s->dac_sub_index == 3) {
1452 s->dac_sub_index = 0;
1453 s->dac_read_index++;
1454 }
1455 return CIRRUS_HOOK_HANDLED;
1456 }
1457
1458 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1459 {
1460 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1461 return CIRRUS_HOOK_NOT_HANDLED;
1462 s->dac_cache[s->dac_sub_index] = reg_value;
1463 if (++s->dac_sub_index == 3) {
1464 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1465 s->dac_cache, 3);
1466 /* XXX update cursor */
1467 s->dac_sub_index = 0;
1468 s->dac_write_index++;
1469 }
1470 return CIRRUS_HOOK_HANDLED;
1471 }
1472
1473 /***************************************
1474 *
1475 * I/O access between 0x3ce-0x3cf
1476 *
1477 ***************************************/
1478
1479 static int
1480 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1481 {
1482 switch (reg_index) {
1483 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1484 *reg_value = s->cirrus_shadow_gr0;
1485 return CIRRUS_HOOK_HANDLED;
1486 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1487 *reg_value = s->cirrus_shadow_gr1;
1488 return CIRRUS_HOOK_HANDLED;
1489 case 0x02: // Standard VGA
1490 case 0x03: // Standard VGA
1491 case 0x04: // Standard VGA
1492 case 0x06: // Standard VGA
1493 case 0x07: // Standard VGA
1494 case 0x08: // Standard VGA
1495 return CIRRUS_HOOK_NOT_HANDLED;
1496 case 0x05: // Standard VGA, Cirrus extended mode
1497 default:
1498 break;
1499 }
1500
1501 if (reg_index < 0x3a) {
1502 *reg_value = s->gr[reg_index];
1503 } else {
1504 #ifdef DEBUG_CIRRUS
1505 printf("cirrus: inport gr_index %02x\n", reg_index);
1506 #endif
1507 *reg_value = 0xff;
1508 }
1509
1510 return CIRRUS_HOOK_HANDLED;
1511 }
1512
1513 static int
1514 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1515 {
1516 #if defined(DEBUG_BITBLT) && 0
1517 printf("gr%02x: %02x\n", reg_index, reg_value);
1518 #endif
1519 switch (reg_index) {
1520 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1521 s->cirrus_shadow_gr0 = reg_value;
1522 return CIRRUS_HOOK_NOT_HANDLED;
1523 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1524 s->cirrus_shadow_gr1 = reg_value;
1525 return CIRRUS_HOOK_NOT_HANDLED;
1526 case 0x02: // Standard VGA
1527 case 0x03: // Standard VGA
1528 case 0x04: // Standard VGA
1529 case 0x06: // Standard VGA
1530 case 0x07: // Standard VGA
1531 case 0x08: // Standard VGA
1532 return CIRRUS_HOOK_NOT_HANDLED;
1533 case 0x05: // Standard VGA, Cirrus extended mode
1534 s->gr[reg_index] = reg_value & 0x7f;
1535 cirrus_update_memory_access(s);
1536 break;
1537 case 0x09: // bank offset #0
1538 case 0x0A: // bank offset #1
1539 s->gr[reg_index] = reg_value;
1540 cirrus_update_bank_ptr(s, 0);
1541 cirrus_update_bank_ptr(s, 1);
1542 cirrus_update_memory_access(s);
1543 break;
1544 case 0x0B:
1545 s->gr[reg_index] = reg_value;
1546 cirrus_update_bank_ptr(s, 0);
1547 cirrus_update_bank_ptr(s, 1);
1548 cirrus_update_memory_access(s);
1549 break;
1550 case 0x10: // BGCOLOR 0x0000ff00
1551 case 0x11: // FGCOLOR 0x0000ff00
1552 case 0x12: // BGCOLOR 0x00ff0000
1553 case 0x13: // FGCOLOR 0x00ff0000
1554 case 0x14: // BGCOLOR 0xff000000
1555 case 0x15: // FGCOLOR 0xff000000
1556 case 0x20: // BLT WIDTH 0x0000ff
1557 case 0x22: // BLT HEIGHT 0x0000ff
1558 case 0x24: // BLT DEST PITCH 0x0000ff
1559 case 0x26: // BLT SRC PITCH 0x0000ff
1560 case 0x28: // BLT DEST ADDR 0x0000ff
1561 case 0x29: // BLT DEST ADDR 0x00ff00
1562 case 0x2c: // BLT SRC ADDR 0x0000ff
1563 case 0x2d: // BLT SRC ADDR 0x00ff00
1564 case 0x2f: // BLT WRITEMASK
1565 case 0x30: // BLT MODE
1566 case 0x32: // RASTER OP
1567 case 0x33: // BLT MODEEXT
1568 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1569 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1570 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1571 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1572 s->gr[reg_index] = reg_value;
1573 break;
1574 case 0x21: // BLT WIDTH 0x001f00
1575 case 0x23: // BLT HEIGHT 0x001f00
1576 case 0x25: // BLT DEST PITCH 0x001f00
1577 case 0x27: // BLT SRC PITCH 0x001f00
1578 s->gr[reg_index] = reg_value & 0x1f;
1579 break;
1580 case 0x2a: // BLT DEST ADDR 0x3f0000
1581 s->gr[reg_index] = reg_value & 0x3f;
1582 /* if auto start mode, starts bit blt now */
1583 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1584 cirrus_bitblt_start(s);
1585 }
1586 break;
1587 case 0x2e: // BLT SRC ADDR 0x3f0000
1588 s->gr[reg_index] = reg_value & 0x3f;
1589 break;
1590 case 0x31: // BLT STATUS/START
1591 cirrus_write_bitblt(s, reg_value);
1592 break;
1593 default:
1594 #ifdef DEBUG_CIRRUS
1595 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1596 reg_value);
1597 #endif
1598 break;
1599 }
1600
1601 return CIRRUS_HOOK_HANDLED;
1602 }
1603
1604 /***************************************
1605 *
1606 * I/O access between 0x3d4-0x3d5
1607 *
1608 ***************************************/
1609
1610 static int
1611 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1612 {
1613 switch (reg_index) {
1614 case 0x00: // Standard VGA
1615 case 0x01: // Standard VGA
1616 case 0x02: // Standard VGA
1617 case 0x03: // Standard VGA
1618 case 0x04: // Standard VGA
1619 case 0x05: // Standard VGA
1620 case 0x06: // Standard VGA
1621 case 0x07: // Standard VGA
1622 case 0x08: // Standard VGA
1623 case 0x09: // Standard VGA
1624 case 0x0a: // Standard VGA
1625 case 0x0b: // Standard VGA
1626 case 0x0c: // Standard VGA
1627 case 0x0d: // Standard VGA
1628 case 0x0e: // Standard VGA
1629 case 0x0f: // Standard VGA
1630 case 0x10: // Standard VGA
1631 case 0x11: // Standard VGA
1632 case 0x12: // Standard VGA
1633 case 0x13: // Standard VGA
1634 case 0x14: // Standard VGA
1635 case 0x15: // Standard VGA
1636 case 0x16: // Standard VGA
1637 case 0x17: // Standard VGA
1638 case 0x18: // Standard VGA
1639 return CIRRUS_HOOK_NOT_HANDLED;
1640 case 0x24: // Attribute Controller Toggle Readback (R)
1641 *reg_value = (s->ar_flip_flop << 7);
1642 break;
1643 case 0x19: // Interlace End
1644 case 0x1a: // Miscellaneous Control
1645 case 0x1b: // Extended Display Control
1646 case 0x1c: // Sync Adjust and Genlock
1647 case 0x1d: // Overlay Extended Control
1648 case 0x22: // Graphics Data Latches Readback (R)
1649 case 0x25: // Part Status
1650 case 0x27: // Part ID (R)
1651 *reg_value = s->cr[reg_index];
1652 break;
1653 case 0x26: // Attribute Controller Index Readback (R)
1654 *reg_value = s->ar_index & 0x3f;
1655 break;
1656 default:
1657 #ifdef DEBUG_CIRRUS
1658 printf("cirrus: inport cr_index %02x\n", reg_index);
1659 *reg_value = 0xff;
1660 #endif
1661 break;
1662 }
1663
1664 return CIRRUS_HOOK_HANDLED;
1665 }
1666
1667 static int
1668 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1669 {
1670 switch (reg_index) {
1671 case 0x00: // Standard VGA
1672 case 0x01: // Standard VGA
1673 case 0x02: // Standard VGA
1674 case 0x03: // Standard VGA
1675 case 0x04: // Standard VGA
1676 case 0x05: // Standard VGA
1677 case 0x06: // Standard VGA
1678 case 0x07: // Standard VGA
1679 case 0x08: // Standard VGA
1680 case 0x09: // Standard VGA
1681 case 0x0a: // Standard VGA
1682 case 0x0b: // Standard VGA
1683 case 0x0c: // Standard VGA
1684 case 0x0d: // Standard VGA
1685 case 0x0e: // Standard VGA
1686 case 0x0f: // Standard VGA
1687 case 0x10: // Standard VGA
1688 case 0x11: // Standard VGA
1689 case 0x12: // Standard VGA
1690 case 0x13: // Standard VGA
1691 case 0x14: // Standard VGA
1692 case 0x15: // Standard VGA
1693 case 0x16: // Standard VGA
1694 case 0x17: // Standard VGA
1695 case 0x18: // Standard VGA
1696 return CIRRUS_HOOK_NOT_HANDLED;
1697 case 0x19: // Interlace End
1698 case 0x1a: // Miscellaneous Control
1699 case 0x1b: // Extended Display Control
1700 case 0x1c: // Sync Adjust and Genlock
1701 case 0x1d: // Overlay Extended Control
1702 s->cr[reg_index] = reg_value;
1703 #ifdef DEBUG_CIRRUS
1704 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1705 reg_index, reg_value);
1706 #endif
1707 break;
1708 case 0x22: // Graphics Data Latches Readback (R)
1709 case 0x24: // Attribute Controller Toggle Readback (R)
1710 case 0x26: // Attribute Controller Index Readback (R)
1711 case 0x27: // Part ID (R)
1712 break;
1713 case 0x25: // Part Status
1714 default:
1715 #ifdef DEBUG_CIRRUS
1716 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1717 reg_value);
1718 #endif
1719 break;
1720 }
1721
1722 return CIRRUS_HOOK_HANDLED;
1723 }
1724
1725 /***************************************
1726 *
1727 * memory-mapped I/O (bitblt)
1728 *
1729 ***************************************/
1730
1731 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1732 {
1733 int value = 0xff;
1734
1735 switch (address) {
1736 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1737 cirrus_hook_read_gr(s, 0x00, &value);
1738 break;
1739 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1740 cirrus_hook_read_gr(s, 0x10, &value);
1741 break;
1742 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1743 cirrus_hook_read_gr(s, 0x12, &value);
1744 break;
1745 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1746 cirrus_hook_read_gr(s, 0x14, &value);
1747 break;
1748 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1749 cirrus_hook_read_gr(s, 0x01, &value);
1750 break;
1751 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1752 cirrus_hook_read_gr(s, 0x11, &value);
1753 break;
1754 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1755 cirrus_hook_read_gr(s, 0x13, &value);
1756 break;
1757 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1758 cirrus_hook_read_gr(s, 0x15, &value);
1759 break;
1760 case (CIRRUS_MMIO_BLTWIDTH + 0):
1761 cirrus_hook_read_gr(s, 0x20, &value);
1762 break;
1763 case (CIRRUS_MMIO_BLTWIDTH + 1):
1764 cirrus_hook_read_gr(s, 0x21, &value);
1765 break;
1766 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1767 cirrus_hook_read_gr(s, 0x22, &value);
1768 break;
1769 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1770 cirrus_hook_read_gr(s, 0x23, &value);
1771 break;
1772 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1773 cirrus_hook_read_gr(s, 0x24, &value);
1774 break;
1775 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1776 cirrus_hook_read_gr(s, 0x25, &value);
1777 break;
1778 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1779 cirrus_hook_read_gr(s, 0x26, &value);
1780 break;
1781 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1782 cirrus_hook_read_gr(s, 0x27, &value);
1783 break;
1784 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1785 cirrus_hook_read_gr(s, 0x28, &value);
1786 break;
1787 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1788 cirrus_hook_read_gr(s, 0x29, &value);
1789 break;
1790 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1791 cirrus_hook_read_gr(s, 0x2a, &value);
1792 break;
1793 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1794 cirrus_hook_read_gr(s, 0x2c, &value);
1795 break;
1796 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1797 cirrus_hook_read_gr(s, 0x2d, &value);
1798 break;
1799 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1800 cirrus_hook_read_gr(s, 0x2e, &value);
1801 break;
1802 case CIRRUS_MMIO_BLTWRITEMASK:
1803 cirrus_hook_read_gr(s, 0x2f, &value);
1804 break;
1805 case CIRRUS_MMIO_BLTMODE:
1806 cirrus_hook_read_gr(s, 0x30, &value);
1807 break;
1808 case CIRRUS_MMIO_BLTROP:
1809 cirrus_hook_read_gr(s, 0x32, &value);
1810 break;
1811 case CIRRUS_MMIO_BLTMODEEXT:
1812 cirrus_hook_read_gr(s, 0x33, &value);
1813 break;
1814 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1815 cirrus_hook_read_gr(s, 0x34, &value);
1816 break;
1817 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1818 cirrus_hook_read_gr(s, 0x35, &value);
1819 break;
1820 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1821 cirrus_hook_read_gr(s, 0x38, &value);
1822 break;
1823 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1824 cirrus_hook_read_gr(s, 0x39, &value);
1825 break;
1826 case CIRRUS_MMIO_BLTSTATUS:
1827 cirrus_hook_read_gr(s, 0x31, &value);
1828 break;
1829 default:
1830 #ifdef DEBUG_CIRRUS
1831 printf("cirrus: mmio read - address 0x%04x\n", address);
1832 #endif
1833 break;
1834 }
1835
1836 return (uint8_t) value;
1837 }
1838
1839 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1840 uint8_t value)
1841 {
1842 switch (address) {
1843 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1844 cirrus_hook_write_gr(s, 0x00, value);
1845 break;
1846 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1847 cirrus_hook_write_gr(s, 0x10, value);
1848 break;
1849 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1850 cirrus_hook_write_gr(s, 0x12, value);
1851 break;
1852 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1853 cirrus_hook_write_gr(s, 0x14, value);
1854 break;
1855 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1856 cirrus_hook_write_gr(s, 0x01, value);
1857 break;
1858 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1859 cirrus_hook_write_gr(s, 0x11, value);
1860 break;
1861 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1862 cirrus_hook_write_gr(s, 0x13, value);
1863 break;
1864 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1865 cirrus_hook_write_gr(s, 0x15, value);
1866 break;
1867 case (CIRRUS_MMIO_BLTWIDTH + 0):
1868 cirrus_hook_write_gr(s, 0x20, value);
1869 break;
1870 case (CIRRUS_MMIO_BLTWIDTH + 1):
1871 cirrus_hook_write_gr(s, 0x21, value);
1872 break;
1873 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1874 cirrus_hook_write_gr(s, 0x22, value);
1875 break;
1876 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1877 cirrus_hook_write_gr(s, 0x23, value);
1878 break;
1879 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1880 cirrus_hook_write_gr(s, 0x24, value);
1881 break;
1882 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1883 cirrus_hook_write_gr(s, 0x25, value);
1884 break;
1885 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1886 cirrus_hook_write_gr(s, 0x26, value);
1887 break;
1888 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1889 cirrus_hook_write_gr(s, 0x27, value);
1890 break;
1891 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1892 cirrus_hook_write_gr(s, 0x28, value);
1893 break;
1894 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1895 cirrus_hook_write_gr(s, 0x29, value);
1896 break;
1897 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1898 cirrus_hook_write_gr(s, 0x2a, value);
1899 break;
1900 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1901 /* ignored */
1902 break;
1903 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1904 cirrus_hook_write_gr(s, 0x2c, value);
1905 break;
1906 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1907 cirrus_hook_write_gr(s, 0x2d, value);
1908 break;
1909 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1910 cirrus_hook_write_gr(s, 0x2e, value);
1911 break;
1912 case CIRRUS_MMIO_BLTWRITEMASK:
1913 cirrus_hook_write_gr(s, 0x2f, value);
1914 break;
1915 case CIRRUS_MMIO_BLTMODE:
1916 cirrus_hook_write_gr(s, 0x30, value);
1917 break;
1918 case CIRRUS_MMIO_BLTROP:
1919 cirrus_hook_write_gr(s, 0x32, value);
1920 break;
1921 case CIRRUS_MMIO_BLTMODEEXT:
1922 cirrus_hook_write_gr(s, 0x33, value);
1923 break;
1924 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1925 cirrus_hook_write_gr(s, 0x34, value);
1926 break;
1927 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1928 cirrus_hook_write_gr(s, 0x35, value);
1929 break;
1930 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1931 cirrus_hook_write_gr(s, 0x38, value);
1932 break;
1933 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1934 cirrus_hook_write_gr(s, 0x39, value);
1935 break;
1936 case CIRRUS_MMIO_BLTSTATUS:
1937 cirrus_hook_write_gr(s, 0x31, value);
1938 break;
1939 default:
1940 #ifdef DEBUG_CIRRUS
1941 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1942 address, value);
1943 #endif
1944 break;
1945 }
1946 }
1947
1948 /***************************************
1949 *
1950 * write mode 4/5
1951 *
1952 * assume TARGET_PAGE_SIZE >= 16
1953 *
1954 ***************************************/
1955
1956 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1957 unsigned mode,
1958 unsigned offset,
1959 uint32_t mem_value)
1960 {
1961 int x;
1962 unsigned val = mem_value;
1963 uint8_t *dst;
1964
1965 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1966 for (x = 0; x < 8; x++) {
1967 if (val & 0x80) {
1968 *dst = s->cirrus_shadow_gr1;
1969 } else if (mode == 5) {
1970 *dst = s->cirrus_shadow_gr0;
1971 }
1972 val <<= 1;
1973 dst++;
1974 }
1975 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1976 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1977 }
1978
1979 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1980 unsigned mode,
1981 unsigned offset,
1982 uint32_t mem_value)
1983 {
1984 int x;
1985 unsigned val = mem_value;
1986 uint8_t *dst;
1987
1988 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1989 for (x = 0; x < 8; x++) {
1990 if (val & 0x80) {
1991 *dst = s->cirrus_shadow_gr1;
1992 *(dst + 1) = s->gr[0x11];
1993 } else if (mode == 5) {
1994 *dst = s->cirrus_shadow_gr0;
1995 *(dst + 1) = s->gr[0x10];
1996 }
1997 val <<= 1;
1998 dst += 2;
1999 }
2000 cpu_physical_memory_set_dirty(s->vram_offset + offset);
2001 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
2002 }
2003
2004 /***************************************
2005 *
2006 * memory access between 0xa0000-0xbffff
2007 *
2008 ***************************************/
2009
2010 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2011 {
2012 CirrusVGAState *s = opaque;
2013 unsigned bank_index;
2014 unsigned bank_offset;
2015 uint32_t val;
2016
2017 if ((s->sr[0x07] & 0x01) == 0) {
2018 return vga_mem_readb(s, addr);
2019 }
2020
2021 addr &= 0x1ffff;
2022
2023 if (addr < 0x10000) {
2024 /* XXX handle bitblt */
2025 /* video memory */
2026 bank_index = addr >> 15;
2027 bank_offset = addr & 0x7fff;
2028 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2029 bank_offset += s->cirrus_bank_base[bank_index];
2030 if ((s->gr[0x0B] & 0x14) == 0x14) {
2031 bank_offset <<= 4;
2032 } else if (s->gr[0x0B] & 0x02) {
2033 bank_offset <<= 3;
2034 }
2035 bank_offset &= s->cirrus_addr_mask;
2036 val = *(s->vram_ptr + bank_offset);
2037 } else
2038 val = 0xff;
2039 } else if (addr >= 0x18000 && addr < 0x18100) {
2040 /* memory-mapped I/O */
2041 val = 0xff;
2042 if ((s->sr[0x17] & 0x44) == 0x04) {
2043 val = cirrus_mmio_blt_read(s, addr & 0xff);
2044 }
2045 } else {
2046 val = 0xff;
2047 #ifdef DEBUG_CIRRUS
2048 printf("cirrus: mem_readb %06x\n", addr);
2049 #endif
2050 }
2051 return val;
2052 }
2053
2054 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2055 {
2056 uint32_t v;
2057 #ifdef TARGET_WORDS_BIGENDIAN
2058 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2059 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2060 #else
2061 v = cirrus_vga_mem_readb(opaque, addr);
2062 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2063 #endif
2064 return v;
2065 }
2066
2067 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2068 {
2069 uint32_t v;
2070 #ifdef TARGET_WORDS_BIGENDIAN
2071 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2072 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2073 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2074 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2075 #else
2076 v = cirrus_vga_mem_readb(opaque, addr);
2077 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2078 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2079 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2080 #endif
2081 return v;
2082 }
2083
2084 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2085 uint32_t mem_value)
2086 {
2087 CirrusVGAState *s = opaque;
2088 unsigned bank_index;
2089 unsigned bank_offset;
2090 unsigned mode;
2091
2092 if ((s->sr[0x07] & 0x01) == 0) {
2093 vga_mem_writeb(s, addr, mem_value);
2094 return;
2095 }
2096
2097 addr &= 0x1ffff;
2098
2099 if (addr < 0x10000) {
2100 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2101 /* bitblt */
2102 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2103 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2104 cirrus_bitblt_cputovideo_next(s);
2105 }
2106 } else {
2107 /* video memory */
2108 bank_index = addr >> 15;
2109 bank_offset = addr & 0x7fff;
2110 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2111 bank_offset += s->cirrus_bank_base[bank_index];
2112 if ((s->gr[0x0B] & 0x14) == 0x14) {
2113 bank_offset <<= 4;
2114 } else if (s->gr[0x0B] & 0x02) {
2115 bank_offset <<= 3;
2116 }
2117 bank_offset &= s->cirrus_addr_mask;
2118 mode = s->gr[0x05] & 0x7;
2119 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2120 *(s->vram_ptr + bank_offset) = mem_value;
2121 cpu_physical_memory_set_dirty(s->vram_offset +
2122 bank_offset);
2123 } else {
2124 if ((s->gr[0x0B] & 0x14) != 0x14) {
2125 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2126 bank_offset,
2127 mem_value);
2128 } else {
2129 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2130 bank_offset,
2131 mem_value);
2132 }
2133 }
2134 }
2135 }
2136 } else if (addr >= 0x18000 && addr < 0x18100) {
2137 /* memory-mapped I/O */
2138 if ((s->sr[0x17] & 0x44) == 0x04) {
2139 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2140 }
2141 } else {
2142 #ifdef DEBUG_CIRRUS
2143 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2144 #endif
2145 }
2146 }
2147
2148 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2149 {
2150 #ifdef TARGET_WORDS_BIGENDIAN
2151 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2152 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2153 #else
2154 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2155 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2156 #endif
2157 }
2158
2159 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2160 {
2161 #ifdef TARGET_WORDS_BIGENDIAN
2162 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2163 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2164 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2165 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2166 #else
2167 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2168 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2169 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2170 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2171 #endif
2172 }
2173
2174 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2175 cirrus_vga_mem_readb,
2176 cirrus_vga_mem_readw,
2177 cirrus_vga_mem_readl,
2178 };
2179
2180 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2181 cirrus_vga_mem_writeb,
2182 cirrus_vga_mem_writew,
2183 cirrus_vga_mem_writel,
2184 };
2185
2186 /***************************************
2187 *
2188 * hardware cursor
2189 *
2190 ***************************************/
2191
2192 static inline void invalidate_cursor1(CirrusVGAState *s)
2193 {
2194 if (s->last_hw_cursor_size) {
2195 vga_invalidate_scanlines((VGAState *)s,
2196 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2197 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2198 }
2199 }
2200
2201 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2202 {
2203 const uint8_t *src;
2204 uint32_t content;
2205 int y, y_min, y_max;
2206
2207 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2208 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2209 src += (s->sr[0x13] & 0x3c) * 256;
2210 y_min = 64;
2211 y_max = -1;
2212 for(y = 0; y < 64; y++) {
2213 content = ((uint32_t *)src)[0] |
2214 ((uint32_t *)src)[1] |
2215 ((uint32_t *)src)[2] |
2216 ((uint32_t *)src)[3];
2217 if (content) {
2218 if (y < y_min)
2219 y_min = y;
2220 if (y > y_max)
2221 y_max = y;
2222 }
2223 src += 16;
2224 }
2225 } else {
2226 src += (s->sr[0x13] & 0x3f) * 256;
2227 y_min = 32;
2228 y_max = -1;
2229 for(y = 0; y < 32; y++) {
2230 content = ((uint32_t *)src)[0] |
2231 ((uint32_t *)(src + 128))[0];
2232 if (content) {
2233 if (y < y_min)
2234 y_min = y;
2235 if (y > y_max)
2236 y_max = y;
2237 }
2238 src += 4;
2239 }
2240 }
2241 if (y_min > y_max) {
2242 s->last_hw_cursor_y_start = 0;
2243 s->last_hw_cursor_y_end = 0;
2244 } else {
2245 s->last_hw_cursor_y_start = y_min;
2246 s->last_hw_cursor_y_end = y_max + 1;
2247 }
2248 }
2249
2250 /* NOTE: we do not currently handle the cursor bitmap change, so we
2251 update the cursor only if it moves. */
2252 static void cirrus_cursor_invalidate(VGAState *s1)
2253 {
2254 CirrusVGAState *s = (CirrusVGAState *)s1;
2255 int size;
2256
2257 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2258 size = 0;
2259 } else {
2260 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2261 size = 64;
2262 else
2263 size = 32;
2264 }
2265 /* invalidate last cursor and new cursor if any change */
2266 if (s->last_hw_cursor_size != size ||
2267 s->last_hw_cursor_x != s->hw_cursor_x ||
2268 s->last_hw_cursor_y != s->hw_cursor_y) {
2269
2270 invalidate_cursor1(s);
2271
2272 s->last_hw_cursor_size = size;
2273 s->last_hw_cursor_x = s->hw_cursor_x;
2274 s->last_hw_cursor_y = s->hw_cursor_y;
2275 /* compute the real cursor min and max y */
2276 cirrus_cursor_compute_yrange(s);
2277 invalidate_cursor1(s);
2278 }
2279 }
2280
2281 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2282 {
2283 CirrusVGAState *s = (CirrusVGAState *)s1;
2284 int w, h, bpp, x1, x2, poffset;
2285 unsigned int color0, color1;
2286 const uint8_t *palette, *src;
2287 uint32_t content;
2288
2289 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2290 return;
2291 /* fast test to see if the cursor intersects with the scan line */
2292 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2293 h = 64;
2294 } else {
2295 h = 32;
2296 }
2297 if (scr_y < s->hw_cursor_y ||
2298 scr_y >= (s->hw_cursor_y + h))
2299 return;
2300
2301 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2302 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2303 src += (s->sr[0x13] & 0x3c) * 256;
2304 src += (scr_y - s->hw_cursor_y) * 16;
2305 poffset = 8;
2306 content = ((uint32_t *)src)[0] |
2307 ((uint32_t *)src)[1] |
2308 ((uint32_t *)src)[2] |
2309 ((uint32_t *)src)[3];
2310 } else {
2311 src += (s->sr[0x13] & 0x3f) * 256;
2312 src += (scr_y - s->hw_cursor_y) * 4;
2313 poffset = 128;
2314 content = ((uint32_t *)src)[0] |
2315 ((uint32_t *)(src + 128))[0];
2316 }
2317 /* if nothing to draw, no need to continue */
2318 if (!content)
2319 return;
2320 w = h;
2321
2322 x1 = s->hw_cursor_x;
2323 if (x1 >= s->last_scr_width)
2324 return;
2325 x2 = s->hw_cursor_x + w;
2326 if (x2 > s->last_scr_width)
2327 x2 = s->last_scr_width;
2328 w = x2 - x1;
2329 palette = s->cirrus_hidden_palette;
2330 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2331 c6_to_8(palette[0x0 * 3 + 1]),
2332 c6_to_8(palette[0x0 * 3 + 2]));
2333 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2334 c6_to_8(palette[0xf * 3 + 1]),
2335 c6_to_8(palette[0xf * 3 + 2]));
2336 bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
2337 d1 += x1 * bpp;
2338 switch(ds_get_bits_per_pixel(s->ds)) {
2339 default:
2340 break;
2341 case 8:
2342 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2343 break;
2344 case 15:
2345 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2346 break;
2347 case 16:
2348 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2349 break;
2350 case 32:
2351 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2352 break;
2353 }
2354 }
2355
2356 /***************************************
2357 *
2358 * LFB memory access
2359 *
2360 ***************************************/
2361
2362 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2363 {
2364 CirrusVGAState *s = (CirrusVGAState *) opaque;
2365 uint32_t ret;
2366
2367 addr &= s->cirrus_addr_mask;
2368
2369 if (((s->sr[0x17] & 0x44) == 0x44) &&
2370 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2371 /* memory-mapped I/O */
2372 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2373 } else if (0) {
2374 /* XXX handle bitblt */
2375 ret = 0xff;
2376 } else {
2377 /* video memory */
2378 if ((s->gr[0x0B] & 0x14) == 0x14) {
2379 addr <<= 4;
2380 } else if (s->gr[0x0B] & 0x02) {
2381 addr <<= 3;
2382 }
2383 addr &= s->cirrus_addr_mask;
2384 ret = *(s->vram_ptr + addr);
2385 }
2386
2387 return ret;
2388 }
2389
2390 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2391 {
2392 uint32_t v;
2393 #ifdef TARGET_WORDS_BIGENDIAN
2394 v = cirrus_linear_readb(opaque, addr) << 8;
2395 v |= cirrus_linear_readb(opaque, addr + 1);
2396 #else
2397 v = cirrus_linear_readb(opaque, addr);
2398 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2399 #endif
2400 return v;
2401 }
2402
2403 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2404 {
2405 uint32_t v;
2406 #ifdef TARGET_WORDS_BIGENDIAN
2407 v = cirrus_linear_readb(opaque, addr) << 24;
2408 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2409 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2410 v |= cirrus_linear_readb(opaque, addr + 3);
2411 #else
2412 v = cirrus_linear_readb(opaque, addr);
2413 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2414 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2415 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2416 #endif
2417 return v;
2418 }
2419
2420 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2421 uint32_t val)
2422 {
2423 CirrusVGAState *s = (CirrusVGAState *) opaque;
2424 unsigned mode;
2425
2426 addr &= s->cirrus_addr_mask;
2427
2428 if (((s->sr[0x17] & 0x44) == 0x44) &&
2429 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2430 /* memory-mapped I/O */
2431 cirrus_mmio_blt_write(s, addr & 0xff, val);
2432 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2433 /* bitblt */
2434 *s->cirrus_srcptr++ = (uint8_t) val;
2435 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2436 cirrus_bitblt_cputovideo_next(s);
2437 }
2438 } else {
2439 /* video memory */
2440 if ((s->gr[0x0B] & 0x14) == 0x14) {
2441 addr <<= 4;
2442 } else if (s->gr[0x0B] & 0x02) {
2443 addr <<= 3;
2444 }
2445 addr &= s->cirrus_addr_mask;
2446
2447 mode = s->gr[0x05] & 0x7;
2448 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2449 *(s->vram_ptr + addr) = (uint8_t) val;
2450 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2451 } else {
2452 if ((s->gr[0x0B] & 0x14) != 0x14) {
2453 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2454 } else {
2455 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2456 }
2457 }
2458 }
2459 }
2460
2461 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2462 uint32_t val)
2463 {
2464 #ifdef TARGET_WORDS_BIGENDIAN
2465 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2466 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2467 #else
2468 cirrus_linear_writeb(opaque, addr, val & 0xff);
2469 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2470 #endif
2471 }
2472
2473 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2474 uint32_t val)
2475 {
2476 #ifdef TARGET_WORDS_BIGENDIAN
2477 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2478 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2479 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2480 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2481 #else
2482 cirrus_linear_writeb(opaque, addr, val & 0xff);
2483 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2484 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2485 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2486 #endif
2487 }
2488
2489
2490 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2491 cirrus_linear_readb,
2492 cirrus_linear_readw,
2493 cirrus_linear_readl,
2494 };
2495
2496 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2497 cirrus_linear_writeb,
2498 cirrus_linear_writew,
2499 cirrus_linear_writel,
2500 };
2501
2502 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2503 uint32_t val)
2504 {
2505 CirrusVGAState *s = (CirrusVGAState *) opaque;
2506
2507 addr &= s->cirrus_addr_mask;
2508 *(s->vram_ptr + addr) = val;
2509 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2510 }
2511
2512 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2513 uint32_t val)
2514 {
2515 CirrusVGAState *s = (CirrusVGAState *) opaque;
2516
2517 addr &= s->cirrus_addr_mask;
2518 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2519 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2520 }
2521
2522 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2523 uint32_t val)
2524 {
2525 CirrusVGAState *s = (CirrusVGAState *) opaque;
2526
2527 addr &= s->cirrus_addr_mask;
2528 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2529 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2530 }
2531
2532 /***************************************
2533 *
2534 * system to screen memory access
2535 *
2536 ***************************************/
2537
2538
2539 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2540 {
2541 uint32_t ret;
2542
2543 /* XXX handle bitblt */
2544 ret = 0xff;
2545 return ret;
2546 }
2547
2548 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2549 {
2550 uint32_t v;
2551 #ifdef TARGET_WORDS_BIGENDIAN
2552 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2553 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2554 #else
2555 v = cirrus_linear_bitblt_readb(opaque, addr);
2556 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2557 #endif
2558 return v;
2559 }
2560
2561 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2562 {
2563 uint32_t v;
2564 #ifdef TARGET_WORDS_BIGENDIAN
2565 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2566 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2567 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2568 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2569 #else
2570 v = cirrus_linear_bitblt_readb(opaque, addr);
2571 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2572 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2573 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2574 #endif
2575 return v;
2576 }
2577
2578 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2579 uint32_t val)
2580 {
2581 CirrusVGAState *s = (CirrusVGAState *) opaque;
2582
2583 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2584 /* bitblt */
2585 *s->cirrus_srcptr++ = (uint8_t) val;
2586 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2587 cirrus_bitblt_cputovideo_next(s);
2588 }
2589 }
2590 }
2591
2592 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2593 uint32_t val)
2594 {
2595 #ifdef TARGET_WORDS_BIGENDIAN
2596 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2597 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2598 #else
2599 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2600 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2601 #endif
2602 }
2603
2604 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2605 uint32_t val)
2606 {
2607 #ifdef TARGET_WORDS_BIGENDIAN
2608 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2609 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2610 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2611 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2612 #else
2613 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2614 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2615 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2616 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2617 #endif
2618 }
2619
2620
2621 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2622 cirrus_linear_bitblt_readb,
2623 cirrus_linear_bitblt_readw,
2624 cirrus_linear_bitblt_readl,
2625 };
2626
2627 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2628 cirrus_linear_bitblt_writeb,
2629 cirrus_linear_bitblt_writew,
2630 cirrus_linear_bitblt_writel,
2631 };
2632
2633 static void map_linear_vram(CirrusVGAState *s)
2634 {
2635
2636 vga_dirty_log_stop((VGAState *)s);
2637 if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2638 s->map_addr = s->lfb_addr;
2639 s->map_end = s->lfb_end;
2640 cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2641 vga_dirty_log_start((VGAState *)s);
2642 }
2643
2644 if (!s->map_addr)
2645 return;
2646
2647 s->lfb_vram_mapped = 0;
2648
2649 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2650 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_UNASSIGNED);
2651 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2652 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_UNASSIGNED);
2653 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2654 && !((s->sr[0x07] & 0x01) == 0)
2655 && !((s->gr[0x0B] & 0x14) == 0x14)
2656 && !(s->gr[0x0B] & 0x02)) {
2657
2658 vga_dirty_log_stop((VGAState *)s);
2659 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2660 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2661 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2662 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2663
2664 s->lfb_vram_mapped = 1;
2665 vga_dirty_log_start((VGAState *)s);
2666 }
2667 else {
2668 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000, s->vga_io_memory);
2669 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000, s->vga_io_memory);
2670 }
2671
2672 }
2673
2674 static void unmap_linear_vram(CirrusVGAState *s)
2675 {
2676 if (s->map_addr && s->lfb_addr && s->lfb_end) {
2677 vga_dirty_log_stop((VGAState *)s);
2678 s->map_addr = s->map_end = 0;
2679 }
2680
2681 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2682 s->vga_io_memory);
2683 }
2684
2685 /* Compute the memory access functions */
2686 static void cirrus_update_memory_access(CirrusVGAState *s)
2687 {
2688 unsigned mode;
2689
2690 if ((s->sr[0x17] & 0x44) == 0x44) {
2691 goto generic_io;
2692 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2693 goto generic_io;
2694 } else {
2695 if ((s->gr[0x0B] & 0x14) == 0x14) {
2696 goto generic_io;
2697 } else if (s->gr[0x0B] & 0x02) {
2698 goto generic_io;
2699 }
2700
2701 mode = s->gr[0x05] & 0x7;
2702 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2703 map_linear_vram(s);
2704 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2705 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2706 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2707 } else {
2708 generic_io:
2709 unmap_linear_vram(s);
2710 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2711 s->cirrus_linear_write[1] = cirrus_linear_writew;
2712 s->cirrus_linear_write[2] = cirrus_linear_writel;
2713 }
2714 }
2715 }
2716
2717
2718 /* I/O ports */
2719
2720 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2721 {
2722 CirrusVGAState *s = opaque;
2723 int val, index;
2724
2725 /* check port range access depending on color/monochrome mode */
2726 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2727 || (addr >= 0x3d0 && addr <= 0x3df
2728 && !(s->msr & MSR_COLOR_EMULATION))) {
2729 val = 0xff;
2730 } else {
2731 switch (addr) {
2732 case 0x3c0:
2733 if (s->ar_flip_flop == 0) {
2734 val = s->ar_index;
2735 } else {
2736 val = 0;
2737 }
2738 break;
2739 case 0x3c1:
2740 index = s->ar_index & 0x1f;
2741 if (index < 21)
2742 val = s->ar[index];
2743 else
2744 val = 0;
2745 break;
2746 case 0x3c2:
2747 val = s->st00;
2748 break;
2749 case 0x3c4:
2750 val = s->sr_index;
2751 break;
2752 case 0x3c5:
2753 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2754 break;
2755 val = s->sr[s->sr_index];
2756 #ifdef DEBUG_VGA_REG
2757 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2758 #endif
2759 break;
2760 case 0x3c6:
2761 cirrus_read_hidden_dac(s, &val);
2762 break;
2763 case 0x3c7:
2764 val = s->dac_state;
2765 break;
2766 case 0x3c8:
2767 val = s->dac_write_index;
2768 s->cirrus_hidden_dac_lockindex = 0;
2769 break;
2770 case 0x3c9:
2771 if (cirrus_hook_read_palette(s, &val))
2772 break;
2773 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2774 if (++s->dac_sub_index == 3) {
2775 s->dac_sub_index = 0;
2776 s->dac_read_index++;
2777 }
2778 break;
2779 case 0x3ca:
2780 val = s->fcr;
2781 break;
2782 case 0x3cc:
2783 val = s->msr;
2784 break;
2785 case 0x3ce:
2786 val = s->gr_index;
2787 break;
2788 case 0x3cf:
2789 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2790 break;
2791 val = s->gr[s->gr_index];
2792 #ifdef DEBUG_VGA_REG
2793 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2794 #endif
2795 break;
2796 case 0x3b4:
2797 case 0x3d4:
2798 val = s->cr_index;
2799 break;
2800 case 0x3b5:
2801 case 0x3d5:
2802 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2803 break;
2804 val = s->cr[s->cr_index];
2805 #ifdef DEBUG_VGA_REG
2806 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2807 #endif
2808 break;
2809 case 0x3ba:
2810 case 0x3da:
2811 /* just toggle to fool polling */
2812 val = s->st01 = s->retrace((VGAState *) s);
2813 s->ar_flip_flop = 0;
2814 break;
2815 default:
2816 val = 0x00;
2817 break;
2818 }
2819 }
2820 #if defined(DEBUG_VGA)
2821 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2822 #endif
2823 return val;
2824 }
2825
2826 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2827 {
2828 CirrusVGAState *s = opaque;
2829 int index;
2830
2831 /* check port range access depending on color/monochrome mode */
2832 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2833 || (addr >= 0x3d0 && addr <= 0x3df
2834 && !(s->msr & MSR_COLOR_EMULATION)))
2835 return;
2836
2837 #ifdef DEBUG_VGA
2838 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2839 #endif
2840
2841 switch (addr) {
2842 case 0x3c0:
2843 if (s->ar_flip_flop == 0) {
2844 val &= 0x3f;
2845 s->ar_index = val;
2846 } else {
2847 index = s->ar_index & 0x1f;
2848 switch (index) {
2849 case 0x00 ... 0x0f:
2850 s->ar[index] = val & 0x3f;
2851 break;
2852 case 0x10:
2853 s->ar[index] = val & ~0x10;
2854 break;
2855 case 0x11:
2856 s->ar[index] = val;
2857 break;
2858 case 0x12:
2859 s->ar[index] = val & ~0xc0;
2860 break;
2861 case 0x13:
2862 s->ar[index] = val & ~0xf0;
2863 break;
2864 case 0x14:
2865 s->ar[index] = val & ~0xf0;
2866 break;
2867 default:
2868 break;
2869 }
2870 }
2871 s->ar_flip_flop ^= 1;
2872 break;
2873 case 0x3c2:
2874 s->msr = val & ~0x10;
2875 s->update_retrace_info((VGAState *) s);
2876 break;
2877 case 0x3c4:
2878 s->sr_index = val;
2879 break;
2880 case 0x3c5:
2881 if (cirrus_hook_write_sr(s, s->sr_index, val))
2882 break;
2883 #ifdef DEBUG_VGA_REG
2884 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2885 #endif
2886 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2887 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2888 break;
2889 case 0x3c6:
2890 cirrus_write_hidden_dac(s, val);
2891 break;
2892 case 0x3c7:
2893 s->dac_read_index = val;
2894 s->dac_sub_index = 0;
2895 s->dac_state = 3;
2896 break;
2897 case 0x3c8:
2898 s->dac_write_index = val;
2899 s->dac_sub_index = 0;
2900 s->dac_state = 0;
2901 break;
2902 case 0x3c9:
2903 if (cirrus_hook_write_palette(s, val))
2904 break;
2905 s->dac_cache[s->dac_sub_index] = val;
2906 if (++s->dac_sub_index == 3) {
2907 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2908 s->dac_sub_index = 0;
2909 s->dac_write_index++;
2910 }
2911 break;
2912 case 0x3ce:
2913 s->gr_index = val;
2914 break;
2915 case 0x3cf:
2916 if (cirrus_hook_write_gr(s, s->gr_index, val))
2917 break;
2918 #ifdef DEBUG_VGA_REG
2919 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2920 #endif
2921 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2922 break;
2923 case 0x3b4:
2924 case 0x3d4:
2925 s->cr_index = val;
2926 break;
2927 case 0x3b5:
2928 case 0x3d5:
2929 if (cirrus_hook_write_cr(s, s->cr_index, val))
2930 break;
2931 #ifdef DEBUG_VGA_REG
2932 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2933 #endif
2934 /* handle CR0-7 protection */
2935 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2936 /* can always write bit 4 of CR7 */
2937 if (s->cr_index == 7)
2938 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2939 return;
2940 }
2941 switch (s->cr_index) {
2942 case 0x01: /* horizontal display end */
2943 case 0x07:
2944 case 0x09:
2945 case 0x0c:
2946 case 0x0d:
2947 case 0x12: /* vertical display end */
2948 s->cr[s->cr_index] = val;
2949 break;
2950
2951 default:
2952 s->cr[s->cr_index] = val;
2953 break;
2954 }
2955
2956 switch(s->cr_index) {
2957 case 0x00:
2958 case 0x04:
2959 case 0x05:
2960 case 0x06:
2961 case 0x07:
2962 case 0x11:
2963 case 0x17:
2964 s->update_retrace_info((VGAState *) s);
2965 break;
2966 }
2967 break;
2968 case 0x3ba:
2969 case 0x3da:
2970 s->fcr = val & 0x10;
2971 break;
2972 }
2973 }
2974
2975 /***************************************
2976 *
2977 * memory-mapped I/O access
2978 *
2979 ***************************************/
2980
2981 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2982 {
2983 CirrusVGAState *s = (CirrusVGAState *) opaque;
2984
2985 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2986
2987 if (addr >= 0x100) {
2988 return cirrus_mmio_blt_read(s, addr - 0x100);
2989 } else {
2990 return vga_ioport_read(s, addr + 0x3c0);
2991 }
2992 }
2993
2994 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2995 {
2996 uint32_t v;
2997 #ifdef TARGET_WORDS_BIGENDIAN
2998 v = cirrus_mmio_readb(opaque, addr) << 8;
2999 v |= cirrus_mmio_readb(opaque, addr + 1);
3000 #else
3001 v = cirrus_mmio_readb(opaque, addr);
3002 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3003 #endif
3004 return v;
3005 }
3006
3007 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
3008 {
3009 uint32_t v;
3010 #ifdef TARGET_WORDS_BIGENDIAN
3011 v = cirrus_mmio_readb(opaque, addr) << 24;
3012 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3013 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3014 v |= cirrus_mmio_readb(opaque, addr + 3);
3015 #else
3016 v = cirrus_mmio_readb(opaque, addr);
3017 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3018 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3019 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3020 #endif
3021 return v;
3022 }
3023
3024 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3025 uint32_t val)
3026 {
3027 CirrusVGAState *s = (CirrusVGAState *) opaque;
3028
3029 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3030
3031 if (addr >= 0x100) {
3032 cirrus_mmio_blt_write(s, addr - 0x100, val);
3033 } else {
3034 vga_ioport_write(s, addr + 0x3c0, val);
3035 }
3036 }
3037
3038 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3039 uint32_t val)
3040 {
3041 #ifdef TARGET_WORDS_BIGENDIAN
3042 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3043 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3044 #else
3045 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3046 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3047 #endif
3048 }
3049
3050 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3051 uint32_t val)
3052 {
3053 #ifdef TARGET_WORDS_BIGENDIAN
3054 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3055 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3056 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3057 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3058 #else
3059 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3060 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3061 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3062 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3063 #endif
3064 }
3065
3066
3067 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3068 cirrus_mmio_readb,
3069 cirrus_mmio_readw,
3070 cirrus_mmio_readl,
3071 };
3072
3073 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3074 cirrus_mmio_writeb,
3075 cirrus_mmio_writew,
3076 cirrus_mmio_writel,
3077 };
3078
3079 /* load/save state */
3080
3081 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3082 {
3083 CirrusVGAState *s = opaque;
3084
3085 if (s->pci_dev)
3086 pci_device_save(s->pci_dev, f);
3087
3088 qemu_put_be32s(f, &s->latch);
3089 qemu_put_8s(f, &s->sr_index);
3090 qemu_put_buffer(f, s->sr, 256);
3091 qemu_put_8s(f, &s->gr_index);
3092 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3093 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3094 qemu_put_buffer(f, s->gr + 2, 254);
3095 qemu_put_8s(f, &s->ar_index);
3096 qemu_put_buffer(f, s->ar, 21);
3097 qemu_put_be32(f, s->ar_flip_flop);
3098 qemu_put_8s(f, &s->cr_index);
3099 qemu_put_buffer(f, s->cr, 256);
3100 qemu_put_8s(f, &s->msr);
3101 qemu_put_8s(f, &s->fcr);
3102 qemu_put_8s(f, &s->st00);
3103 qemu_put_8s(f, &s->st01);
3104
3105 qemu_put_8s(f, &s->dac_state);
3106 qemu_put_8s(f, &s->dac_sub_index);
3107 qemu_put_8s(f, &s->dac_read_index);
3108 qemu_put_8s(f, &s->dac_write_index);
3109 qemu_put_buffer(f, s->dac_cache, 3);
3110 qemu_put_buffer(f, s->palette, 768);
3111
3112 qemu_put_be32(f, s->bank_offset);
3113
3114 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3115 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3116
3117 qemu_put_be32s(f, &s->hw_cursor_x);
3118 qemu_put_be32s(f, &s->hw_cursor_y);
3119 /* XXX: we do not save the bitblt state - we assume we do not save
3120 the state when the blitter is active */
3121 }
3122
3123 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3124 {
3125 CirrusVGAState *s = opaque;
3126 int ret;
3127
3128 if (version_id > 2)
3129 return -EINVAL;
3130
3131 if (s->pci_dev && version_id >= 2) {
3132 ret = pci_device_load(s->pci_dev, f);
3133 if (ret < 0)
3134 return ret;
3135 }
3136
3137 qemu_get_be32s(f, &s->latch);
3138 qemu_get_8s(f, &s->sr_index);
3139 qemu_get_buffer(f, s->sr, 256);
3140 qemu_get_8s(f, &s->gr_index);
3141 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3142 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3143 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3144 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3145 qemu_get_buffer(f, s->gr + 2, 254);
3146 qemu_get_8s(f, &s->ar_index);
3147 qemu_get_buffer(f, s->ar, 21);
3148 s->ar_flip_flop=qemu_get_be32(f);
3149 qemu_get_8s(f, &s->cr_index);
3150 qemu_get_buffer(f, s->cr, 256);
3151 qemu_get_8s(f, &s->msr);
3152 qemu_get_8s(f, &s->fcr);
3153 qemu_get_8s(f, &s->st00);
3154 qemu_get_8s(f, &s->st01);
3155
3156 qemu_get_8s(f, &s->dac_state);
3157 qemu_get_8s(f, &s->dac_sub_index);
3158 qemu_get_8s(f, &s->dac_read_index);
3159 qemu_get_8s(f, &s->dac_write_index);
3160 qemu_get_buffer(f, s->dac_cache, 3);
3161 qemu_get_buffer(f, s->palette, 768);
3162
3163 s->bank_offset=qemu_get_be32(f);
3164
3165 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3166 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3167
3168 qemu_get_be32s(f, &s->hw_cursor_x);
3169 qemu_get_be32s(f, &s->hw_cursor_y);
3170
3171 cirrus_update_memory_access(s);
3172 /* force refresh */
3173 s->graphic_mode = -1;
3174 cirrus_update_bank_ptr(s, 0);
3175 cirrus_update_bank_ptr(s, 1);
3176 return 0;
3177 }
3178
3179 /***************************************
3180 *
3181 * initialize
3182 *
3183 ***************************************/
3184
3185 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3186 {
3187 int i;
3188 static int inited;
3189
3190 if (!inited) {
3191 inited = 1;
3192 for(i = 0;i < 256; i++)
3193 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3194 rop_to_index[CIRRUS_ROP_0] = 0;
3195 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3196 rop_to_index[CIRRUS_ROP_NOP] = 2;
3197 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3198 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3199 rop_to_index[CIRRUS_ROP_SRC] = 5;
3200 rop_to_index[CIRRUS_ROP_1] = 6;
3201 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3202 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3203 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3204 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3205 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3206 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3207 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3208 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3209 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3210 }
3211
3212 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3213
3214 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3215 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3216 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3217 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3218
3219 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3220
3221 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3222 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3223 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3224 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3225
3226 s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3227 cirrus_vga_mem_write, s);
3228 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3229 s->vga_io_memory);
3230 if (kvm_enabled())
3231 qemu_kvm_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3232
3233 s->sr[0x06] = 0x0f;
3234 if (device_id == CIRRUS_ID_CLGD5446) {
3235 /* 4MB 64 bit memory config, always PCI */
3236 s->sr[0x1F] = 0x2d; // MemClock
3237 s->gr[0x18] = 0x0f; // fastest memory configuration
3238 #if 1
3239 s->sr[0x0f] = 0x98;
3240 s->sr[0x17] = 0x20;
3241 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3242 s->real_vram_size = 4096 * 1024;
3243 #else
3244 s->sr[0x0f] = 0x18;
3245 s->sr[0x17] = 0x20;
3246 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3247 s->real_vram_size = 2048 * 1024;
3248 #endif
3249 } else {
3250 s->sr[0x1F] = 0x22; // MemClock
3251 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3252 if (is_pci)
3253 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3254 else
3255 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3256 s->real_vram_size = 2048 * 1024;
3257 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3258 }
3259 s->cr[0x27] = device_id;
3260
3261 /* Win2K seems to assume that the pattern buffer is at 0xff
3262 initially ! */
3263 memset(s->vram_ptr, 0xff, s->real_vram_size);
3264
3265 s->cirrus_hidden_dac_lockindex = 5;
3266 s->cirrus_hidden_dac_data = 0;
3267
3268 /* I/O handler for LFB */
3269 s->cirrus_linear_io_addr =
3270 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3271 s);
3272 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3273
3274 /* I/O handler for LFB */
3275 s->cirrus_linear_bitblt_io_addr =
3276 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3277 s);
3278
3279 /* I/O handler for memory-mapped I/O */
3280 s->cirrus_mmio_io_addr =
3281 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3282
3283 /* XXX: s->vram_size must be a power of two */
3284 s->cirrus_addr_mask = s->real_vram_size - 1;
3285 s->linear_mmio_mask = s->real_vram_size - 256;
3286
3287 s->get_bpp = cirrus_get_bpp;
3288 s->get_offsets = cirrus_get_offsets;
3289 s->get_resolution = cirrus_get_resolution;
3290 s->cursor_invalidate = cirrus_cursor_invalidate;
3291 s->cursor_draw_line = cirrus_cursor_draw_line;
3292
3293 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3294 }
3295
3296 /***************************************
3297 *
3298 * ISA bus support
3299 *
3300 ***************************************/
3301
3302 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3303 ram_addr_t vga_ram_offset, int vga_ram_size)
3304 {
3305 CirrusVGAState *s;
3306
3307 s = qemu_mallocz(sizeof(CirrusVGAState));
3308
3309 vga_common_init((VGAState *)s,
3310 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3311 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3312 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3313 s->screen_dump, s->text_update, s);
3314 /* XXX ISA-LFB support */
3315 }
3316
3317 /***************************************
3318 *
3319 * PCI bus support
3320 *
3321 ***************************************/
3322
3323 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3324 uint32_t addr, uint32_t size, int type)
3325 {
3326 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3327
3328 /* XXX: add byte swapping apertures */
3329 cpu_register_physical_memory(addr, s->vram_size,
3330 s->cirrus_linear_io_addr);
3331 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3332 s->cirrus_linear_bitblt_io_addr);
3333
3334 s->map_addr = s->map_end = 0;
3335 s->lfb_addr = addr & TARGET_PAGE_MASK;
3336 s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3337 /* account for overflow */
3338 if (s->lfb_end < addr + VGA_RAM_SIZE)
3339 s->lfb_end = addr + VGA_RAM_SIZE;
3340 }
3341
3342 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3343 uint32_t addr, uint32_t size, int type)
3344 {
3345 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3346
3347 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3348 s->cirrus_mmio_io_addr);
3349 }
3350
3351 static void pci_cirrus_write_config(PCIDevice *d,
3352 uint32_t address, uint32_t val, int len)
3353 {
3354 PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
3355 CirrusVGAState *s = &pvs->cirrus_vga;
3356
3357 vga_dirty_log_stop((VGAState *)s);
3358 pci_default_write_config(d, address, val, len);
3359 vga_dirty_log_start((VGAState *)s);
3360 }
3361
3362 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3363 ram_addr_t vga_ram_offset, int vga_ram_size)
3364 {
3365 PCICirrusVGAState *d;
3366 uint8_t *pci_conf;
3367 CirrusVGAState *s;
3368 int device_id;
3369
3370 device_id = CIRRUS_ID_CLGD5446;
3371
3372 /* setup PCI configuration registers */
3373 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3374 sizeof(PCICirrusVGAState),
3375 -1, NULL, pci_cirrus_write_config);
3376 pci_conf = d->dev.config;
3377 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3378 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3379 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3380 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3381 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3382 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3383 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3384 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3385
3386 /* setup VGA */
3387 s = &d->cirrus_vga;
3388 vga_common_init((VGAState *)s,
3389 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3390 cirrus_init_common(s, device_id, 1);
3391
3392 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3393 s->screen_dump, s->text_update, s);
3394
3395 s->pci_dev = (PCIDevice *)d;
3396
3397 /* setup memory space */
3398 /* memory #0 LFB */
3399 /* memory #1 memory-mapped I/O */
3400 /* XXX: s->vram_size must be a power of two */
3401 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3402 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3403 if (device_id == CIRRUS_ID_CLGD5446) {
3404 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3405 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3406 }
3407 /* XXX: ROM BIOS */
3408 }
Patches shipped by Fedora