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Remove leftover from previous way to load 64 bit constants
[qemu-kvm/fedora.git] / hw / nseries.c
blob5e9d8f79756b178ebaf4537f518de0cb4e4e6c86
1 /*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23 #include "qemu-common.h"
24 #include "sysemu.h"
25 #include "omap.h"
26 #include "arm-misc.h"
27 #include "irq.h"
28 #include "console.h"
29 #include "boards.h"
30 #include "i2c.h"
31 #include "devices.h"
32 #include "flash.h"
33 #include "hw.h"
34
35 /* Nokia N8x0 support */
36 struct n800_s {
37 struct omap_mpu_state_s *cpu;
38
39 struct rfbi_chip_s blizzard;
40 struct {
41 void *opaque;
42 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
43 struct uwire_slave_s *chip;
44 } ts;
45 i2c_bus *i2c;
46
47 int keymap[0x80];
48 i2c_slave *kbd;
49
50 struct tusb_s *usb;
51 void *retu;
52 void *tahvo;
53 };
54
55 /* GPIO pins */
56 #define N8X0_TUSB_ENABLE_GPIO 0
57 #define N800_MMC2_WP_GPIO 8
58 #define N800_UNKNOWN_GPIO0 9 /* out */
59 #define N810_MMC2_VIOSD_GPIO 9
60 #define N810_HEADSET_AMP_GPIO 10
61 #define N800_CAM_TURN_GPIO 12
62 #define N810_GPS_RESET_GPIO 12
63 #define N800_BLIZZARD_POWERDOWN_GPIO 15
64 #define N800_MMC1_WP_GPIO 23
65 #define N810_MMC2_VSD_GPIO 23
66 #define N8X0_ONENAND_GPIO 26
67 #define N810_BLIZZARD_RESET_GPIO 30
68 #define N800_UNKNOWN_GPIO2 53 /* out */
69 #define N8X0_TUSB_INT_GPIO 58
70 #define N8X0_BT_WKUP_GPIO 61
71 #define N8X0_STI_GPIO 62
72 #define N8X0_CBUS_SEL_GPIO 64
73 #define N8X0_CBUS_DAT_GPIO 65
74 #define N8X0_CBUS_CLK_GPIO 66
75 #define N8X0_WLAN_IRQ_GPIO 87
76 #define N8X0_BT_RESET_GPIO 92
77 #define N8X0_TEA5761_CS_GPIO 93
78 #define N800_UNKNOWN_GPIO 94
79 #define N810_TSC_RESET_GPIO 94
80 #define N800_CAM_ACT_GPIO 95
81 #define N810_GPS_WAKEUP_GPIO 95
82 #define N8X0_MMC_CS_GPIO 96
83 #define N8X0_WLAN_PWR_GPIO 97
84 #define N8X0_BT_HOST_WKUP_GPIO 98
85 #define N810_SPEAKER_AMP_GPIO 101
86 #define N810_KB_LOCK_GPIO 102
87 #define N800_TSC_TS_GPIO 103
88 #define N810_TSC_TS_GPIO 106
89 #define N8X0_HEADPHONE_GPIO 107
90 #define N8X0_RETU_GPIO 108
91 #define N800_TSC_KP_IRQ_GPIO 109
92 #define N810_KEYBOARD_GPIO 109
93 #define N800_BAT_COVER_GPIO 110
94 #define N810_SLIDE_GPIO 110
95 #define N8X0_TAHVO_GPIO 111
96 #define N800_UNKNOWN_GPIO4 112 /* out */
97 #define N810_SLEEPX_LED_GPIO 112
98 #define N800_TSC_RESET_GPIO 118 /* ? */
99 #define N810_AIC33_RESET_GPIO 118
100 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
101 #define N8X0_TMP105_GPIO 125
102
103 /* Config */
104 #define XLDR_LL_UART 1
105
106 /* Addresses on the I2C bus 0 */
107 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
108 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
109 #define N810_LP5521_ADDR 0x32 /* LEDs */
110 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
111 #define N810_LM8323_ADDR 0x45 /* Keyboard */
112 /* Addresses on the I2C bus 1 */
113 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
114 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
115
116 /* Chipselects on GPMC NOR interface */
117 #define N8X0_ONENAND_CS 0
118 #define N8X0_USB_ASYNC_CS 1
119 #define N8X0_USB_SYNC_CS 4
120
121 static void n800_mmc_cs_cb(void *opaque, int line, int level)
122 {
123 /* TODO: this seems to actually be connected to the menelaus, to
124 * which also both MMC slots connect. */
125 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
126
127 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
128 }
129
130 static void n8x0_gpio_setup(struct n800_s *s)
131 {
132 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
133 omap2_gpio_out_set(s->cpu->gpif, N8X0_MMC_CS_GPIO, mmc_cs[0]);
134
135 qemu_irq_lower(omap2_gpio_in_get(s->cpu->gpif, N800_BAT_COVER_GPIO)[0]);
136 }
137
138 static void n8x0_nand_setup(struct n800_s *s)
139 {
140 /* Either ec40xx or ec48xx are OK for the ID */
141 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
142 onenand_base_unmap,
143 onenand_init(0xec4800, 1,
144 omap2_gpio_in_get(s->cpu->gpif,
145 N8X0_ONENAND_GPIO)[0]));
146 }
147
148 static void n8x0_i2c_setup(struct n800_s *s)
149 {
150 qemu_irq tmp_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TMP105_GPIO)[0];
151
152 /* Attach the CPU on one end of our I2C bus. */
153 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
154
155 /* Attach a menelaus PM chip */
156 i2c_set_slave_address(
157 twl92230_init(s->i2c,
158 s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]),
159 N8X0_MENELAUS_ADDR);
160
161 /* Attach a TMP105 PM chip (A0 wired to ground) */
162 i2c_set_slave_address(tmp105_init(s->i2c, tmp_irq), N8X0_TMP105_ADDR);
163 }
164
165 /* Touchscreen and keypad controller */
166 static struct mouse_transform_info_s n800_pointercal = {
167 .x = 800,
168 .y = 480,
169 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
170 };
171
172 static struct mouse_transform_info_s n810_pointercal = {
173 .x = 800,
174 .y = 480,
175 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
176 };
177
178 #define RETU_KEYCODE 61 /* F3 */
179
180 static void n800_key_event(void *opaque, int keycode)
181 {
182 struct n800_s *s = (struct n800_s *) opaque;
183 int code = s->keymap[keycode & 0x7f];
184
185 if (code == -1) {
186 if ((keycode & 0x7f) == RETU_KEYCODE)
187 retu_key_event(s->retu, !(keycode & 0x80));
188 return;
189 }
190
191 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
192 }
193
194 static const int n800_keys[16] = {
195 -1,
196 72, /* Up */
197 63, /* Home (F5) */
198 -1,
199 75, /* Left */
200 28, /* Enter */
201 77, /* Right */
202 -1,
203 1, /* Cycle (ESC) */
204 80, /* Down */
205 62, /* Menu (F4) */
206 -1,
207 66, /* Zoom- (F8) */
208 64, /* FullScreen (F6) */
209 65, /* Zoom+ (F7) */
210 -1,
211 };
212
213 static void n800_tsc_kbd_setup(struct n800_s *s)
214 {
215 int i;
216
217 /* XXX: are the three pins inverted inside the chip between the
218 * tsc and the cpu (N4111)? */
219 qemu_irq penirq = 0; /* NC */
220 qemu_irq kbirq = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_KP_IRQ_GPIO)[0];
221 qemu_irq dav = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_TS_GPIO)[0];
222
223 s->ts.chip = tsc2301_init(penirq, kbirq, dav, 0);
224 s->ts.opaque = s->ts.chip->opaque;
225 s->ts.txrx = tsc210x_txrx;
226
227 for (i = 0; i < 0x80; i ++)
228 s->keymap[i] = -1;
229 for (i = 0; i < 0x10; i ++)
230 if (n800_keys[i] >= 0)
231 s->keymap[n800_keys[i]] = i;
232
233 qemu_add_kbd_event_handler(n800_key_event, s);
234
235 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
236 }
237
238 static void n810_tsc_setup(struct n800_s *s)
239 {
240 qemu_irq pintdav = omap2_gpio_in_get(s->cpu->gpif, N810_TSC_TS_GPIO)[0];
241
242 s->ts.opaque = tsc2005_init(pintdav);
243 s->ts.txrx = tsc2005_txrx;
244
245 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
246 }
247
248 /* N810 Keyboard controller */
249 static void n810_key_event(void *opaque, int keycode)
250 {
251 struct n800_s *s = (struct n800_s *) opaque;
252 int code = s->keymap[keycode & 0x7f];
253
254 if (code == -1) {
255 if ((keycode & 0x7f) == RETU_KEYCODE)
256 retu_key_event(s->retu, !(keycode & 0x80));
257 return;
258 }
259
260 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
261 }
262
263 #define M 0
264
265 static int n810_keys[0x80] = {
266 [0x01] = 16, /* Q */
267 [0x02] = 37, /* K */
268 [0x03] = 24, /* O */
269 [0x04] = 25, /* P */
270 [0x05] = 14, /* Backspace */
271 [0x06] = 30, /* A */
272 [0x07] = 31, /* S */
273 [0x08] = 32, /* D */
274 [0x09] = 33, /* F */
275 [0x0a] = 34, /* G */
276 [0x0b] = 35, /* H */
277 [0x0c] = 36, /* J */
278
279 [0x11] = 17, /* W */
280 [0x12] = 62, /* Menu (F4) */
281 [0x13] = 38, /* L */
282 [0x14] = 40, /* ' (Apostrophe) */
283 [0x16] = 44, /* Z */
284 [0x17] = 45, /* X */
285 [0x18] = 46, /* C */
286 [0x19] = 47, /* V */
287 [0x1a] = 48, /* B */
288 [0x1b] = 49, /* N */
289 [0x1c] = 42, /* Shift (Left shift) */
290 [0x1f] = 65, /* Zoom+ (F7) */
291
292 [0x21] = 18, /* E */
293 [0x22] = 39, /* ; (Semicolon) */
294 [0x23] = 12, /* - (Minus) */
295 [0x24] = 13, /* = (Equal) */
296 [0x2b] = 56, /* Fn (Left Alt) */
297 [0x2c] = 50, /* M */
298 [0x2f] = 66, /* Zoom- (F8) */
299
300 [0x31] = 19, /* R */
301 [0x32] = 29 | M, /* Right Ctrl */
302 [0x34] = 57, /* Space */
303 [0x35] = 51, /* , (Comma) */
304 [0x37] = 72 | M, /* Up */
305 [0x3c] = 82 | M, /* Compose (Insert) */
306 [0x3f] = 64, /* FullScreen (F6) */
307
308 [0x41] = 20, /* T */
309 [0x44] = 52, /* . (Dot) */
310 [0x46] = 77 | M, /* Right */
311 [0x4f] = 63, /* Home (F5) */
312 [0x51] = 21, /* Y */
313 [0x53] = 80 | M, /* Down */
314 [0x55] = 28, /* Enter */
315 [0x5f] = 1, /* Cycle (ESC) */
316
317 [0x61] = 22, /* U */
318 [0x64] = 75 | M, /* Left */
319
320 [0x71] = 23, /* I */
321 #if 0
322 [0x75] = 28 | M, /* KP Enter (KP Enter) */
323 #else
324 [0x75] = 15, /* KP Enter (Tab) */
325 #endif
326 };
327
328 #undef M
329
330 static void n810_kbd_setup(struct n800_s *s)
331 {
332 qemu_irq kbd_irq = omap2_gpio_in_get(s->cpu->gpif, N810_KEYBOARD_GPIO)[0];
333 int i;
334
335 for (i = 0; i < 0x80; i ++)
336 s->keymap[i] = -1;
337 for (i = 0; i < 0x80; i ++)
338 if (n810_keys[i] > 0)
339 s->keymap[n810_keys[i]] = i;
340
341 qemu_add_kbd_event_handler(n810_key_event, s);
342
343 /* Attach the LM8322 keyboard to the I2C bus,
344 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
345 s->kbd = lm8323_init(s->i2c, kbd_irq);
346 i2c_set_slave_address(s->kbd, N810_LM8323_ADDR);
347 }
348
349 /* LCD MIPI DBI-C controller (URAL) */
350 struct mipid_s {
351 int resp[4];
352 int param[4];
353 int p;
354 int pm;
355 int cmd;
356
357 int sleep;
358 int booster;
359 int te;
360 int selfcheck;
361 int partial;
362 int normal;
363 int vscr;
364 int invert;
365 int onoff;
366 int gamma;
367 uint32_t id;
368 };
369
370 static void mipid_reset(struct mipid_s *s)
371 {
372 if (!s->sleep)
373 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
374
375 s->pm = 0;
376 s->cmd = 0;
377
378 s->sleep = 1;
379 s->booster = 0;
380 s->selfcheck =
381 (1 << 7) | /* Register loading OK. */
382 (1 << 5) | /* The chip is attached. */
383 (1 << 4); /* Display glass still in one piece. */
384 s->te = 0;
385 s->partial = 0;
386 s->normal = 1;
387 s->vscr = 0;
388 s->invert = 0;
389 s->onoff = 1;
390 s->gamma = 0;
391 }
392
393 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
394 {
395 struct mipid_s *s = (struct mipid_s *) opaque;
396 uint8_t ret;
397
398 if (len > 9)
399 cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
400 __FUNCTION__, len);
401
402 if (s->p >= sizeof(s->resp) / sizeof(*s->resp))
403 ret = 0;
404 else
405 ret = s->resp[s->p ++];
406 if (s->pm --> 0)
407 s->param[s->pm] = cmd;
408 else
409 s->cmd = cmd;
410
411 switch (s->cmd) {
412 case 0x00: /* NOP */
413 break;
414
415 case 0x01: /* SWRESET */
416 mipid_reset(s);
417 break;
418
419 case 0x02: /* BSTROFF */
420 s->booster = 0;
421 break;
422 case 0x03: /* BSTRON */
423 s->booster = 1;
424 break;
425
426 case 0x04: /* RDDID */
427 s->p = 0;
428 s->resp[0] = (s->id >> 16) & 0xff;
429 s->resp[1] = (s->id >> 8) & 0xff;
430 s->resp[2] = (s->id >> 0) & 0xff;
431 break;
432
433 case 0x06: /* RD_RED */
434 case 0x07: /* RD_GREEN */
435 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
436 * for the bootloader one needs to change this. */
437 case 0x08: /* RD_BLUE */
438 s->p = 0;
439 /* TODO: return first pixel components */
440 s->resp[0] = 0x01;
441 break;
442
443 case 0x09: /* RDDST */
444 s->p = 0;
445 s->resp[0] = s->booster << 7;
446 s->resp[1] = (5 << 4) | (s->partial << 2) |
447 (s->sleep << 1) | s->normal;
448 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
449 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
450 s->resp[3] = s->gamma << 6;
451 break;
452
453 case 0x0a: /* RDDPM */
454 s->p = 0;
455 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
456 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
457 break;
458 case 0x0b: /* RDDMADCTR */
459 s->p = 0;
460 s->resp[0] = 0;
461 break;
462 case 0x0c: /* RDDCOLMOD */
463 s->p = 0;
464 s->resp[0] = 5; /* 65K colours */
465 break;
466 case 0x0d: /* RDDIM */
467 s->p = 0;
468 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
469 break;
470 case 0x0e: /* RDDSM */
471 s->p = 0;
472 s->resp[0] = s->te << 7;
473 break;
474 case 0x0f: /* RDDSDR */
475 s->p = 0;
476 s->resp[0] = s->selfcheck;
477 break;
478
479 case 0x10: /* SLPIN */
480 s->sleep = 1;
481 break;
482 case 0x11: /* SLPOUT */
483 s->sleep = 0;
484 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
485 break;
486
487 case 0x12: /* PTLON */
488 s->partial = 1;
489 s->normal = 0;
490 s->vscr = 0;
491 break;
492 case 0x13: /* NORON */
493 s->partial = 0;
494 s->normal = 1;
495 s->vscr = 0;
496 break;
497
498 case 0x20: /* INVOFF */
499 s->invert = 0;
500 break;
501 case 0x21: /* INVON */
502 s->invert = 1;
503 break;
504
505 case 0x22: /* APOFF */
506 case 0x23: /* APON */
507 goto bad_cmd;
508
509 case 0x25: /* WRCNTR */
510 if (s->pm < 0)
511 s->pm = 1;
512 goto bad_cmd;
513
514 case 0x26: /* GAMSET */
515 if (!s->pm)
516 s->gamma = ffs(s->param[0] & 0xf) - 1;
517 else if (s->pm < 0)
518 s->pm = 1;
519 break;
520
521 case 0x28: /* DISPOFF */
522 s->onoff = 0;
523 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
524 break;
525 case 0x29: /* DISPON */
526 s->onoff = 1;
527 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
528 break;
529
530 case 0x2a: /* CASET */
531 case 0x2b: /* RASET */
532 case 0x2c: /* RAMWR */
533 case 0x2d: /* RGBSET */
534 case 0x2e: /* RAMRD */
535 case 0x30: /* PTLAR */
536 case 0x33: /* SCRLAR */
537 goto bad_cmd;
538
539 case 0x34: /* TEOFF */
540 s->te = 0;
541 break;
542 case 0x35: /* TEON */
543 if (!s->pm)
544 s->te = 1;
545 else if (s->pm < 0)
546 s->pm = 1;
547 break;
548
549 case 0x36: /* MADCTR */
550 goto bad_cmd;
551
552 case 0x37: /* VSCSAD */
553 s->partial = 0;
554 s->normal = 0;
555 s->vscr = 1;
556 break;
557
558 case 0x38: /* IDMOFF */
559 case 0x39: /* IDMON */
560 case 0x3a: /* COLMOD */
561 goto bad_cmd;
562
563 case 0xb0: /* CLKINT / DISCTL */
564 case 0xb1: /* CLKEXT */
565 if (s->pm < 0)
566 s->pm = 2;
567 break;
568
569 case 0xb4: /* FRMSEL */
570 break;
571
572 case 0xb5: /* FRM8SEL */
573 case 0xb6: /* TMPRNG / INIESC */
574 case 0xb7: /* TMPHIS / NOP2 */
575 case 0xb8: /* TMPREAD / MADCTL */
576 case 0xba: /* DISTCTR */
577 case 0xbb: /* EPVOL */
578 goto bad_cmd;
579
580 case 0xbd: /* Unknown */
581 s->p = 0;
582 s->resp[0] = 0;
583 s->resp[1] = 1;
584 break;
585
586 case 0xc2: /* IFMOD */
587 if (s->pm < 0)
588 s->pm = 2;
589 break;
590
591 case 0xc6: /* PWRCTL */
592 case 0xc7: /* PPWRCTL */
593 case 0xd0: /* EPWROUT */
594 case 0xd1: /* EPWRIN */
595 case 0xd4: /* RDEV */
596 case 0xd5: /* RDRR */
597 goto bad_cmd;
598
599 case 0xda: /* RDID1 */
600 s->p = 0;
601 s->resp[0] = (s->id >> 16) & 0xff;
602 break;
603 case 0xdb: /* RDID2 */
604 s->p = 0;
605 s->resp[0] = (s->id >> 8) & 0xff;
606 break;
607 case 0xdc: /* RDID3 */
608 s->p = 0;
609 s->resp[0] = (s->id >> 0) & 0xff;
610 break;
611
612 default:
613 bad_cmd:
614 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
615 break;
616 }
617
618 return ret;
619 }
620
621 static void *mipid_init(void)
622 {
623 struct mipid_s *s = (struct mipid_s *) qemu_mallocz(sizeof(*s));
624
625 s->id = 0x838f03;
626 mipid_reset(s);
627
628 return s;
629 }
630
631 static void n8x0_spi_setup(struct n800_s *s)
632 {
633 void *tsc = s->ts.opaque;
634 void *mipid = mipid_init();
635
636 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
637 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
638 }
639
640 /* This task is normally performed by the bootloader. If we're loading
641 * a kernel directly, we need to enable the Blizzard ourselves. */
642 static void n800_dss_init(struct rfbi_chip_s *chip)
643 {
644 uint8_t *fb_blank;
645
646 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
647 chip->write(chip->opaque, 1, 0x64);
648 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
649 chip->write(chip->opaque, 1, 0x1e);
650 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
651 chip->write(chip->opaque, 1, 0xe0);
652 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
653 chip->write(chip->opaque, 1, 0x01);
654 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
655 chip->write(chip->opaque, 1, 0x06);
656 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
657 chip->write(chip->opaque, 1, 1); /* Enable bit */
658
659 chip->write(chip->opaque, 0, 0x6c);
660 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
661 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
662 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
663 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
664 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
665 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
666 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
667 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
668 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
669 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
670 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
671 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
672 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
673 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
674 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
675 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
676 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
677 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
678
679 fb_blank = memset(qemu_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
680 /* Display Memory Data Port */
681 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
682 free(fb_blank);
683 }
684
685 static void n8x0_dss_setup(struct n800_s *s, DisplayState *ds)
686 {
687 s->blizzard.opaque = s1d13745_init(0, ds);
688 s->blizzard.block = s1d13745_write_block;
689 s->blizzard.write = s1d13745_write;
690 s->blizzard.read = s1d13745_read;
691
692 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
693 }
694
695 static void n8x0_cbus_setup(struct n800_s *s)
696 {
697 qemu_irq dat_out = omap2_gpio_in_get(s->cpu->gpif, N8X0_CBUS_DAT_GPIO)[0];
698 qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0];
699 qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0];
700
701 struct cbus_s *cbus = cbus_init(dat_out);
702
703 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk);
704 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat);
705 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_SEL_GPIO, cbus->sel);
706
707 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
708 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
709 }
710
711 static void n8x0_usb_power_cb(void *opaque, int line, int level)
712 {
713 struct n800_s *s = opaque;
714
715 tusb6010_power(s->usb, level);
716 }
717
718 static void n8x0_usb_setup(struct n800_s *s)
719 {
720 qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0];
721 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
722 struct tusb_s *tusb = tusb6010_init(tusb_irq);
723
724 /* Using the NOR interface */
725 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
726 tusb6010_async_io(tusb), 0, 0, tusb);
727 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
728 tusb6010_sync_io(tusb), 0, 0, tusb);
729
730 s->usb = tusb;
731 omap2_gpio_out_set(s->cpu->gpif, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
732 }
733
734 /* Setup done before the main bootloader starts by some early setup code
735 * - used when we want to run the main bootloader in emulation. This
736 * isn't documented. */
737 static uint32_t n800_pinout[104] = {
738 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
739 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
740 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
741 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
742 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
743 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
744 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
745 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
746 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
747 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
748 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
749 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
750 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
751 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
752 0x00000000, 0x00000038, 0x00340000, 0x00000000,
753 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
754 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
755 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
756 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
757 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
758 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
759 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
760 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
761 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
762 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
763 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
764 };
765
766 static void n800_setup_nolo_tags(void *sram_base)
767 {
768 int i;
769 uint32_t *p = sram_base + 0x8000;
770 uint32_t *v = sram_base + 0xa000;
771
772 memset(p, 0, 0x3000);
773
774 strcpy((void *) (p + 0), "QEMU N800");
775
776 strcpy((void *) (p + 8), "F5");
777
778 stl_raw(p + 10, 0x04f70000);
779 strcpy((void *) (p + 9), "RX-34");
780
781 /* RAM size in MB? */
782 stl_raw(p + 12, 0x80);
783
784 /* Pointer to the list of tags */
785 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
786
787 /* The NOLO tags start here */
788 p = sram_base + 0x9000;
789 #define ADD_TAG(tag, len) \
790 stw_raw((uint16_t *) p + 0, tag); \
791 stw_raw((uint16_t *) p + 1, len); p ++; \
792 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
793
794 /* OMAP STI console? Pin out settings? */
795 ADD_TAG(0x6e01, 414);
796 for (i = 0; i < sizeof(n800_pinout) / 4; i ++)
797 stl_raw(v ++, n800_pinout[i]);
798
799 /* Kernel memsize? */
800 ADD_TAG(0x6e05, 1);
801 stl_raw(v ++, 2);
802
803 /* NOLO serial console */
804 ADD_TAG(0x6e02, 4);
805 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
806
807 #if 0
808 /* CBUS settings (Retu/AVilma) */
809 ADD_TAG(0x6e03, 6);
810 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
811 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
812 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
813 v += 2;
814 #endif
815
816 /* Nokia ASIC BB5 (Retu/Tahvo) */
817 ADD_TAG(0x6e0a, 4);
818 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
819 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
820 v ++;
821
822 /* LCD console? */
823 ADD_TAG(0x6e04, 4);
824 stw_raw((uint16_t *) v + 0, 30); /* ??? */
825 stw_raw((uint16_t *) v + 1, 24); /* ??? */
826 v ++;
827
828 #if 0
829 /* LCD settings */
830 ADD_TAG(0x6e06, 2);
831 stw_raw((uint16_t *) (v ++), 15); /* ??? */
832 #endif
833
834 /* I^2C (Menelaus) */
835 ADD_TAG(0x6e07, 4);
836 stl_raw(v ++, 0x00720000); /* ??? */
837
838 /* Unknown */
839 ADD_TAG(0x6e0b, 6);
840 stw_raw((uint16_t *) v + 0, 94); /* ??? */
841 stw_raw((uint16_t *) v + 1, 23); /* ??? */
842 stw_raw((uint16_t *) v + 2, 0); /* ??? */
843 v += 2;
844
845 /* OMAP gpio switch info */
846 ADD_TAG(0x6e0c, 80);
847 strcpy((void *) v, "bat_cover"); v += 3;
848 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
849 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
850 v += 2;
851 strcpy((void *) v, "cam_act"); v += 3;
852 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
853 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
854 v += 2;
855 strcpy((void *) v, "cam_turn"); v += 3;
856 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
857 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
858 v += 2;
859 strcpy((void *) v, "headphone"); v += 3;
860 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
861 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
862 v += 2;
863
864 /* Bluetooth */
865 ADD_TAG(0x6e0e, 12);
866 stl_raw(v ++, 0x5c623d01); /* ??? */
867 stl_raw(v ++, 0x00000201); /* ??? */
868 stl_raw(v ++, 0x00000000); /* ??? */
869
870 /* CX3110x WLAN settings */
871 ADD_TAG(0x6e0f, 8);
872 stl_raw(v ++, 0x00610025); /* ??? */
873 stl_raw(v ++, 0xffff0057); /* ??? */
874
875 /* MMC host settings */
876 ADD_TAG(0x6e10, 12);
877 stl_raw(v ++, 0xffff000f); /* ??? */
878 stl_raw(v ++, 0xffffffff); /* ??? */
879 stl_raw(v ++, 0x00000060); /* ??? */
880
881 /* OneNAND chip select */
882 ADD_TAG(0x6e11, 10);
883 stl_raw(v ++, 0x00000401); /* ??? */
884 stl_raw(v ++, 0x0002003a); /* ??? */
885 stl_raw(v ++, 0x00000002); /* ??? */
886
887 /* TEA5761 sensor settings */
888 ADD_TAG(0x6e12, 2);
889 stl_raw(v ++, 93); /* GPIO num ??? */
890
891 #if 0
892 /* Unknown tag */
893 ADD_TAG(6e09, 0);
894
895 /* Kernel UART / console */
896 ADD_TAG(6e12, 0);
897 #endif
898
899 /* End of the list */
900 stl_raw(p ++, 0x00000000);
901 stl_raw(p ++, 0x00000000);
902 }
903
904 /* This task is normally performed by the bootloader. If we're loading
905 * a kernel directly, we need to set up GPMC mappings ourselves. */
906 static void n800_gpmc_init(struct n800_s *s)
907 {
908 uint32_t config7 =
909 (0xf << 8) | /* MASKADDRESS */
910 (1 << 6) | /* CSVALID */
911 (4 << 0); /* BASEADDRESS */
912
913 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
914 (void *) &config7, sizeof(config7));
915 }
916
917 /* Setup sequence done by the bootloader */
918 static void n8x0_boot_init(void *opaque)
919 {
920 struct n800_s *s = (struct n800_s *) opaque;
921 uint32_t buf;
922
923 /* PRCM setup */
924 #define omap_writel(addr, val) \
925 buf = (val); \
926 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
927
928 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
929 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
930 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
931 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
932 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
933 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
934 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
935 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
936 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
937 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
938 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
939 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
940 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
941 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
942 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
943 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
944 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
945 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
946 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
947 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
948 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
949 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
950 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
951 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
952 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
953 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
954 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
955 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
956 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
957 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
958 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
959 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
960 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
961 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
962 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
963 (0x78 << 12) | (6 << 8));
964 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
965
966 /* GPMC setup */
967 n800_gpmc_init(s);
968
969 /* Video setup */
970 n800_dss_init(&s->blizzard);
971
972 /* CPU setup */
973 s->cpu->env->regs[15] = s->cpu->env->boot_info->loader_start;
974 s->cpu->env->GE = 0x5;
975
976 /* If the machine has a slided keyboard, open it */
977 if (s->kbd)
978 qemu_irq_raise(omap2_gpio_in_get(s->cpu->gpif, N810_SLIDE_GPIO)[0]);
979 }
980
981 #define OMAP_TAG_NOKIA_BT 0x4e01
982 #define OMAP_TAG_WLAN_CX3110X 0x4e02
983 #define OMAP_TAG_CBUS 0x4e03
984 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
985
986 static struct omap_gpiosw_info_s {
987 const char *name;
988 int line;
989 int type;
990 } n800_gpiosw_info[] = {
991 {
992 "bat_cover", N800_BAT_COVER_GPIO,
993 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
994 }, {
995 "cam_act", N800_CAM_ACT_GPIO,
996 OMAP_GPIOSW_TYPE_ACTIVITY,
997 }, {
998 "cam_turn", N800_CAM_TURN_GPIO,
999 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1000 }, {
1001 "headphone", N8X0_HEADPHONE_GPIO,
1002 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1003 },
1004 { 0 }
1005 }, n810_gpiosw_info[] = {
1006 {
1007 "gps_reset", N810_GPS_RESET_GPIO,
1008 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1009 }, {
1010 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1011 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1012 }, {
1013 "headphone", N8X0_HEADPHONE_GPIO,
1014 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1015 }, {
1016 "kb_lock", N810_KB_LOCK_GPIO,
1017 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1018 }, {
1019 "sleepx_led", N810_SLEEPX_LED_GPIO,
1020 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1021 }, {
1022 "slide", N810_SLIDE_GPIO,
1023 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1024 },
1025 { 0 }
1026 };
1027
1028 static struct omap_partition_info_s {
1029 uint32_t offset;
1030 uint32_t size;
1031 int mask;
1032 const char *name;
1033 } n800_part_info[] = {
1034 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1035 { 0x00020000, 0x00060000, 0x0, "config" },
1036 { 0x00080000, 0x00200000, 0x0, "kernel" },
1037 { 0x00280000, 0x00200000, 0x3, "initfs" },
1038 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1039
1040 { 0, 0, 0, 0 }
1041 }, n810_part_info[] = {
1042 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1043 { 0x00020000, 0x00060000, 0x0, "config" },
1044 { 0x00080000, 0x00220000, 0x0, "kernel" },
1045 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1046 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1047
1048 { 0, 0, 0, 0 }
1049 };
1050
1051 static int n8x0_atag_setup(void *p, int model)
1052 {
1053 uint8_t *b;
1054 uint16_t *w;
1055 uint32_t *l;
1056 struct omap_gpiosw_info_s *gpiosw;
1057 struct omap_partition_info_s *partition;
1058 const char *tag;
1059
1060 w = p;
1061
1062 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1063 stw_raw(w ++, 4); /* u16 len */
1064 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1065 w ++;
1066
1067 #if 0
1068 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1069 stw_raw(w ++, 4); /* u16 len */
1070 stw_raw(w ++, XLDR_LL_UART); /* u8 console_uart */
1071 stw_raw(w ++, 115200); /* u32 console_speed */
1072 #endif
1073
1074 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1075 stw_raw(w ++, 36); /* u16 len */
1076 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1077 w += 8;
1078 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1079 w += 8;
1080 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1081 stw_raw(w ++, 24); /* u8 data_lines */
1082
1083 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1084 stw_raw(w ++, 8); /* u16 len */
1085 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1086 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1087 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1088 w ++;
1089
1090 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1091 stw_raw(w ++, 4); /* u16 len */
1092 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1093 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1094
1095 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1096 for (; gpiosw->name; gpiosw ++) {
1097 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1098 stw_raw(w ++, 20); /* u16 len */
1099 strcpy((void *) w, gpiosw->name); /* char name[12] */
1100 w += 6;
1101 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1102 stw_raw(w ++, gpiosw->type);
1103 stw_raw(w ++, 0);
1104 stw_raw(w ++, 0);
1105 }
1106
1107 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1108 stw_raw(w ++, 12); /* u16 len */
1109 b = (void *) w;
1110 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1111 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1112 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1113 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1114 stb_raw(b ++, 1); /* u8 bt_uart */
1115 memset(b, 0, 6); /* u8 bd_addr[6] */
1116 b += 6;
1117 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1118 w = (void *) b;
1119
1120 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1121 stw_raw(w ++, 8); /* u16 len */
1122 stw_raw(w ++, 0x25); /* u8 chip_type */
1123 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1124 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1125 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1126
1127 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1128 stw_raw(w ++, 16); /* u16 len */
1129 if (model == 810) {
1130 stw_raw(w ++, 0x23f); /* unsigned flags */
1131 stw_raw(w ++, -1); /* s16 power_pin */
1132 stw_raw(w ++, -1); /* s16 switch_pin */
1133 stw_raw(w ++, -1); /* s16 wp_pin */
1134 stw_raw(w ++, 0x240); /* unsigned flags */
1135 stw_raw(w ++, 0xc000); /* s16 power_pin */
1136 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1137 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1138 } else {
1139 stw_raw(w ++, 0xf); /* unsigned flags */
1140 stw_raw(w ++, -1); /* s16 power_pin */
1141 stw_raw(w ++, -1); /* s16 switch_pin */
1142 stw_raw(w ++, -1); /* s16 wp_pin */
1143 stw_raw(w ++, 0); /* unsigned flags */
1144 stw_raw(w ++, 0); /* s16 power_pin */
1145 stw_raw(w ++, 0); /* s16 switch_pin */
1146 stw_raw(w ++, 0); /* s16 wp_pin */
1147 }
1148
1149 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1150 stw_raw(w ++, 4); /* u16 len */
1151 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1152 w ++;
1153
1154 partition = (model == 810) ? n810_part_info : n800_part_info;
1155 for (; partition->name; partition ++) {
1156 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1157 stw_raw(w ++, 28); /* u16 len */
1158 strcpy((void *) w, partition->name); /* char name[16] */
1159 l = (void *) (w + 8);
1160 stl_raw(l ++, partition->size); /* unsigned int size */
1161 stl_raw(l ++, partition->offset); /* unsigned int offset */
1162 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1163 w = (void *) l;
1164 }
1165
1166 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1167 stw_raw(w ++, 12); /* u16 len */
1168 #if 0
1169 strcpy((void *) w, "por"); /* char reason_str[12] */
1170 strcpy((void *) w, "charger"); /* char reason_str[12] */
1171 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1172 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1173 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1174 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1175 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1176 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1177 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1178 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1179 #else
1180 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1181 #endif
1182 w += 6;
1183
1184 tag = (model == 810) ? "RX-44" : "RX-34";
1185 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1186 stw_raw(w ++, 24); /* u16 len */
1187 strcpy((void *) w, "product"); /* char component[12] */
1188 w += 6;
1189 strcpy((void *) w, tag); /* char version[12] */
1190 w += 6;
1191
1192 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1193 stw_raw(w ++, 24); /* u16 len */
1194 strcpy((void *) w, "hw-build"); /* char component[12] */
1195 w += 6;
1196 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
1197 w += 6;
1198
1199 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1200 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1201 stw_raw(w ++, 24); /* u16 len */
1202 strcpy((void *) w, "nolo"); /* char component[12] */
1203 w += 6;
1204 strcpy((void *) w, tag); /* char version[12] */
1205 w += 6;
1206
1207 return (void *) w - p;
1208 }
1209
1210 static int n800_atag_setup(struct arm_boot_info *info, void *p)
1211 {
1212 return n8x0_atag_setup(p, 800);
1213 }
1214
1215 static int n810_atag_setup(struct arm_boot_info *info, void *p)
1216 {
1217 return n8x0_atag_setup(p, 810);
1218 }
1219
1220 static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
1221 DisplayState *ds, const char *kernel_filename,
1222 const char *kernel_cmdline, const char *initrd_filename,
1223 const char *cpu_model, struct arm_boot_info *binfo, int model)
1224 {
1225 struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s));
1226 int sdram_size = binfo->ram_size;
1227 int onenandram_size = 0x00010000;
1228
1229 if (ram_size < sdram_size + onenandram_size + OMAP242X_SRAM_SIZE) {
1230 fprintf(stderr, "This architecture uses %i bytes of memory\n",
1231 sdram_size + onenandram_size + OMAP242X_SRAM_SIZE);
1232 exit(1);
1233 }
1234
1235 s->cpu = omap2420_mpu_init(sdram_size, NULL, cpu_model);
1236
1237 /* Setup peripherals
1238 *
1239 * Believed external peripherals layout in the N810:
1240 * (spi bus 1)
1241 * tsc2005
1242 * lcd_mipid
1243 * (spi bus 2)
1244 * Conexant cx3110x (WLAN)
1245 * optional: pc2400m (WiMAX)
1246 * (i2c bus 0)
1247 * TLV320AIC33 (audio codec)
1248 * TCM825x (camera by Toshiba)
1249 * lp5521 (clever LEDs)
1250 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1251 * lm8323 (keypad, manf 00, rev 04)
1252 * (i2c bus 1)
1253 * tmp105 (temperature sensor, hwmon)
1254 * menelaus (pm)
1255 * (somewhere on i2c - maybe N800-only)
1256 * tea5761 (FM tuner)
1257 * (serial 0)
1258 * GPS
1259 * (some serial port)
1260 * csr41814 (Bluetooth)
1261 */
1262 n8x0_gpio_setup(s);
1263 n8x0_nand_setup(s);
1264 n8x0_i2c_setup(s);
1265 if (model == 800)
1266 n800_tsc_kbd_setup(s);
1267 else if (model == 810) {
1268 n810_tsc_setup(s);
1269 n810_kbd_setup(s);
1270 }
1271 n8x0_spi_setup(s);
1272 n8x0_dss_setup(s, ds);
1273 n8x0_cbus_setup(s);
1274 if (usb_enabled)
1275 n8x0_usb_setup(s);
1276
1277 /* Setup initial (reset) machine state */
1278
1279 /* Start at the OneNAND bootloader. */
1280 s->cpu->env->regs[15] = 0;
1281
1282 if (kernel_filename) {
1283 /* Or at the linux loader. */
1284 binfo->kernel_filename = kernel_filename;
1285 binfo->kernel_cmdline = kernel_cmdline;
1286 binfo->initrd_filename = initrd_filename;
1287 arm_load_kernel(s->cpu->env, binfo);
1288
1289 qemu_register_reset(n8x0_boot_init, s);
1290 n8x0_boot_init(s);
1291 }
1292
1293 if (option_rom[0] && (boot_device[0] == 'n' || !kernel_filename)) {
1294 /* No, wait, better start at the ROM. */
1295 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1296
1297 /* This is intended for loading the `secondary.bin' program from
1298 * Nokia images (the NOLO bootloader). The entry point seems
1299 * to be at OMAP2_Q2_BASE + 0x400000.
1300 *
1301 * The `2nd.bin' files contain some kind of earlier boot code and
1302 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1303 *
1304 * The code above is for loading the `zImage' file from Nokia
1305 * images. */
1306 printf("%i bytes of image loaded\n", load_image(option_rom[0],
1307 phys_ram_base + 0x400000));
1308
1309 n800_setup_nolo_tags(phys_ram_base + sdram_size);
1310 }
1311 /* FIXME: We shouldn't really be doing this here. The LCD controller
1312 will set the size once configured, so this just sets an initial
1313 size until the guest activates the display. */
1314 dpy_resize(ds, 800, 480);
1315 }
1316
1317 static struct arm_boot_info n800_binfo = {
1318 .loader_start = OMAP2_Q2_BASE,
1319 /* Actually two chips of 0x4000000 bytes each */
1320 .ram_size = 0x08000000,
1321 .board_id = 0x4f7,
1322 .atag_board = n800_atag_setup,
1323 };
1324
1325 static struct arm_boot_info n810_binfo = {
1326 .loader_start = OMAP2_Q2_BASE,
1327 /* Actually two chips of 0x4000000 bytes each */
1328 .ram_size = 0x08000000,
1329 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1330 * used by some older versions of the bootloader and 5555 is used
1331 * instead (including versions that shipped with many devices). */
1332 .board_id = 0x60c,
1333 .atag_board = n810_atag_setup,
1334 };
1335
1336 static void n800_init(ram_addr_t ram_size, int vga_ram_size,
1337 const char *boot_device, DisplayState *ds,
1338 const char *kernel_filename, const char *kernel_cmdline,
1339 const char *initrd_filename, const char *cpu_model)
1340 {
1341 return n8x0_init(ram_size, boot_device, ds,
1342 kernel_filename, kernel_cmdline, initrd_filename,
1343 cpu_model, &n800_binfo, 800);
1344 }
1345
1346 static void n810_init(ram_addr_t ram_size, int vga_ram_size,
1347 const char *boot_device, DisplayState *ds,
1348 const char *kernel_filename, const char *kernel_cmdline,
1349 const char *initrd_filename, const char *cpu_model)
1350 {
1351 return n8x0_init(ram_size, boot_device, ds,
1352 kernel_filename, kernel_cmdline, initrd_filename,
1353 cpu_model, &n810_binfo, 810);
1354 }
1355
1356 QEMUMachine n800_machine = {
1357 "n800",
1358 "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1359 n800_init,
1360 (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED,
1361 };
1362
1363 QEMUMachine n810_machine = {
1364 "n810",
1365 "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1366 n810_init,
1367 (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED,
1368 };
Patches shipped by Fedora