hw/iommu.c

   1 /*
   2  * QEMU SPARC iommu emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26
  27 /* debug iommu */
  28 //#define DEBUG_IOMMU
  29
  30 #ifdef DEBUG_IOMMU
  31 #define DPRINTF(fmt, args...) \
  32 do { printf("IOMMU: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 #define IOMMU_NREGS (3*4096/4)
  38 #define IOMMU_CTRL          (0x0000 >> 2)
  39 #define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
  40 #define IOMMU_CTRL_VERS     0x0f000000 /* Version */
  41 #define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
  42 #define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
  43 #define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
  44 #define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
  45 #define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
  46 #define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
  47 #define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
  48 #define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
  49 #define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
  50 #define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
  51 #define IOMMU_CTRL_MASK     0x0000001d
  52
  53 #define IOMMU_BASE          (0x0004 >> 2)
  54 #define IOMMU_BASE_MASK     0x07fffc00
  55
  56 #define IOMMU_TLBFLUSH      (0x0014 >> 2)
  57 #define IOMMU_TLBFLUSH_MASK 0xffffffff
  58
  59 #define IOMMU_PGFLUSH       (0x0018 >> 2)
  60 #define IOMMU_PGFLUSH_MASK  0xffffffff
  61
  62 #define IOMMU_AFSR          (0x1000 >> 2)
  63 #define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
  64 #define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
  65                                           transaction */
  66 #define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
  67                                           12.8 us. */
  68 #define IOMMU_AFSR_BE       0x10000000 /* Write access received error
  69                                           acknowledge */
  70 #define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
  71 #define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
  72 #define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
  73                                           hardware */
  74 #define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
  75 #define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
  76 #define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
  77 #define IOMMU_AFSR_MASK     0xff0fffff
  78
  79 #define IOMMU_AFAR          (0x1004 >> 2)
  80
  81 #define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
  82 #define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
  83 #define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
  84 #define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
  85 #define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
  86                                           bypass enabled */
  87 #define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
  88 #define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
  89 #define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
  90                                           produced by this device as pure
  91                                           physical. */
  92 #define IOMMU_SBCFG_MASK    0x00010003
  93
  94 #define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
  95 #define IOMMU_ARBEN_MASK    0x001f0000
  96 #define IOMMU_MID           0x00000008
  97
  98 /* The format of an iopte in the page tables */
  99 #define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
 100 #define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
 101                                           Viking/MXCC) */
 102 #define IOPTE_WRITE         0x00000004 /* Writeable */
 103 #define IOPTE_VALID         0x00000002 /* IOPTE is valid */
 104 #define IOPTE_WAZ           0x00000001 /* Write as zeros */
 105
 106 #define PAGE_SHIFT      12
 107 #define PAGE_SIZE       (1 << PAGE_SHIFT)
 108 #define PAGE_MASK       (PAGE_SIZE - 1)
 109
 110 typedef struct IOMMUState {
 111     target_phys_addr_t addr;
 112     uint32_t regs[IOMMU_NREGS];
 113     target_phys_addr_t iostart;
 114     uint32_t version;
 115 } IOMMUState;
 116
 117 static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
 118 {
 119     IOMMUState *s = opaque;
 120     target_phys_addr_t saddr;
 121
 122     saddr = (addr - s->addr) >> 2;
 123     switch (saddr) {
 124     default:
 125         DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
 126         return s->regs[saddr];
 127         break;
 128     }
 129     return 0;
 130 }
 131
 132 static void iommu_mem_writew(void *opaque, target_phys_addr_t addr,
 133                              uint32_t val)
 134 {
 135     IOMMUState *s = opaque;
 136     target_phys_addr_t saddr;
 137
 138     saddr = (addr - s->addr) >> 2;
 139     DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
 140     switch (saddr) {
 141     case IOMMU_CTRL:
 142         switch (val & IOMMU_CTRL_RNGE) {
 143         case IOMMU_RNGE_16MB:
 144             s->iostart = 0xffffffffff000000ULL;
 145             break;
 146         case IOMMU_RNGE_32MB:
 147             s->iostart = 0xfffffffffe000000ULL;
 148             break;
 149         case IOMMU_RNGE_64MB:
 150             s->iostart = 0xfffffffffc000000ULL;
 151             break;
 152         case IOMMU_RNGE_128MB:
 153             s->iostart = 0xfffffffff8000000ULL;
 154             break;
 155         case IOMMU_RNGE_256MB:
 156             s->iostart = 0xfffffffff0000000ULL;
 157             break;
 158         case IOMMU_RNGE_512MB:
 159             s->iostart = 0xffffffffe0000000ULL;
 160             break;
 161         case IOMMU_RNGE_1GB:
 162             s->iostart = 0xffffffffc0000000ULL;
 163             break;
 164         default:
 165         case IOMMU_RNGE_2GB:
 166             s->iostart = 0xffffffff80000000ULL;
 167             break;
 168         }
 169         DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
 170         s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
 171         break;
 172     case IOMMU_BASE:
 173         s->regs[saddr] = val & IOMMU_BASE_MASK;
 174         break;
 175     case IOMMU_TLBFLUSH:
 176         DPRINTF("tlb flush %x\n", val);
 177         s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
 178         break;
 179     case IOMMU_PGFLUSH:
 180         DPRINTF("page flush %x\n", val);
 181         s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
 182         break;
 183     case IOMMU_AFSR:
 184         s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
 185         break;
 186     case IOMMU_SBCFG0:
 187     case IOMMU_SBCFG1:
 188     case IOMMU_SBCFG2:
 189     case IOMMU_SBCFG3:
 190         s->regs[saddr] = val & IOMMU_SBCFG_MASK;
 191         break;
 192     case IOMMU_ARBEN:
 193         // XXX implement SBus probing: fault when reading unmapped
 194         // addresses, fault cause and address stored to MMU/IOMMU
 195         s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
 196         break;
 197     default:
 198         s->regs[saddr] = val;
 199         break;
 200     }
 201 }
 202
 203 static CPUReadMemoryFunc *iommu_mem_read[3] = {
 204     iommu_mem_readw,
 205     iommu_mem_readw,
 206     iommu_mem_readw,
 207 };
 208
 209 static CPUWriteMemoryFunc *iommu_mem_write[3] = {
 210     iommu_mem_writew,
 211     iommu_mem_writew,
 212     iommu_mem_writew,
 213 };
 214
 215 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
 216 {
 217     uint32_t ret;
 218     target_phys_addr_t iopte;
 219 #ifdef DEBUG_IOMMU
 220     target_phys_addr_t pa = addr;
 221 #endif
 222
 223     iopte = s->regs[IOMMU_BASE] << 4;
 224     addr &= ~s->iostart;
 225     iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
 226     cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
 227     tswap32s(&ret);
 228     DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
 229             ", *pte = %x\n", pa, iopte, ret);
 230
 231     return ret;
 232 }
 233
 234 static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
 235                                              target_phys_addr_t addr,
 236                                              uint32_t pte)
 237 {
 238     uint32_t tmppte;
 239     target_phys_addr_t pa;
 240
 241     tmppte = pte;
 242     pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
 243     DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
 244             " (iopte = %x)\n", addr, pa, tmppte);
 245
 246     return pa;
 247 }
 248
 249 static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
 250                            int is_write)
 251 {
 252     DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
 253     s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
 254         IOMMU_AFSR_FAV;
 255     if (!is_write)
 256         s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
 257     s->regs[IOMMU_AFAR] = addr;
 258 }
 259
 260 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
 261                            uint8_t *buf, int len, int is_write)
 262 {
 263     int l;
 264     uint32_t flags;
 265     target_phys_addr_t page, phys_addr;
 266
 267     while (len > 0) {
 268         page = addr & TARGET_PAGE_MASK;
 269         l = (page + TARGET_PAGE_SIZE) - addr;
 270         if (l > len)
 271             l = len;
 272         flags = iommu_page_get_flags(opaque, page);
 273         if (!(flags & IOPTE_VALID)) {
 274             iommu_bad_addr(opaque, page, is_write);
 275             return;
 276         }
 277         phys_addr = iommu_translate_pa(opaque, addr, flags);
 278         if (is_write) {
 279             if (!(flags & IOPTE_WRITE)) {
 280                 iommu_bad_addr(opaque, page, is_write);
 281                 return;
 282             }
 283             cpu_physical_memory_write(phys_addr, buf, len);
 284         } else {
 285             cpu_physical_memory_read(phys_addr, buf, len);
 286         }
 287         len -= l;
 288         buf += l;
 289         addr += l;
 290     }
 291 }
 292
 293 static void iommu_save(QEMUFile *f, void *opaque)
 294 {
 295     IOMMUState *s = opaque;
 296     int i;
 297
 298     for (i = 0; i < IOMMU_NREGS; i++)
 299         qemu_put_be32s(f, &s->regs[i]);
 300     qemu_put_be64s(f, &s->iostart);
 301 }
 302
 303 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
 304 {
 305     IOMMUState *s = opaque;
 306     int i;
 307
 308     if (version_id != 2)
 309         return -EINVAL;
 310
 311     for (i = 0; i < IOMMU_NREGS; i++)
 312         qemu_get_be32s(f, &s->regs[i]);
 313     qemu_get_be64s(f, &s->iostart);
 314
 315     return 0;
 316 }
 317
 318 static void iommu_reset(void *opaque)
 319 {
 320     IOMMUState *s = opaque;
 321
 322     memset(s->regs, 0, IOMMU_NREGS * 4);
 323     s->iostart = 0;
 324     s->regs[IOMMU_CTRL] = s->version;
 325     s->regs[IOMMU_ARBEN] = IOMMU_MID;
 326     s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
 327 }
 328
 329 void *iommu_init(target_phys_addr_t addr, uint32_t version)
 330 {
 331     IOMMUState *s;
 332     int iommu_io_memory;
 333
 334     s = qemu_mallocz(sizeof(IOMMUState));
 335     if (!s)
 336         return NULL;
 337
 338     s->addr = addr;
 339     s->version = version;
 340
 341     iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
 342                                              iommu_mem_write, s);
 343     cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
 344
 345     register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
 346     qemu_register_reset(iommu_reset, s);
 347     iommu_reset(s);
 348     return s;
 349 }