2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
34 //#define DEBUG_IRQ_LATENCY
35 //#define DEBUG_IRQ_COUNT
37 typedef struct PicState
{
38 uint8_t last_irr
; /* edge detection */
39 uint8_t irr
; /* interrupt request register */
40 uint8_t imr
; /* interrupt mask register */
41 uint8_t isr
; /* interrupt service register */
42 uint8_t priority_add
; /* highest irq priority */
44 uint8_t read_reg_select
;
49 uint8_t rotate_on_auto_eoi
;
50 uint8_t special_fully_nested_mode
;
51 uint8_t init4
; /* true if 4 byte init */
52 uint8_t single_mode
; /* true if slave pic is not initialized */
53 uint8_t elcr
; /* PIIX edge/trigger selection*/
55 PicState2
*pics_state
;
59 /* 0 is master pic, 1 is slave pic */
60 /* XXX: better separation between the two pics */
63 void *irq_request_opaque
;
64 /* IOAPIC callback support */
65 SetIRQFunc
*alt_irq_func
;
69 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
70 static int irq_level
[16];
72 #ifdef DEBUG_IRQ_COUNT
73 static uint64_t irq_count
[16];
76 /* set irq level. If an edge is detected, then the IRR is set to 1 */
77 static inline void pic_set_irq1(PicState
*s
, int irq
, int level
)
93 if ((s
->last_irr
& mask
) == 0)
102 /* return the highest priority found in mask (highest = smallest
103 number). Return 8 if no irq */
104 static inline int get_priority(PicState
*s
, int mask
)
110 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0)
115 /* return the pic wanted interrupt. return -1 if none */
116 static int pic_get_irq(PicState
*s
)
118 int mask
, cur_priority
, priority
;
120 mask
= s
->irr
& ~s
->imr
;
121 priority
= get_priority(s
, mask
);
124 /* compute current priority. If special fully nested mode on the
125 master, the IRQ coming from the slave is not taken into account
126 for the priority computation. */
130 if (s
->special_fully_nested_mode
&& s
== &s
->pics_state
->pics
[0])
132 cur_priority
= get_priority(s
, mask
);
133 if (priority
< cur_priority
) {
134 /* higher priority found: an irq should be generated */
135 return (priority
+ s
->priority_add
) & 7;
141 /* raise irq to CPU if necessary. must be called every time the active
143 /* XXX: should not export it, but it is needed for an APIC kludge */
144 void pic_update_irq(PicState2
*s
)
148 /* first look at slave pic */
149 irq2
= pic_get_irq(&s
->pics
[1]);
151 /* if irq request by slave pic, signal master PIC */
152 pic_set_irq1(&s
->pics
[0], 2, 1);
153 pic_set_irq1(&s
->pics
[0], 2, 0);
155 /* look at requested irq */
156 irq
= pic_get_irq(&s
->pics
[0]);
158 #if defined(DEBUG_PIC)
161 for(i
= 0; i
< 2; i
++) {
162 printf("pic%d: imr=%x irr=%x padd=%d\n",
163 i
, s
->pics
[i
].imr
, s
->pics
[i
].irr
,
164 s
->pics
[i
].priority_add
);
168 printf("pic: cpu_interrupt\n");
170 qemu_irq_raise(s
->parent_irq
);
173 /* all targets should do this rather than acking the IRQ in the cpu */
174 #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
176 qemu_irq_lower(s
->parent_irq
);
181 #ifdef DEBUG_IRQ_LATENCY
182 int64_t irq_time
[16];
185 static void i8259_set_irq(void *opaque
, int irq
, int level
)
187 PicState2
*s
= opaque
;
188 #ifdef KVM_CAP_IRQCHIP
191 if (kvm_set_irq(irq
, level
, &pic_ret
)) {
193 apic_set_irq_delivered();
198 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
199 if (level
!= irq_level
[irq
]) {
200 #if defined(DEBUG_PIC)
201 printf("i8259_set_irq: irq=%d level=%d\n", irq
, level
);
203 irq_level
[irq
] = level
;
204 #ifdef DEBUG_IRQ_COUNT
210 #ifdef DEBUG_IRQ_LATENCY
212 irq_time
[irq
] = qemu_get_clock(vm_clock
);
215 pic_set_irq1(&s
->pics
[irq
>> 3], irq
& 7, level
);
216 /* used for IOAPIC irqs */
218 s
->alt_irq_func(s
->alt_irq_opaque
, irq
, level
);
222 /* acknowledge interrupt 'irq' */
223 static inline void pic_intack(PicState
*s
, int irq
)
226 if (s
->rotate_on_auto_eoi
)
227 s
->priority_add
= (irq
+ 1) & 7;
229 s
->isr
|= (1 << irq
);
232 /* We don't clear a level sensitive interrupt here */
233 if (!(s
->elcr
& (1 << irq
)))
234 s
->irr
&= ~(1 << irq
);
238 extern int time_drift_fix
;
240 int pic_read_irq(PicState2
*s
)
242 int irq
, irq2
, intno
;
244 irq
= pic_get_irq(&s
->pics
[0]);
247 pic_intack(&s
->pics
[0], irq
);
249 if (time_drift_fix
&& irq
== 0) {
250 extern int64_t timer_acks
, timer_ints_to_push
;
252 if (timer_ints_to_push
> 0) {
253 timer_ints_to_push
--;
254 /* simulate an edge irq0, like the one generated by i8254 */
255 pic_set_irq1(&s
->pics
[0], 0, 0);
256 pic_set_irq1(&s
->pics
[0], 0, 1);
261 irq2
= pic_get_irq(&s
->pics
[1]);
263 pic_intack(&s
->pics
[1], irq2
);
265 /* spurious IRQ on slave controller */
268 intno
= s
->pics
[1].irq_base
+ irq2
;
271 intno
= s
->pics
[0].irq_base
+ irq
;
274 /* spurious IRQ on host controller */
276 intno
= s
->pics
[0].irq_base
+ irq
;
280 #ifdef DEBUG_IRQ_LATENCY
281 printf("IRQ%d latency=%0.3fus\n",
283 (double)(qemu_get_clock(vm_clock
) - irq_time
[irq
]) * 1000000.0 / ticks_per_sec
);
285 #if defined(DEBUG_PIC)
286 printf("pic_interrupt: irq=%d\n", irq
);
291 static void pic_reset(void *opaque
)
293 PicState
*s
= opaque
;
301 s
->read_reg_select
= 0;
306 s
->rotate_on_auto_eoi
= 0;
307 s
->special_fully_nested_mode
= 0;
310 /* Note: ELCR is not reset */
313 static void pic_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
315 PicState
*s
= opaque
;
316 int priority
, cmd
, irq
;
319 printf("pic_write: addr=0x%02x val=0x%02x\n", addr
, val
);
326 /* deassert a pending interrupt */
327 qemu_irq_lower(s
->pics_state
->parent_irq
);
330 s
->single_mode
= val
& 2;
332 hw_error("level sensitive irq not supported");
333 } else if (val
& 0x08) {
337 s
->read_reg_select
= val
& 1;
339 s
->special_mask
= (val
>> 5) & 1;
345 s
->rotate_on_auto_eoi
= cmd
>> 2;
347 case 1: /* end of interrupt */
349 priority
= get_priority(s
, s
->isr
);
351 irq
= (priority
+ s
->priority_add
) & 7;
352 s
->isr
&= ~(1 << irq
);
354 s
->priority_add
= (irq
+ 1) & 7;
355 pic_update_irq(s
->pics_state
);
360 s
->isr
&= ~(1 << irq
);
361 pic_update_irq(s
->pics_state
);
364 s
->priority_add
= (val
+ 1) & 7;
365 pic_update_irq(s
->pics_state
);
369 s
->isr
&= ~(1 << irq
);
370 s
->priority_add
= (irq
+ 1) & 7;
371 pic_update_irq(s
->pics_state
);
379 switch(s
->init_state
) {
383 pic_update_irq(s
->pics_state
);
386 s
->irq_base
= val
& 0xf8;
387 s
->init_state
= s
->single_mode
? (s
->init4
? 3 : 0) : 2;
397 s
->special_fully_nested_mode
= (val
>> 4) & 1;
398 s
->auto_eoi
= (val
>> 1) & 1;
405 static uint32_t pic_poll_read (PicState
*s
, uint32_t addr1
)
409 ret
= pic_get_irq(s
);
412 s
->pics_state
->pics
[0].isr
&= ~(1 << 2);
413 s
->pics_state
->pics
[0].irr
&= ~(1 << 2);
415 s
->irr
&= ~(1 << ret
);
416 s
->isr
&= ~(1 << ret
);
417 if (addr1
>> 7 || ret
!= 2)
418 pic_update_irq(s
->pics_state
);
421 pic_update_irq(s
->pics_state
);
427 static uint32_t pic_ioport_read(void *opaque
, uint32_t addr1
)
429 PicState
*s
= opaque
;
436 ret
= pic_poll_read(s
, addr1
);
440 if (s
->read_reg_select
)
449 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1
, ret
);
454 /* memory mapped interrupt status */
455 /* XXX: may be the same than pic_read_irq() */
456 uint32_t pic_intack_read(PicState2
*s
)
460 ret
= pic_poll_read(&s
->pics
[0], 0x00);
462 ret
= pic_poll_read(&s
->pics
[1], 0x80) + 8;
463 /* Prepare for ISR read */
464 s
->pics
[0].read_reg_select
= 1;
469 static void elcr_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
471 PicState
*s
= opaque
;
472 s
->elcr
= val
& s
->elcr_mask
;
475 static uint32_t elcr_ioport_read(void *opaque
, uint32_t addr1
)
477 PicState
*s
= opaque
;
481 static void kvm_kernel_pic_save_to_user(PicState
*s
)
483 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
484 struct kvm_irqchip chip
;
485 struct kvm_pic_state
*kpic
;
487 chip
.chip_id
= (&s
->pics_state
->pics
[0] == s
) ?
488 KVM_IRQCHIP_PIC_MASTER
:
489 KVM_IRQCHIP_PIC_SLAVE
;
490 kvm_get_irqchip(kvm_context
, &chip
);
491 kpic
= &chip
.chip
.pic
;
493 s
->last_irr
= kpic
->last_irr
;
497 s
->priority_add
= kpic
->priority_add
;
498 s
->irq_base
= kpic
->irq_base
;
499 s
->read_reg_select
= kpic
->read_reg_select
;
500 s
->poll
= kpic
->poll
;
501 s
->special_mask
= kpic
->special_mask
;
502 s
->init_state
= kpic
->init_state
;
503 s
->auto_eoi
= kpic
->auto_eoi
;
504 s
->rotate_on_auto_eoi
= kpic
->rotate_on_auto_eoi
;
505 s
->special_fully_nested_mode
= kpic
->special_fully_nested_mode
;
506 s
->init4
= kpic
->init4
;
507 s
->elcr
= kpic
->elcr
;
508 s
->elcr_mask
= kpic
->elcr_mask
;
512 static void kvm_kernel_pic_load_from_user(PicState
*s
)
514 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
515 struct kvm_irqchip chip
;
516 struct kvm_pic_state
*kpic
;
518 chip
.chip_id
= (&s
->pics_state
->pics
[0] == s
) ?
519 KVM_IRQCHIP_PIC_MASTER
:
520 KVM_IRQCHIP_PIC_SLAVE
;
521 kpic
= &chip
.chip
.pic
;
523 kpic
->last_irr
= s
->last_irr
;
527 kpic
->priority_add
= s
->priority_add
;
528 kpic
->irq_base
= s
->irq_base
;
529 kpic
->read_reg_select
= s
->read_reg_select
;
530 kpic
->poll
= s
->poll
;
531 kpic
->special_mask
= s
->special_mask
;
532 kpic
->init_state
= s
->init_state
;
533 kpic
->auto_eoi
= s
->auto_eoi
;
534 kpic
->rotate_on_auto_eoi
= s
->rotate_on_auto_eoi
;
535 kpic
->special_fully_nested_mode
= s
->special_fully_nested_mode
;
536 kpic
->init4
= s
->init4
;
537 kpic
->elcr
= s
->elcr
;
538 kpic
->elcr_mask
= s
->elcr_mask
;
540 kvm_set_irqchip(kvm_context
, &chip
);
544 static void pic_save(QEMUFile
*f
, void *opaque
)
546 PicState
*s
= opaque
;
548 if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
549 kvm_kernel_pic_save_to_user(s
);
552 qemu_put_8s(f
, &s
->last_irr
);
553 qemu_put_8s(f
, &s
->irr
);
554 qemu_put_8s(f
, &s
->imr
);
555 qemu_put_8s(f
, &s
->isr
);
556 qemu_put_8s(f
, &s
->priority_add
);
557 qemu_put_8s(f
, &s
->irq_base
);
558 qemu_put_8s(f
, &s
->read_reg_select
);
559 qemu_put_8s(f
, &s
->poll
);
560 qemu_put_8s(f
, &s
->special_mask
);
561 qemu_put_8s(f
, &s
->init_state
);
562 qemu_put_8s(f
, &s
->auto_eoi
);
563 qemu_put_8s(f
, &s
->rotate_on_auto_eoi
);
564 qemu_put_8s(f
, &s
->special_fully_nested_mode
);
565 qemu_put_8s(f
, &s
->init4
);
566 qemu_put_8s(f
, &s
->single_mode
);
567 qemu_put_8s(f
, &s
->elcr
);
570 static int pic_load(QEMUFile
*f
, void *opaque
, int version_id
)
572 PicState
*s
= opaque
;
577 qemu_get_8s(f
, &s
->last_irr
);
578 qemu_get_8s(f
, &s
->irr
);
579 qemu_get_8s(f
, &s
->imr
);
580 qemu_get_8s(f
, &s
->isr
);
581 qemu_get_8s(f
, &s
->priority_add
);
582 qemu_get_8s(f
, &s
->irq_base
);
583 qemu_get_8s(f
, &s
->read_reg_select
);
584 qemu_get_8s(f
, &s
->poll
);
585 qemu_get_8s(f
, &s
->special_mask
);
586 qemu_get_8s(f
, &s
->init_state
);
587 qemu_get_8s(f
, &s
->auto_eoi
);
588 qemu_get_8s(f
, &s
->rotate_on_auto_eoi
);
589 qemu_get_8s(f
, &s
->special_fully_nested_mode
);
590 qemu_get_8s(f
, &s
->init4
);
591 qemu_get_8s(f
, &s
->single_mode
);
592 qemu_get_8s(f
, &s
->elcr
);
594 if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
595 kvm_kernel_pic_load_from_user(s
);
601 /* XXX: add generic master/slave system */
602 static void pic_init1(int io_addr
, int elcr_addr
, PicState
*s
)
604 register_ioport_write(io_addr
, 2, 1, pic_ioport_write
, s
);
605 register_ioport_read(io_addr
, 2, 1, pic_ioport_read
, s
);
606 if (elcr_addr
>= 0) {
607 register_ioport_write(elcr_addr
, 1, 1, elcr_ioport_write
, s
);
608 register_ioport_read(elcr_addr
, 1, 1, elcr_ioport_read
, s
);
610 register_savevm("i8259", io_addr
, 1, pic_save
, pic_load
, s
);
611 qemu_register_reset(pic_reset
, s
);
614 void pic_info(Monitor
*mon
)
623 s
= &isa_pic
->pics
[i
];
624 monitor_printf(mon
, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
625 "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
626 i
, s
->irr
, s
->imr
, s
->isr
, s
->priority_add
,
627 s
->irq_base
, s
->read_reg_select
, s
->elcr
,
628 s
->special_fully_nested_mode
);
632 void irq_info(Monitor
*mon
)
634 #ifndef DEBUG_IRQ_COUNT
635 monitor_printf(mon
, "irq statistic code not compiled.\n");
640 monitor_printf(mon
, "IRQ statistics:\n");
641 for (i
= 0; i
< 16; i
++) {
642 count
= irq_count
[i
];
644 monitor_printf(mon
, "%2d: %" PRId64
"\n", i
, count
);
649 qemu_irq
*i8259_init(qemu_irq parent_irq
)
653 s
= qemu_mallocz(sizeof(PicState2
));
654 pic_init1(0x20, 0x4d0, &s
->pics
[0]);
655 pic_init1(0xa0, 0x4d1, &s
->pics
[1]);
656 s
->pics
[0].elcr_mask
= 0xf8;
657 s
->pics
[1].elcr_mask
= 0xde;
658 s
->parent_irq
= parent_irq
;
659 s
->pics
[0].pics_state
= s
;
660 s
->pics
[1].pics_state
= s
;
662 return qemu_allocate_irqs(i8259_set_irq
, s
, 16);
665 void pic_set_alt_irq_func(PicState2
*s
, SetIRQFunc
*alt_irq_func
,
666 void *alt_irq_opaque
)
668 s
->alt_irq_func
= alt_irq_func
;
669 s
->alt_irq_opaque
= alt_irq_opaque
;