hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  18  */
  19 #include "hw.h"
  20 #include "pc.h"
  21 #include "pci.h"
  22 #include "qemu-timer.h"
  23 #include "sysemu.h"
  24 #include "i2c.h"
  25 #include "smbus.h"
  26 #include "kvm.h"
  27 #include "qemu-kvm.h"
  28 #include "string.h"
  29
  30 //#define DEBUG
  31
  32 /* i82731AB (PIIX4) compatible power management function */
  33 #define PM_FREQ 3579545
  34
  35 #define ACPI_DBG_IO_ADDR  0xb044
  36
  37 typedef struct PIIX4PMState {
  38     PCIDevice dev;
  39     uint16_t pmsts;
  40     uint16_t pmen;
  41     uint16_t pmcntrl;
  42     uint8_t apmc;
  43     uint8_t apms;
  44     QEMUTimer *tmr_timer;
  45     int64_t tmr_overflow_time;
  46     i2c_bus *smbus;
  47     uint8_t smb_stat;
  48     uint8_t smb_ctl;
  49     uint8_t smb_cmd;
  50     uint8_t smb_addr;
  51     uint8_t smb_data0;
  52     uint8_t smb_data1;
  53     uint8_t smb_data[32];
  54     uint8_t smb_index;
  55     qemu_irq irq;
  56 } PIIX4PMState;
  57
  58 #define RSM_STS (1 << 15)
  59 #define PWRBTN_STS (1 << 8)
  60 #define RTC_EN (1 << 10)
  61 #define PWRBTN_EN (1 << 8)
  62 #define GBL_EN (1 << 5)
  63 #define TMROF_EN (1 << 0)
  64
  65 #define SCI_EN (1 << 0)
  66
  67 #define SUS_EN (1 << 13)
  68
  69 #define ACPI_ENABLE 0xf1
  70 #define ACPI_DISABLE 0xf0
  71
  72 #define SMBHSTSTS 0x00
  73 #define SMBHSTCNT 0x02
  74 #define SMBHSTCMD 0x03
  75 #define SMBHSTADD 0x04
  76 #define SMBHSTDAT0 0x05
  77 #define SMBHSTDAT1 0x06
  78 #define SMBBLKDAT 0x07
  79
  80 static PIIX4PMState *pm_state;
  81
  82 static uint32_t get_pmtmr(PIIX4PMState *s)
  83 {
  84     uint32_t d;
  85     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  86     return d & 0xffffff;
  87 }
  88
  89 static int get_pmsts(PIIX4PMState *s)
  90 {
  91     int64_t d;
  92     int pmsts;
  93     pmsts = s->pmsts;
  94     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  95     if (d >= s->tmr_overflow_time)
  96         s->pmsts |= TMROF_EN;
  97     return s->pmsts;
  98 }
  99
 100 static void pm_update_sci(PIIX4PMState *s)
 101 {
 102     int sci_level, pmsts;
 103     int64_t expire_time;
 104
 105     pmsts = get_pmsts(s);
 106     sci_level = (((pmsts & s->pmen) &
 107                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 108     qemu_set_irq(s->irq, sci_level);
 109     /* schedule a timer interruption if needed */
 110     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 111         expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
 112         qemu_mod_timer(s->tmr_timer, expire_time);
 113     } else {
 114         qemu_del_timer(s->tmr_timer);
 115     }
 116 }
 117
 118 static void pm_tmr_timer(void *opaque)
 119 {
 120     PIIX4PMState *s = opaque;
 121     pm_update_sci(s);
 122 }
 123
 124 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 125 {
 126     PIIX4PMState *s = opaque;
 127     addr &= 0x3f;
 128     switch(addr) {
 129     case 0x00:
 130         {
 131             int64_t d;
 132             int pmsts;
 133             pmsts = get_pmsts(s);
 134             if (pmsts & val & TMROF_EN) {
 135                 /* if TMRSTS is reset, then compute the new overflow time */
 136                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
 137                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 138             }
 139             s->pmsts &= ~val;
 140             pm_update_sci(s);
 141         }
 142         break;
 143     case 0x02:
 144         s->pmen = val;
 145         pm_update_sci(s);
 146         break;
 147     case 0x04:
 148         {
 149             int sus_typ;
 150             s->pmcntrl = val & ~(SUS_EN);
 151             if (val & SUS_EN) {
 152                 /* change suspend type */
 153                 sus_typ = (val >> 10) & 7;
 154                 switch(sus_typ) {
 155                 case 0: /* soft power off */
 156                     qemu_system_shutdown_request();
 157                     break;
 158                 case 1:
 159                     /* RSM_STS should be set on resume. Pretend that resume
 160                        was caused by power button */
 161                     s->pmsts |= (RSM_STS | PWRBTN_STS);
 162                     qemu_system_reset_request();
 163 #if defined(TARGET_I386)
 164                     cmos_set_s3_resume();
 165 #endif
 166                 default:
 167                     break;
 168                 }
 169             }
 170         }
 171         break;
 172     default:
 173         break;
 174     }
 175 #ifdef DEBUG
 176     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 177 #endif
 178 }
 179
 180 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 181 {
 182     PIIX4PMState *s = opaque;
 183     uint32_t val;
 184
 185     addr &= 0x3f;
 186     switch(addr) {
 187     case 0x00:
 188         val = get_pmsts(s);
 189         break;
 190     case 0x02:
 191         val = s->pmen;
 192         break;
 193     case 0x04:
 194         val = s->pmcntrl;
 195         break;
 196     default:
 197         val = 0;
 198         break;
 199     }
 200 #ifdef DEBUG
 201     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 202 #endif
 203     return val;
 204 }
 205
 206 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 207 {
 208     //    PIIX4PMState *s = opaque;
 209     addr &= 0x3f;
 210 #ifdef DEBUG
 211     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 212 #endif
 213 }
 214
 215 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 216 {
 217     PIIX4PMState *s = opaque;
 218     uint32_t val;
 219
 220     addr &= 0x3f;
 221     switch(addr) {
 222     case 0x08:
 223         val = get_pmtmr(s);
 224         break;
 225     default:
 226         val = 0;
 227         break;
 228     }
 229 #ifdef DEBUG
 230     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 231 #endif
 232     return val;
 233 }
 234
 235 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 236 {
 237     PIIX4PMState *s = opaque;
 238     addr &= 1;
 239 #ifdef DEBUG
 240     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 241 #endif
 242     if (addr == 0) {
 243         s->apmc = val;
 244
 245         /* ACPI specs 3.0, 4.7.2.5 */
 246         if (val == ACPI_ENABLE) {
 247             s->pmcntrl |= SCI_EN;
 248         } else if (val == ACPI_DISABLE) {
 249             s->pmcntrl &= ~SCI_EN;
 250         }
 251
 252         if (s->dev.config[0x5b] & (1 << 1)) {
 253             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 254         }
 255     } else {
 256         s->apms = val;
 257     }
 258 }
 259
 260 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 261 {
 262     PIIX4PMState *s = opaque;
 263     uint32_t val;
 264
 265     addr &= 1;
 266     if (addr == 0) {
 267         val = s->apmc;
 268     } else {
 269         val = s->apms;
 270     }
 271 #ifdef DEBUG
 272     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 273 #endif
 274     return val;
 275 }
 276
 277 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 278 {
 279 #if defined(DEBUG)
 280     printf("ACPI: DBG: 0x%08x\n", val);
 281 #endif
 282 }
 283
 284 static void smb_transaction(PIIX4PMState *s)
 285 {
 286     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 287     uint8_t read = s->smb_addr & 0x01;
 288     uint8_t cmd = s->smb_cmd;
 289     uint8_t addr = s->smb_addr >> 1;
 290     i2c_bus *bus = s->smbus;
 291
 292 #ifdef DEBUG
 293     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 294 #endif
 295     switch(prot) {
 296     case 0x0:
 297         smbus_quick_command(bus, addr, read);
 298         break;
 299     case 0x1:
 300         if (read) {
 301             s->smb_data0 = smbus_receive_byte(bus, addr);
 302         } else {
 303             smbus_send_byte(bus, addr, cmd);
 304         }
 305         break;
 306     case 0x2:
 307         if (read) {
 308             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 309         } else {
 310             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 311         }
 312         break;
 313     case 0x3:
 314         if (read) {
 315             uint16_t val;
 316             val = smbus_read_word(bus, addr, cmd);
 317             s->smb_data0 = val;
 318             s->smb_data1 = val >> 8;
 319         } else {
 320             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 321         }
 322         break;
 323     case 0x5:
 324         if (read) {
 325             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 326         } else {
 327             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 328         }
 329         break;
 330     default:
 331         goto error;
 332     }
 333     return;
 334
 335   error:
 336     s->smb_stat |= 0x04;
 337 }
 338
 339 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 340 {
 341     PIIX4PMState *s = opaque;
 342     addr &= 0x3f;
 343 #ifdef DEBUG
 344     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 345 #endif
 346     switch(addr) {
 347     case SMBHSTSTS:
 348         s->smb_stat = 0;
 349         s->smb_index = 0;
 350         break;
 351     case SMBHSTCNT:
 352         s->smb_ctl = val;
 353         if (val & 0x40)
 354             smb_transaction(s);
 355         break;
 356     case SMBHSTCMD:
 357         s->smb_cmd = val;
 358         break;
 359     case SMBHSTADD:
 360         s->smb_addr = val;
 361         break;
 362     case SMBHSTDAT0:
 363         s->smb_data0 = val;
 364         break;
 365     case SMBHSTDAT1:
 366         s->smb_data1 = val;
 367         break;
 368     case SMBBLKDAT:
 369         s->smb_data[s->smb_index++] = val;
 370         if (s->smb_index > 31)
 371             s->smb_index = 0;
 372         break;
 373     default:
 374         break;
 375     }
 376 }
 377
 378 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 379 {
 380     PIIX4PMState *s = opaque;
 381     uint32_t val;
 382
 383     addr &= 0x3f;
 384     switch(addr) {
 385     case SMBHSTSTS:
 386         val = s->smb_stat;
 387         break;
 388     case SMBHSTCNT:
 389         s->smb_index = 0;
 390         val = s->smb_ctl & 0x1f;
 391         break;
 392     case SMBHSTCMD:
 393         val = s->smb_cmd;
 394         break;
 395     case SMBHSTADD:
 396         val = s->smb_addr;
 397         break;
 398     case SMBHSTDAT0:
 399         val = s->smb_data0;
 400         break;
 401     case SMBHSTDAT1:
 402         val = s->smb_data1;
 403         break;
 404     case SMBBLKDAT:
 405         val = s->smb_data[s->smb_index++];
 406         if (s->smb_index > 31)
 407             s->smb_index = 0;
 408         break;
 409     default:
 410         val = 0;
 411         break;
 412     }
 413 #ifdef DEBUG
 414     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 415 #endif
 416     return val;
 417 }
 418
 419 static void pm_io_space_update(PIIX4PMState *s)
 420 {
 421     uint32_t pm_io_base;
 422
 423     if (s->dev.config[0x80] & 1) {
 424         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 425         pm_io_base &= 0xffc0;
 426
 427         /* XXX: need to improve memory and ioport allocation */
 428 #if defined(DEBUG)
 429         printf("PM: mapping to 0x%x\n", pm_io_base);
 430 #endif
 431         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 432         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 433         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 434         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 435     }
 436 }
 437
 438 static void pm_write_config(PCIDevice *d,
 439                             uint32_t address, uint32_t val, int len)
 440 {
 441     pci_default_write_config(d, address, val, len);
 442     if (address == 0x80)
 443         pm_io_space_update((PIIX4PMState *)d);
 444 }
 445
 446 static void pm_save(QEMUFile* f,void *opaque)
 447 {
 448     PIIX4PMState *s = opaque;
 449
 450     pci_device_save(&s->dev, f);
 451
 452     qemu_put_be16s(f, &s->pmsts);
 453     qemu_put_be16s(f, &s->pmen);
 454     qemu_put_be16s(f, &s->pmcntrl);
 455     qemu_put_8s(f, &s->apmc);
 456     qemu_put_8s(f, &s->apms);
 457     qemu_put_timer(f, s->tmr_timer);
 458     qemu_put_be64(f, s->tmr_overflow_time);
 459 }
 460
 461 static int pm_load(QEMUFile* f,void* opaque,int version_id)
 462 {
 463     PIIX4PMState *s = opaque;
 464     int ret;
 465
 466     if (version_id > 1)
 467         return -EINVAL;
 468
 469     ret = pci_device_load(&s->dev, f);
 470     if (ret < 0)
 471         return ret;
 472
 473     qemu_get_be16s(f, &s->pmsts);
 474     qemu_get_be16s(f, &s->pmen);
 475     qemu_get_be16s(f, &s->pmcntrl);
 476     qemu_get_8s(f, &s->apmc);
 477     qemu_get_8s(f, &s->apms);
 478     qemu_get_timer(f, s->tmr_timer);
 479     s->tmr_overflow_time=qemu_get_be64(f);
 480
 481     pm_io_space_update(s);
 482
 483     return 0;
 484 }
 485
 486 static void piix4_reset(void *opaque)
 487 {
 488     PIIX4PMState *s = opaque;
 489     uint8_t *pci_conf = s->dev.config;
 490
 491     pci_conf[0x58] = 0;
 492     pci_conf[0x59] = 0;
 493     pci_conf[0x5a] = 0;
 494     pci_conf[0x5b] = 0;
 495
 496     if (kvm_enabled()) {
 497         /* Mark SMM as already inited (until KVM supports SMM). */
 498         pci_conf[0x5B] = 0x02;
 499     }
 500 }
 501
 502 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 503                        qemu_irq sci_irq)
 504 {
 505     PIIX4PMState *s;
 506     uint8_t *pci_conf;
 507
 508     s = (PIIX4PMState *)pci_register_device(bus,
 509                                          "PM", sizeof(PIIX4PMState),
 510                                          devfn, NULL, pm_write_config);
 511     pm_state = s;
 512     pci_conf = s->dev.config;
 513     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 514     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 515     pci_conf[0x06] = 0x80;
 516     pci_conf[0x07] = 0x02;
 517     pci_conf[0x08] = 0x03; // revision number
 518     pci_conf[0x09] = 0x00;
 519     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 520     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 521     pci_conf[0x3d] = 0x01; // interrupt pin 1
 522
 523     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 524
 525 #if defined(TARGET_IA64)
 526     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 527     pci_conf[0x41] = 0x1f;
 528     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 529     s->pmcntrl = SCI_EN;
 530 #endif
 531
 532     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 533     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 534
 535     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 536
 537     if (kvm_enabled()) {
 538         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 539          * support SMM mode. */
 540         pci_conf[0x5B] = 0x02;
 541     }
 542
 543     /* XXX: which specification is used ? The i82731AB has different
 544        mappings */
 545     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 546     pci_conf[0x63] = 0x60;
 547     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 548         (serial_hds[1] != NULL ? 0x90 : 0);
 549
 550     pci_conf[0x90] = smb_io_base | 1;
 551     pci_conf[0x91] = smb_io_base >> 8;
 552     pci_conf[0xd2] = 0x09;
 553     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 554     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 555
 556     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 557
 558     register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
 559
 560     s->smbus = i2c_init_bus();
 561     s->irq = sci_irq;
 562     qemu_register_reset(piix4_reset, s);
 563
 564     return s->smbus;
 565 }
 566
 567 #if defined(TARGET_I386)
 568 void qemu_system_powerdown(void)
 569 {
 570     if (!pm_state) {
 571         qemu_system_shutdown_request();
 572     } else if (pm_state->pmen & PWRBTN_EN) {
 573         pm_state->pmsts |= PWRBTN_EN;
 574         pm_update_sci(pm_state);
 575     }
 576 }
 577 #endif
 578
 579 #define GPE_BASE 0xafe0
 580 #define PROC_BASE 0xaf00
 581 #define PCI_BASE 0xae00
 582 #define PCI_EJ_BASE 0xae08
 583
 584 struct gpe_regs {
 585     uint16_t sts; /* status */
 586     uint16_t en;  /* enabled */
 587     uint8_t cpus_sts[32];
 588 };
 589
 590 struct pci_status {
 591     uint32_t up;
 592     uint32_t down;
 593 };
 594
 595 static struct gpe_regs gpe;
 596 static struct pci_status pci0_status;
 597
 598 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 599 {
 600     if (addr & 1)
 601         return (val >> 8) & 0xff;
 602     return val & 0xff;
 603 }
 604
 605 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 606 {
 607     uint32_t val = 0;
 608     struct gpe_regs *g = opaque;
 609     switch (addr) {
 610         case PROC_BASE ... PROC_BASE+31:
 611             val = g->cpus_sts[addr - PROC_BASE];
 612             break;
 613
 614         case GPE_BASE:
 615         case GPE_BASE + 1:
 616             val = gpe_read_val(g->sts, addr);
 617             break;
 618         case GPE_BASE + 2:
 619         case GPE_BASE + 3:
 620             val = gpe_read_val(g->en, addr);
 621             break;
 622         default:
 623             break;
 624     }
 625
 626 #if defined(DEBUG)
 627     printf("gpe read %x == %x\n", addr, val);
 628 #endif
 629     return val;
 630 }
 631
 632 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 633 {
 634     if (addr & 1)
 635         *cur = (*cur & 0xff) | (val << 8);
 636     else
 637         *cur = (*cur & 0xff00) | (val & 0xff);
 638 }
 639
 640 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 641 {
 642     uint16_t x1, x0 = val & 0xff;
 643     int shift = (addr & 1) ? 8 : 0;
 644
 645     x1 = (*cur >> shift) & 0xff;
 646
 647     x1 = x1 & ~x0;
 648
 649     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 650 }
 651
 652 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 653 {
 654     struct gpe_regs *g = opaque;
 655     switch (addr) {
 656         case PROC_BASE ... PROC_BASE + 31:
 657             /* don't allow to change cpus_sts from inside a guest */
 658             break;
 659
 660         case GPE_BASE:
 661         case GPE_BASE + 1:
 662             gpe_reset_val(&g->sts, addr, val);
 663             break;
 664         case GPE_BASE + 2:
 665         case GPE_BASE + 3:
 666             gpe_write_val(&g->en, addr, val);
 667             break;
 668         default:
 669             break;
 670    }
 671
 672 #if defined(DEBUG)
 673     printf("gpe write %x <== %d\n", addr, val);
 674 #endif
 675 }
 676
 677 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 678 {
 679     uint32_t val = 0;
 680     struct pci_status *g = opaque;
 681     switch (addr) {
 682         case PCI_BASE:
 683             val = g->up;
 684             break;
 685         case PCI_BASE + 4:
 686             val = g->down;
 687             break;
 688         default:
 689             break;
 690     }
 691
 692 #if defined(DEBUG)
 693     printf("pcihotplug read %x == %x\n", addr, val);
 694 #endif
 695     return val;
 696 }
 697
 698 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 699 {
 700     struct pci_status *g = opaque;
 701     switch (addr) {
 702         case PCI_BASE:
 703             g->up = val;
 704             break;
 705         case PCI_BASE + 4:
 706             g->down = val;
 707             break;
 708    }
 709
 710 #if defined(DEBUG)
 711     printf("pcihotplug write %x <== %d\n", addr, val);
 712 #endif
 713 }
 714
 715 static uint32_t pciej_read(void *opaque, uint32_t addr)
 716 {
 717 #if defined(DEBUG)
 718     printf("pciej read %x\n", addr);
 719 #endif
 720     return 0;
 721 }
 722
 723 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 724 {
 725 #if defined (TARGET_I386)
 726     int slot = ffs(val) - 1;
 727
 728     pci_device_hot_remove_success(0, slot);
 729 #endif
 730
 731 #if defined(DEBUG)
 732     printf("pciej write %x <== %d\n", addr, val);
 733 #endif
 734 }
 735
 736 static const char *model;
 737
 738 void qemu_system_hot_add_init(const char *cpu_model)
 739 {
 740     int i = 0, cpus = smp_cpus;
 741
 742     while (cpus > 0) {
 743         gpe.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 744         cpus -= 8;
 745     }
 746     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 747     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 748
 749     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, &gpe);
 750     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, &gpe);
 751
 752     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 753     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 754
 755     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
 756     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, NULL);
 757
 758     model = cpu_model;
 759 }
 760
 761 static void enable_processor(struct gpe_regs *g, int cpu)
 762 {
 763     g->sts |= 4;
 764     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 765 }
 766
 767 static void disable_processor(struct gpe_regs *g, int cpu)
 768 {
 769     g->sts |= 4;
 770     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 771 }
 772
 773 #if defined(TARGET_I386) || defined(TARGET_X86_64)
 774 #ifdef USE_KVM
 775 static CPUState *qemu_kvm_cpu_env(int index)
 776 {
 777     CPUState *penv;
 778
 779     penv = first_cpu;
 780
 781     while (penv) {
 782         if (penv->cpu_index == index)
 783             return penv;
 784         penv = (CPUState *)penv->next_cpu;
 785     }
 786
 787     return NULL;
 788 }
 789 #endif
 790
 791
 792 void qemu_system_cpu_hot_add(int cpu, int state)
 793 {
 794     CPUState *env;
 795
 796     if (state
 797 #ifdef USE_KVM
 798         && (!qemu_kvm_cpu_env(cpu))
 799 #endif
 800     ) {
 801         env = pc_new_cpu(cpu, model, 1);
 802         if (!env) {
 803             fprintf(stderr, "cpu %d creation failed\n", cpu);
 804             return;
 805         }
 806     }
 807
 808     if (state)
 809         enable_processor(&gpe, cpu);
 810     else
 811         disable_processor(&gpe, cpu);
 812     if (gpe.en & 4) {
 813         qemu_set_irq(pm_state->irq, 1);
 814         qemu_set_irq(pm_state->irq, 0);
 815     }
 816 }
 817 #endif
 818
 819 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 820 {
 821     g->sts |= 2;
 822     p->up |= (1 << slot);
 823 }
 824
 825 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 826 {
 827     g->sts |= 2;
 828     p->down |= (1 << slot);
 829 }
 830
 831 void qemu_system_device_hot_add(int bus, int slot, int state)
 832 {
 833     pci0_status.up = 0;
 834     pci0_status.down = 0;
 835     if (state)
 836         enable_device(&pci0_status, &gpe, slot);
 837     else
 838         disable_device(&pci0_status, &gpe, slot);
 839     if (gpe.en & 2) {
 840         qemu_set_irq(pm_state->irq, 1);
 841         qemu_set_irq(pm_state->irq, 0);
 842     }
 843 }
 844
 845 struct acpi_table_header
 846 {
 847     char signature [4];    /* ACPI signature (4 ASCII characters) */
 848     uint32_t length;          /* Length of table, in bytes, including header */
 849     uint8_t revision;         /* ACPI Specification minor version # */
 850     uint8_t checksum;         /* To make sum of entire table == 0 */
 851     char oem_id [6];       /* OEM identification */
 852     char oem_table_id [8]; /* OEM table identification */
 853     uint32_t oem_revision;    /* OEM revision number */
 854     char asl_compiler_id [4]; /* ASL compiler vendor ID */
 855     uint32_t asl_compiler_revision; /* ASL compiler revision number */
 856 } __attribute__((packed));
 857
 858 char *acpi_tables;
 859 size_t acpi_tables_len;
 860
 861 static int acpi_checksum(const uint8_t *data, int len)
 862 {
 863     int sum, i;
 864     sum = 0;
 865     for(i = 0; i < len; i++)
 866         sum += data[i];
 867     return (-sum) & 0xff;
 868 }
 869
 870 int acpi_table_add(const char *t)
 871 {
 872     static const char *dfl_id = "QEMUQEMU";
 873     char buf[1024], *p, *f;
 874     struct acpi_table_header acpi_hdr;
 875     unsigned long val;
 876     size_t off;
 877
 878     memset(&acpi_hdr, 0, sizeof(acpi_hdr));
 879
 880     if (get_param_value(buf, sizeof(buf), "sig", t)) {
 881         strncpy(acpi_hdr.signature, buf, 4);
 882     } else {
 883         strncpy(acpi_hdr.signature, dfl_id, 4);
 884     }
 885     if (get_param_value(buf, sizeof(buf), "rev", t)) {
 886         val = strtoul(buf, &p, 10);
 887         if (val > 255 || *p != '\0')
 888             goto out;
 889     } else {
 890         val = 1;
 891     }
 892     acpi_hdr.revision = (int8_t)val;
 893
 894     if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
 895         strncpy(acpi_hdr.oem_id, buf, 6);
 896     } else {
 897         strncpy(acpi_hdr.oem_id, dfl_id, 6);
 898     }
 899
 900     if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
 901         strncpy(acpi_hdr.oem_table_id, buf, 8);
 902     } else {
 903         strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
 904     }
 905
 906     if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
 907         val = strtol(buf, &p, 10);
 908         if(*p != '\0')
 909             goto out;
 910     } else {
 911         val = 1;
 912     }
 913     acpi_hdr.oem_revision = cpu_to_le32(val);
 914
 915     if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
 916         strncpy(acpi_hdr.asl_compiler_id, buf, 4);
 917     } else {
 918         strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
 919     }
 920
 921     if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
 922         val = strtol(buf, &p, 10);
 923         if(*p != '\0')
 924             goto out;
 925     } else {
 926         val = 1;
 927     }
 928     acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
 929
 930     if (!get_param_value(buf, sizeof(buf), "data", t)) {
 931          buf[0] = '\0';
 932     }
 933
 934     acpi_hdr.length = sizeof(acpi_hdr);
 935
 936     f = buf;
 937     while (buf[0]) {
 938         struct stat s;
 939         char *n = strchr(f, ':');
 940         if (n)
 941             *n = '\0';
 942         if(stat(f, &s) < 0) {
 943             fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
 944             goto out;
 945         }
 946         acpi_hdr.length += s.st_size;
 947         if (!n)
 948             break;
 949         *n = ':';
 950         f = n + 1;
 951     }
 952
 953     if (!acpi_tables) {
 954         acpi_tables_len = sizeof(uint16_t);
 955         acpi_tables = qemu_mallocz(acpi_tables_len);
 956     }
 957     p = acpi_tables + acpi_tables_len;
 958     acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
 959     acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len);
 960
 961     acpi_hdr.length = cpu_to_le32(acpi_hdr.length);
 962     *(uint16_t*)p = acpi_hdr.length;
 963     p += sizeof(uint16_t);
 964     memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
 965     off = sizeof(acpi_hdr);
 966
 967     f = buf;
 968     while (buf[0]) {
 969         struct stat s;
 970         int fd;
 971         char *n = strchr(f, ':');
 972         if (n)
 973             *n = '\0';
 974         fd = open(f, O_RDONLY);
 975
 976         if(fd < 0)
 977             goto out;
 978         if(fstat(fd, &s) < 0) {
 979             close(fd);
 980             goto out;
 981         }
 982
 983         do {
 984             int r;
 985             r = read(fd, p + off, s.st_size);
 986             if (r > 0) {
 987                 off += r;
 988                 s.st_size -= r;
 989             } else if ((r < 0 && errno != EINTR) || r == 0) {
 990                 close(fd);
 991                 goto out;
 992             }
 993         } while(s.st_size);
 994
 995         close(fd);
 996         if (!n)
 997             break;
 998         f = n + 1;
 999     }
1000
1001     ((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
1002     /* increase number of tables */
1003     (*(uint16_t*)acpi_tables) =
1004             cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
1005     return 0;
1006 out:
1007     if (acpi_tables) {
1008         free(acpi_tables);
1009         acpi_tables = NULL;
1010     }
1011     return -1;
1012 }