tcg/sparc/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  26     "%g0",
  27     "%g1",
  28     "%g2",
  29     "%g3",
  30     "%g4",
  31     "%g5",
  32     "%g6",
  33     "%g7",
  34     "%o0",
  35     "%o1",
  36     "%o2",
  37     "%o3",
  38     "%o4",
  39     "%o5",
  40     "%o6",
  41     "%o7",
  42     "%l0",
  43     "%l1",
  44     "%l2",
  45     "%l3",
  46     "%l4",
  47     "%l5",
  48     "%l6",
  49     "%l7",
  50     "%i0",
  51     "%i1",
  52     "%i2",
  53     "%i3",
  54     "%i4",
  55     "%i5",
  56     "%i6",
  57     "%i7",
  58 };
  59
  60 static const int tcg_target_reg_alloc_order[] = {
  61     TCG_REG_L0,
  62     TCG_REG_L1,
  63     TCG_REG_L2,
  64     TCG_REG_L3,
  65     TCG_REG_L4,
  66     TCG_REG_L5,
  67     TCG_REG_L6,
  68     TCG_REG_L7,
  69     TCG_REG_I0,
  70     TCG_REG_I1,
  71     TCG_REG_I2,
  72     TCG_REG_I3,
  73     TCG_REG_I4,
  74 };
  75
  76 static const int tcg_target_call_iarg_regs[6] = {
  77     TCG_REG_O0,
  78     TCG_REG_O1,
  79     TCG_REG_O2,
  80     TCG_REG_O3,
  81     TCG_REG_O4,
  82     TCG_REG_O5,
  83 };
  84
  85 static const int tcg_target_call_oarg_regs[2] = {
  86     TCG_REG_O0,
  87     TCG_REG_O1,
  88 };
  89
  90 static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
  91 {
  92     return (val << ((sizeof(tcg_target_long) * 8 - bits))
  93             >> (sizeof(tcg_target_long) * 8 - bits)) == val;
  94 }
  95
  96 static inline int check_fit_i32(uint32_t val, unsigned int bits)
  97 {
  98     return ((val << (32 - bits)) >> (32 - bits)) == val;
  99 }
 100
 101 static void patch_reloc(uint8_t *code_ptr, int type,
 102                         tcg_target_long value, tcg_target_long addend)
 103 {
 104     value += addend;
 105     switch (type) {
 106     case R_SPARC_32:
 107         if (value != (uint32_t)value)
 108             tcg_abort();
 109         *(uint32_t *)code_ptr = value;
 110         break;
 111     case R_SPARC_WDISP22:
 112         value -= (long)code_ptr;
 113         value >>= 2;
 114         if (!check_fit_tl(value, 22))
 115             tcg_abort();
 116         *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
 117         break;
 118     default:
 119         tcg_abort();
 120     }
 121 }
 122
 123 /* maximum number of register used for input function arguments */
 124 static inline int tcg_target_get_call_iarg_regs_count(int flags)
 125 {
 126     return 6;
 127 }
 128
 129 /* parse target specific constraints */
 130 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 131 {
 132     const char *ct_str;
 133
 134     ct_str = *pct_str;
 135     switch (ct_str[0]) {
 136     case 'r':
 137     case 'L': /* qemu_ld/st constraint */
 138         ct->ct |= TCG_CT_REG;
 139         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
 140         tcg_regset_reset_reg(ct->u.regs, TCG_REG_I0);
 141         tcg_regset_reset_reg(ct->u.regs, TCG_REG_I1);
 142         break;
 143     case 'I':
 144         ct->ct |= TCG_CT_CONST_S11;
 145         break;
 146     case 'J':
 147         ct->ct |= TCG_CT_CONST_S13;
 148         break;
 149     default:
 150         return -1;
 151     }
 152     ct_str++;
 153     *pct_str = ct_str;
 154     return 0;
 155 }
 156
 157 /* test if a constant matches the constraint */
 158 static inline int tcg_target_const_match(tcg_target_long val,
 159                                          const TCGArgConstraint *arg_ct)
 160 {
 161     int ct;
 162
 163     ct = arg_ct->ct;
 164     if (ct & TCG_CT_CONST)
 165         return 1;
 166     else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
 167         return 1;
 168     else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
 169         return 1;
 170     else
 171         return 0;
 172 }
 173
 174 #define INSN_OP(x)  ((x) << 30)
 175 #define INSN_OP2(x) ((x) << 22)
 176 #define INSN_OP3(x) ((x) << 19)
 177 #define INSN_OPF(x) ((x) << 5)
 178 #define INSN_RD(x)  ((x) << 25)
 179 #define INSN_RS1(x) ((x) << 14)
 180 #define INSN_RS2(x) (x)
 181 #define INSN_ASI(x) ((x) << 5)
 182
 183 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
 184 #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
 185
 186 #define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
 187 #define COND_N     0x0
 188 #define COND_E     0x1
 189 #define COND_LE    0x2
 190 #define COND_L     0x3
 191 #define COND_LEU   0x4
 192 #define COND_CS    0x5
 193 #define COND_NEG   0x6
 194 #define COND_VS    0x7
 195 #define COND_A     0x8
 196 #define COND_NE    0x9
 197 #define COND_G     0xa
 198 #define COND_GE    0xb
 199 #define COND_GU    0xc
 200 #define COND_CC    0xd
 201 #define COND_POS   0xe
 202 #define COND_VC    0xf
 203 #define BA         (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
 204
 205 #define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
 206 #define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
 207 #define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
 208 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
 209 #define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
 210 #define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x04))
 211 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
 212 #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
 213 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
 214 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
 215 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
 216 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
 217 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
 218 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
 219 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
 220
 221 #define SHIFT_SLL  (INSN_OP(2) | INSN_OP3(0x25))
 222 #define SHIFT_SRL  (INSN_OP(2) | INSN_OP3(0x26))
 223 #define SHIFT_SRA  (INSN_OP(2) | INSN_OP3(0x27))
 224
 225 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
 226 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
 227 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
 228
 229 #define WRY        (INSN_OP(2) | INSN_OP3(0x30))
 230 #define JMPL       (INSN_OP(2) | INSN_OP3(0x38))
 231 #define SAVE       (INSN_OP(2) | INSN_OP3(0x3c))
 232 #define RESTORE    (INSN_OP(2) | INSN_OP3(0x3d))
 233 #define SETHI      (INSN_OP(0) | INSN_OP2(0x4))
 234 #define CALL       INSN_OP(1)
 235 #define LDUB       (INSN_OP(3) | INSN_OP3(0x01))
 236 #define LDSB       (INSN_OP(3) | INSN_OP3(0x09))
 237 #define LDUH       (INSN_OP(3) | INSN_OP3(0x02))
 238 #define LDSH       (INSN_OP(3) | INSN_OP3(0x0a))
 239 #define LDUW       (INSN_OP(3) | INSN_OP3(0x00))
 240 #define LDSW       (INSN_OP(3) | INSN_OP3(0x08))
 241 #define LDX        (INSN_OP(3) | INSN_OP3(0x0b))
 242 #define STB        (INSN_OP(3) | INSN_OP3(0x05))
 243 #define STH        (INSN_OP(3) | INSN_OP3(0x06))
 244 #define STW        (INSN_OP(3) | INSN_OP3(0x04))
 245 #define STX        (INSN_OP(3) | INSN_OP3(0x0e))
 246 #define LDUBA      (INSN_OP(3) | INSN_OP3(0x11))
 247 #define LDSBA      (INSN_OP(3) | INSN_OP3(0x19))
 248 #define LDUHA      (INSN_OP(3) | INSN_OP3(0x12))
 249 #define LDSHA      (INSN_OP(3) | INSN_OP3(0x1a))
 250 #define LDUWA      (INSN_OP(3) | INSN_OP3(0x10))
 251 #define LDSWA      (INSN_OP(3) | INSN_OP3(0x18))
 252 #define LDXA       (INSN_OP(3) | INSN_OP3(0x1b))
 253 #define STBA       (INSN_OP(3) | INSN_OP3(0x15))
 254 #define STHA       (INSN_OP(3) | INSN_OP3(0x16))
 255 #define STWA       (INSN_OP(3) | INSN_OP3(0x14))
 256 #define STXA       (INSN_OP(3) | INSN_OP3(0x1e))
 257
 258 #ifndef ASI_PRIMARY_LITTLE
 259 #define ASI_PRIMARY_LITTLE 0x88
 260 #endif
 261
 262 static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
 263                                  int op)
 264 {
 265     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
 266               INSN_RS2(rs2));
 267 }
 268
 269 static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, int offset,
 270                                   int op)
 271 {
 272     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
 273               INSN_IMM13(offset));
 274 }
 275
 276 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
 277 {
 278     tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
 279 }
 280
 281 static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
 282 {
 283     tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
 284 }
 285
 286 static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
 287 {
 288     tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
 289 }
 290
 291 static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
 292 {
 293     if (check_fit_i32(arg, 13))
 294         tcg_out_movi_imm13(s, ret, arg);
 295     else {
 296         tcg_out_sethi(s, ret, arg);
 297         if (arg & 0x3ff)
 298             tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
 299     }
 300 }
 301
 302 static inline void tcg_out_movi(TCGContext *s, TCGType type,
 303                                 int ret, tcg_target_long arg)
 304 {
 305 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 306     if (!check_fit_tl(arg, 32) && (arg & ~0xffffffffULL) != 0) {
 307         tcg_out_movi_imm32(s, TCG_REG_I4, arg >> 32);
 308         tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
 309         tcg_out_movi_imm32(s, ret, arg);
 310         tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
 311     } else
 312 #endif
 313         tcg_out_movi_imm32(s, ret, arg);
 314 }
 315
 316 static inline void tcg_out_ld_raw(TCGContext *s, int ret,
 317                                   tcg_target_long arg)
 318 {
 319     tcg_out_sethi(s, ret, arg);
 320     tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
 321               INSN_IMM13(arg & 0x3ff));
 322 }
 323
 324 static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
 325                                   tcg_target_long arg)
 326 {
 327     if (!check_fit_tl(arg, 10))
 328         tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
 329 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 330     tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
 331               INSN_IMM13(arg & 0x3ff));
 332 #else
 333     tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
 334               INSN_IMM13(arg & 0x3ff));
 335 #endif
 336 }
 337
 338 static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
 339 {
 340     if (check_fit_tl(offset, 13))
 341         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
 342                   INSN_IMM13(offset));
 343     else {
 344         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
 345         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
 346                   INSN_RS2(addr));
 347     }
 348 }
 349
 350 static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
 351                                     int offset, int op, int asi)
 352 {
 353     tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
 354     tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
 355               INSN_ASI(asi) | INSN_RS2(addr));
 356 }
 357
 358 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
 359                               int arg1, tcg_target_long arg2)
 360 {
 361     if (type == TCG_TYPE_I32)
 362         tcg_out_ldst(s, ret, arg1, arg2, LDUW);
 363     else
 364         tcg_out_ldst(s, ret, arg1, arg2, LDX);
 365 }
 366
 367 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
 368                               int arg1, tcg_target_long arg2)
 369 {
 370     if (type == TCG_TYPE_I32)
 371         tcg_out_ldst(s, arg, arg1, arg2, STW);
 372     else
 373         tcg_out_ldst(s, arg, arg1, arg2, STX);
 374 }
 375
 376 static inline void tcg_out_sety(TCGContext *s, tcg_target_long val)
 377 {
 378     if (val == 0 || val == -1)
 379         tcg_out32(s, WRY | INSN_IMM13(val));
 380     else
 381         fprintf(stderr, "unimplemented sety %ld\n", (long)val);
 382 }
 383
 384 static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
 385 {
 386     if (val != 0) {
 387         if (check_fit_tl(val, 13))
 388             tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
 389         else {
 390             tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
 391             tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
 392         }
 393     }
 394 }
 395
 396 static inline void tcg_out_nop(TCGContext *s)
 397 {
 398     tcg_out_sethi(s, TCG_REG_G0, 0);
 399 }
 400
 401 static void tcg_out_branch(TCGContext *s, int opc, int label_index)
 402 {
 403     int32_t val;
 404     TCGLabel *l = &s->labels[label_index];
 405
 406     if (l->has_value) {
 407         val = l->u.value - (tcg_target_long)s->code_ptr;
 408         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
 409                       | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
 410     } else {
 411         tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
 412         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
 413     }
 414 }
 415
 416 static const uint8_t tcg_cond_to_bcond[10] = {
 417     [TCG_COND_EQ] = COND_E,
 418     [TCG_COND_NE] = COND_NE,
 419     [TCG_COND_LT] = COND_L,
 420     [TCG_COND_GE] = COND_GE,
 421     [TCG_COND_LE] = COND_LE,
 422     [TCG_COND_GT] = COND_G,
 423     [TCG_COND_LTU] = COND_CS,
 424     [TCG_COND_GEU] = COND_CC,
 425     [TCG_COND_LEU] = COND_LEU,
 426     [TCG_COND_GTU] = COND_GU,
 427 };
 428
 429 static void tcg_out_brcond(TCGContext *s, int cond,
 430                            TCGArg arg1, TCGArg arg2, int const_arg2,
 431                            int label_index)
 432 {
 433     if (const_arg2 && arg2 == 0)
 434         /* orcc %g0, r, %g0 */
 435         tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, arg1, ARITH_ORCC);
 436     else
 437         /* subcc r1, r2, %g0 */
 438         tcg_out_arith(s, TCG_REG_G0, arg1, arg2, ARITH_SUBCC);
 439     tcg_out_branch(s, tcg_cond_to_bcond[cond], label_index);
 440     tcg_out_nop(s);
 441 }
 442
 443 /* Generate global QEMU prologue and epilogue code */
 444 void tcg_target_qemu_prologue(TCGContext *s)
 445 {
 446     tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
 447               INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
 448     tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |
 449               INSN_RS2(TCG_REG_G0));
 450     tcg_out_nop(s);
 451 }
 452
 453 #if defined(CONFIG_SOFTMMU)
 454 extern void __ldb_mmu(void);
 455 extern void __ldw_mmu(void);
 456 extern void __ldl_mmu(void);
 457 extern void __ldq_mmu(void);
 458
 459 extern void __stb_mmu(void);
 460 extern void __stw_mmu(void);
 461 extern void __stl_mmu(void);
 462 extern void __stq_mmu(void);
 463
 464
 465 static const void * const qemu_ld_helpers[4] = {
 466     __ldb_mmu,
 467     __ldw_mmu,
 468     __ldl_mmu,
 469     __ldq_mmu,
 470 };
 471
 472 static const void * const qemu_st_helpers[4] = {
 473     __stb_mmu,
 474     __stw_mmu,
 475     __stl_mmu,
 476     __stq_mmu,
 477 };
 478 #endif
 479
 480 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
 481                             int opc)
 482 {
 483     int addr_reg, data_reg, r0, r1, mem_index, s_bits, ld_op;
 484 #if defined(CONFIG_SOFTMMU)
 485     uint8_t *label1_ptr, *label2_ptr;
 486 #endif
 487
 488     data_reg = *args++;
 489     addr_reg = *args++;
 490     mem_index = *args;
 491     s_bits = opc & 3;
 492
 493     r0 = TCG_REG_I0;
 494     r1 = TCG_REG_I1;
 495
 496 #if TARGET_LONG_BITS == 32
 497     ld_op = LDUW;
 498 #else
 499     ld_op = LDX;
 500 #endif
 501
 502 #if defined(CONFIG_SOFTMMU)
 503     /* srl addr_reg, x, r1 */
 504     tcg_out_arithi(s, r1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
 505                    SHIFT_SRL);
 506     /* and addr_reg, x, r0 */
 507     tcg_out_arithi(s, r0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
 508                    ARITH_AND);
 509
 510     /* and r1, x, r1 */
 511     tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
 512                    ARITH_AND);
 513
 514     /* add r1, x, r1 */
 515     tcg_out_arithi(s, r1, r1, offsetof(CPUState, tlb_table[mem_index][0].addr_read),
 516                    ARITH_ADD);
 517
 518     /* ld [env + r1], r1 */
 519     tcg_out_ldst(s, r1, TCG_AREG0, r1, ld_op);
 520
 521     /* subcc r0, r1, %g0 */
 522     tcg_out_arith(s, TCG_REG_G0, r0, r1, ARITH_SUBCC);
 523
 524     /* will become:
 525        be label1 */
 526     label1_ptr = s->code_ptr;
 527     tcg_out32(s, 0);
 528
 529     /* mov (delay slot)*/
 530     tcg_out_mov(s, r0, addr_reg);
 531
 532     /* XXX: move that code at the end of the TB */
 533     tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
 534                            - (tcg_target_ulong)s->code_ptr) >> 2)
 535                          & 0x3fffffff));
 536     /* mov (delay slot)*/
 537     tcg_out_movi(s, TCG_TYPE_I32, r1, mem_index);
 538
 539     switch(opc) {
 540     case 0 | 4:
 541         /* sll i0, 24/56, i0 */
 542         tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
 543                        sizeof(tcg_target_long) * 8 - 8, SHIFT_SLL);
 544         /* sra i0, 24/56, data_reg */
 545         tcg_out_arithi(s, data_reg, TCG_REG_I0,
 546                        sizeof(tcg_target_long) * 8 - 8, SHIFT_SRA);
 547         break;
 548     case 1 | 4:
 549         /* sll i0, 16/48, i0 */
 550         tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
 551                        sizeof(tcg_target_long) * 8 - 16, SHIFT_SLL);
 552         /* sra i0, 16/48, data_reg */
 553         tcg_out_arithi(s, data_reg, TCG_REG_I0,
 554                        sizeof(tcg_target_long) * 8 - 16, SHIFT_SRA);
 555         break;
 556     case 2 | 4:
 557         /* sll i0, 32, i0 */
 558         tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, 32, SHIFT_SLL);
 559         /* sra i0, 32, data_reg */
 560         tcg_out_arithi(s, data_reg, TCG_REG_I0, 32, SHIFT_SRA);
 561         break;
 562     case 0:
 563     case 1:
 564     case 2:
 565     case 3:
 566     default:
 567         /* mov */
 568         tcg_out_mov(s, data_reg, TCG_REG_I0);
 569         break;
 570     }
 571
 572     /* will become:
 573        ba label2 */
 574     label2_ptr = s->code_ptr;
 575     tcg_out32(s, 0);
 576
 577     /* label1: */
 578     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
 579                    INSN_OFF22((unsigned long)label1_ptr -
 580                               (unsigned long)s->code_ptr));
 581
 582     /* ld [r1 + x], r1 */
 583     tcg_out_ldst(s, r1, r1, offsetof(CPUTLBEntry, addend) -
 584                  offsetof(CPUTLBEntry, addr_read), ld_op);
 585     /* add x(r1), r0 */
 586     tcg_out_arith(s, r0, r1, r0, ARITH_ADD);
 587 #else
 588     r0 = addr_reg;
 589 #endif
 590
 591     switch(opc) {
 592     case 0:
 593         /* ldub [r0], data_reg */
 594         tcg_out_ldst(s, data_reg, r0, 0, LDUB);
 595         break;
 596     case 0 | 4:
 597         /* ldsb [r0], data_reg */
 598         tcg_out_ldst(s, data_reg, r0, 0, LDSB);
 599         break;
 600     case 1:
 601 #ifdef TARGET_WORDS_BIGENDIAN
 602         /* lduh [r0], data_reg */
 603         tcg_out_ldst(s, data_reg, r0, 0, LDUH);
 604 #else
 605         /* lduha [r0] ASI_PRIMARY_LITTLE, data_reg */
 606         tcg_out_ldst_asi(s, data_reg, r0, 0, LDUHA, ASI_PRIMARY_LITTLE);
 607 #endif
 608         break;
 609     case 1 | 4:
 610 #ifdef TARGET_WORDS_BIGENDIAN
 611         /* ldsh [r0], data_reg */
 612         tcg_out_ldst(s, data_reg, r0, 0, LDSH);
 613 #else
 614         /* ldsha [r0] ASI_PRIMARY_LITTLE, data_reg */
 615         tcg_out_ldst_asi(s, data_reg, r0, 0, LDSHA, ASI_PRIMARY_LITTLE);
 616 #endif
 617         break;
 618     case 2:
 619 #ifdef TARGET_WORDS_BIGENDIAN
 620         /* lduw [r0], data_reg */
 621         tcg_out_ldst(s, data_reg, r0, 0, LDUW);
 622 #else
 623         /* lduwa [r0] ASI_PRIMARY_LITTLE, data_reg */
 624         tcg_out_ldst_asi(s, data_reg, r0, 0, LDUWA, ASI_PRIMARY_LITTLE);
 625 #endif
 626         break;
 627     case 2 | 4:
 628 #ifdef TARGET_WORDS_BIGENDIAN
 629         /* ldsw [r0], data_reg */
 630         tcg_out_ldst(s, data_reg, r0, 0, LDSW);
 631 #else
 632         /* ldswa [r0] ASI_PRIMARY_LITTLE, data_reg */
 633         tcg_out_ldst_asi(s, data_reg, r0, 0, LDSWA, ASI_PRIMARY_LITTLE);
 634 #endif
 635         break;
 636     case 3:
 637 #ifdef TARGET_WORDS_BIGENDIAN
 638         /* ldx [r0], data_reg */
 639         tcg_out_ldst(s, data_reg, r0, 0, LDX);
 640 #else
 641         /* ldxa [r0] ASI_PRIMARY_LITTLE, data_reg */
 642         tcg_out_ldst_asi(s, data_reg, r0, 0, LDXA, ASI_PRIMARY_LITTLE);
 643 #endif
 644         break;
 645     default:
 646         tcg_abort();
 647     }
 648
 649 #if defined(CONFIG_SOFTMMU)
 650     /* label2: */
 651     *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
 652                    INSN_OFF22((unsigned long)label2_ptr -
 653                               (unsigned long)s->code_ptr));
 654 #endif
 655 }
 656
 657 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
 658                             int opc)
 659 {
 660     int addr_reg, data_reg, r0, r1, mem_index, s_bits, ld_op;
 661 #if defined(CONFIG_SOFTMMU)
 662     uint8_t *label1_ptr, *label2_ptr;
 663 #endif
 664
 665     data_reg = *args++;
 666     addr_reg = *args++;
 667     mem_index = *args;
 668
 669     s_bits = opc;
 670
 671     r0 = TCG_REG_I5;
 672     r1 = TCG_REG_I4;
 673
 674 #if TARGET_LONG_BITS == 32
 675     ld_op = LDUW;
 676 #else
 677     ld_op = LDX;
 678 #endif
 679
 680 #if defined(CONFIG_SOFTMMU)
 681     /* srl addr_reg, x, r1 */
 682     tcg_out_arithi(s, r1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
 683                    SHIFT_SRL);
 684     /* and addr_reg, x, r0 */
 685     tcg_out_arithi(s, r0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
 686                    ARITH_AND);
 687
 688     /* and r1, x, r1 */
 689     tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
 690                    ARITH_AND);
 691
 692     /* add r1, x, r1 */
 693     tcg_out_arithi(s, r1, r1,
 694                    offsetof(CPUState, tlb_table[mem_index][0].addr_write),
 695                    ARITH_ADD);
 696
 697     /* ld [env + r1], r1 */
 698     tcg_out_ldst(s, r1, TCG_AREG0, r1, ld_op);
 699
 700     /* subcc r0, r1, %g0 */
 701     tcg_out_arith(s, TCG_REG_G0, r0, r1, ARITH_SUBCC);
 702
 703     /* will become:
 704        be label1 */
 705     label1_ptr = s->code_ptr;
 706     tcg_out32(s, 0);
 707     /* mov (delay slot)*/
 708     tcg_out_mov(s, r0, addr_reg);
 709
 710     switch(opc) {
 711     case 0 | 4:
 712         /* sll i0, 24/56, i0 */
 713         tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
 714                        sizeof(tcg_target_long) * 8 - 8, SHIFT_SLL);
 715         /* sra i0, 24/56, data_reg */
 716         tcg_out_arithi(s, data_reg, TCG_REG_I0,
 717                        sizeof(tcg_target_long) * 8 - 8, SHIFT_SRA);
 718         break;
 719     case 1 | 4:
 720         /* sll i0, 16/48, i0 */
 721         tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
 722                        sizeof(tcg_target_long) * 8 - 16, SHIFT_SLL);
 723         /* sra i0, 16/48, data_reg */
 724         tcg_out_arithi(s, data_reg, TCG_REG_I0,
 725                        sizeof(tcg_target_long) * 8 - 16, SHIFT_SRA);
 726         break;
 727     case 2 | 4:
 728         /* sll i0, 32, i0 */
 729         tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, 32, SHIFT_SLL);
 730         /* sra i0, 32, data_reg */
 731         tcg_out_arithi(s, data_reg, TCG_REG_I0, 32, SHIFT_SRA);
 732         break;
 733     case 0:
 734     case 1:
 735     case 2:
 736     case 3:
 737     default:
 738         /* mov */
 739         tcg_out_mov(s, data_reg, TCG_REG_I0);
 740         break;
 741     }
 742
 743     tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
 744                            - (tcg_target_ulong)s->code_ptr) >> 2)
 745                          & 0x3fffffff));
 746     /* mov (delay slot)*/
 747     tcg_out_movi(s, TCG_TYPE_I32, r1, mem_index);
 748
 749     /* will become:
 750        ba label2 */
 751     label2_ptr = s->code_ptr;
 752     tcg_out32(s, 0);
 753
 754     /* label1: */
 755     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
 756                    INSN_OFF22((unsigned long)label1_ptr -
 757                               (unsigned long)s->code_ptr));
 758
 759     /* ld [r1 + x], r1 */
 760     tcg_out_ldst(s, r1, r1, offsetof(CPUTLBEntry, addend) -
 761                  offsetof(CPUTLBEntry, addr_write), ld_op);
 762     /* add x(r1), r0 */
 763     tcg_out_arith(s, r0, r1, r0, ARITH_ADD);
 764 #else
 765     r0 = addr_reg;
 766 #endif
 767
 768     switch(opc) {
 769     case 0:
 770         /* stb data_reg, [r0] */
 771         tcg_out_ldst(s, data_reg, r0, 0, STB);
 772         break;
 773     case 1:
 774 #ifdef TARGET_WORDS_BIGENDIAN
 775         /* sth data_reg, [r0] */
 776         tcg_out_ldst(s, data_reg, r0, 0, STH);
 777 #else
 778         /* stha data_reg, [r0] ASI_PRIMARY_LITTLE */
 779         tcg_out_ldst_asi(s, data_reg, r0, 0, STHA, ASI_PRIMARY_LITTLE);
 780 #endif
 781         break;
 782     case 2:
 783 #ifdef TARGET_WORDS_BIGENDIAN
 784         /* stw data_reg, [r0] */
 785         tcg_out_ldst(s, data_reg, r0, 0, STW);
 786 #else
 787         /* stwa data_reg, [r0] ASI_PRIMARY_LITTLE */
 788         tcg_out_ldst_asi(s, data_reg, r0, 0, STWA, ASI_PRIMARY_LITTLE);
 789 #endif
 790         break;
 791     case 3:
 792 #ifdef TARGET_WORDS_BIGENDIAN
 793         /* stx data_reg, [r0] */
 794         tcg_out_ldst(s, data_reg, r0, 0, STX);
 795 #else
 796         /* stxa data_reg, [r0] ASI_PRIMARY_LITTLE */
 797         tcg_out_ldst_asi(s, data_reg, r0, 0, STXA, ASI_PRIMARY_LITTLE);
 798 #endif
 799         break;
 800     default:
 801         tcg_abort();
 802     }
 803
 804 #if defined(CONFIG_SOFTMMU)
 805     /* label2: */
 806     *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
 807                    INSN_OFF22((unsigned long)label2_ptr -
 808                               (unsigned long)s->code_ptr));
 809 #endif
 810 }
 811
 812 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
 813                               const int *const_args)
 814 {
 815     int c;
 816
 817     switch (opc) {
 818     case INDEX_op_exit_tb:
 819         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
 820         tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
 821                   INSN_IMM13(8));
 822         tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
 823                       INSN_RS2(TCG_REG_G0));
 824         break;
 825     case INDEX_op_goto_tb:
 826         if (s->tb_jmp_offset) {
 827             /* direct jump method */
 828             tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
 829             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
 830                       INSN_IMM13((args[0] & 0x1fff)));
 831             s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
 832         } else {
 833             /* indirect jump method */
 834             tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
 835             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
 836                       INSN_RS2(TCG_REG_G0));
 837         }
 838         tcg_out_nop(s);
 839         s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
 840         break;
 841     case INDEX_op_call:
 842         {
 843             unsigned int st_op, ld_op;
 844
 845 #ifdef __arch64__
 846             st_op = STX;
 847             ld_op = LDX;
 848 #else
 849             st_op = STW;
 850             ld_op = LDUW;
 851 #endif
 852             if (const_args[0])
 853                 tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
 854                                        - (tcg_target_ulong)s->code_ptr) >> 2)
 855                                      & 0x3fffffff));
 856             else {
 857                 tcg_out_ld_ptr(s, TCG_REG_I5,
 858                                (tcg_target_long)(s->tb_next + args[0]));
 859                 tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
 860                           INSN_RS2(TCG_REG_G0));
 861             }
 862             /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
 863                global registers */
 864             tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
 865                          TCG_TARGET_CALL_STACK_OFFSET - sizeof(long),
 866                          st_op); // delay slot
 867             tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
 868                          TCG_TARGET_CALL_STACK_OFFSET - sizeof(long),
 869                          ld_op);
 870         }
 871         break;
 872     case INDEX_op_jmp:
 873     case INDEX_op_br:
 874         tcg_out_branch(s, COND_A, args[0]);
 875         tcg_out_nop(s);
 876         break;
 877     case INDEX_op_movi_i32:
 878         tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
 879         break;
 880
 881 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 882 #define OP_32_64(x)                             \
 883         glue(glue(case INDEX_op_, x), _i32:)    \
 884         glue(glue(case INDEX_op_, x), _i64:)
 885 #else
 886 #define OP_32_64(x)                             \
 887         glue(glue(case INDEX_op_, x), _i32:)
 888 #endif
 889         OP_32_64(ld8u);
 890         tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
 891         break;
 892         OP_32_64(ld8s);
 893         tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
 894         break;
 895         OP_32_64(ld16u);
 896         tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
 897         break;
 898         OP_32_64(ld16s);
 899         tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
 900         break;
 901     case INDEX_op_ld_i32:
 902 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 903     case INDEX_op_ld32u_i64:
 904 #endif
 905         tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
 906         break;
 907         OP_32_64(st8);
 908         tcg_out_ldst(s, args[0], args[1], args[2], STB);
 909         break;
 910         OP_32_64(st16);
 911         tcg_out_ldst(s, args[0], args[1], args[2], STH);
 912         break;
 913     case INDEX_op_st_i32:
 914 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 915     case INDEX_op_st32_i64:
 916 #endif
 917         tcg_out_ldst(s, args[0], args[1], args[2], STW);
 918         break;
 919         OP_32_64(add);
 920         c = ARITH_ADD;
 921         goto gen_arith32;
 922         OP_32_64(sub);
 923         c = ARITH_SUB;
 924         goto gen_arith32;
 925         OP_32_64(and);
 926         c = ARITH_AND;
 927         goto gen_arith32;
 928         OP_32_64(or);
 929         c = ARITH_OR;
 930         goto gen_arith32;
 931         OP_32_64(xor);
 932         c = ARITH_XOR;
 933         goto gen_arith32;
 934     case INDEX_op_shl_i32:
 935         c = SHIFT_SLL;
 936         goto gen_arith32;
 937     case INDEX_op_shr_i32:
 938         c = SHIFT_SRL;
 939         goto gen_arith32;
 940     case INDEX_op_sar_i32:
 941         c = SHIFT_SRA;
 942         goto gen_arith32;
 943     case INDEX_op_mul_i32:
 944         c = ARITH_UMUL;
 945         goto gen_arith32;
 946     case INDEX_op_div2_i32:
 947 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
 948         c = ARITH_SDIVX;
 949         goto gen_arith32;
 950 #else
 951         tcg_out_sety(s, 0);
 952         c = ARITH_SDIV;
 953         goto gen_arith32;
 954 #endif
 955     case INDEX_op_divu2_i32:
 956 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
 957         c = ARITH_UDIVX;
 958         goto gen_arith32;
 959 #else
 960         tcg_out_sety(s, 0);
 961         c = ARITH_UDIV;
 962         goto gen_arith32;
 963 #endif
 964
 965     case INDEX_op_brcond_i32:
 966         tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
 967                        args[3]);
 968         break;
 969
 970     case INDEX_op_qemu_ld8u:
 971         tcg_out_qemu_ld(s, args, 0);
 972         break;
 973     case INDEX_op_qemu_ld8s:
 974         tcg_out_qemu_ld(s, args, 0 | 4);
 975         break;
 976     case INDEX_op_qemu_ld16u:
 977         tcg_out_qemu_ld(s, args, 1);
 978         break;
 979     case INDEX_op_qemu_ld16s:
 980         tcg_out_qemu_ld(s, args, 1 | 4);
 981         break;
 982     case INDEX_op_qemu_ld32u:
 983         tcg_out_qemu_ld(s, args, 2);
 984         break;
 985     case INDEX_op_qemu_ld32s:
 986         tcg_out_qemu_ld(s, args, 2 | 4);
 987         break;
 988     case INDEX_op_qemu_st8:
 989         tcg_out_qemu_st(s, args, 0);
 990         break;
 991     case INDEX_op_qemu_st16:
 992         tcg_out_qemu_st(s, args, 1);
 993         break;
 994     case INDEX_op_qemu_st32:
 995         tcg_out_qemu_st(s, args, 2);
 996         break;
 997
 998 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 999     case INDEX_op_movi_i64:
1000         tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1001         break;
1002     case INDEX_op_ld32s_i64:
1003         tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1004         break;
1005     case INDEX_op_ld_i64:
1006         tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1007         break;
1008     case INDEX_op_st_i64:
1009         tcg_out_ldst(s, args[0], args[1], args[2], STX);
1010         break;
1011     case INDEX_op_shl_i64:
1012         c = SHIFT_SLLX;
1013         goto gen_arith32;
1014     case INDEX_op_shr_i64:
1015         c = SHIFT_SRLX;
1016         goto gen_arith32;
1017     case INDEX_op_sar_i64:
1018         c = SHIFT_SRAX;
1019         goto gen_arith32;
1020     case INDEX_op_mul_i64:
1021         c = ARITH_MULX;
1022         goto gen_arith32;
1023     case INDEX_op_div2_i64:
1024         c = ARITH_SDIVX;
1025         goto gen_arith32;
1026     case INDEX_op_divu2_i64:
1027         c = ARITH_UDIVX;
1028         goto gen_arith32;
1029
1030     case INDEX_op_brcond_i64:
1031         tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1032                        args[3]);
1033         break;
1034     case INDEX_op_qemu_ld64:
1035         tcg_out_qemu_ld(s, args, 3);
1036         break;
1037     case INDEX_op_qemu_st64:
1038         tcg_out_qemu_st(s, args, 3);
1039         break;
1040
1041 #endif
1042     gen_arith32:
1043         if (const_args[2]) {
1044             tcg_out_arithi(s, args[0], args[1], args[2], c);
1045         } else {
1046             tcg_out_arith(s, args[0], args[1], args[2], c);
1047         }
1048         break;
1049
1050     default:
1051         fprintf(stderr, "unknown opcode 0x%x\n", opc);
1052         tcg_abort();
1053     }
1054 }
1055
1056 static const TCGTargetOpDef sparc_op_defs[] = {
1057     { INDEX_op_exit_tb, { } },
1058     { INDEX_op_goto_tb, { } },
1059     { INDEX_op_call, { "ri" } },
1060     { INDEX_op_jmp, { "ri" } },
1061     { INDEX_op_br, { } },
1062
1063     { INDEX_op_mov_i32, { "r", "r" } },
1064     { INDEX_op_movi_i32, { "r" } },
1065     { INDEX_op_ld8u_i32, { "r", "r" } },
1066     { INDEX_op_ld8s_i32, { "r", "r" } },
1067     { INDEX_op_ld16u_i32, { "r", "r" } },
1068     { INDEX_op_ld16s_i32, { "r", "r" } },
1069     { INDEX_op_ld_i32, { "r", "r" } },
1070     { INDEX_op_st8_i32, { "r", "r" } },
1071     { INDEX_op_st16_i32, { "r", "r" } },
1072     { INDEX_op_st_i32, { "r", "r" } },
1073
1074     { INDEX_op_add_i32, { "r", "r", "rJ" } },
1075     { INDEX_op_mul_i32, { "r", "r", "rJ" } },
1076     { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
1077     { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
1078     { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1079     { INDEX_op_and_i32, { "r", "r", "rJ" } },
1080     { INDEX_op_or_i32, { "r", "r", "rJ" } },
1081     { INDEX_op_xor_i32, { "r", "r", "rJ" } },
1082
1083     { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1084     { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1085     { INDEX_op_sar_i32, { "r", "r", "rJ" } },
1086
1087     { INDEX_op_brcond_i32, { "r", "ri" } },
1088
1089     { INDEX_op_qemu_ld8u, { "r", "L" } },
1090     { INDEX_op_qemu_ld8s, { "r", "L" } },
1091     { INDEX_op_qemu_ld16u, { "r", "L" } },
1092     { INDEX_op_qemu_ld16s, { "r", "L" } },
1093     { INDEX_op_qemu_ld32u, { "r", "L" } },
1094     { INDEX_op_qemu_ld32s, { "r", "L" } },
1095
1096     { INDEX_op_qemu_st8, { "L", "L" } },
1097     { INDEX_op_qemu_st16, { "L", "L" } },
1098     { INDEX_op_qemu_st32, { "L", "L" } },
1099
1100 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1101     { INDEX_op_mov_i64, { "r", "r" } },
1102     { INDEX_op_movi_i64, { "r" } },
1103     { INDEX_op_ld8u_i64, { "r", "r" } },
1104     { INDEX_op_ld8s_i64, { "r", "r" } },
1105     { INDEX_op_ld16u_i64, { "r", "r" } },
1106     { INDEX_op_ld16s_i64, { "r", "r" } },
1107     { INDEX_op_ld32u_i64, { "r", "r" } },
1108     { INDEX_op_ld32s_i64, { "r", "r" } },
1109     { INDEX_op_ld_i64, { "r", "r" } },
1110     { INDEX_op_st8_i64, { "r", "r" } },
1111     { INDEX_op_st16_i64, { "r", "r" } },
1112     { INDEX_op_st32_i64, { "r", "r" } },
1113     { INDEX_op_st_i64, { "r", "r" } },
1114
1115     { INDEX_op_add_i64, { "r", "r", "rJ" } },
1116     { INDEX_op_mul_i64, { "r", "r", "rJ" } },
1117     { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
1118     { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
1119     { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1120     { INDEX_op_and_i64, { "r", "r", "rJ" } },
1121     { INDEX_op_or_i64, { "r", "r", "rJ" } },
1122     { INDEX_op_xor_i64, { "r", "r", "rJ" } },
1123
1124     { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1125     { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1126     { INDEX_op_sar_i64, { "r", "r", "rJ" } },
1127
1128     { INDEX_op_brcond_i64, { "r", "ri" } },
1129 #endif
1130     { -1 },
1131 };
1132
1133 void tcg_target_init(TCGContext *s)
1134 {
1135     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1136 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1137     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1138 #endif
1139     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1140                      (1 << TCG_REG_G1) |
1141                      (1 << TCG_REG_G2) |
1142                      (1 << TCG_REG_G3) |
1143                      (1 << TCG_REG_G4) |
1144                      (1 << TCG_REG_G5) |
1145                      (1 << TCG_REG_G6) |
1146                      (1 << TCG_REG_G7) |
1147                      (1 << TCG_REG_O0) |
1148                      (1 << TCG_REG_O1) |
1149                      (1 << TCG_REG_O2) |
1150                      (1 << TCG_REG_O3) |
1151                      (1 << TCG_REG_O4) |
1152                      (1 << TCG_REG_O5) |
1153                      (1 << TCG_REG_O7));
1154
1155     tcg_regset_clear(s->reserved_regs);
1156     tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1157 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1158     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1159 #endif
1160     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
1161     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1162     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1163     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1164     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1165     tcg_add_target_add_op_defs(sparc_op_defs);
1166 }