hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29 #include "pc.h"
  30 #include "qemu-kvm.h"
  31 #include "device-assignment.h"
  32
  33 //#define DEBUG_PCI
  34
  35 struct PCIBus {
  36     BusState qbus;
  37     int bus_num;
  38     int devfn_min;
  39     pci_set_irq_fn set_irq;
  40     pci_map_irq_fn map_irq;
  41     uint32_t config_reg; /* XXX: suppress */
  42     /* low level pic */
  43     SetIRQFunc *low_set_irq;
  44     qemu_irq *irq_opaque;
  45     PCIDevice *devices[256];
  46     PCIDevice *parent_dev;
  47     PCIBus *next;
  48     /* The bus IRQ state is the logical OR of the connected devices.
  49        Keep a count of the number of devices with raised IRQs.  */
  50     int nirq;
  51     int irq_count[];
  52 };
  53
  54 static void pci_update_mappings(PCIDevice *d);
  55 static void pci_set_irq(void *opaque, int irq_num, int level);
  56
  57 target_phys_addr_t pci_mem_base;
  58 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  59 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  60 static PCIBus *first_bus;
  61
  62 static void pcibus_save(QEMUFile *f, void *opaque)
  63 {
  64     PCIBus *bus = (PCIBus *)opaque;
  65     int i;
  66
  67     qemu_put_be32(f, bus->nirq);
  68     for (i = 0; i < bus->nirq; i++)
  69         qemu_put_be32(f, bus->irq_count[i]);
  70 }
  71
  72 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  73 {
  74     PCIBus *bus = (PCIBus *)opaque;
  75     int i, nirq;
  76
  77     if (version_id != 1)
  78         return -EINVAL;
  79
  80     nirq = qemu_get_be32(f);
  81     if (bus->nirq != nirq) {
  82         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  83                 nirq, bus->nirq);
  84         return -EINVAL;
  85     }
  86
  87     for (i = 0; i < nirq; i++)
  88         bus->irq_count[i] = qemu_get_be32(f);
  89
  90     return 0;
  91 }
  92
  93 static void pci_bus_reset(void *opaque)
  94 {
  95     PCIBus *bus = (PCIBus *)opaque;
  96     int i;
  97
  98     for (i = 0; i < bus->nirq; i++) {
  99         bus->irq_count[i] = 0;
 100     }
 101     for (i = 0; i < 256; i++) {
 102         if (bus->devices[i])
 103             memset(bus->devices[i]->irq_state, 0,
 104                    sizeof(bus->devices[i]->irq_state));
 105     }
 106 }
 107
 108 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 109                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 110                          qemu_irq *pic, int devfn_min, int nirq)
 111 {
 112     PCIBus *bus;
 113     static int nbus = 0;
 114
 115     bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI,
 116                                         sizeof(PCIBus) + (nirq * sizeof(int)),
 117                                         parent, name));
 118     bus->set_irq = set_irq;
 119     bus->map_irq = map_irq;
 120     bus->irq_opaque = pic;
 121     bus->devfn_min = devfn_min;
 122     bus->nirq = nirq;
 123     bus->next = first_bus;
 124     first_bus = bus;
 125     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 126     qemu_register_reset(pci_bus_reset, 0, bus);
 127     return bus;
 128 }
 129
 130 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 131 {
 132     PCIBus *bus;
 133     bus = qemu_mallocz(sizeof(PCIBus));
 134     bus->map_irq = map_irq;
 135     bus->parent_dev = dev;
 136     bus->next = dev->bus->next;
 137     dev->bus->next = bus;
 138     return bus;
 139 }
 140
 141 int pci_bus_num(PCIBus *s)
 142 {
 143     return s->bus_num;
 144 }
 145
 146 void pci_device_save(PCIDevice *s, QEMUFile *f)
 147 {
 148     int i;
 149
 150     qemu_put_be32(f, 2); /* PCI device version */
 151     qemu_put_buffer(f, s->config, 256);
 152     for (i = 0; i < 4; i++)
 153         qemu_put_be32(f, s->irq_state[i]);
 154 }
 155
 156 int pci_device_load(PCIDevice *s, QEMUFile *f)
 157 {
 158     uint32_t version_id;
 159     int i;
 160
 161     version_id = qemu_get_be32(f);
 162     if (version_id > 2)
 163         return -EINVAL;
 164     qemu_get_buffer(f, s->config, 256);
 165     pci_update_mappings(s);
 166
 167     if (version_id >= 2)
 168         for (i = 0; i < 4; i ++)
 169             s->irq_state[i] = qemu_get_be32(f);
 170
 171     return 0;
 172 }
 173
 174 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 175 {
 176     uint16_t *id;
 177
 178     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 179     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 180     id[1] = cpu_to_le16(pci_default_sub_device_id);
 181     return 0;
 182 }
 183
 184 /*
 185  * Parse pci address in qemu command
 186  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 187  */
 188 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 189 {
 190     const char *p;
 191     char *e;
 192     unsigned long val;
 193     unsigned long dom = 0, bus = 0;
 194     unsigned slot = 0;
 195
 196     p = addr;
 197     val = strtoul(p, &e, 16);
 198     if (e == p)
 199         return -1;
 200     if (*e == ':') {
 201         bus = val;
 202         p = e + 1;
 203         val = strtoul(p, &e, 16);
 204         if (e == p)
 205             return -1;
 206         if (*e == ':') {
 207             dom = bus;
 208             bus = val;
 209             p = e + 1;
 210             val = strtoul(p, &e, 16);
 211             if (e == p)
 212                 return -1;
 213         }
 214     }
 215
 216     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 217         return -1;
 218
 219     slot = val;
 220
 221     if (*e)
 222         return -1;
 223
 224     /* Note: QEMU doesn't implement domains other than 0 */
 225     if (dom != 0 || pci_find_bus(bus) == NULL)
 226         return -1;
 227
 228     *domp = dom;
 229     *busp = bus;
 230     *slotp = slot;
 231     return 0;
 232 }
 233
 234 /*
 235  * Parse device bdf in device assignment command:
 236  *
 237  * -pcidevice host=bus:dev.func
 238  *
 239  * Parse <bus>:<slot>.<func> return -1 on error
 240  */
 241 int pci_parse_host_devaddr(const char *addr, int *busp,
 242                            int *slotp, int *funcp)
 243 {
 244     const char *p;
 245     char *e;
 246     int val;
 247     int bus = 0, slot = 0, func = 0;
 248
 249     p = addr;
 250     val = strtoul(p, &e, 16);
 251     if (e == p)
 252         return -1;
 253     if (*e == ':') {
 254         bus = val;
 255         p = e + 1;
 256         val = strtoul(p, &e, 16);
 257         if (e == p)
 258             return -1;
 259         if (*e == '.') {
 260             slot = val;
 261             p = e + 1;
 262             val = strtoul(p, &e, 16);
 263             if (e == p)
 264                 return -1;
 265             func = val;
 266         } else
 267             return -1;
 268     } else
 269         return -1;
 270
 271     if (bus > 0xff || slot > 0x1f || func > 0x7)
 272         return -1;
 273
 274     if (*e)
 275         return -1;
 276
 277     *busp = bus;
 278     *slotp = slot;
 279     *funcp = func;
 280     return 0;
 281 }
 282
 283 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 284 {
 285     char devaddr[32];
 286
 287     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 288         return -1;
 289
 290     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 291 }
 292
 293 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 294 {
 295     int dom, bus;
 296     unsigned slot;
 297
 298     if (!devaddr) {
 299         *devfnp = -1;
 300         return pci_find_bus(0);
 301     }
 302
 303     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 304         return NULL;
 305     }
 306
 307     *devfnp = slot << 3;
 308     return pci_find_bus(bus);
 309 }
 310
 311 static void pci_init_wmask(PCIDevice *dev)
 312 {
 313     int i;
 314     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 315     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 316     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 317                               | PCI_COMMAND_MASTER;
 318     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 319         dev->wmask[i] = 0xff;
 320 }
 321
 322 /* -1 for devfn means auto assign */
 323 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 324                                          const char *name, int devfn,
 325                                          PCIConfigReadFunc *config_read,
 326                                          PCIConfigWriteFunc *config_write)
 327 {
 328     if (devfn < 0) {
 329         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 330             if (!bus->devices[devfn])
 331                 goto found;
 332         }
 333         return NULL;
 334     found: ;
 335     } else if (bus->devices[devfn]) {
 336         return NULL;
 337     }
 338     pci_dev->bus = bus;
 339     pci_dev->devfn = devfn;
 340     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 341     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 342     pci_set_default_subsystem_id(pci_dev);
 343     pci_init_wmask(pci_dev);
 344
 345     if (!config_read)
 346         config_read = pci_default_read_config;
 347     if (!config_write)
 348         config_write = pci_default_write_config;
 349     pci_dev->config_read = config_read;
 350     pci_dev->config_write = config_write;
 351     bus->devices[devfn] = pci_dev;
 352     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 353     return pci_dev;
 354 }
 355
 356 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 357                                int instance_size, int devfn,
 358                                PCIConfigReadFunc *config_read,
 359                                PCIConfigWriteFunc *config_write)
 360 {
 361     PCIDevice *pci_dev;
 362
 363     pci_dev = qemu_mallocz(instance_size);
 364     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 365                                      config_read, config_write);
 366     return pci_dev;
 367 }
 368 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 369 {
 370     return addr + pci_mem_base;
 371 }
 372
 373 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 374 {
 375     PCIIORegion *r;
 376     int i;
 377
 378     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 379         r = &pci_dev->io_regions[i];
 380         if (!r->size || r->addr == -1)
 381             continue;
 382         if (r->type == PCI_ADDRESS_SPACE_IO) {
 383             isa_unassign_ioport(r->addr, r->size);
 384         } else {
 385             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 386                                                      r->size,
 387                                                      IO_MEM_UNASSIGNED);
 388         }
 389     }
 390 }
 391
 392 int pci_unregister_device(PCIDevice *pci_dev, int assigned)
 393 {
 394     int ret = 0;
 395
 396     if (pci_dev->unregister)
 397         ret = pci_dev->unregister(pci_dev);
 398     if (ret)
 399         return ret;
 400
 401     pci_unregister_io_regions(pci_dev);
 402
 403     qemu_free_irqs(pci_dev->irq);
 404     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 405
 406     if (assigned)
 407         qemu_free(pci_dev);
 408     else
 409         qdev_free(&pci_dev->qdev);
 410     return 0;
 411 }
 412
 413 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 414                             uint32_t size, int type,
 415                             PCIMapIORegionFunc *map_func)
 416 {
 417     PCIIORegion *r;
 418     uint32_t addr;
 419     uint32_t wmask;
 420
 421     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 422         return;
 423
 424     if (size & (size-1)) {
 425         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 426                     "type=0x%x, size=0x%x\n", type, size);
 427         exit(1);
 428     }
 429
 430     r = &pci_dev->io_regions[region_num];
 431     r->addr = -1;
 432     r->size = size;
 433     r->type = type;
 434     r->map_func = map_func;
 435
 436     wmask = ~(size - 1);
 437     if (region_num == PCI_ROM_SLOT) {
 438         addr = 0x30;
 439         /* ROM enable bit is writeable */
 440         wmask |= 1;
 441     } else {
 442         addr = 0x10 + region_num * 4;
 443     }
 444     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 445     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 446 }
 447
 448 static void pci_update_mappings(PCIDevice *d)
 449 {
 450     PCIIORegion *r;
 451     int cmd, i;
 452     uint32_t last_addr, new_addr, config_ofs;
 453
 454     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 455     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 456         r = &d->io_regions[i];
 457         if (i == PCI_ROM_SLOT) {
 458             config_ofs = 0x30;
 459         } else {
 460             config_ofs = 0x10 + i * 4;
 461         }
 462         if (r->size != 0) {
 463             if (r->type & PCI_ADDRESS_SPACE_IO) {
 464                 if (cmd & PCI_COMMAND_IO) {
 465                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 466                                                          config_ofs));
 467                     new_addr = new_addr & ~(r->size - 1);
 468                     last_addr = new_addr + r->size - 1;
 469                     /* NOTE: we have only 64K ioports on PC */
 470                     if (last_addr <= new_addr || new_addr == 0 ||
 471                         last_addr >= 0x10000) {
 472                         new_addr = -1;
 473                     }
 474                 } else {
 475                     new_addr = -1;
 476                 }
 477             } else {
 478                 if (cmd & PCI_COMMAND_MEMORY) {
 479                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 480                                                          config_ofs));
 481                     /* the ROM slot has a specific enable bit */
 482                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 483                         goto no_mem_map;
 484                     new_addr = new_addr & ~(r->size - 1);
 485                     last_addr = new_addr + r->size - 1;
 486                     /* NOTE: we do not support wrapping */
 487                     /* XXX: as we cannot support really dynamic
 488                        mappings, we handle specific values as invalid
 489                        mappings. */
 490                     if (last_addr <= new_addr || new_addr == 0 ||
 491                         last_addr == -1) {
 492                         new_addr = -1;
 493                     }
 494                 } else {
 495                 no_mem_map:
 496                     new_addr = -1;
 497                 }
 498             }
 499             /* now do the real mapping */
 500             if (new_addr != r->addr) {
 501                 if (r->addr != -1) {
 502                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 503                         int class;
 504                         /* NOTE: specific hack for IDE in PC case:
 505                            only one byte must be mapped. */
 506                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 507                         if (class == 0x0101 && r->size == 4) {
 508                             isa_unassign_ioport(r->addr + 2, 1);
 509                         } else {
 510                             isa_unassign_ioport(r->addr, r->size);
 511                         }
 512                     } else {
 513                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 514                                                      r->size,
 515                                                      IO_MEM_UNASSIGNED);
 516                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 517                     }
 518                 }
 519                 r->addr = new_addr;
 520                 if (r->addr != -1) {
 521                     r->map_func(d, i, r->addr, r->size, r->type);
 522                 }
 523             }
 524         }
 525     }
 526 }
 527
 528 static uint32_t pci_read_config(PCIDevice *d,
 529                                 uint32_t address, int len)
 530 {
 531     uint32_t val;
 532
 533     switch(len) {
 534     default:
 535     case 4:
 536         if (address <= 0xfc) {
 537             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 538             break;
 539         }
 540         /* fall through */
 541     case 2:
 542         if (address <= 0xfe) {
 543             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 544             break;
 545         }
 546         /* fall through */
 547     case 1:
 548         val = d->config[address];
 549         break;
 550     }
 551     return val;
 552 }
 553
 554 static void pci_write_config(PCIDevice *pci_dev,
 555                              uint32_t address, uint32_t val, int len)
 556 {
 557     int i;
 558     for (i = 0; i < len; i++) {
 559         pci_dev->config[address + i] = val & 0xff;
 560         val >>= 8;
 561     }
 562 }
 563
 564 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len)
 565 {
 566     if (pci_dev->cap.supported && address >= pci_dev->cap.start &&
 567             (address + len) < pci_dev->cap.start + pci_dev->cap.length)
 568         return 1;
 569     return 0;
 570 }
 571
 572 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 573                                      uint32_t address, int len)
 574 {
 575     return pci_read_config(pci_dev, address, len);
 576 }
 577
 578 void pci_default_cap_write_config(PCIDevice *pci_dev,
 579                                   uint32_t address, uint32_t val, int len)
 580 {
 581     pci_write_config(pci_dev, address, val, len);
 582 }
 583
 584 uint32_t pci_default_read_config(PCIDevice *d,
 585                                  uint32_t address, int len)
 586 {
 587     if (pci_access_cap_config(d, address, len))
 588         return d->cap.config_read(d, address, len);
 589
 590     return pci_read_config(d, address, len);
 591 }
 592
 593 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 594 {
 595     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 596     int i;
 597
 598     if (pci_access_cap_config(d, addr, l)) {
 599         d->cap.config_write(d, addr, val, l);
 600         return;
 601     }
 602
 603     /* not efficient, but simple */
 604     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 605     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 606         uint8_t wmask = d->wmask[addr];
 607         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 608     }
 609
 610 #ifdef USE_KVM_DEVICE_ASSIGNMENT
 611     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel() &&
 612         addr >= PIIX_CONFIG_IRQ_ROUTE &&
 613         addr < PIIX_CONFIG_IRQ_ROUTE + 4)
 614         assigned_dev_update_irqs();
 615 #endif /* USE_KVM_DEVICE_ASSIGNMENT */
 616
 617     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 618         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 619             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 620         pci_update_mappings(d);
 621
 622 }
 623
 624 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 625 {
 626     PCIBus *s = opaque;
 627     PCIDevice *pci_dev;
 628     int config_addr, bus_num;
 629
 630 #if defined(DEBUG_PCI) && 0
 631     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 632            addr, val, len);
 633 #endif
 634     bus_num = (addr >> 16) & 0xff;
 635     while (s && s->bus_num != bus_num)
 636         s = s->next;
 637     if (!s)
 638         return;
 639     pci_dev = s->devices[(addr >> 8) & 0xff];
 640     if (!pci_dev)
 641         return;
 642     config_addr = addr & 0xff;
 643 #if defined(DEBUG_PCI)
 644     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 645            pci_dev->name, config_addr, val, len);
 646 #endif
 647     pci_dev->config_write(pci_dev, config_addr, val, len);
 648 }
 649
 650 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 651 {
 652     PCIBus *s = opaque;
 653     PCIDevice *pci_dev;
 654     int config_addr, bus_num;
 655     uint32_t val;
 656
 657     bus_num = (addr >> 16) & 0xff;
 658     while (s && s->bus_num != bus_num)
 659         s= s->next;
 660     if (!s)
 661         goto fail;
 662     pci_dev = s->devices[(addr >> 8) & 0xff];
 663     if (!pci_dev) {
 664     fail:
 665         switch(len) {
 666         case 1:
 667             val = 0xff;
 668             break;
 669         case 2:
 670             val = 0xffff;
 671             break;
 672         default:
 673         case 4:
 674             val = 0xffffffff;
 675             break;
 676         }
 677         goto the_end;
 678     }
 679     config_addr = addr & 0xff;
 680     val = pci_dev->config_read(pci_dev, config_addr, len);
 681 #if defined(DEBUG_PCI)
 682     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 683            pci_dev->name, config_addr, val, len);
 684 #endif
 685  the_end:
 686 #if defined(DEBUG_PCI) && 0
 687     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 688            addr, val, len);
 689 #endif
 690     return val;
 691 }
 692
 693 /***********************************************************/
 694 /* generic PCI irq support */
 695
 696 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 697 static void pci_set_irq(void *opaque, int irq_num, int level)
 698 {
 699     PCIDevice *pci_dev = (PCIDevice *)opaque;
 700     PCIBus *bus;
 701     int change;
 702
 703     change = level - pci_dev->irq_state[irq_num];
 704     if (!change)
 705         return;
 706
 707     pci_dev->irq_state[irq_num] = level;
 708
 709 #if defined(TARGET_IA64)
 710     ioapic_set_irq(pci_dev, irq_num, level);
 711 #endif
 712
 713     for (;;) {
 714         bus = pci_dev->bus;
 715         irq_num = bus->map_irq(pci_dev, irq_num);
 716         if (bus->set_irq)
 717             break;
 718         pci_dev = bus->parent_dev;
 719     }
 720     bus->irq_count[irq_num] += change;
 721     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 722 }
 723
 724 int pci_map_irq(PCIDevice *pci_dev, int pin)
 725 {
 726     return pci_dev->bus->map_irq(pci_dev, pin);
 727 }
 728
 729 /***********************************************************/
 730 /* monitor info on PCI */
 731
 732 typedef struct {
 733     uint16_t class;
 734     const char *desc;
 735 } pci_class_desc;
 736
 737 static const pci_class_desc pci_class_descriptions[] =
 738 {
 739     { 0x0100, "SCSI controller"},
 740     { 0x0101, "IDE controller"},
 741     { 0x0102, "Floppy controller"},
 742     { 0x0103, "IPI controller"},
 743     { 0x0104, "RAID controller"},
 744     { 0x0106, "SATA controller"},
 745     { 0x0107, "SAS controller"},
 746     { 0x0180, "Storage controller"},
 747     { 0x0200, "Ethernet controller"},
 748     { 0x0201, "Token Ring controller"},
 749     { 0x0202, "FDDI controller"},
 750     { 0x0203, "ATM controller"},
 751     { 0x0280, "Network controller"},
 752     { 0x0300, "VGA controller"},
 753     { 0x0301, "XGA controller"},
 754     { 0x0302, "3D controller"},
 755     { 0x0380, "Display controller"},
 756     { 0x0400, "Video controller"},
 757     { 0x0401, "Audio controller"},
 758     { 0x0402, "Phone"},
 759     { 0x0480, "Multimedia controller"},
 760     { 0x0500, "RAM controller"},
 761     { 0x0501, "Flash controller"},
 762     { 0x0580, "Memory controller"},
 763     { 0x0600, "Host bridge"},
 764     { 0x0601, "ISA bridge"},
 765     { 0x0602, "EISA bridge"},
 766     { 0x0603, "MC bridge"},
 767     { 0x0604, "PCI bridge"},
 768     { 0x0605, "PCMCIA bridge"},
 769     { 0x0606, "NUBUS bridge"},
 770     { 0x0607, "CARDBUS bridge"},
 771     { 0x0608, "RACEWAY bridge"},
 772     { 0x0680, "Bridge"},
 773     { 0x0c03, "USB controller"},
 774     { 0, NULL}
 775 };
 776
 777 static void pci_info_device(PCIDevice *d)
 778 {
 779     Monitor *mon = cur_mon;
 780     int i, class;
 781     PCIIORegion *r;
 782     const pci_class_desc *desc;
 783
 784     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 785                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 786     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 787     monitor_printf(mon, "    ");
 788     desc = pci_class_descriptions;
 789     while (desc->desc && class != desc->class)
 790         desc++;
 791     if (desc->desc) {
 792         monitor_printf(mon, "%s", desc->desc);
 793     } else {
 794         monitor_printf(mon, "Class %04x", class);
 795     }
 796     monitor_printf(mon, ": PCI device %04x:%04x\n",
 797            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 798            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 799
 800     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 801         monitor_printf(mon, "      IRQ %d.\n",
 802                        d->config[PCI_INTERRUPT_LINE]);
 803     }
 804     if (class == 0x0604) {
 805         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 806     }
 807     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 808         r = &d->io_regions[i];
 809         if (r->size != 0) {
 810             monitor_printf(mon, "      BAR%d: ", i);
 811             if (r->type & PCI_ADDRESS_SPACE_IO) {
 812                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 813                                r->addr, r->addr + r->size - 1);
 814             } else {
 815                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 816                                r->addr, r->addr + r->size - 1);
 817             }
 818         }
 819     }
 820     if (class == 0x0604 && d->config[0x19] != 0) {
 821         pci_for_each_device(d->config[0x19], pci_info_device);
 822     }
 823 }
 824
 825 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 826 {
 827     PCIBus *bus = first_bus;
 828     PCIDevice *d;
 829     int devfn;
 830
 831     while (bus && bus->bus_num != bus_num)
 832         bus = bus->next;
 833     if (bus) {
 834         for(devfn = 0; devfn < 256; devfn++) {
 835             d = bus->devices[devfn];
 836             if (d)
 837                 fn(d);
 838         }
 839     }
 840 }
 841
 842 void pci_info(Monitor *mon)
 843 {
 844     pci_for_each_device(0, pci_info_device);
 845 }
 846
 847 PCIDevice *pci_create(const char *name, const char *devaddr)
 848 {
 849     PCIBus *bus;
 850     int devfn;
 851     DeviceState *dev;
 852
 853     bus = pci_get_bus_devfn(&devfn, devaddr);
 854     if (!bus) {
 855         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 856                 devaddr, name);
 857         exit(1);
 858     }
 859
 860     dev = qdev_create(&bus->qbus, name);
 861     qdev_set_prop_int(dev, "devfn", devfn);
 862     return (PCIDevice *)dev;
 863 }
 864
 865 static const char * const pci_nic_models[] = {
 866     "ne2k_pci",
 867     "i82551",
 868     "i82557b",
 869     "i82559er",
 870     "rtl8139",
 871     "e1000",
 872     "pcnet",
 873     "virtio",
 874     NULL
 875 };
 876
 877 static const char * const pci_nic_names[] = {
 878     "ne2k_pci",
 879     "i82551",
 880     "i82557b",
 881     "i82559er",
 882     "rtl8139",
 883     "e1000",
 884     "pcnet",
 885     "virtio-net-pci",
 886     NULL
 887 };
 888
 889 /* Initialize a PCI NIC.  */
 890 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 891                         const char *default_devaddr)
 892 {
 893     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 894     PCIDevice *pci_dev;
 895     DeviceState *dev;
 896     int i;
 897
 898     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 899
 900     for (i = 0; pci_nic_models[i]; i++) {
 901         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 902             pci_dev = pci_create(pci_nic_names[i], devaddr);
 903             dev = &pci_dev->qdev;
 904             qdev_set_netdev(dev, nd);
 905             qdev_init(dev);
 906             nd->private = dev;
 907             return pci_dev;
 908         }
 909     }
 910
 911     return NULL;
 912 }
 913
 914 typedef struct {
 915     PCIDevice dev;
 916     PCIBus *bus;
 917 } PCIBridge;
 918
 919 static void pci_bridge_write_config(PCIDevice *d,
 920                              uint32_t address, uint32_t val, int len)
 921 {
 922     PCIBridge *s = (PCIBridge *)d;
 923
 924     pci_default_write_config(d, address, val, len);
 925     s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
 926 }
 927
 928 PCIBus *pci_find_bus(int bus_num)
 929 {
 930     PCIBus *bus = first_bus;
 931
 932     while (bus && bus->bus_num != bus_num)
 933         bus = bus->next;
 934
 935     return bus;
 936 }
 937
 938 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 939 {
 940     PCIBus *bus = pci_find_bus(bus_num);
 941
 942     if (!bus)
 943         return NULL;
 944
 945     return bus->devices[PCI_DEVFN(slot, function)];
 946 }
 947
 948 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 949                         pci_map_irq_fn map_irq, const char *name)
 950 {
 951     PCIBridge *s;
 952     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 953                                          devfn, NULL, pci_bridge_write_config);
 954
 955     pci_config_set_vendor_id(s->dev.config, vid);
 956     pci_config_set_device_id(s->dev.config, did);
 957
 958     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 959     s->dev.config[0x05] = 0x00;
 960     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 961     s->dev.config[0x07] = 0x00; // status = fast devsel
 962     s->dev.config[0x08] = 0x00; // revision
 963     s->dev.config[0x09] = 0x00; // programming i/f
 964     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 965     s->dev.config[0x0D] = 0x10; // latency_timer
 966     s->dev.config[PCI_HEADER_TYPE] =
 967         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 968     s->dev.config[0x1E] = 0xa0; // secondary status
 969
 970     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 971     return s->bus;
 972 }
 973
 974 typedef struct {
 975     DeviceInfo qdev;
 976     pci_qdev_initfn init;
 977 } PCIDeviceInfo;
 978
 979 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 980 {
 981     PCIDevice *pci_dev = (PCIDevice *)qdev;
 982     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 983     PCIBus *bus;
 984     int devfn;
 985
 986     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 987     devfn = qdev_get_prop_int(qdev, "devfn", -1);
 988     pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
 989                                      NULL, NULL);//FIXME:config_read, config_write);
 990     assert(pci_dev);
 991     info->init(pci_dev);
 992 }
 993
 994 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)
 995 {
 996     PCIDeviceInfo *info;
 997
 998     info = qemu_mallocz(sizeof(*info));
 999     info->qdev.name = qemu_strdup(name);
1000     info->qdev.size = size;
1001     info->init = init;
1002     info->qdev.init = pci_qdev_init;
1003     info->qdev.bus_type = BUS_TYPE_PCI;
1004
1005     qdev_register(&info->qdev);
1006 }
1007
1008 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1009 {
1010     DeviceState *dev;
1011
1012     dev = qdev_create(&bus->qbus, name);
1013     qdev_set_prop_int(dev, "devfn", devfn);
1014     qdev_init(dev);
1015
1016     return (PCIDevice *)dev;
1017 }
1018
1019 int pci_enable_capability_support(PCIDevice *pci_dev,
1020                                   uint32_t config_start,
1021                                   PCICapConfigReadFunc *config_read,
1022                                   PCICapConfigWriteFunc *config_write,
1023                                   PCICapConfigInitFunc *config_init)
1024 {
1025     if (!pci_dev)
1026         return -ENODEV;
1027
1028     pci_dev->config[0x06] |= 0x10; // status = capabilities
1029
1030     if (config_start == 0)
1031         pci_dev->cap.start = PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR;
1032     else if (config_start >= 0x40 && config_start < 0xff)
1033         pci_dev->cap.start = config_start;
1034     else
1035         return -EINVAL;
1036
1037     if (config_read)
1038         pci_dev->cap.config_read = config_read;
1039     else
1040         pci_dev->cap.config_read = pci_default_cap_read_config;
1041     if (config_write)
1042         pci_dev->cap.config_write = config_write;
1043     else
1044         pci_dev->cap.config_write = pci_default_cap_write_config;
1045     pci_dev->cap.supported = 1;
1046     pci_dev->config[PCI_CAPABILITY_LIST] = pci_dev->cap.start;
1047     return config_init(pci_dev);
1048 }