hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "pci.h"
  21 #include "qemu-timer.h"
  22 #include "sysemu.h"
  23 #include "i2c.h"
  24 #include "smbus.h"
  25 #include "kvm.h"
  26 #include "qemu-kvm.h"
  27 #include "string.h"
  28
  29 //#define DEBUG
  30
  31 /* i82731AB (PIIX4) compatible power management function */
  32 #define PM_FREQ 3579545
  33
  34 #define ACPI_DBG_IO_ADDR  0xb044
  35
  36 typedef struct PIIX4PMState {
  37     PCIDevice dev;
  38     uint16_t pmsts;
  39     uint16_t pmen;
  40     uint16_t pmcntrl;
  41     uint8_t apmc;
  42     uint8_t apms;
  43     QEMUTimer *tmr_timer;
  44     int64_t tmr_overflow_time;
  45     i2c_bus *smbus;
  46     uint8_t smb_stat;
  47     uint8_t smb_ctl;
  48     uint8_t smb_cmd;
  49     uint8_t smb_addr;
  50     uint8_t smb_data0;
  51     uint8_t smb_data1;
  52     uint8_t smb_data[32];
  53     uint8_t smb_index;
  54     qemu_irq irq;
  55 } PIIX4PMState;
  56
  57 #define RSM_STS (1 << 15)
  58 #define PWRBTN_STS (1 << 8)
  59 #define RTC_EN (1 << 10)
  60 #define PWRBTN_EN (1 << 8)
  61 #define GBL_EN (1 << 5)
  62 #define TMROF_EN (1 << 0)
  63
  64 #define SCI_EN (1 << 0)
  65
  66 #define SUS_EN (1 << 13)
  67
  68 #define ACPI_ENABLE 0xf1
  69 #define ACPI_DISABLE 0xf0
  70
  71 #define SMBHSTSTS 0x00
  72 #define SMBHSTCNT 0x02
  73 #define SMBHSTCMD 0x03
  74 #define SMBHSTADD 0x04
  75 #define SMBHSTDAT0 0x05
  76 #define SMBHSTDAT1 0x06
  77 #define SMBBLKDAT 0x07
  78
  79 static PIIX4PMState *pm_state;
  80
  81 static uint32_t get_pmtmr(PIIX4PMState *s)
  82 {
  83     uint32_t d;
  84     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  85     return d & 0xffffff;
  86 }
  87
  88 static int get_pmsts(PIIX4PMState *s)
  89 {
  90     int64_t d;
  91     int pmsts;
  92     pmsts = s->pmsts;
  93     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  94     if (d >= s->tmr_overflow_time)
  95         s->pmsts |= TMROF_EN;
  96     return s->pmsts;
  97 }
  98
  99 static void pm_update_sci(PIIX4PMState *s)
 100 {
 101     int sci_level, pmsts;
 102     int64_t expire_time;
 103
 104     pmsts = get_pmsts(s);
 105     sci_level = (((pmsts & s->pmen) &
 106                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 107     qemu_set_irq(s->irq, sci_level);
 108     /* schedule a timer interruption if needed */
 109     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 110         expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
 111         qemu_mod_timer(s->tmr_timer, expire_time);
 112     } else {
 113         qemu_del_timer(s->tmr_timer);
 114     }
 115 }
 116
 117 static void pm_tmr_timer(void *opaque)
 118 {
 119     PIIX4PMState *s = opaque;
 120     pm_update_sci(s);
 121 }
 122
 123 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 124 {
 125     PIIX4PMState *s = opaque;
 126     addr &= 0x3f;
 127     switch(addr) {
 128     case 0x00:
 129         {
 130             int64_t d;
 131             int pmsts;
 132             pmsts = get_pmsts(s);
 133             if (pmsts & val & TMROF_EN) {
 134                 /* if TMRSTS is reset, then compute the new overflow time */
 135                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
 136                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 137             }
 138             s->pmsts &= ~val;
 139             pm_update_sci(s);
 140         }
 141         break;
 142     case 0x02:
 143         s->pmen = val;
 144         pm_update_sci(s);
 145         break;
 146     case 0x04:
 147         {
 148             int sus_typ;
 149             s->pmcntrl = val & ~(SUS_EN);
 150             if (val & SUS_EN) {
 151                 /* change suspend type */
 152                 sus_typ = (val >> 10) & 7;
 153                 switch(sus_typ) {
 154                 case 0: /* soft power off */
 155                     qemu_system_shutdown_request();
 156                     break;
 157                 case 1:
 158                     /* RSM_STS should be set on resume. Pretend that resume
 159                        was caused by power button */
 160                     s->pmsts |= (RSM_STS | PWRBTN_STS);
 161                     qemu_system_reset_request();
 162 #if defined(TARGET_I386)
 163                     cmos_set_s3_resume();
 164 #endif
 165                 default:
 166                     break;
 167                 }
 168             }
 169         }
 170         break;
 171     default:
 172         break;
 173     }
 174 #ifdef DEBUG
 175     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 176 #endif
 177 }
 178
 179 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 180 {
 181     PIIX4PMState *s = opaque;
 182     uint32_t val;
 183
 184     addr &= 0x3f;
 185     switch(addr) {
 186     case 0x00:
 187         val = get_pmsts(s);
 188         break;
 189     case 0x02:
 190         val = s->pmen;
 191         break;
 192     case 0x04:
 193         val = s->pmcntrl;
 194         break;
 195     default:
 196         val = 0;
 197         break;
 198     }
 199 #ifdef DEBUG
 200     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 201 #endif
 202     return val;
 203 }
 204
 205 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 206 {
 207     //    PIIX4PMState *s = opaque;
 208     addr &= 0x3f;
 209 #ifdef DEBUG
 210     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 211 #endif
 212 }
 213
 214 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 215 {
 216     PIIX4PMState *s = opaque;
 217     uint32_t val;
 218
 219     addr &= 0x3f;
 220     switch(addr) {
 221     case 0x08:
 222         val = get_pmtmr(s);
 223         break;
 224     default:
 225         val = 0;
 226         break;
 227     }
 228 #ifdef DEBUG
 229     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 230 #endif
 231     return val;
 232 }
 233
 234 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 235 {
 236     PIIX4PMState *s = opaque;
 237     addr &= 1;
 238 #ifdef DEBUG
 239     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 240 #endif
 241     if (addr == 0) {
 242         s->apmc = val;
 243
 244         /* ACPI specs 3.0, 4.7.2.5 */
 245         if (val == ACPI_ENABLE) {
 246             s->pmcntrl |= SCI_EN;
 247         } else if (val == ACPI_DISABLE) {
 248             s->pmcntrl &= ~SCI_EN;
 249         }
 250
 251         if (s->dev.config[0x5b] & (1 << 1)) {
 252             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 253         }
 254     } else {
 255         s->apms = val;
 256     }
 257 }
 258
 259 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 260 {
 261     PIIX4PMState *s = opaque;
 262     uint32_t val;
 263
 264     addr &= 1;
 265     if (addr == 0) {
 266         val = s->apmc;
 267     } else {
 268         val = s->apms;
 269     }
 270 #ifdef DEBUG
 271     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 272 #endif
 273     return val;
 274 }
 275
 276 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 277 {
 278 #if defined(DEBUG)
 279     printf("ACPI: DBG: 0x%08x\n", val);
 280 #endif
 281 }
 282
 283 static void smb_transaction(PIIX4PMState *s)
 284 {
 285     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 286     uint8_t read = s->smb_addr & 0x01;
 287     uint8_t cmd = s->smb_cmd;
 288     uint8_t addr = s->smb_addr >> 1;
 289     i2c_bus *bus = s->smbus;
 290
 291 #ifdef DEBUG
 292     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 293 #endif
 294     switch(prot) {
 295     case 0x0:
 296         smbus_quick_command(bus, addr, read);
 297         break;
 298     case 0x1:
 299         if (read) {
 300             s->smb_data0 = smbus_receive_byte(bus, addr);
 301         } else {
 302             smbus_send_byte(bus, addr, cmd);
 303         }
 304         break;
 305     case 0x2:
 306         if (read) {
 307             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 308         } else {
 309             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 310         }
 311         break;
 312     case 0x3:
 313         if (read) {
 314             uint16_t val;
 315             val = smbus_read_word(bus, addr, cmd);
 316             s->smb_data0 = val;
 317             s->smb_data1 = val >> 8;
 318         } else {
 319             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 320         }
 321         break;
 322     case 0x5:
 323         if (read) {
 324             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 325         } else {
 326             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 327         }
 328         break;
 329     default:
 330         goto error;
 331     }
 332     return;
 333
 334   error:
 335     s->smb_stat |= 0x04;
 336 }
 337
 338 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 339 {
 340     PIIX4PMState *s = opaque;
 341     addr &= 0x3f;
 342 #ifdef DEBUG
 343     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 344 #endif
 345     switch(addr) {
 346     case SMBHSTSTS:
 347         s->smb_stat = 0;
 348         s->smb_index = 0;
 349         break;
 350     case SMBHSTCNT:
 351         s->smb_ctl = val;
 352         if (val & 0x40)
 353             smb_transaction(s);
 354         break;
 355     case SMBHSTCMD:
 356         s->smb_cmd = val;
 357         break;
 358     case SMBHSTADD:
 359         s->smb_addr = val;
 360         break;
 361     case SMBHSTDAT0:
 362         s->smb_data0 = val;
 363         break;
 364     case SMBHSTDAT1:
 365         s->smb_data1 = val;
 366         break;
 367     case SMBBLKDAT:
 368         s->smb_data[s->smb_index++] = val;
 369         if (s->smb_index > 31)
 370             s->smb_index = 0;
 371         break;
 372     default:
 373         break;
 374     }
 375 }
 376
 377 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 378 {
 379     PIIX4PMState *s = opaque;
 380     uint32_t val;
 381
 382     addr &= 0x3f;
 383     switch(addr) {
 384     case SMBHSTSTS:
 385         val = s->smb_stat;
 386         break;
 387     case SMBHSTCNT:
 388         s->smb_index = 0;
 389         val = s->smb_ctl & 0x1f;
 390         break;
 391     case SMBHSTCMD:
 392         val = s->smb_cmd;
 393         break;
 394     case SMBHSTADD:
 395         val = s->smb_addr;
 396         break;
 397     case SMBHSTDAT0:
 398         val = s->smb_data0;
 399         break;
 400     case SMBHSTDAT1:
 401         val = s->smb_data1;
 402         break;
 403     case SMBBLKDAT:
 404         val = s->smb_data[s->smb_index++];
 405         if (s->smb_index > 31)
 406             s->smb_index = 0;
 407         break;
 408     default:
 409         val = 0;
 410         break;
 411     }
 412 #ifdef DEBUG
 413     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 414 #endif
 415     return val;
 416 }
 417
 418 static void pm_io_space_update(PIIX4PMState *s)
 419 {
 420     uint32_t pm_io_base;
 421
 422     if (s->dev.config[0x80] & 1) {
 423         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 424         pm_io_base &= 0xffc0;
 425
 426         /* XXX: need to improve memory and ioport allocation */
 427 #if defined(DEBUG)
 428         printf("PM: mapping to 0x%x\n", pm_io_base);
 429 #endif
 430         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 431         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 432         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 433         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 434     }
 435 }
 436
 437 static void pm_write_config(PCIDevice *d,
 438                             uint32_t address, uint32_t val, int len)
 439 {
 440     pci_default_write_config(d, address, val, len);
 441     if (address == 0x80)
 442         pm_io_space_update((PIIX4PMState *)d);
 443 }
 444
 445 static void pm_save(QEMUFile* f,void *opaque)
 446 {
 447     PIIX4PMState *s = opaque;
 448
 449     pci_device_save(&s->dev, f);
 450
 451     qemu_put_be16s(f, &s->pmsts);
 452     qemu_put_be16s(f, &s->pmen);
 453     qemu_put_be16s(f, &s->pmcntrl);
 454     qemu_put_8s(f, &s->apmc);
 455     qemu_put_8s(f, &s->apms);
 456     qemu_put_timer(f, s->tmr_timer);
 457     qemu_put_be64(f, s->tmr_overflow_time);
 458 }
 459
 460 static int pm_load(QEMUFile* f,void* opaque,int version_id)
 461 {
 462     PIIX4PMState *s = opaque;
 463     int ret;
 464
 465     if (version_id > 1)
 466         return -EINVAL;
 467
 468     ret = pci_device_load(&s->dev, f);
 469     if (ret < 0)
 470         return ret;
 471
 472     qemu_get_be16s(f, &s->pmsts);
 473     qemu_get_be16s(f, &s->pmen);
 474     qemu_get_be16s(f, &s->pmcntrl);
 475     qemu_get_8s(f, &s->apmc);
 476     qemu_get_8s(f, &s->apms);
 477     qemu_get_timer(f, s->tmr_timer);
 478     s->tmr_overflow_time=qemu_get_be64(f);
 479
 480     pm_io_space_update(s);
 481
 482     return 0;
 483 }
 484
 485 static void piix4_reset(void *opaque)
 486 {
 487     PIIX4PMState *s = opaque;
 488     uint8_t *pci_conf = s->dev.config;
 489
 490     pci_conf[0x58] = 0;
 491     pci_conf[0x59] = 0;
 492     pci_conf[0x5a] = 0;
 493     pci_conf[0x5b] = 0;
 494
 495     if (kvm_enabled()) {
 496         /* Mark SMM as already inited (until KVM supports SMM). */
 497         pci_conf[0x5B] = 0x02;
 498     }
 499 }
 500
 501 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 502                        qemu_irq sci_irq)
 503 {
 504     PIIX4PMState *s;
 505     uint8_t *pci_conf;
 506
 507     s = (PIIX4PMState *)pci_register_device(bus,
 508                                          "PM", sizeof(PIIX4PMState),
 509                                          devfn, NULL, pm_write_config);
 510     pm_state = s;
 511     pci_conf = s->dev.config;
 512     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 513     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 514     pci_conf[0x06] = 0x80;
 515     pci_conf[0x07] = 0x02;
 516     pci_conf[0x08] = 0x03; // revision number
 517     pci_conf[0x09] = 0x00;
 518     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 519     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 520     pci_conf[0x3d] = 0x01; // interrupt pin 1
 521
 522     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 523
 524 #if defined(TARGET_IA64)
 525     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 526     pci_conf[0x41] = 0x1f;
 527     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 528     s->pmcntrl = SCI_EN;
 529 #endif
 530
 531     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 532     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 533
 534     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 535
 536     if (kvm_enabled()) {
 537         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 538          * support SMM mode. */
 539         pci_conf[0x5B] = 0x02;
 540     }
 541
 542     /* XXX: which specification is used ? The i82731AB has different
 543        mappings */
 544     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 545     pci_conf[0x63] = 0x60;
 546     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 547         (serial_hds[1] != NULL ? 0x90 : 0);
 548
 549     pci_conf[0x90] = smb_io_base | 1;
 550     pci_conf[0x91] = smb_io_base >> 8;
 551     pci_conf[0xd2] = 0x09;
 552     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 553     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 554
 555     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 556
 557     register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
 558
 559     s->smbus = i2c_init_bus(NULL, "i2c");
 560     s->irq = sci_irq;
 561     qemu_register_reset(piix4_reset, s);
 562
 563     return s->smbus;
 564 }
 565
 566 #if defined(TARGET_I386)
 567 void qemu_system_powerdown(void)
 568 {
 569     if (!pm_state) {
 570         qemu_system_shutdown_request();
 571     } else if (pm_state->pmen & PWRBTN_EN) {
 572         pm_state->pmsts |= PWRBTN_EN;
 573         pm_update_sci(pm_state);
 574     }
 575 }
 576 #endif
 577
 578 #define GPE_BASE 0xafe0
 579 #define PROC_BASE 0xaf00
 580 #define PCI_BASE 0xae00
 581 #define PCI_EJ_BASE 0xae08
 582
 583 struct gpe_regs {
 584     uint16_t sts; /* status */
 585     uint16_t en;  /* enabled */
 586     uint8_t cpus_sts[32];
 587 };
 588
 589 struct pci_status {
 590     uint32_t up;
 591     uint32_t down;
 592 };
 593
 594 static struct gpe_regs gpe;
 595 static struct pci_status pci0_status;
 596
 597 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 598 {
 599     if (addr & 1)
 600         return (val >> 8) & 0xff;
 601     return val & 0xff;
 602 }
 603
 604 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 605 {
 606     uint32_t val = 0;
 607     struct gpe_regs *g = opaque;
 608     switch (addr) {
 609         case PROC_BASE ... PROC_BASE+31:
 610             val = g->cpus_sts[addr - PROC_BASE];
 611             break;
 612
 613         case GPE_BASE:
 614         case GPE_BASE + 1:
 615             val = gpe_read_val(g->sts, addr);
 616             break;
 617         case GPE_BASE + 2:
 618         case GPE_BASE + 3:
 619             val = gpe_read_val(g->en, addr);
 620             break;
 621         default:
 622             break;
 623     }
 624
 625 #if defined(DEBUG)
 626     printf("gpe read %x == %x\n", addr, val);
 627 #endif
 628     return val;
 629 }
 630
 631 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 632 {
 633     if (addr & 1)
 634         *cur = (*cur & 0xff) | (val << 8);
 635     else
 636         *cur = (*cur & 0xff00) | (val & 0xff);
 637 }
 638
 639 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 640 {
 641     uint16_t x1, x0 = val & 0xff;
 642     int shift = (addr & 1) ? 8 : 0;
 643
 644     x1 = (*cur >> shift) & 0xff;
 645
 646     x1 = x1 & ~x0;
 647
 648     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 649 }
 650
 651 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 652 {
 653     struct gpe_regs *g = opaque;
 654     switch (addr) {
 655         case PROC_BASE ... PROC_BASE + 31:
 656             /* don't allow to change cpus_sts from inside a guest */
 657             break;
 658
 659         case GPE_BASE:
 660         case GPE_BASE + 1:
 661             gpe_reset_val(&g->sts, addr, val);
 662             break;
 663         case GPE_BASE + 2:
 664         case GPE_BASE + 3:
 665             gpe_write_val(&g->en, addr, val);
 666             break;
 667         default:
 668             break;
 669    }
 670
 671 #if defined(DEBUG)
 672     printf("gpe write %x <== %d\n", addr, val);
 673 #endif
 674 }
 675
 676 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 677 {
 678     uint32_t val = 0;
 679     struct pci_status *g = opaque;
 680     switch (addr) {
 681         case PCI_BASE:
 682             val = g->up;
 683             break;
 684         case PCI_BASE + 4:
 685             val = g->down;
 686             break;
 687         default:
 688             break;
 689     }
 690
 691 #if defined(DEBUG)
 692     printf("pcihotplug read %x == %x\n", addr, val);
 693 #endif
 694     return val;
 695 }
 696
 697 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 698 {
 699     struct pci_status *g = opaque;
 700     switch (addr) {
 701         case PCI_BASE:
 702             g->up = val;
 703             break;
 704         case PCI_BASE + 4:
 705             g->down = val;
 706             break;
 707    }
 708
 709 #if defined(DEBUG)
 710     printf("pcihotplug write %x <== %d\n", addr, val);
 711 #endif
 712 }
 713
 714 static uint32_t pciej_read(void *opaque, uint32_t addr)
 715 {
 716 #if defined(DEBUG)
 717     printf("pciej read %x\n", addr);
 718 #endif
 719     return 0;
 720 }
 721
 722 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 723 {
 724 #if defined (TARGET_I386)
 725     int slot = ffs(val) - 1;
 726
 727     pci_device_hot_remove_success(0, slot);
 728 #endif
 729
 730 #if defined(DEBUG)
 731     printf("pciej write %x <== %d\n", addr, val);
 732 #endif
 733 }
 734
 735 static const char *model;
 736
 737 static void piix4_device_hot_add(int bus, int slot, int state);
 738
 739 void piix4_acpi_system_hot_add_init(const char *cpu_model)
 740 {
 741     int i = 0, cpus = smp_cpus;
 742
 743     while (cpus > 0) {
 744         gpe.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 745         cpus -= 8;
 746     }
 747     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 748     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 749
 750     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, &gpe);
 751     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, &gpe);
 752
 753     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 754     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 755
 756     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
 757     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, NULL);
 758
 759     model = cpu_model;
 760
 761     qemu_system_device_hot_add_register(piix4_device_hot_add);
 762 }
 763
 764 static void enable_processor(struct gpe_regs *g, int cpu)
 765 {
 766     g->sts |= 4;
 767     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 768 }
 769
 770 static void disable_processor(struct gpe_regs *g, int cpu)
 771 {
 772     g->sts |= 4;
 773     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 774 }
 775
 776 #if defined(TARGET_I386) || defined(TARGET_X86_64)
 777 void qemu_system_cpu_hot_add(int cpu, int state)
 778 {
 779     CPUState *env;
 780
 781     if (state && !qemu_get_cpu(cpu)) {
 782         env = pc_new_cpu(model);
 783         if (!env) {
 784             fprintf(stderr, "cpu %d creation failed\n", cpu);
 785             return;
 786         }
 787         env->cpuid_apic_id = cpu;
 788     }
 789
 790     if (state)
 791         enable_processor(&gpe, cpu);
 792     else
 793         disable_processor(&gpe, cpu);
 794     if (gpe.en & 4) {
 795         qemu_set_irq(pm_state->irq, 1);
 796         qemu_set_irq(pm_state->irq, 0);
 797     }
 798 }
 799 #endif
 800
 801 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 802 {
 803     g->sts |= 2;
 804     p->up |= (1 << slot);
 805 }
 806
 807 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 808 {
 809     g->sts |= 2;
 810     p->down |= (1 << slot);
 811 }
 812
 813 static void piix4_device_hot_add(int bus, int slot, int state)
 814 {
 815     pci0_status.up = 0;
 816     pci0_status.down = 0;
 817     if (state)
 818         enable_device(&pci0_status, &gpe, slot);
 819     else
 820         disable_device(&pci0_status, &gpe, slot);
 821     if (gpe.en & 2) {
 822         qemu_set_irq(pm_state->irq, 1);
 823         qemu_set_irq(pm_state->irq, 0);
 824     }
 825 }
 826
 827 static qemu_system_device_hot_add_t device_hot_add_callback;
 828 void qemu_system_device_hot_add_register(qemu_system_device_hot_add_t callback)
 829 {
 830     device_hot_add_callback = callback;
 831 }
 832
 833 void qemu_system_device_hot_add(int pcibus, int slot, int state)
 834 {
 835     if (device_hot_add_callback)
 836         device_hot_add_callback(pcibus, slot, state);
 837 }
 838
 839 struct acpi_table_header
 840 {
 841     char signature [4];    /* ACPI signature (4 ASCII characters) */
 842     uint32_t length;          /* Length of table, in bytes, including header */
 843     uint8_t revision;         /* ACPI Specification minor version # */
 844     uint8_t checksum;         /* To make sum of entire table == 0 */
 845     char oem_id [6];       /* OEM identification */
 846     char oem_table_id [8]; /* OEM table identification */
 847     uint32_t oem_revision;    /* OEM revision number */
 848     char asl_compiler_id [4]; /* ASL compiler vendor ID */
 849     uint32_t asl_compiler_revision; /* ASL compiler revision number */
 850 } __attribute__((packed));
 851
 852 char *acpi_tables;
 853 size_t acpi_tables_len;
 854
 855 static int acpi_checksum(const uint8_t *data, int len)
 856 {
 857     int sum, i;
 858     sum = 0;
 859     for(i = 0; i < len; i++)
 860         sum += data[i];
 861     return (-sum) & 0xff;
 862 }
 863
 864 int acpi_table_add(const char *t)
 865 {
 866     static const char *dfl_id = "QEMUQEMU";
 867     char buf[1024], *p, *f;
 868     struct acpi_table_header acpi_hdr;
 869     unsigned long val;
 870     size_t off;
 871
 872     memset(&acpi_hdr, 0, sizeof(acpi_hdr));
 873
 874     if (get_param_value(buf, sizeof(buf), "sig", t)) {
 875         strncpy(acpi_hdr.signature, buf, 4);
 876     } else {
 877         strncpy(acpi_hdr.signature, dfl_id, 4);
 878     }
 879     if (get_param_value(buf, sizeof(buf), "rev", t)) {
 880         val = strtoul(buf, &p, 10);
 881         if (val > 255 || *p != '\0')
 882             goto out;
 883     } else {
 884         val = 1;
 885     }
 886     acpi_hdr.revision = (int8_t)val;
 887
 888     if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
 889         strncpy(acpi_hdr.oem_id, buf, 6);
 890     } else {
 891         strncpy(acpi_hdr.oem_id, dfl_id, 6);
 892     }
 893
 894     if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
 895         strncpy(acpi_hdr.oem_table_id, buf, 8);
 896     } else {
 897         strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
 898     }
 899
 900     if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
 901         val = strtol(buf, &p, 10);
 902         if(*p != '\0')
 903             goto out;
 904     } else {
 905         val = 1;
 906     }
 907     acpi_hdr.oem_revision = cpu_to_le32(val);
 908
 909     if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
 910         strncpy(acpi_hdr.asl_compiler_id, buf, 4);
 911     } else {
 912         strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
 913     }
 914
 915     if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
 916         val = strtol(buf, &p, 10);
 917         if(*p != '\0')
 918             goto out;
 919     } else {
 920         val = 1;
 921     }
 922     acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
 923
 924     if (!get_param_value(buf, sizeof(buf), "data", t)) {
 925          buf[0] = '\0';
 926     }
 927
 928     acpi_hdr.length = sizeof(acpi_hdr);
 929
 930     f = buf;
 931     while (buf[0]) {
 932         struct stat s;
 933         char *n = strchr(f, ':');
 934         if (n)
 935             *n = '\0';
 936         if(stat(f, &s) < 0) {
 937             fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
 938             goto out;
 939         }
 940         acpi_hdr.length += s.st_size;
 941         if (!n)
 942             break;
 943         *n = ':';
 944         f = n + 1;
 945     }
 946
 947     if (!acpi_tables) {
 948         acpi_tables_len = sizeof(uint16_t);
 949         acpi_tables = qemu_mallocz(acpi_tables_len);
 950     }
 951     p = acpi_tables + acpi_tables_len;
 952     acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
 953     acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len);
 954
 955     acpi_hdr.length = cpu_to_le32(acpi_hdr.length);
 956     *(uint16_t*)p = acpi_hdr.length;
 957     p += sizeof(uint16_t);
 958     memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
 959     off = sizeof(acpi_hdr);
 960
 961     f = buf;
 962     while (buf[0]) {
 963         struct stat s;
 964         int fd;
 965         char *n = strchr(f, ':');
 966         if (n)
 967             *n = '\0';
 968         fd = open(f, O_RDONLY);
 969
 970         if(fd < 0)
 971             goto out;
 972         if(fstat(fd, &s) < 0) {
 973             close(fd);
 974             goto out;
 975         }
 976
 977         do {
 978             int r;
 979             r = read(fd, p + off, s.st_size);
 980             if (r > 0) {
 981                 off += r;
 982                 s.st_size -= r;
 983             } else if ((r < 0 && errno != EINTR) || r == 0) {
 984                 close(fd);
 985                 goto out;
 986             }
 987         } while(s.st_size);
 988
 989         close(fd);
 990         if (!n)
 991             break;
 992         f = n + 1;
 993     }
 994
 995     ((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
 996     /* increase number of tables */
 997     (*(uint16_t*)acpi_tables) =
 998             cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
 999     return 0;
1000 out:
1001     if (acpi_tables) {
1002         free(acpi_tables);
1003         acpi_tables = NULL;
1004     }
1005     return -1;
1006 }