target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ARM_H
  21 #define CPU_ARM_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define ELF_MACHINE     EM_ARM
  26
  27 #include "cpu-defs.h"
  28
  29 #include "softfloat.h"
  30
  31 #define TARGET_HAS_ICE 1
  32
  33 #define EXCP_UDEF            1   /* undefined instruction */
  34 #define EXCP_SWI             2   /* software interrupt */
  35 #define EXCP_PREFETCH_ABORT  3
  36 #define EXCP_DATA_ABORT      4
  37 #define EXCP_IRQ             5
  38 #define EXCP_FIQ             6
  39 #define EXCP_BKPT            7
  40 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  41 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  42
  43 #define ARMV7M_EXCP_RESET   1
  44 #define ARMV7M_EXCP_NMI     2
  45 #define ARMV7M_EXCP_HARD    3
  46 #define ARMV7M_EXCP_MEM     4
  47 #define ARMV7M_EXCP_BUS     5
  48 #define ARMV7M_EXCP_USAGE   6
  49 #define ARMV7M_EXCP_SVC     11
  50 #define ARMV7M_EXCP_DEBUG   12
  51 #define ARMV7M_EXCP_PENDSV  14
  52 #define ARMV7M_EXCP_SYSTICK 15
  53
  54 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  55                             int srcreg, int operand, uint32_t value);
  56 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  57                                int dstreg, int operand);
  58
  59 struct arm_boot_info;
  60
  61 #define NB_MMU_MODES 2
  62
  63 /* We currently assume float and double are IEEE single and double
  64    precision respectively.
  65    Doing runtime conversions is tricky because VFP registers may contain
  66    integer values (eg. as the result of a FTOSI instruction).
  67    s<2n> maps to the least significant half of d<n>
  68    s<2n+1> maps to the most significant half of d<n>
  69  */
  70
  71 typedef struct CPUARMState {
  72     /* Regs for current mode.  */
  73     uint32_t regs[16];
  74     /* Frequently accessed CPSR bits are stored separately for efficiently.
  75        This contains all the other bits.  Use cpsr_{read,write} to access
  76        the whole CPSR.  */
  77     uint32_t uncached_cpsr;
  78     uint32_t spsr;
  79
  80     /* Banked registers.  */
  81     uint32_t banked_spsr[6];
  82     uint32_t banked_r13[6];
  83     uint32_t banked_r14[6];
  84
  85     /* These hold r8-r12.  */
  86     uint32_t usr_regs[5];
  87     uint32_t fiq_regs[5];
  88
  89     /* cpsr flag cache for faster execution */
  90     uint32_t CF; /* 0 or 1 */
  91     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  92     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
  93     uint32_t ZF; /* Z set if zero.  */
  94     uint32_t QF; /* 0 or 1 */
  95     uint32_t GE; /* cpsr[19:16] */
  96     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
  97     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
  98
  99     /* System control coprocessor (cp15) */
 100     struct {
 101         uint32_t c0_cpuid;
 102         uint32_t c0_cachetype;
 103         uint32_t c0_c1[8]; /* Feature registers.  */
 104         uint32_t c0_c2[8]; /* Instruction set registers.  */
 105         uint32_t c1_sys; /* System control register.  */
 106         uint32_t c1_coproc; /* Coprocessor access register.  */
 107         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 108         uint32_t c2_base0; /* MMU translation table base 0.  */
 109         uint32_t c2_base1; /* MMU translation table base 1.  */
 110         uint32_t c2_mask; /* MMU translation table base mask.  */
 111         uint32_t c2_data; /* MPU data cachable bits.  */
 112         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 113         uint32_t c3; /* MMU domain access control register
 114                         MPU write buffer control.  */
 115         uint32_t c5_insn; /* Fault status registers.  */
 116         uint32_t c5_data;
 117         uint32_t c6_region[8]; /* MPU base/size registers.  */
 118         uint32_t c6_insn; /* Fault address registers.  */
 119         uint32_t c6_data;
 120         uint32_t c9_insn; /* Cache lockdown registers.  */
 121         uint32_t c9_data;
 122         uint32_t c13_fcse; /* FCSE PID.  */
 123         uint32_t c13_context; /* Context ID.  */
 124         uint32_t c13_tls1; /* User RW Thread register.  */
 125         uint32_t c13_tls2; /* User RO Thread register.  */
 126         uint32_t c13_tls3; /* Privileged Thread register.  */
 127         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 128         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 129         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 130         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 131         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 132     } cp15;
 133
 134     struct {
 135         uint32_t other_sp;
 136         uint32_t vecbase;
 137         uint32_t basepri;
 138         uint32_t control;
 139         int current_sp;
 140         int exception;
 141         int pending_exception;
 142         void *nvic;
 143     } v7m;
 144
 145     /* Coprocessor IO used by peripherals */
 146     struct {
 147         ARMReadCPFunc *cp_read;
 148         ARMWriteCPFunc *cp_write;
 149         void *opaque;
 150     } cp[15];
 151
 152     /* Internal CPU feature flags.  */
 153     uint32_t features;
 154
 155     /* Callback for vectored interrupt controller.  */
 156     int (*get_irq_vector)(struct CPUARMState *);
 157     void *irq_opaque;
 158
 159     /* exception/interrupt handling */
 160     int interrupt_request;
 161     int user_mode_only;
 162
 163     /* VFP coprocessor state.  */
 164     struct {
 165         float64 regs[32];
 166
 167         uint32_t xregs[16];
 168         /* We store these fpcsr fields separately for convenience.  */
 169         int vec_len;
 170         int vec_stride;
 171
 172         /* scratch space when Tn are not sufficient.  */
 173         uint32_t scratch[8];
 174
 175         float_status fp_status;
 176     } vfp;
 177 #if defined(CONFIG_USER_ONLY)
 178     struct mmon_state *mmon_entry;
 179 #else
 180     uint32_t mmon_addr;
 181 #endif
 182
 183     /* iwMMXt coprocessor state.  */
 184     struct {
 185         uint64_t regs[16];
 186         uint64_t val;
 187
 188         uint32_t cregs[16];
 189     } iwmmxt;
 190
 191 #if defined(CONFIG_USER_ONLY)
 192     /* For usermode syscall translation.  */
 193     int eabi;
 194 #endif
 195
 196     CPU_COMMON
 197
 198     /* These fields after the common ones so they are preserved on reset.  */
 199     struct arm_boot_info *boot_info;
 200 } CPUARMState;
 201
 202 CPUARMState *cpu_arm_init(const char *cpu_model);
 203 void arm_translate_init(void);
 204 int cpu_arm_exec(CPUARMState *s);
 205 void cpu_arm_close(CPUARMState *s);
 206 void do_interrupt(CPUARMState *);
 207 void switch_mode(CPUARMState *, int);
 208 uint32_t do_arm_semihosting(CPUARMState *env);
 209
 210 /* you can call this signal handler from your SIGBUS and SIGSEGV
 211    signal handlers to inform the virtual CPU of exceptions. non zero
 212    is returned if the signal was handled by the virtual CPU.  */
 213 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 214                            void *puc);
 215
 216 void cpu_lock(void);
 217 void cpu_unlock(void);
 218 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 219 {
 220   env->cp15.c13_tls2 = newtls;
 221 }
 222
 223 #define CPSR_M (0x1f)
 224 #define CPSR_T (1 << 5)
 225 #define CPSR_F (1 << 6)
 226 #define CPSR_I (1 << 7)
 227 #define CPSR_A (1 << 8)
 228 #define CPSR_E (1 << 9)
 229 #define CPSR_IT_2_7 (0xfc00)
 230 #define CPSR_GE (0xf << 16)
 231 #define CPSR_RESERVED (0xf << 20)
 232 #define CPSR_J (1 << 24)
 233 #define CPSR_IT_0_1 (3 << 25)
 234 #define CPSR_Q (1 << 27)
 235 #define CPSR_V (1 << 28)
 236 #define CPSR_C (1 << 29)
 237 #define CPSR_Z (1 << 30)
 238 #define CPSR_N (1 << 31)
 239 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 240
 241 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 242 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 243 /* Bits writable in user mode.  */
 244 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 245 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 246 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 247
 248 /* Return the current CPSR value.  */
 249 uint32_t cpsr_read(CPUARMState *env);
 250 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 251 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 252
 253 /* Return the current xPSR value.  */
 254 static inline uint32_t xpsr_read(CPUARMState *env)
 255 {
 256     int ZF;
 257     ZF = (env->ZF == 0);
 258     return (env->NF & 0x80000000) | (ZF << 30)
 259         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 260         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 261         | ((env->condexec_bits & 0xfc) << 8)
 262         | env->v7m.exception;
 263 }
 264
 265 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 266 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 267 {
 268     if (mask & CPSR_NZCV) {
 269         env->ZF = (~val) & CPSR_Z;
 270         env->NF = val;
 271         env->CF = (val >> 29) & 1;
 272         env->VF = (val << 3) & 0x80000000;
 273     }
 274     if (mask & CPSR_Q)
 275         env->QF = ((val & CPSR_Q) != 0);
 276     if (mask & (1 << 24))
 277         env->thumb = ((val & (1 << 24)) != 0);
 278     if (mask & CPSR_IT_0_1) {
 279         env->condexec_bits &= ~3;
 280         env->condexec_bits |= (val >> 25) & 3;
 281     }
 282     if (mask & CPSR_IT_2_7) {
 283         env->condexec_bits &= 3;
 284         env->condexec_bits |= (val >> 8) & 0xfc;
 285     }
 286     if (mask & 0x1ff) {
 287         env->v7m.exception = val & 0x1ff;
 288     }
 289 }
 290
 291 enum arm_cpu_mode {
 292   ARM_CPU_MODE_USR = 0x10,
 293   ARM_CPU_MODE_FIQ = 0x11,
 294   ARM_CPU_MODE_IRQ = 0x12,
 295   ARM_CPU_MODE_SVC = 0x13,
 296   ARM_CPU_MODE_ABT = 0x17,
 297   ARM_CPU_MODE_UND = 0x1b,
 298   ARM_CPU_MODE_SYS = 0x1f
 299 };
 300
 301 /* VFP system registers.  */
 302 #define ARM_VFP_FPSID   0
 303 #define ARM_VFP_FPSCR   1
 304 #define ARM_VFP_MVFR1   6
 305 #define ARM_VFP_MVFR0   7
 306 #define ARM_VFP_FPEXC   8
 307 #define ARM_VFP_FPINST  9
 308 #define ARM_VFP_FPINST2 10
 309
 310 /* iwMMXt coprocessor control registers.  */
 311 #define ARM_IWMMXT_wCID         0
 312 #define ARM_IWMMXT_wCon         1
 313 #define ARM_IWMMXT_wCSSF        2
 314 #define ARM_IWMMXT_wCASF        3
 315 #define ARM_IWMMXT_wCGR0        8
 316 #define ARM_IWMMXT_wCGR1        9
 317 #define ARM_IWMMXT_wCGR2        10
 318 #define ARM_IWMMXT_wCGR3        11
 319
 320 enum arm_features {
 321     ARM_FEATURE_VFP,
 322     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 323     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 324     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 325     ARM_FEATURE_V6,
 326     ARM_FEATURE_V6K,
 327     ARM_FEATURE_V7,
 328     ARM_FEATURE_THUMB2,
 329     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 330     ARM_FEATURE_VFP3,
 331     ARM_FEATURE_NEON,
 332     ARM_FEATURE_DIV,
 333     ARM_FEATURE_M, /* Microcontroller profile.  */
 334     ARM_FEATURE_OMAPCP  /* OMAP specific CP15 ops handling.  */
 335 };
 336
 337 static inline int arm_feature(CPUARMState *env, int feature)
 338 {
 339     return (env->features & (1u << feature)) != 0;
 340 }
 341
 342 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 343
 344 /* Interface between CPU and Interrupt controller.  */
 345 void armv7m_nvic_set_pending(void *opaque, int irq);
 346 int armv7m_nvic_acknowledge_irq(void *opaque);
 347 void armv7m_nvic_complete_irq(void *opaque, int irq);
 348
 349 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 350                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 351                        void *opaque);
 352
 353 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 354    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 355    conventional cores (ie. Application or Realtime profile).  */
 356
 357 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 358 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
 359
 360 #define ARM_CPUID_ARM1026     0x4106a262
 361 #define ARM_CPUID_ARM926      0x41069265
 362 #define ARM_CPUID_ARM946      0x41059461
 363 #define ARM_CPUID_TI915T      0x54029152
 364 #define ARM_CPUID_TI925T      0x54029252
 365 #define ARM_CPUID_PXA250      0x69052100
 366 #define ARM_CPUID_PXA255      0x69052d00
 367 #define ARM_CPUID_PXA260      0x69052903
 368 #define ARM_CPUID_PXA261      0x69052d05
 369 #define ARM_CPUID_PXA262      0x69052d06
 370 #define ARM_CPUID_PXA270      0x69054110
 371 #define ARM_CPUID_PXA270_A0   0x69054110
 372 #define ARM_CPUID_PXA270_A1   0x69054111
 373 #define ARM_CPUID_PXA270_B0   0x69054112
 374 #define ARM_CPUID_PXA270_B1   0x69054113
 375 #define ARM_CPUID_PXA270_C0   0x69054114
 376 #define ARM_CPUID_PXA270_C5   0x69054117
 377 #define ARM_CPUID_ARM1136     0x4117b363
 378 #define ARM_CPUID_ARM1136_R2  0x4107b362
 379 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 380 #define ARM_CPUID_CORTEXA8    0x410fc080
 381 #define ARM_CPUID_CORTEXM3    0x410fc231
 382 #define ARM_CPUID_ANY         0xffffffff
 383
 384 #if defined(CONFIG_USER_ONLY)
 385 #define TARGET_PAGE_BITS 12
 386 #else
 387 /* The ARM MMU allows 1k pages.  */
 388 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 389    architecture revisions.  Maybe a configure option to disable them.  */
 390 #define TARGET_PAGE_BITS 10
 391 #endif
 392
 393 #define CPUState CPUARMState
 394 #define cpu_init cpu_arm_init
 395 #define cpu_exec cpu_arm_exec
 396 #define cpu_gen_code cpu_arm_gen_code
 397 #define cpu_signal_handler cpu_arm_signal_handler
 398 #define cpu_list arm_cpu_list
 399
 400 #define ARM_CPU_SAVE_VERSION 1
 401
 402 /* MMU modes definitions */
 403 #define MMU_MODE0_SUFFIX _kernel
 404 #define MMU_MODE1_SUFFIX _user
 405 #define MMU_USER_IDX 1
 406 static inline int cpu_mmu_index (CPUState *env)
 407 {
 408     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 409 }
 410
 411 #if defined(CONFIG_USER_ONLY)
 412 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 413 {
 414     if (newsp)
 415         env->regs[13] = newsp;
 416     env->regs[0] = 0;
 417 }
 418 #endif
 419
 420 #include "cpu-all.h"
 421
 422 #endif