hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28
  29 #include "qemu-kvm.h"
  30
  31 typedef uint32_t pci_addr_t;
  32 #include "pci_host.h"
  33
  34 typedef PCIHostState I440FXState;
  35
  36 static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
  37 {
  38     I440FXState *s = opaque;
  39     s->config_reg = val;
  40 }
  41
  42 static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
  43 {
  44     I440FXState *s = opaque;
  45     return s->config_reg;
  46 }
  47
  48 static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);
  49
  50 /* return the global irq number corresponding to a given device irq
  51    pin. We could also use the bus number to have a more precise
  52    mapping. */
  53 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
  54 {
  55     int slot_addend;
  56     slot_addend = (pci_dev->devfn >> 3) - 1;
  57     return (irq_num + slot_addend) & 3;
  58 }
  59
  60 static target_phys_addr_t isa_page_descs[384 / 4];
  61 static uint8_t smm_enabled;
  62 static int pci_irq_levels[4];
  63
  64 static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
  65 {
  66     uint32_t addr;
  67
  68     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  69     switch(r) {
  70     case 3:
  71         /* RAM */
  72         cpu_register_physical_memory(start, end - start,
  73                                      start);
  74         break;
  75     case 1:
  76         /* ROM (XXX: not quite correct) */
  77         cpu_register_physical_memory(start, end - start,
  78                                      start | IO_MEM_ROM);
  79         break;
  80     case 2:
  81     case 0:
  82         /* XXX: should distinguish read/write cases */
  83         for(addr = start; addr < end; addr += 4096) {
  84             cpu_register_physical_memory(addr, 4096,
  85                                          isa_page_descs[(addr - 0xa0000) >> 12]);
  86         }
  87         break;
  88     }
  89 }
  90
  91 static void i440fx_update_memory_mappings(PCIDevice *d)
  92 {
  93     int i, r;
  94     uint32_t smram, addr;
  95
  96     if (kvm_enabled()) {
  97         /* FIXME: Support remappings and protection changes. */
  98         return;
  99     }
 100     update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
 101     for(i = 0; i < 12; i++) {
 102         r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
 103         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 104     }
 105     smram = d->config[0x72];
 106     if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 107         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 108     } else {
 109         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 110             cpu_register_physical_memory(addr, 4096,
 111                                          isa_page_descs[(addr - 0xa0000) >> 12]);
 112         }
 113     }
 114 }
 115
 116 void i440fx_set_smm(PCIDevice *d, int val)
 117 {
 118     val = (val != 0);
 119     if (smm_enabled != val) {
 120         smm_enabled = val;
 121         i440fx_update_memory_mappings(d);
 122     }
 123 }
 124
 125
 126 /* XXX: suppress when better memory API. We make the assumption that
 127    no device (in particular the VGA) changes the memory mappings in
 128    the 0xa0000-0x100000 range */
 129 void i440fx_init_memory_mappings(PCIDevice *d)
 130 {
 131     int i;
 132     for(i = 0; i < 96; i++) {
 133         isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 134     }
 135 }
 136
 137 static void i440fx_write_config(PCIDevice *d,
 138                                 uint32_t address, uint32_t val, int len)
 139 {
 140     /* XXX: implement SMRAM.D_LOCK */
 141     pci_default_write_config(d, address, val, len);
 142     if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
 143         i440fx_update_memory_mappings(d);
 144 }
 145
 146 static void i440fx_save(QEMUFile* f, void *opaque)
 147 {
 148     PCIDevice *d = opaque;
 149     int i;
 150
 151     pci_device_save(d, f);
 152     qemu_put_8s(f, &smm_enabled);
 153
 154     for (i = 0; i < 4; i++)
 155         qemu_put_be32(f, pci_irq_levels[i]);
 156 }
 157
 158 static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
 159 {
 160     PCIDevice *d = opaque;
 161     int ret, i;
 162
 163     if (version_id > 2)
 164         return -EINVAL;
 165     ret = pci_device_load(d, f);
 166     if (ret < 0)
 167         return ret;
 168     i440fx_update_memory_mappings(d);
 169     qemu_get_8s(f, &smm_enabled);
 170
 171     if (version_id >= 2)
 172         for (i = 0; i < 4; i++)
 173             pci_irq_levels[i] = qemu_get_be32(f);
 174
 175     return 0;
 176 }
 177
 178 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
 179 {
 180     PCIBus *b;
 181     PCIDevice *d;
 182     I440FXState *s;
 183
 184     s = qemu_mallocz(sizeof(I440FXState));
 185     b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
 186     s->bus = b;
 187
 188     register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
 189     register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
 190
 191     register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
 192     register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
 193     register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
 194     register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
 195     register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
 196     register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
 197
 198     d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
 199                             NULL, i440fx_write_config);
 200
 201     d->config[0x00] = 0x86; // vendor_id
 202     d->config[0x01] = 0x80;
 203     d->config[0x02] = 0x37; // device_id
 204     d->config[0x03] = 0x12;
 205     d->config[0x08] = 0x02; // revision
 206     d->config[0x0a] = 0x00; // class_sub = host2pci
 207     d->config[0x0b] = 0x06; // class_base = PCI_bridge
 208     d->config[0x0e] = 0x00; // header_type
 209
 210     d->config[0x72] = 0x02; /* SMRAM */
 211
 212     register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
 213     *pi440fx_state = d;
 214     return b;
 215 }
 216
 217 /* PIIX3 PCI to ISA bridge */
 218
 219 static PCIDevice *piix3_dev;
 220 PCIDevice *piix4_dev;
 221
 222 /* just used for simpler irq handling. */
 223 #define PCI_IRQ_WORDS   ((PCI_DEVICES_MAX + 31) / 32)
 224
 225 static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
 226 {
 227     int i, pic_irq, pic_level;
 228
 229     pci_irq_levels[irq_num] = level;
 230
 231     /* now we change the pic irq level according to the piix irq mappings */
 232     /* XXX: optimize */
 233     pic_irq = piix3_dev->config[0x60 + irq_num];
 234     if (pic_irq < 16) {
 235         /* The pic level is the logical OR of all the PCI irqs mapped
 236            to it */
 237         pic_level = 0;
 238         for (i = 0; i < 4; i++) {
 239             if (pic_irq == piix3_dev->config[0x60 + i])
 240                 pic_level |= pci_irq_levels[i];
 241         }
 242         qemu_set_irq(pic[pic_irq], pic_level);
 243     }
 244 }
 245
 246 int piix_get_irq(int pin)
 247 {
 248     if (piix3_dev)
 249         return piix3_dev->config[0x60+pin];
 250     if (piix4_dev)
 251         return piix4_dev->config[0x60+pin];
 252
 253     return 0;
 254 }
 255
 256 static void piix3_reset(PCIDevice *d)
 257 {
 258     uint8_t *pci_conf = d->config;
 259
 260     pci_conf[0x04] = 0x07; // master, memory and I/O
 261     pci_conf[0x05] = 0x00;
 262     pci_conf[0x06] = 0x00;
 263     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 264     pci_conf[0x4c] = 0x4d;
 265     pci_conf[0x4e] = 0x03;
 266     pci_conf[0x4f] = 0x00;
 267     pci_conf[0x60] = 0x80;
 268     pci_conf[0x61] = 0x80;
 269     pci_conf[0x62] = 0x80;
 270     pci_conf[0x63] = 0x80;
 271     pci_conf[0x69] = 0x02;
 272     pci_conf[0x70] = 0x80;
 273     pci_conf[0x76] = 0x0c;
 274     pci_conf[0x77] = 0x0c;
 275     pci_conf[0x78] = 0x02;
 276     pci_conf[0x79] = 0x00;
 277     pci_conf[0x80] = 0x00;
 278     pci_conf[0x82] = 0x00;
 279     pci_conf[0xa0] = 0x08;
 280     pci_conf[0xa2] = 0x00;
 281     pci_conf[0xa3] = 0x00;
 282     pci_conf[0xa4] = 0x00;
 283     pci_conf[0xa5] = 0x00;
 284     pci_conf[0xa6] = 0x00;
 285     pci_conf[0xa7] = 0x00;
 286     pci_conf[0xa8] = 0x0f;
 287     pci_conf[0xaa] = 0x00;
 288     pci_conf[0xab] = 0x00;
 289     pci_conf[0xac] = 0x00;
 290     pci_conf[0xae] = 0x00;
 291 }
 292
 293 static void piix4_reset(PCIDevice *d)
 294 {
 295     uint8_t *pci_conf = d->config;
 296
 297     pci_conf[0x04] = 0x07; // master, memory and I/O
 298     pci_conf[0x05] = 0x00;
 299     pci_conf[0x06] = 0x00;
 300     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 301     pci_conf[0x4c] = 0x4d;
 302     pci_conf[0x4e] = 0x03;
 303     pci_conf[0x4f] = 0x00;
 304     pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
 305     pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
 306     pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
 307     pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
 308     pci_conf[0x69] = 0x02;
 309     pci_conf[0x70] = 0x80;
 310     pci_conf[0x76] = 0x0c;
 311     pci_conf[0x77] = 0x0c;
 312     pci_conf[0x78] = 0x02;
 313     pci_conf[0x79] = 0x00;
 314     pci_conf[0x80] = 0x00;
 315     pci_conf[0x82] = 0x00;
 316     pci_conf[0xa0] = 0x08;
 317     pci_conf[0xa2] = 0x00;
 318     pci_conf[0xa3] = 0x00;
 319     pci_conf[0xa4] = 0x00;
 320     pci_conf[0xa5] = 0x00;
 321     pci_conf[0xa6] = 0x00;
 322     pci_conf[0xa7] = 0x00;
 323     pci_conf[0xa8] = 0x0f;
 324     pci_conf[0xaa] = 0x00;
 325     pci_conf[0xab] = 0x00;
 326     pci_conf[0xac] = 0x00;
 327     pci_conf[0xae] = 0x00;
 328 }
 329
 330 static void piix_save(QEMUFile* f, void *opaque)
 331 {
 332     PCIDevice *d = opaque;
 333     pci_device_save(d, f);
 334 }
 335
 336 static int piix_load(QEMUFile* f, void *opaque, int version_id)
 337 {
 338     PCIDevice *d = opaque;
 339     if (version_id != 2)
 340         return -EINVAL;
 341     return pci_device_load(d, f);
 342 }
 343
 344 int piix3_init(PCIBus *bus, int devfn)
 345 {
 346     PCIDevice *d;
 347     uint8_t *pci_conf;
 348
 349     d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice),
 350                                     devfn, NULL, NULL);
 351     register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
 352
 353     piix3_dev = d;
 354     pci_conf = d->config;
 355
 356     pci_conf[0x00] = 0x86; // Intel
 357     pci_conf[0x01] = 0x80;
 358     pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 359     pci_conf[0x03] = 0x70;
 360     pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
 361     pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
 362     pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
 363
 364     piix3_reset(d);
 365     return d->devfn;
 366 }
 367
 368 int piix4_init(PCIBus *bus, int devfn)
 369 {
 370     PCIDevice *d;
 371     uint8_t *pci_conf;
 372
 373     d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice),
 374                                     devfn, NULL, NULL);
 375     register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
 376
 377     piix4_dev = d;
 378     pci_conf = d->config;
 379
 380     pci_conf[0x00] = 0x86; // Intel
 381     pci_conf[0x01] = 0x80;
 382     pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
 383     pci_conf[0x03] = 0x71;
 384     pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
 385     pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
 386     pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
 387
 388     piix4_reset(d);
 389     return d->devfn;
 390 }