Clean up KVM/QEMU interaction
[qemu-kvm/fedora.git] / qemu-kvm-powerpc.c
blob5cd6acf6099b08d4e53e0413756f1621be5d05da
2 #include "config.h"
3 #include "config-host.h"
5 #include <string.h>
6 #include "hw/hw.h"
7 #include "sysemu.h"
8 #include "cpu.h"
9 #include "helper_regs.h"
11 #include "qemu-kvm.h"
12 #include <libkvm.h>
13 #include <pthread.h>
14 #include <sys/utsname.h>
16 extern kvm_context_t kvm_context;
18 void cpu_reset(CPUState *env)
20 cpu_ppc_reset(env);
24 int kvm_arch_qemu_create_context(void)
26 return 0;
29 void kvm_arch_load_regs(CPUState *env)
31 struct kvm_regs regs;
32 int rc,i;
34 rc = kvm_get_regs(kvm_context, env->cpu_index, &regs);
35 if (rc == -1)
36 perror("kvm_get_regs FAILED");
38 /* cr is untouched in qemu and not existant in CPUState fr ppr */
39 /* hflags is a morphed to MSR on ppc, no need to sync that down to kvm */
41 regs.pc = env->nip;
43 regs.ctr = env->ctr;
44 regs.lr = env->lr;
45 regs.xer = ppc_load_xer(env);
46 regs.msr = env->msr;
48 regs.srr0 = env->spr[SPR_SRR0];
49 regs.srr1 = env->spr[SPR_SRR1];
51 regs.sprg0 = env->spr[SPR_SPRG0];
52 regs.sprg1 = env->spr[SPR_SPRG1];
53 regs.sprg2 = env->spr[SPR_SPRG2];
54 regs.sprg3 = env->spr[SPR_SPRG3];
55 regs.sprg4 = env->spr[SPR_SPRG4];
56 regs.sprg5 = env->spr[SPR_SPRG5];
57 regs.sprg6 = env->spr[SPR_SPRG6];
58 regs.sprg7 = env->spr[SPR_SPRG7];
60 for (i = 0;i < 32; i++){
61 regs.gpr[i] = env->gpr[i];
62 regs.fpr[i] = env->fpr[i];
65 rc = kvm_set_regs(kvm_context, env->cpu_index, &regs);
66 if (rc == -1)
67 perror("kvm_set_regs FAILED");
71 void kvm_arch_save_regs(CPUState *env)
73 struct kvm_regs regs;
74 uint32_t i, rc;
76 rc = kvm_get_regs(kvm_context, env->cpu_index, &regs);
77 if (rc == -1)
78 perror("kvm_get_regs FAILED");
80 env->ctr =regs.ctr;
81 env->lr = regs.lr;
82 ppc_store_xer(env,regs.xer);
83 env->msr = regs.msr;
84 /* calculate hflags based on the current msr using the ppc qemu helper */
85 hreg_compute_hflags(env);
87 env->nip = regs.pc;
89 env->spr[SPR_SRR0] = regs.srr0;
90 env->spr[SPR_SRR1] = regs.srr1;
92 env->spr[SPR_SPRG0] = regs.sprg0;
93 env->spr[SPR_SPRG1] = regs.sprg1;
94 env->spr[SPR_SPRG2] = regs.sprg2;
95 env->spr[SPR_SPRG3] = regs.sprg3;
96 env->spr[SPR_SPRG4] = regs.sprg4;
97 env->spr[SPR_SPRG5] = regs.sprg5;
98 env->spr[SPR_SPRG6] = regs.sprg6;
99 env->spr[SPR_SPRG7] = regs.sprg7;
101 for (i = 0;i < 32; i++){
102 env->gpr[i] = regs.gpr[i];
103 env->fpr[i] = regs.fpr[i];
108 int kvm_arch_qemu_init_env(CPUState *cenv)
110 return 0;
113 int kvm_arch_halt(void *opaque, int vcpu)
115 CPUState *env = cpu_single_env;
117 if (!(env->interrupt_request & CPU_INTERRUPT_HARD)
118 && (msr_ee))
120 env->halted = 1;
121 env->exception_index = EXCP_HLT;
123 return 1;
126 void kvm_arch_pre_kvm_run(void *opaque, int vcpu)
128 return;
131 void kvm_arch_post_kvm_run(void *opaque, int vcpu)
133 CPUState *env = qemu_kvm_cpu_env(vcpu);
134 cpu_single_env = env;
135 env->ready_for_interrupt_injection = \
136 kvm_is_ready_for_interrupt_injection(kvm_context, vcpu);
139 int kvm_arch_has_work(CPUState *env)
141 if ((env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT)) &&
142 (msr_ee))
143 return 1;
144 return 0;
147 int kvm_arch_try_push_interrupts(void *opaque)
149 CPUState *env = cpu_single_env;
150 int r;
151 unsigned irq;
153 if (env->ready_for_interrupt_injection &&
154 (env->interrupt_request & CPU_INTERRUPT_HARD))
156 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
158 /* For now KVM disregards the 'irq' argument. However, in the
159 * future KVM could cache it in-kernel to avoid a heavyweight exit
160 * when reading the UIC.
162 irq = -1U;
164 r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
165 if (r < 0)
166 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
169 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
172 void kvm_arch_update_regs_for_sipi(CPUState *env)
174 printf("%s: no kvm-powerpc multi processor support yet!\n", __func__);
177 /* map dcr access to existing qemu dcr emulation */
178 int handle_powerpc_dcr_read(int vcpu, uint32_t dcrn, uint32_t *data)
180 CPUState *env = cpu_single_env;
181 ppc_dcr_read(env->dcr_env, dcrn, data);
182 return 0; /* XXX ignore failed DCR ops */
185 int handle_powerpc_dcr_write(int vcpu, uint32_t dcrn, uint32_t data)
187 CPUState *env = cpu_single_env;
188 ppc_dcr_write(env->dcr_env, dcrn, data);
189 return 0; /* XXX ignore failed DCR ops */