2 * PowerPC CPU initialization for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DEBUG_IRQ
33 const unsigned char *name
;
43 void (*init_proc
)(CPUPPCState
*env
);
46 /* For user-mode emulation, we don't emulate any IRQ controller */
47 #if defined(CONFIG_USER_ONLY)
48 #define PPC_IRQ_INIT_FN(name) \
49 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
53 #define PPC_IRQ_INIT_FN(name) \
54 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
62 * do nothing but store/retrieve spr value
64 #ifdef PPC_DUMP_SPR_ACCESSES
65 static void spr_read_generic (void *opaque
, int sprn
)
67 gen_op_load_dump_spr(sprn
);
70 static void spr_write_generic (void *opaque
, int sprn
)
72 gen_op_store_dump_spr(sprn
);
75 static void spr_read_generic (void *opaque
, int sprn
)
77 gen_op_load_spr(sprn
);
80 static void spr_write_generic (void *opaque
, int sprn
)
82 gen_op_store_spr(sprn
);
86 #if !defined(CONFIG_USER_ONLY)
87 static void spr_write_clear (void *opaque
, int sprn
)
89 gen_op_mask_spr(sprn
);
93 /* SPR common to all PowerPC */
95 static void spr_read_xer (void *opaque
, int sprn
)
100 static void spr_write_xer (void *opaque
, int sprn
)
106 static void spr_read_lr (void *opaque
, int sprn
)
111 static void spr_write_lr (void *opaque
, int sprn
)
117 static void spr_read_ctr (void *opaque
, int sprn
)
122 static void spr_write_ctr (void *opaque
, int sprn
)
127 /* User read access to SPR */
133 static void spr_read_ureg (void *opaque
, int sprn
)
135 gen_op_load_spr(sprn
+ 0x10);
138 /* SPR common to all non-embedded PowerPC */
140 #if !defined(CONFIG_USER_ONLY)
141 static void spr_read_decr (void *opaque
, int sprn
)
146 static void spr_write_decr (void *opaque
, int sprn
)
152 /* SPR common to all non-embedded PowerPC, except 601 */
154 static void spr_read_tbl (void *opaque
, int sprn
)
159 static void spr_read_tbu (void *opaque
, int sprn
)
164 __attribute__ (( unused
))
165 static void spr_read_atbl (void *opaque
, int sprn
)
170 __attribute__ (( unused
))
171 static void spr_read_atbu (void *opaque
, int sprn
)
176 #if !defined(CONFIG_USER_ONLY)
177 static void spr_write_tbl (void *opaque
, int sprn
)
182 static void spr_write_tbu (void *opaque
, int sprn
)
187 __attribute__ (( unused
))
188 static void spr_write_atbl (void *opaque
, int sprn
)
193 __attribute__ (( unused
))
194 static void spr_write_atbu (void *opaque
, int sprn
)
200 #if !defined(CONFIG_USER_ONLY)
201 /* IBAT0U...IBAT0U */
202 /* IBAT0L...IBAT7L */
203 static void spr_read_ibat (void *opaque
, int sprn
)
205 gen_op_load_ibat(sprn
& 1, (sprn
- SPR_IBAT0U
) / 2);
208 static void spr_read_ibat_h (void *opaque
, int sprn
)
210 gen_op_load_ibat(sprn
& 1, (sprn
- SPR_IBAT4U
) / 2);
213 static void spr_write_ibatu (void *opaque
, int sprn
)
215 gen_op_store_ibatu((sprn
- SPR_IBAT0U
) / 2);
218 static void spr_write_ibatu_h (void *opaque
, int sprn
)
220 gen_op_store_ibatu((sprn
- SPR_IBAT4U
) / 2);
223 static void spr_write_ibatl (void *opaque
, int sprn
)
225 gen_op_store_ibatl((sprn
- SPR_IBAT0L
) / 2);
228 static void spr_write_ibatl_h (void *opaque
, int sprn
)
230 gen_op_store_ibatl((sprn
- SPR_IBAT4L
) / 2);
233 /* DBAT0U...DBAT7U */
234 /* DBAT0L...DBAT7L */
235 static void spr_read_dbat (void *opaque
, int sprn
)
237 gen_op_load_dbat(sprn
& 1, (sprn
- SPR_DBAT0U
) / 2);
240 static void spr_read_dbat_h (void *opaque
, int sprn
)
242 gen_op_load_dbat(sprn
& 1, (sprn
- SPR_DBAT4U
) / 2);
245 static void spr_write_dbatu (void *opaque
, int sprn
)
247 gen_op_store_dbatu((sprn
- SPR_DBAT0U
) / 2);
250 static void spr_write_dbatu_h (void *opaque
, int sprn
)
252 gen_op_store_dbatu((sprn
- SPR_DBAT4U
) / 2);
255 static void spr_write_dbatl (void *opaque
, int sprn
)
257 gen_op_store_dbatl((sprn
- SPR_DBAT0L
) / 2);
260 static void spr_write_dbatl_h (void *opaque
, int sprn
)
262 gen_op_store_dbatl((sprn
- SPR_DBAT4L
) / 2);
266 static void spr_read_sdr1 (void *opaque
, int sprn
)
271 static void spr_write_sdr1 (void *opaque
, int sprn
)
276 /* 64 bits PowerPC specific SPRs */
278 #if defined(TARGET_PPC64)
279 __attribute__ (( unused
))
280 static void spr_read_asr (void *opaque
, int sprn
)
285 __attribute__ (( unused
))
286 static void spr_write_asr (void *opaque
, int sprn
)
293 /* PowerPC 601 specific registers */
295 static void spr_read_601_rtcl (void *opaque
, int sprn
)
297 gen_op_load_601_rtcl();
300 static void spr_read_601_rtcu (void *opaque
, int sprn
)
302 gen_op_load_601_rtcu();
305 #if !defined(CONFIG_USER_ONLY)
306 static void spr_write_601_rtcu (void *opaque
, int sprn
)
308 gen_op_store_601_rtcu();
311 static void spr_write_601_rtcl (void *opaque
, int sprn
)
313 gen_op_store_601_rtcl();
318 #if !defined(CONFIG_USER_ONLY)
319 static void spr_read_601_ubat (void *opaque
, int sprn
)
321 gen_op_load_601_bat(sprn
& 1, (sprn
- SPR_IBAT0U
) / 2);
324 static void spr_write_601_ubatu (void *opaque
, int sprn
)
326 gen_op_store_601_batu((sprn
- SPR_IBAT0U
) / 2);
329 static void spr_write_601_ubatl (void *opaque
, int sprn
)
331 gen_op_store_601_batl((sprn
- SPR_IBAT0L
) / 2);
335 /* PowerPC 40x specific registers */
336 #if !defined(CONFIG_USER_ONLY)
337 static void spr_read_40x_pit (void *opaque
, int sprn
)
339 gen_op_load_40x_pit();
342 static void spr_write_40x_pit (void *opaque
, int sprn
)
344 gen_op_store_40x_pit();
347 static void spr_write_40x_dbcr0 (void *opaque
, int sprn
)
349 DisasContext
*ctx
= opaque
;
351 gen_op_store_40x_dbcr0();
352 /* We must stop translation as we may have rebooted */
356 static void spr_write_40x_sler (void *opaque
, int sprn
)
358 gen_op_store_40x_sler();
361 static void spr_write_booke_tcr (void *opaque
, int sprn
)
363 gen_op_store_booke_tcr();
366 static void spr_write_booke_tsr (void *opaque
, int sprn
)
368 gen_op_store_booke_tsr();
372 /* PowerPC 403 specific registers */
373 /* PBL1 / PBU1 / PBL2 / PBU2 */
374 #if !defined(CONFIG_USER_ONLY)
375 static void spr_read_403_pbr (void *opaque
, int sprn
)
377 gen_op_load_403_pb(sprn
- SPR_403_PBL1
);
380 static void spr_write_403_pbr (void *opaque
, int sprn
)
382 gen_op_store_403_pb(sprn
- SPR_403_PBL1
);
385 static void spr_write_pir (void *opaque
, int sprn
)
391 #if !defined(CONFIG_USER_ONLY)
392 /* Callback used to write the exception vector base */
393 static void spr_write_excp_prefix (void *opaque
, int sprn
)
395 gen_op_store_excp_prefix();
396 gen_op_store_spr(sprn
);
399 static void spr_write_excp_vector (void *opaque
, int sprn
)
401 DisasContext
*ctx
= opaque
;
403 if (sprn
>= SPR_BOOKE_IVOR0
&& sprn
<= SPR_BOOKE_IVOR15
) {
404 gen_op_store_excp_vector(sprn
- SPR_BOOKE_IVOR0
);
405 gen_op_store_spr(sprn
);
406 } else if (sprn
>= SPR_BOOKE_IVOR32
&& sprn
<= SPR_BOOKE_IVOR37
) {
407 gen_op_store_excp_vector(sprn
- SPR_BOOKE_IVOR32
+ 32);
408 gen_op_store_spr(sprn
);
410 printf("Trying to write an unknown exception vector %d %03x\n",
412 GEN_EXCP_PRIVREG(ctx
);
417 #if defined(CONFIG_USER_ONLY)
418 #define spr_register(env, num, name, uea_read, uea_write, \
419 oea_read, oea_write, initial_value) \
421 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
423 static inline void _spr_register (CPUPPCState
*env
, int num
,
424 const unsigned char *name
,
425 void (*uea_read
)(void *opaque
, int sprn
),
426 void (*uea_write
)(void *opaque
, int sprn
),
427 target_ulong initial_value
)
429 static inline void spr_register (CPUPPCState
*env
, int num
,
430 const unsigned char *name
,
431 void (*uea_read
)(void *opaque
, int sprn
),
432 void (*uea_write
)(void *opaque
, int sprn
),
433 void (*oea_read
)(void *opaque
, int sprn
),
434 void (*oea_write
)(void *opaque
, int sprn
),
435 target_ulong initial_value
)
440 spr
= &env
->spr_cb
[num
];
441 if (spr
->name
!= NULL
||env
-> spr
[num
] != 0x00000000 ||
442 #if !defined(CONFIG_USER_ONLY)
443 spr
->oea_read
!= NULL
|| spr
->oea_write
!= NULL
||
445 spr
->uea_read
!= NULL
|| spr
->uea_write
!= NULL
) {
446 printf("Error: Trying to register SPR %d (%03x) twice !\n", num
, num
);
449 #if defined(PPC_DEBUG_SPR)
450 printf("*** register spr %d (%03x) %s val " ADDRX
"\n", num
, num
, name
,
454 spr
->uea_read
= uea_read
;
455 spr
->uea_write
= uea_write
;
456 #if !defined(CONFIG_USER_ONLY)
457 spr
->oea_read
= oea_read
;
458 spr
->oea_write
= oea_write
;
460 env
->spr
[num
] = initial_value
;
463 /* Generic PowerPC SPRs */
464 static void gen_spr_generic (CPUPPCState
*env
)
466 /* Integer processing */
467 spr_register(env
, SPR_XER
, "XER",
468 &spr_read_xer
, &spr_write_xer
,
469 &spr_read_xer
, &spr_write_xer
,
472 spr_register(env
, SPR_LR
, "LR",
473 &spr_read_lr
, &spr_write_lr
,
474 &spr_read_lr
, &spr_write_lr
,
476 spr_register(env
, SPR_CTR
, "CTR",
477 &spr_read_ctr
, &spr_write_ctr
,
478 &spr_read_ctr
, &spr_write_ctr
,
480 /* Interrupt processing */
481 spr_register(env
, SPR_SRR0
, "SRR0",
482 SPR_NOACCESS
, SPR_NOACCESS
,
483 &spr_read_generic
, &spr_write_generic
,
485 spr_register(env
, SPR_SRR1
, "SRR1",
486 SPR_NOACCESS
, SPR_NOACCESS
,
487 &spr_read_generic
, &spr_write_generic
,
489 /* Processor control */
490 spr_register(env
, SPR_SPRG0
, "SPRG0",
491 SPR_NOACCESS
, SPR_NOACCESS
,
492 &spr_read_generic
, &spr_write_generic
,
494 spr_register(env
, SPR_SPRG1
, "SPRG1",
495 SPR_NOACCESS
, SPR_NOACCESS
,
496 &spr_read_generic
, &spr_write_generic
,
498 spr_register(env
, SPR_SPRG2
, "SPRG2",
499 SPR_NOACCESS
, SPR_NOACCESS
,
500 &spr_read_generic
, &spr_write_generic
,
502 spr_register(env
, SPR_SPRG3
, "SPRG3",
503 SPR_NOACCESS
, SPR_NOACCESS
,
504 &spr_read_generic
, &spr_write_generic
,
508 /* SPR common to all non-embedded PowerPC, including 601 */
509 static void gen_spr_ne_601 (CPUPPCState
*env
)
511 /* Exception processing */
512 spr_register(env
, SPR_DSISR
, "DSISR",
513 SPR_NOACCESS
, SPR_NOACCESS
,
514 &spr_read_generic
, &spr_write_generic
,
516 spr_register(env
, SPR_DAR
, "DAR",
517 SPR_NOACCESS
, SPR_NOACCESS
,
518 &spr_read_generic
, &spr_write_generic
,
521 spr_register(env
, SPR_DECR
, "DECR",
522 SPR_NOACCESS
, SPR_NOACCESS
,
523 &spr_read_decr
, &spr_write_decr
,
525 /* Memory management */
526 spr_register(env
, SPR_SDR1
, "SDR1",
527 SPR_NOACCESS
, SPR_NOACCESS
,
528 &spr_read_sdr1
, &spr_write_sdr1
,
533 static void gen_low_BATs (CPUPPCState
*env
)
535 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
536 SPR_NOACCESS
, SPR_NOACCESS
,
537 &spr_read_ibat
, &spr_write_ibatu
,
539 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
540 SPR_NOACCESS
, SPR_NOACCESS
,
541 &spr_read_ibat
, &spr_write_ibatl
,
543 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
544 SPR_NOACCESS
, SPR_NOACCESS
,
545 &spr_read_ibat
, &spr_write_ibatu
,
547 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
548 SPR_NOACCESS
, SPR_NOACCESS
,
549 &spr_read_ibat
, &spr_write_ibatl
,
551 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
552 SPR_NOACCESS
, SPR_NOACCESS
,
553 &spr_read_ibat
, &spr_write_ibatu
,
555 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
556 SPR_NOACCESS
, SPR_NOACCESS
,
557 &spr_read_ibat
, &spr_write_ibatl
,
559 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
560 SPR_NOACCESS
, SPR_NOACCESS
,
561 &spr_read_ibat
, &spr_write_ibatu
,
563 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
564 SPR_NOACCESS
, SPR_NOACCESS
,
565 &spr_read_ibat
, &spr_write_ibatl
,
567 spr_register(env
, SPR_DBAT0U
, "DBAT0U",
568 SPR_NOACCESS
, SPR_NOACCESS
,
569 &spr_read_dbat
, &spr_write_dbatu
,
571 spr_register(env
, SPR_DBAT0L
, "DBAT0L",
572 SPR_NOACCESS
, SPR_NOACCESS
,
573 &spr_read_dbat
, &spr_write_dbatl
,
575 spr_register(env
, SPR_DBAT1U
, "DBAT1U",
576 SPR_NOACCESS
, SPR_NOACCESS
,
577 &spr_read_dbat
, &spr_write_dbatu
,
579 spr_register(env
, SPR_DBAT1L
, "DBAT1L",
580 SPR_NOACCESS
, SPR_NOACCESS
,
581 &spr_read_dbat
, &spr_write_dbatl
,
583 spr_register(env
, SPR_DBAT2U
, "DBAT2U",
584 SPR_NOACCESS
, SPR_NOACCESS
,
585 &spr_read_dbat
, &spr_write_dbatu
,
587 spr_register(env
, SPR_DBAT2L
, "DBAT2L",
588 SPR_NOACCESS
, SPR_NOACCESS
,
589 &spr_read_dbat
, &spr_write_dbatl
,
591 spr_register(env
, SPR_DBAT3U
, "DBAT3U",
592 SPR_NOACCESS
, SPR_NOACCESS
,
593 &spr_read_dbat
, &spr_write_dbatu
,
595 spr_register(env
, SPR_DBAT3L
, "DBAT3L",
596 SPR_NOACCESS
, SPR_NOACCESS
,
597 &spr_read_dbat
, &spr_write_dbatl
,
603 static void gen_high_BATs (CPUPPCState
*env
)
605 spr_register(env
, SPR_IBAT4U
, "IBAT4U",
606 SPR_NOACCESS
, SPR_NOACCESS
,
607 &spr_read_ibat_h
, &spr_write_ibatu_h
,
609 spr_register(env
, SPR_IBAT4L
, "IBAT4L",
610 SPR_NOACCESS
, SPR_NOACCESS
,
611 &spr_read_ibat_h
, &spr_write_ibatl_h
,
613 spr_register(env
, SPR_IBAT5U
, "IBAT5U",
614 SPR_NOACCESS
, SPR_NOACCESS
,
615 &spr_read_ibat_h
, &spr_write_ibatu_h
,
617 spr_register(env
, SPR_IBAT5L
, "IBAT5L",
618 SPR_NOACCESS
, SPR_NOACCESS
,
619 &spr_read_ibat_h
, &spr_write_ibatl_h
,
621 spr_register(env
, SPR_IBAT6U
, "IBAT6U",
622 SPR_NOACCESS
, SPR_NOACCESS
,
623 &spr_read_ibat_h
, &spr_write_ibatu_h
,
625 spr_register(env
, SPR_IBAT6L
, "IBAT6L",
626 SPR_NOACCESS
, SPR_NOACCESS
,
627 &spr_read_ibat_h
, &spr_write_ibatl_h
,
629 spr_register(env
, SPR_IBAT7U
, "IBAT7U",
630 SPR_NOACCESS
, SPR_NOACCESS
,
631 &spr_read_ibat_h
, &spr_write_ibatu_h
,
633 spr_register(env
, SPR_IBAT7L
, "IBAT7L",
634 SPR_NOACCESS
, SPR_NOACCESS
,
635 &spr_read_ibat_h
, &spr_write_ibatl_h
,
637 spr_register(env
, SPR_DBAT4U
, "DBAT4U",
638 SPR_NOACCESS
, SPR_NOACCESS
,
639 &spr_read_dbat_h
, &spr_write_dbatu_h
,
641 spr_register(env
, SPR_DBAT4L
, "DBAT4L",
642 SPR_NOACCESS
, SPR_NOACCESS
,
643 &spr_read_dbat_h
, &spr_write_dbatl_h
,
645 spr_register(env
, SPR_DBAT5U
, "DBAT5U",
646 SPR_NOACCESS
, SPR_NOACCESS
,
647 &spr_read_dbat_h
, &spr_write_dbatu_h
,
649 spr_register(env
, SPR_DBAT5L
, "DBAT5L",
650 SPR_NOACCESS
, SPR_NOACCESS
,
651 &spr_read_dbat_h
, &spr_write_dbatl_h
,
653 spr_register(env
, SPR_DBAT6U
, "DBAT6U",
654 SPR_NOACCESS
, SPR_NOACCESS
,
655 &spr_read_dbat_h
, &spr_write_dbatu_h
,
657 spr_register(env
, SPR_DBAT6L
, "DBAT6L",
658 SPR_NOACCESS
, SPR_NOACCESS
,
659 &spr_read_dbat_h
, &spr_write_dbatl_h
,
661 spr_register(env
, SPR_DBAT7U
, "DBAT7U",
662 SPR_NOACCESS
, SPR_NOACCESS
,
663 &spr_read_dbat_h
, &spr_write_dbatu_h
,
665 spr_register(env
, SPR_DBAT7L
, "DBAT7L",
666 SPR_NOACCESS
, SPR_NOACCESS
,
667 &spr_read_dbat_h
, &spr_write_dbatl_h
,
672 /* Generic PowerPC time base */
673 static void gen_tbl (CPUPPCState
*env
)
675 spr_register(env
, SPR_VTBL
, "TBL",
676 &spr_read_tbl
, SPR_NOACCESS
,
677 &spr_read_tbl
, SPR_NOACCESS
,
679 spr_register(env
, SPR_TBL
, "TBL",
680 SPR_NOACCESS
, SPR_NOACCESS
,
681 SPR_NOACCESS
, &spr_write_tbl
,
683 spr_register(env
, SPR_VTBU
, "TBU",
684 &spr_read_tbu
, SPR_NOACCESS
,
685 &spr_read_tbu
, SPR_NOACCESS
,
687 spr_register(env
, SPR_TBU
, "TBU",
688 SPR_NOACCESS
, SPR_NOACCESS
,
689 SPR_NOACCESS
, &spr_write_tbu
,
693 /* Softare table search registers */
694 static void gen_6xx_7xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
696 env
->nb_tlb
= nb_tlbs
;
697 env
->nb_ways
= nb_ways
;
699 spr_register(env
, SPR_DMISS
, "DMISS",
700 SPR_NOACCESS
, SPR_NOACCESS
,
701 &spr_read_generic
, SPR_NOACCESS
,
703 spr_register(env
, SPR_DCMP
, "DCMP",
704 SPR_NOACCESS
, SPR_NOACCESS
,
705 &spr_read_generic
, SPR_NOACCESS
,
707 spr_register(env
, SPR_HASH1
, "HASH1",
708 SPR_NOACCESS
, SPR_NOACCESS
,
709 &spr_read_generic
, SPR_NOACCESS
,
711 spr_register(env
, SPR_HASH2
, "HASH2",
712 SPR_NOACCESS
, SPR_NOACCESS
,
713 &spr_read_generic
, SPR_NOACCESS
,
715 spr_register(env
, SPR_IMISS
, "IMISS",
716 SPR_NOACCESS
, SPR_NOACCESS
,
717 &spr_read_generic
, SPR_NOACCESS
,
719 spr_register(env
, SPR_ICMP
, "ICMP",
720 SPR_NOACCESS
, SPR_NOACCESS
,
721 &spr_read_generic
, SPR_NOACCESS
,
723 spr_register(env
, SPR_RPA
, "RPA",
724 SPR_NOACCESS
, SPR_NOACCESS
,
725 &spr_read_generic
, &spr_write_generic
,
729 /* SPR common to MPC755 and G2 */
730 static void gen_spr_G2_755 (CPUPPCState
*env
)
733 spr_register(env
, SPR_SPRG4
, "SPRG4",
734 SPR_NOACCESS
, SPR_NOACCESS
,
735 &spr_read_generic
, &spr_write_generic
,
737 spr_register(env
, SPR_SPRG5
, "SPRG5",
738 SPR_NOACCESS
, SPR_NOACCESS
,
739 &spr_read_generic
, &spr_write_generic
,
741 spr_register(env
, SPR_SPRG6
, "SPRG6",
742 SPR_NOACCESS
, SPR_NOACCESS
,
743 &spr_read_generic
, &spr_write_generic
,
745 spr_register(env
, SPR_SPRG7
, "SPRG7",
746 SPR_NOACCESS
, SPR_NOACCESS
,
747 &spr_read_generic
, &spr_write_generic
,
749 /* External access control */
750 /* XXX : not implemented */
751 spr_register(env
, SPR_EAR
, "EAR",
752 SPR_NOACCESS
, SPR_NOACCESS
,
753 &spr_read_generic
, &spr_write_generic
,
757 /* SPR common to all 7xx PowerPC implementations */
758 static void gen_spr_7xx (CPUPPCState
*env
)
761 /* XXX : not implemented */
762 spr_register(env
, SPR_DABR
, "DABR",
763 SPR_NOACCESS
, SPR_NOACCESS
,
764 &spr_read_generic
, &spr_write_generic
,
766 /* XXX : not implemented */
767 spr_register(env
, SPR_IABR
, "IABR",
768 SPR_NOACCESS
, SPR_NOACCESS
,
769 &spr_read_generic
, &spr_write_generic
,
771 /* Cache management */
772 /* XXX : not implemented */
773 spr_register(env
, SPR_ICTC
, "ICTC",
774 SPR_NOACCESS
, SPR_NOACCESS
,
775 &spr_read_generic
, &spr_write_generic
,
777 /* XXX : not implemented */
778 spr_register(env
, SPR_L2CR
, "L2CR",
779 SPR_NOACCESS
, SPR_NOACCESS
,
780 &spr_read_generic
, &spr_write_generic
,
782 /* Performance monitors */
783 /* XXX : not implemented */
784 spr_register(env
, SPR_MMCR0
, "MMCR0",
785 SPR_NOACCESS
, SPR_NOACCESS
,
786 &spr_read_generic
, &spr_write_generic
,
788 /* XXX : not implemented */
789 spr_register(env
, SPR_MMCR1
, "MMCR1",
790 SPR_NOACCESS
, SPR_NOACCESS
,
791 &spr_read_generic
, &spr_write_generic
,
793 /* XXX : not implemented */
794 spr_register(env
, SPR_PMC1
, "PMC1",
795 SPR_NOACCESS
, SPR_NOACCESS
,
796 &spr_read_generic
, &spr_write_generic
,
798 /* XXX : not implemented */
799 spr_register(env
, SPR_PMC2
, "PMC2",
800 SPR_NOACCESS
, SPR_NOACCESS
,
801 &spr_read_generic
, &spr_write_generic
,
803 /* XXX : not implemented */
804 spr_register(env
, SPR_PMC3
, "PMC3",
805 SPR_NOACCESS
, SPR_NOACCESS
,
806 &spr_read_generic
, &spr_write_generic
,
808 /* XXX : not implemented */
809 spr_register(env
, SPR_PMC4
, "PMC4",
810 SPR_NOACCESS
, SPR_NOACCESS
,
811 &spr_read_generic
, &spr_write_generic
,
813 /* XXX : not implemented */
814 spr_register(env
, SPR_SIAR
, "SIAR",
815 SPR_NOACCESS
, SPR_NOACCESS
,
816 &spr_read_generic
, SPR_NOACCESS
,
818 /* XXX : not implemented */
819 spr_register(env
, SPR_UMMCR0
, "UMMCR0",
820 &spr_read_ureg
, SPR_NOACCESS
,
821 &spr_read_ureg
, SPR_NOACCESS
,
823 /* XXX : not implemented */
824 spr_register(env
, SPR_UMMCR1
, "UMMCR1",
825 &spr_read_ureg
, SPR_NOACCESS
,
826 &spr_read_ureg
, SPR_NOACCESS
,
828 /* XXX : not implemented */
829 spr_register(env
, SPR_UPMC1
, "UPMC1",
830 &spr_read_ureg
, SPR_NOACCESS
,
831 &spr_read_ureg
, SPR_NOACCESS
,
833 /* XXX : not implemented */
834 spr_register(env
, SPR_UPMC2
, "UPMC2",
835 &spr_read_ureg
, SPR_NOACCESS
,
836 &spr_read_ureg
, SPR_NOACCESS
,
838 /* XXX : not implemented */
839 spr_register(env
, SPR_UPMC3
, "UPMC3",
840 &spr_read_ureg
, SPR_NOACCESS
,
841 &spr_read_ureg
, SPR_NOACCESS
,
843 /* XXX : not implemented */
844 spr_register(env
, SPR_UPMC4
, "UPMC4",
845 &spr_read_ureg
, SPR_NOACCESS
,
846 &spr_read_ureg
, SPR_NOACCESS
,
848 /* XXX : not implemented */
849 spr_register(env
, SPR_USIAR
, "USIAR",
850 &spr_read_ureg
, SPR_NOACCESS
,
851 &spr_read_ureg
, SPR_NOACCESS
,
853 /* External access control */
854 /* XXX : not implemented */
855 spr_register(env
, SPR_EAR
, "EAR",
856 SPR_NOACCESS
, SPR_NOACCESS
,
857 &spr_read_generic
, &spr_write_generic
,
861 static void gen_spr_thrm (CPUPPCState
*env
)
863 /* Thermal management */
864 /* XXX : not implemented */
865 spr_register(env
, SPR_THRM1
, "THRM1",
866 SPR_NOACCESS
, SPR_NOACCESS
,
867 &spr_read_generic
, &spr_write_generic
,
869 /* XXX : not implemented */
870 spr_register(env
, SPR_THRM2
, "THRM2",
871 SPR_NOACCESS
, SPR_NOACCESS
,
872 &spr_read_generic
, &spr_write_generic
,
874 /* XXX : not implemented */
875 spr_register(env
, SPR_THRM3
, "THRM3",
876 SPR_NOACCESS
, SPR_NOACCESS
,
877 &spr_read_generic
, &spr_write_generic
,
881 /* SPR specific to PowerPC 604 implementation */
882 static void gen_spr_604 (CPUPPCState
*env
)
884 /* Processor identification */
885 spr_register(env
, SPR_PIR
, "PIR",
886 SPR_NOACCESS
, SPR_NOACCESS
,
887 &spr_read_generic
, &spr_write_pir
,
890 /* XXX : not implemented */
891 spr_register(env
, SPR_IABR
, "IABR",
892 SPR_NOACCESS
, SPR_NOACCESS
,
893 &spr_read_generic
, &spr_write_generic
,
895 /* XXX : not implemented */
896 spr_register(env
, SPR_DABR
, "DABR",
897 SPR_NOACCESS
, SPR_NOACCESS
,
898 &spr_read_generic
, &spr_write_generic
,
900 /* Performance counters */
901 /* XXX : not implemented */
902 spr_register(env
, SPR_MMCR0
, "MMCR0",
903 SPR_NOACCESS
, SPR_NOACCESS
,
904 &spr_read_generic
, &spr_write_generic
,
906 /* XXX : not implemented */
907 spr_register(env
, SPR_MMCR1
, "MMCR1",
908 SPR_NOACCESS
, SPR_NOACCESS
,
909 &spr_read_generic
, &spr_write_generic
,
911 /* XXX : not implemented */
912 spr_register(env
, SPR_PMC1
, "PMC1",
913 SPR_NOACCESS
, SPR_NOACCESS
,
914 &spr_read_generic
, &spr_write_generic
,
916 /* XXX : not implemented */
917 spr_register(env
, SPR_PMC2
, "PMC2",
918 SPR_NOACCESS
, SPR_NOACCESS
,
919 &spr_read_generic
, &spr_write_generic
,
921 /* XXX : not implemented */
922 spr_register(env
, SPR_PMC3
, "PMC3",
923 SPR_NOACCESS
, SPR_NOACCESS
,
924 &spr_read_generic
, &spr_write_generic
,
926 /* XXX : not implemented */
927 spr_register(env
, SPR_PMC4
, "PMC4",
928 SPR_NOACCESS
, SPR_NOACCESS
,
929 &spr_read_generic
, &spr_write_generic
,
931 /* XXX : not implemented */
932 spr_register(env
, SPR_SIAR
, "SIAR",
933 SPR_NOACCESS
, SPR_NOACCESS
,
934 &spr_read_generic
, SPR_NOACCESS
,
936 /* XXX : not implemented */
937 spr_register(env
, SPR_SDA
, "SDA",
938 SPR_NOACCESS
, SPR_NOACCESS
,
939 &spr_read_generic
, SPR_NOACCESS
,
941 /* External access control */
942 /* XXX : not implemented */
943 spr_register(env
, SPR_EAR
, "EAR",
944 SPR_NOACCESS
, SPR_NOACCESS
,
945 &spr_read_generic
, &spr_write_generic
,
949 /* SPR specific to PowerPC 603 implementation */
950 static void gen_spr_603 (CPUPPCState
*env
)
952 /* External access control */
953 /* XXX : not implemented */
954 spr_register(env
, SPR_EAR
, "EAR",
955 SPR_NOACCESS
, SPR_NOACCESS
,
956 &spr_read_generic
, &spr_write_generic
,
960 /* SPR specific to PowerPC G2 implementation */
961 static void gen_spr_G2 (CPUPPCState
*env
)
963 /* Memory base address */
965 /* XXX : not implemented */
966 spr_register(env
, SPR_MBAR
, "MBAR",
967 SPR_NOACCESS
, SPR_NOACCESS
,
968 &spr_read_generic
, &spr_write_generic
,
970 /* System version register */
972 /* XXX : TODO: initialize it to an appropriate value */
973 spr_register(env
, SPR_SVR
, "SVR",
974 SPR_NOACCESS
, SPR_NOACCESS
,
975 &spr_read_generic
, SPR_NOACCESS
,
977 /* Exception processing */
978 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
979 SPR_NOACCESS
, SPR_NOACCESS
,
980 &spr_read_generic
, &spr_write_generic
,
982 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
983 SPR_NOACCESS
, SPR_NOACCESS
,
984 &spr_read_generic
, &spr_write_generic
,
987 /* XXX : not implemented */
988 spr_register(env
, SPR_DABR
, "DABR",
989 SPR_NOACCESS
, SPR_NOACCESS
,
990 &spr_read_generic
, &spr_write_generic
,
992 /* XXX : not implemented */
993 spr_register(env
, SPR_DABR2
, "DABR2",
994 SPR_NOACCESS
, SPR_NOACCESS
,
995 &spr_read_generic
, &spr_write_generic
,
997 /* XXX : not implemented */
998 spr_register(env
, SPR_IABR
, "IABR",
999 SPR_NOACCESS
, SPR_NOACCESS
,
1000 &spr_read_generic
, &spr_write_generic
,
1002 /* XXX : not implemented */
1003 spr_register(env
, SPR_IABR2
, "IABR2",
1004 SPR_NOACCESS
, SPR_NOACCESS
,
1005 &spr_read_generic
, &spr_write_generic
,
1007 /* XXX : not implemented */
1008 spr_register(env
, SPR_IBCR
, "IBCR",
1009 SPR_NOACCESS
, SPR_NOACCESS
,
1010 &spr_read_generic
, &spr_write_generic
,
1012 /* XXX : not implemented */
1013 spr_register(env
, SPR_DBCR
, "DBCR",
1014 SPR_NOACCESS
, SPR_NOACCESS
,
1015 &spr_read_generic
, &spr_write_generic
,
1019 /* SPR specific to PowerPC 602 implementation */
1020 static void gen_spr_602 (CPUPPCState
*env
)
1023 /* XXX : not implemented */
1024 spr_register(env
, SPR_SER
, "SER",
1025 SPR_NOACCESS
, SPR_NOACCESS
,
1026 &spr_read_generic
, &spr_write_generic
,
1028 /* XXX : not implemented */
1029 spr_register(env
, SPR_SEBR
, "SEBR",
1030 SPR_NOACCESS
, SPR_NOACCESS
,
1031 &spr_read_generic
, &spr_write_generic
,
1033 /* XXX : not implemented */
1034 spr_register(env
, SPR_ESASRR
, "ESASRR",
1035 SPR_NOACCESS
, SPR_NOACCESS
,
1036 &spr_read_generic
, &spr_write_generic
,
1038 /* Floating point status */
1039 /* XXX : not implemented */
1040 spr_register(env
, SPR_SP
, "SP",
1041 SPR_NOACCESS
, SPR_NOACCESS
,
1042 &spr_read_generic
, &spr_write_generic
,
1044 /* XXX : not implemented */
1045 spr_register(env
, SPR_LT
, "LT",
1046 SPR_NOACCESS
, SPR_NOACCESS
,
1047 &spr_read_generic
, &spr_write_generic
,
1049 /* Watchdog timer */
1050 /* XXX : not implemented */
1051 spr_register(env
, SPR_TCR
, "TCR",
1052 SPR_NOACCESS
, SPR_NOACCESS
,
1053 &spr_read_generic
, &spr_write_generic
,
1055 /* Interrupt base */
1056 spr_register(env
, SPR_IBR
, "IBR",
1057 SPR_NOACCESS
, SPR_NOACCESS
,
1058 &spr_read_generic
, &spr_write_generic
,
1060 /* XXX : not implemented */
1061 spr_register(env
, SPR_IABR
, "IABR",
1062 SPR_NOACCESS
, SPR_NOACCESS
,
1063 &spr_read_generic
, &spr_write_generic
,
1067 /* SPR specific to PowerPC 601 implementation */
1068 static void gen_spr_601 (CPUPPCState
*env
)
1070 /* Multiplication/division register */
1072 spr_register(env
, SPR_MQ
, "MQ",
1073 &spr_read_generic
, &spr_write_generic
,
1074 &spr_read_generic
, &spr_write_generic
,
1077 spr_register(env
, SPR_601_RTCU
, "RTCU",
1078 SPR_NOACCESS
, SPR_NOACCESS
,
1079 SPR_NOACCESS
, &spr_write_601_rtcu
,
1081 spr_register(env
, SPR_601_VRTCU
, "RTCU",
1082 &spr_read_601_rtcu
, SPR_NOACCESS
,
1083 &spr_read_601_rtcu
, SPR_NOACCESS
,
1085 spr_register(env
, SPR_601_RTCL
, "RTCL",
1086 SPR_NOACCESS
, SPR_NOACCESS
,
1087 SPR_NOACCESS
, &spr_write_601_rtcl
,
1089 spr_register(env
, SPR_601_VRTCL
, "RTCL",
1090 &spr_read_601_rtcl
, SPR_NOACCESS
,
1091 &spr_read_601_rtcl
, SPR_NOACCESS
,
1095 spr_register(env
, SPR_601_UDECR
, "UDECR",
1096 &spr_read_decr
, SPR_NOACCESS
,
1097 &spr_read_decr
, SPR_NOACCESS
,
1100 /* External access control */
1101 /* XXX : not implemented */
1102 spr_register(env
, SPR_EAR
, "EAR",
1103 SPR_NOACCESS
, SPR_NOACCESS
,
1104 &spr_read_generic
, &spr_write_generic
,
1106 /* Memory management */
1107 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
1108 SPR_NOACCESS
, SPR_NOACCESS
,
1109 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1111 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
1112 SPR_NOACCESS
, SPR_NOACCESS
,
1113 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1115 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
1116 SPR_NOACCESS
, SPR_NOACCESS
,
1117 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1119 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
1120 SPR_NOACCESS
, SPR_NOACCESS
,
1121 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1123 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
1124 SPR_NOACCESS
, SPR_NOACCESS
,
1125 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1127 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
1128 SPR_NOACCESS
, SPR_NOACCESS
,
1129 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1131 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
1132 SPR_NOACCESS
, SPR_NOACCESS
,
1133 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1135 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
1136 SPR_NOACCESS
, SPR_NOACCESS
,
1137 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1142 static void gen_spr_74xx (CPUPPCState
*env
)
1144 /* Processor identification */
1145 spr_register(env
, SPR_PIR
, "PIR",
1146 SPR_NOACCESS
, SPR_NOACCESS
,
1147 &spr_read_generic
, &spr_write_pir
,
1149 /* XXX : not implemented */
1150 spr_register(env
, SPR_MMCR2
, "MMCR2",
1151 SPR_NOACCESS
, SPR_NOACCESS
,
1152 &spr_read_generic
, &spr_write_generic
,
1154 /* XXX : not implemented */
1155 spr_register(env
, SPR_UMMCR2
, "UMMCR2",
1156 &spr_read_ureg
, SPR_NOACCESS
,
1157 &spr_read_ureg
, SPR_NOACCESS
,
1159 /* XXX: not implemented */
1160 spr_register(env
, SPR_BAMR
, "BAMR",
1161 SPR_NOACCESS
, SPR_NOACCESS
,
1162 &spr_read_generic
, &spr_write_generic
,
1164 /* XXX : not implemented */
1165 spr_register(env
, SPR_UBAMR
, "UBAMR",
1166 &spr_read_ureg
, SPR_NOACCESS
,
1167 &spr_read_ureg
, SPR_NOACCESS
,
1169 /* XXX : not implemented */
1170 spr_register(env
, SPR_MSSCR0
, "MSSCR0",
1171 SPR_NOACCESS
, SPR_NOACCESS
,
1172 &spr_read_generic
, &spr_write_generic
,
1174 /* Hardware implementation registers */
1175 /* XXX : not implemented */
1176 spr_register(env
, SPR_HID0
, "HID0",
1177 SPR_NOACCESS
, SPR_NOACCESS
,
1178 &spr_read_generic
, &spr_write_generic
,
1180 /* XXX : not implemented */
1181 spr_register(env
, SPR_HID1
, "HID1",
1182 SPR_NOACCESS
, SPR_NOACCESS
,
1183 &spr_read_generic
, &spr_write_generic
,
1186 spr_register(env
, SPR_VRSAVE
, "VRSAVE",
1187 &spr_read_generic
, &spr_write_generic
,
1188 &spr_read_generic
, &spr_write_generic
,
1192 static void gen_l3_ctrl (CPUPPCState
*env
)
1195 /* XXX : not implemented */
1196 spr_register(env
, SPR_L3CR
, "L3CR",
1197 SPR_NOACCESS
, SPR_NOACCESS
,
1198 &spr_read_generic
, &spr_write_generic
,
1201 /* XXX : not implemented */
1202 spr_register(env
, SPR_L3ITCR0
, "L3ITCR0",
1203 SPR_NOACCESS
, SPR_NOACCESS
,
1204 &spr_read_generic
, &spr_write_generic
,
1207 /* XXX : not implemented */
1208 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
1209 SPR_NOACCESS
, SPR_NOACCESS
,
1210 &spr_read_generic
, &spr_write_generic
,
1213 /* XXX : not implemented */
1214 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
1215 SPR_NOACCESS
, SPR_NOACCESS
,
1216 &spr_read_generic
, &spr_write_generic
,
1219 /* XXX : not implemented */
1220 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
1221 SPR_NOACCESS
, SPR_NOACCESS
,
1222 &spr_read_generic
, &spr_write_generic
,
1225 /* XXX : not implemented */
1226 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
1227 SPR_NOACCESS
, SPR_NOACCESS
,
1228 &spr_read_generic
, &spr_write_generic
,
1231 /* XXX : not implemented */
1232 spr_register(env
, SPR_L3PM
, "L3PM",
1233 SPR_NOACCESS
, SPR_NOACCESS
,
1234 &spr_read_generic
, &spr_write_generic
,
1238 static void gen_74xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
1240 env
->nb_tlb
= nb_tlbs
;
1241 env
->nb_ways
= nb_ways
;
1243 /* XXX : not implemented */
1244 spr_register(env
, SPR_PTEHI
, "PTEHI",
1245 SPR_NOACCESS
, SPR_NOACCESS
,
1246 &spr_read_generic
, &spr_write_generic
,
1248 /* XXX : not implemented */
1249 spr_register(env
, SPR_PTELO
, "PTELO",
1250 SPR_NOACCESS
, SPR_NOACCESS
,
1251 &spr_read_generic
, &spr_write_generic
,
1253 /* XXX : not implemented */
1254 spr_register(env
, SPR_TLBMISS
, "TLBMISS",
1255 SPR_NOACCESS
, SPR_NOACCESS
,
1256 &spr_read_generic
, &spr_write_generic
,
1260 /* PowerPC BookE SPR */
1261 static void gen_spr_BookE (CPUPPCState
*env
)
1263 /* Processor identification */
1264 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
1265 SPR_NOACCESS
, SPR_NOACCESS
,
1266 &spr_read_generic
, &spr_write_pir
,
1268 /* Interrupt processing */
1269 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
1270 SPR_NOACCESS
, SPR_NOACCESS
,
1271 &spr_read_generic
, &spr_write_generic
,
1273 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1274 SPR_NOACCESS
, SPR_NOACCESS
,
1275 &spr_read_generic
, &spr_write_generic
,
1278 spr_register(env
, SPR_BOOKE_DSRR0
, "DSRR0",
1279 SPR_NOACCESS
, SPR_NOACCESS
,
1280 &spr_read_generic
, &spr_write_generic
,
1282 spr_register(env
, SPR_BOOKE_DSRR1
, "DSRR1",
1283 SPR_NOACCESS
, SPR_NOACCESS
,
1284 &spr_read_generic
, &spr_write_generic
,
1288 /* XXX : not implemented */
1289 spr_register(env
, SPR_BOOKE_IAC1
, "IAC1",
1290 SPR_NOACCESS
, SPR_NOACCESS
,
1291 &spr_read_generic
, &spr_write_generic
,
1293 /* XXX : not implemented */
1294 spr_register(env
, SPR_BOOKE_IAC2
, "IAC2",
1295 SPR_NOACCESS
, SPR_NOACCESS
,
1296 &spr_read_generic
, &spr_write_generic
,
1298 /* XXX : not implemented */
1299 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
1300 SPR_NOACCESS
, SPR_NOACCESS
,
1301 &spr_read_generic
, &spr_write_generic
,
1303 /* XXX : not implemented */
1304 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
1305 SPR_NOACCESS
, SPR_NOACCESS
,
1306 &spr_read_generic
, &spr_write_generic
,
1308 /* XXX : not implemented */
1309 spr_register(env
, SPR_BOOKE_DAC1
, "DAC1",
1310 SPR_NOACCESS
, SPR_NOACCESS
,
1311 &spr_read_generic
, &spr_write_generic
,
1313 /* XXX : not implemented */
1314 spr_register(env
, SPR_BOOKE_DAC2
, "DAC2",
1315 SPR_NOACCESS
, SPR_NOACCESS
,
1316 &spr_read_generic
, &spr_write_generic
,
1318 /* XXX : not implemented */
1319 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
1320 SPR_NOACCESS
, SPR_NOACCESS
,
1321 &spr_read_generic
, &spr_write_generic
,
1323 /* XXX : not implemented */
1324 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
1325 SPR_NOACCESS
, SPR_NOACCESS
,
1326 &spr_read_generic
, &spr_write_generic
,
1328 /* XXX : not implemented */
1329 spr_register(env
, SPR_BOOKE_DBCR0
, "DBCR0",
1330 SPR_NOACCESS
, SPR_NOACCESS
,
1331 &spr_read_generic
, &spr_write_generic
,
1333 /* XXX : not implemented */
1334 spr_register(env
, SPR_BOOKE_DBCR1
, "DBCR1",
1335 SPR_NOACCESS
, SPR_NOACCESS
,
1336 &spr_read_generic
, &spr_write_generic
,
1338 /* XXX : not implemented */
1339 spr_register(env
, SPR_BOOKE_DBCR2
, "DBCR2",
1340 SPR_NOACCESS
, SPR_NOACCESS
,
1341 &spr_read_generic
, &spr_write_generic
,
1343 /* XXX : not implemented */
1344 spr_register(env
, SPR_BOOKE_DBSR
, "DBSR",
1345 SPR_NOACCESS
, SPR_NOACCESS
,
1346 &spr_read_generic
, &spr_write_clear
,
1348 spr_register(env
, SPR_BOOKE_DEAR
, "DEAR",
1349 SPR_NOACCESS
, SPR_NOACCESS
,
1350 &spr_read_generic
, &spr_write_generic
,
1352 spr_register(env
, SPR_BOOKE_ESR
, "ESR",
1353 SPR_NOACCESS
, SPR_NOACCESS
,
1354 &spr_read_generic
, &spr_write_generic
,
1356 spr_register(env
, SPR_BOOKE_IVPR
, "IVPR",
1357 SPR_NOACCESS
, SPR_NOACCESS
,
1358 &spr_read_generic
, &spr_write_excp_prefix
,
1360 /* Exception vectors */
1361 spr_register(env
, SPR_BOOKE_IVOR0
, "IVOR0",
1362 SPR_NOACCESS
, SPR_NOACCESS
,
1363 &spr_read_generic
, &spr_write_excp_vector
,
1365 spr_register(env
, SPR_BOOKE_IVOR1
, "IVOR1",
1366 SPR_NOACCESS
, SPR_NOACCESS
,
1367 &spr_read_generic
, &spr_write_excp_vector
,
1369 spr_register(env
, SPR_BOOKE_IVOR2
, "IVOR2",
1370 SPR_NOACCESS
, SPR_NOACCESS
,
1371 &spr_read_generic
, &spr_write_excp_vector
,
1373 spr_register(env
, SPR_BOOKE_IVOR3
, "IVOR3",
1374 SPR_NOACCESS
, SPR_NOACCESS
,
1375 &spr_read_generic
, &spr_write_excp_vector
,
1377 spr_register(env
, SPR_BOOKE_IVOR4
, "IVOR4",
1378 SPR_NOACCESS
, SPR_NOACCESS
,
1379 &spr_read_generic
, &spr_write_excp_vector
,
1381 spr_register(env
, SPR_BOOKE_IVOR5
, "IVOR5",
1382 SPR_NOACCESS
, SPR_NOACCESS
,
1383 &spr_read_generic
, &spr_write_excp_vector
,
1385 spr_register(env
, SPR_BOOKE_IVOR6
, "IVOR6",
1386 SPR_NOACCESS
, SPR_NOACCESS
,
1387 &spr_read_generic
, &spr_write_excp_vector
,
1389 spr_register(env
, SPR_BOOKE_IVOR7
, "IVOR7",
1390 SPR_NOACCESS
, SPR_NOACCESS
,
1391 &spr_read_generic
, &spr_write_excp_vector
,
1393 spr_register(env
, SPR_BOOKE_IVOR8
, "IVOR8",
1394 SPR_NOACCESS
, SPR_NOACCESS
,
1395 &spr_read_generic
, &spr_write_excp_vector
,
1397 spr_register(env
, SPR_BOOKE_IVOR9
, "IVOR9",
1398 SPR_NOACCESS
, SPR_NOACCESS
,
1399 &spr_read_generic
, &spr_write_excp_vector
,
1401 spr_register(env
, SPR_BOOKE_IVOR10
, "IVOR10",
1402 SPR_NOACCESS
, SPR_NOACCESS
,
1403 &spr_read_generic
, &spr_write_excp_vector
,
1405 spr_register(env
, SPR_BOOKE_IVOR11
, "IVOR11",
1406 SPR_NOACCESS
, SPR_NOACCESS
,
1407 &spr_read_generic
, &spr_write_excp_vector
,
1409 spr_register(env
, SPR_BOOKE_IVOR12
, "IVOR12",
1410 SPR_NOACCESS
, SPR_NOACCESS
,
1411 &spr_read_generic
, &spr_write_excp_vector
,
1413 spr_register(env
, SPR_BOOKE_IVOR13
, "IVOR13",
1414 SPR_NOACCESS
, SPR_NOACCESS
,
1415 &spr_read_generic
, &spr_write_excp_vector
,
1417 spr_register(env
, SPR_BOOKE_IVOR14
, "IVOR14",
1418 SPR_NOACCESS
, SPR_NOACCESS
,
1419 &spr_read_generic
, &spr_write_excp_vector
,
1421 spr_register(env
, SPR_BOOKE_IVOR15
, "IVOR15",
1422 SPR_NOACCESS
, SPR_NOACCESS
,
1423 &spr_read_generic
, &spr_write_excp_vector
,
1426 spr_register(env
, SPR_BOOKE_IVOR32
, "IVOR32",
1427 SPR_NOACCESS
, SPR_NOACCESS
,
1428 &spr_read_generic
, &spr_write_excp_vector
,
1430 spr_register(env
, SPR_BOOKE_IVOR33
, "IVOR33",
1431 SPR_NOACCESS
, SPR_NOACCESS
,
1432 &spr_read_generic
, &spr_write_excp_vector
,
1434 spr_register(env
, SPR_BOOKE_IVOR34
, "IVOR34",
1435 SPR_NOACCESS
, SPR_NOACCESS
,
1436 &spr_read_generic
, &spr_write_excp_vector
,
1438 spr_register(env
, SPR_BOOKE_IVOR35
, "IVOR35",
1439 SPR_NOACCESS
, SPR_NOACCESS
,
1440 &spr_read_generic
, &spr_write_excp_vector
,
1442 spr_register(env
, SPR_BOOKE_IVOR36
, "IVOR36",
1443 SPR_NOACCESS
, SPR_NOACCESS
,
1444 &spr_read_generic
, &spr_write_excp_vector
,
1446 spr_register(env
, SPR_BOOKE_IVOR37
, "IVOR37",
1447 SPR_NOACCESS
, SPR_NOACCESS
,
1448 &spr_read_generic
, &spr_write_excp_vector
,
1451 spr_register(env
, SPR_BOOKE_PID
, "PID",
1452 SPR_NOACCESS
, SPR_NOACCESS
,
1453 &spr_read_generic
, &spr_write_generic
,
1455 spr_register(env
, SPR_BOOKE_TCR
, "TCR",
1456 SPR_NOACCESS
, SPR_NOACCESS
,
1457 &spr_read_generic
, &spr_write_booke_tcr
,
1459 spr_register(env
, SPR_BOOKE_TSR
, "TSR",
1460 SPR_NOACCESS
, SPR_NOACCESS
,
1461 &spr_read_generic
, &spr_write_booke_tsr
,
1464 spr_register(env
, SPR_DECR
, "DECR",
1465 SPR_NOACCESS
, SPR_NOACCESS
,
1466 &spr_read_decr
, &spr_write_decr
,
1468 spr_register(env
, SPR_BOOKE_DECAR
, "DECAR",
1469 SPR_NOACCESS
, SPR_NOACCESS
,
1470 SPR_NOACCESS
, &spr_write_generic
,
1473 spr_register(env
, SPR_USPRG0
, "USPRG0",
1474 &spr_read_generic
, &spr_write_generic
,
1475 &spr_read_generic
, &spr_write_generic
,
1477 spr_register(env
, SPR_SPRG4
, "SPRG4",
1478 SPR_NOACCESS
, SPR_NOACCESS
,
1479 &spr_read_generic
, &spr_write_generic
,
1481 spr_register(env
, SPR_USPRG4
, "USPRG4",
1482 &spr_read_ureg
, SPR_NOACCESS
,
1483 &spr_read_ureg
, SPR_NOACCESS
,
1485 spr_register(env
, SPR_SPRG5
, "SPRG5",
1486 SPR_NOACCESS
, SPR_NOACCESS
,
1487 &spr_read_generic
, &spr_write_generic
,
1489 spr_register(env
, SPR_USPRG5
, "USPRG5",
1490 &spr_read_ureg
, SPR_NOACCESS
,
1491 &spr_read_ureg
, SPR_NOACCESS
,
1493 spr_register(env
, SPR_SPRG6
, "SPRG6",
1494 SPR_NOACCESS
, SPR_NOACCESS
,
1495 &spr_read_generic
, &spr_write_generic
,
1497 spr_register(env
, SPR_USPRG6
, "USPRG6",
1498 &spr_read_ureg
, SPR_NOACCESS
,
1499 &spr_read_ureg
, SPR_NOACCESS
,
1501 spr_register(env
, SPR_SPRG7
, "SPRG7",
1502 SPR_NOACCESS
, SPR_NOACCESS
,
1503 &spr_read_generic
, &spr_write_generic
,
1505 spr_register(env
, SPR_USPRG7
, "USPRG7",
1506 &spr_read_ureg
, SPR_NOACCESS
,
1507 &spr_read_ureg
, SPR_NOACCESS
,
1511 /* FSL storage control registers */
1512 static void gen_spr_BookE_FSL (CPUPPCState
*env
)
1514 /* TLB assist registers */
1515 /* XXX : not implemented */
1516 spr_register(env
, SPR_BOOKE_MAS0
, "MAS0",
1517 SPR_NOACCESS
, SPR_NOACCESS
,
1518 &spr_read_generic
, &spr_write_generic
,
1520 /* XXX : not implemented */
1521 spr_register(env
, SPR_BOOKE_MAS1
, "MAS2",
1522 SPR_NOACCESS
, SPR_NOACCESS
,
1523 &spr_read_generic
, &spr_write_generic
,
1525 /* XXX : not implemented */
1526 spr_register(env
, SPR_BOOKE_MAS2
, "MAS3",
1527 SPR_NOACCESS
, SPR_NOACCESS
,
1528 &spr_read_generic
, &spr_write_generic
,
1530 /* XXX : not implemented */
1531 spr_register(env
, SPR_BOOKE_MAS3
, "MAS4",
1532 SPR_NOACCESS
, SPR_NOACCESS
,
1533 &spr_read_generic
, &spr_write_generic
,
1535 /* XXX : not implemented */
1536 spr_register(env
, SPR_BOOKE_MAS4
, "MAS5",
1537 SPR_NOACCESS
, SPR_NOACCESS
,
1538 &spr_read_generic
, &spr_write_generic
,
1540 /* XXX : not implemented */
1541 spr_register(env
, SPR_BOOKE_MAS6
, "MAS6",
1542 SPR_NOACCESS
, SPR_NOACCESS
,
1543 &spr_read_generic
, &spr_write_generic
,
1545 /* XXX : not implemented */
1546 spr_register(env
, SPR_BOOKE_MAS7
, "MAS7",
1547 SPR_NOACCESS
, SPR_NOACCESS
,
1548 &spr_read_generic
, &spr_write_generic
,
1550 if (env
->nb_pids
> 1) {
1551 /* XXX : not implemented */
1552 spr_register(env
, SPR_BOOKE_PID1
, "PID1",
1553 SPR_NOACCESS
, SPR_NOACCESS
,
1554 &spr_read_generic
, &spr_write_generic
,
1557 if (env
->nb_pids
> 2) {
1558 /* XXX : not implemented */
1559 spr_register(env
, SPR_BOOKE_PID2
, "PID2",
1560 SPR_NOACCESS
, SPR_NOACCESS
,
1561 &spr_read_generic
, &spr_write_generic
,
1564 /* XXX : not implemented */
1565 spr_register(env
, SPR_BOOKE_MMUCFG
, "MMUCFG",
1566 SPR_NOACCESS
, SPR_NOACCESS
,
1567 &spr_read_generic
, SPR_NOACCESS
,
1568 0x00000000); /* TOFIX */
1569 /* XXX : not implemented */
1570 spr_register(env
, SPR_BOOKE_MMUCSR0
, "MMUCSR0",
1571 SPR_NOACCESS
, SPR_NOACCESS
,
1572 &spr_read_generic
, &spr_write_generic
,
1573 0x00000000); /* TOFIX */
1574 switch (env
->nb_ways
) {
1576 /* XXX : not implemented */
1577 spr_register(env
, SPR_BOOKE_TLB3CFG
, "TLB3CFG",
1578 SPR_NOACCESS
, SPR_NOACCESS
,
1579 &spr_read_generic
, SPR_NOACCESS
,
1580 0x00000000); /* TOFIX */
1583 /* XXX : not implemented */
1584 spr_register(env
, SPR_BOOKE_TLB2CFG
, "TLB2CFG",
1585 SPR_NOACCESS
, SPR_NOACCESS
,
1586 &spr_read_generic
, SPR_NOACCESS
,
1587 0x00000000); /* TOFIX */
1590 /* XXX : not implemented */
1591 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
1592 SPR_NOACCESS
, SPR_NOACCESS
,
1593 &spr_read_generic
, SPR_NOACCESS
,
1594 0x00000000); /* TOFIX */
1597 /* XXX : not implemented */
1598 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
1599 SPR_NOACCESS
, SPR_NOACCESS
,
1600 &spr_read_generic
, SPR_NOACCESS
,
1601 0x00000000); /* TOFIX */
1609 /* SPR specific to PowerPC 440 implementation */
1610 static void gen_spr_440 (CPUPPCState
*env
)
1613 /* XXX : not implemented */
1614 spr_register(env
, SPR_440_DNV0
, "DNV0",
1615 SPR_NOACCESS
, SPR_NOACCESS
,
1616 &spr_read_generic
, &spr_write_generic
,
1618 /* XXX : not implemented */
1619 spr_register(env
, SPR_440_DNV1
, "DNV1",
1620 SPR_NOACCESS
, SPR_NOACCESS
,
1621 &spr_read_generic
, &spr_write_generic
,
1623 /* XXX : not implemented */
1624 spr_register(env
, SPR_440_DNV2
, "DNV2",
1625 SPR_NOACCESS
, SPR_NOACCESS
,
1626 &spr_read_generic
, &spr_write_generic
,
1628 /* XXX : not implemented */
1629 spr_register(env
, SPR_440_DNV3
, "DNV3",
1630 SPR_NOACCESS
, SPR_NOACCESS
,
1631 &spr_read_generic
, &spr_write_generic
,
1633 /* XXX : not implemented */
1634 spr_register(env
, SPR_440_DTV0
, "DTV0",
1635 SPR_NOACCESS
, SPR_NOACCESS
,
1636 &spr_read_generic
, &spr_write_generic
,
1638 /* XXX : not implemented */
1639 spr_register(env
, SPR_440_DTV1
, "DTV1",
1640 SPR_NOACCESS
, SPR_NOACCESS
,
1641 &spr_read_generic
, &spr_write_generic
,
1643 /* XXX : not implemented */
1644 spr_register(env
, SPR_440_DTV2
, "DTV2",
1645 SPR_NOACCESS
, SPR_NOACCESS
,
1646 &spr_read_generic
, &spr_write_generic
,
1648 /* XXX : not implemented */
1649 spr_register(env
, SPR_440_DTV3
, "DTV3",
1650 SPR_NOACCESS
, SPR_NOACCESS
,
1651 &spr_read_generic
, &spr_write_generic
,
1653 /* XXX : not implemented */
1654 spr_register(env
, SPR_440_DVLIM
, "DVLIM",
1655 SPR_NOACCESS
, SPR_NOACCESS
,
1656 &spr_read_generic
, &spr_write_generic
,
1658 /* XXX : not implemented */
1659 spr_register(env
, SPR_440_INV0
, "INV0",
1660 SPR_NOACCESS
, SPR_NOACCESS
,
1661 &spr_read_generic
, &spr_write_generic
,
1663 /* XXX : not implemented */
1664 spr_register(env
, SPR_440_INV1
, "INV1",
1665 SPR_NOACCESS
, SPR_NOACCESS
,
1666 &spr_read_generic
, &spr_write_generic
,
1668 /* XXX : not implemented */
1669 spr_register(env
, SPR_440_INV2
, "INV2",
1670 SPR_NOACCESS
, SPR_NOACCESS
,
1671 &spr_read_generic
, &spr_write_generic
,
1673 /* XXX : not implemented */
1674 spr_register(env
, SPR_440_INV3
, "INV3",
1675 SPR_NOACCESS
, SPR_NOACCESS
,
1676 &spr_read_generic
, &spr_write_generic
,
1678 /* XXX : not implemented */
1679 spr_register(env
, SPR_440_ITV0
, "ITV0",
1680 SPR_NOACCESS
, SPR_NOACCESS
,
1681 &spr_read_generic
, &spr_write_generic
,
1683 /* XXX : not implemented */
1684 spr_register(env
, SPR_440_ITV1
, "ITV1",
1685 SPR_NOACCESS
, SPR_NOACCESS
,
1686 &spr_read_generic
, &spr_write_generic
,
1688 /* XXX : not implemented */
1689 spr_register(env
, SPR_440_ITV2
, "ITV2",
1690 SPR_NOACCESS
, SPR_NOACCESS
,
1691 &spr_read_generic
, &spr_write_generic
,
1693 /* XXX : not implemented */
1694 spr_register(env
, SPR_440_ITV3
, "ITV3",
1695 SPR_NOACCESS
, SPR_NOACCESS
,
1696 &spr_read_generic
, &spr_write_generic
,
1698 /* XXX : not implemented */
1699 spr_register(env
, SPR_440_IVLIM
, "IVLIM",
1700 SPR_NOACCESS
, SPR_NOACCESS
,
1701 &spr_read_generic
, &spr_write_generic
,
1704 /* XXX : not implemented */
1705 spr_register(env
, SPR_BOOKE_DCDBTRH
, "DCDBTRH",
1706 SPR_NOACCESS
, SPR_NOACCESS
,
1707 &spr_read_generic
, SPR_NOACCESS
,
1709 /* XXX : not implemented */
1710 spr_register(env
, SPR_BOOKE_DCDBTRL
, "DCDBTRL",
1711 SPR_NOACCESS
, SPR_NOACCESS
,
1712 &spr_read_generic
, SPR_NOACCESS
,
1714 /* XXX : not implemented */
1715 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1716 SPR_NOACCESS
, SPR_NOACCESS
,
1717 &spr_read_generic
, SPR_NOACCESS
,
1719 /* XXX : not implemented */
1720 spr_register(env
, SPR_BOOKE_ICDBTRH
, "ICDBTRH",
1721 SPR_NOACCESS
, SPR_NOACCESS
,
1722 &spr_read_generic
, SPR_NOACCESS
,
1724 /* XXX : not implemented */
1725 spr_register(env
, SPR_BOOKE_ICDBTRL
, "ICDBTRL",
1726 SPR_NOACCESS
, SPR_NOACCESS
,
1727 &spr_read_generic
, SPR_NOACCESS
,
1729 /* XXX : not implemented */
1730 spr_register(env
, SPR_440_DBDR
, "DBDR",
1731 SPR_NOACCESS
, SPR_NOACCESS
,
1732 &spr_read_generic
, &spr_write_generic
,
1734 /* Processor control */
1735 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1736 SPR_NOACCESS
, SPR_NOACCESS
,
1737 &spr_read_generic
, &spr_write_generic
,
1739 spr_register(env
, SPR_440_RSTCFG
, "RSTCFG",
1740 SPR_NOACCESS
, SPR_NOACCESS
,
1741 &spr_read_generic
, SPR_NOACCESS
,
1743 /* Storage control */
1744 spr_register(env
, SPR_440_MMUCR
, "MMUCR",
1745 SPR_NOACCESS
, SPR_NOACCESS
,
1746 &spr_read_generic
, &spr_write_generic
,
1750 /* SPR shared between PowerPC 40x implementations */
1751 static void gen_spr_40x (CPUPPCState
*env
)
1754 /* not emulated, as Qemu do not emulate caches */
1755 spr_register(env
, SPR_40x_DCCR
, "DCCR",
1756 SPR_NOACCESS
, SPR_NOACCESS
,
1757 &spr_read_generic
, &spr_write_generic
,
1759 /* not emulated, as Qemu do not emulate caches */
1760 spr_register(env
, SPR_40x_ICCR
, "ICCR",
1761 SPR_NOACCESS
, SPR_NOACCESS
,
1762 &spr_read_generic
, &spr_write_generic
,
1764 /* not emulated, as Qemu do not emulate caches */
1765 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1766 SPR_NOACCESS
, SPR_NOACCESS
,
1767 &spr_read_generic
, SPR_NOACCESS
,
1770 spr_register(env
, SPR_40x_DEAR
, "DEAR",
1771 SPR_NOACCESS
, SPR_NOACCESS
,
1772 &spr_read_generic
, &spr_write_generic
,
1774 spr_register(env
, SPR_40x_ESR
, "ESR",
1775 SPR_NOACCESS
, SPR_NOACCESS
,
1776 &spr_read_generic
, &spr_write_generic
,
1778 spr_register(env
, SPR_40x_EVPR
, "EVPR",
1779 SPR_NOACCESS
, SPR_NOACCESS
,
1780 &spr_read_generic
, &spr_write_excp_prefix
,
1782 spr_register(env
, SPR_40x_SRR2
, "SRR2",
1783 &spr_read_generic
, &spr_write_generic
,
1784 &spr_read_generic
, &spr_write_generic
,
1786 spr_register(env
, SPR_40x_SRR3
, "SRR3",
1787 &spr_read_generic
, &spr_write_generic
,
1788 &spr_read_generic
, &spr_write_generic
,
1791 spr_register(env
, SPR_40x_PIT
, "PIT",
1792 SPR_NOACCESS
, SPR_NOACCESS
,
1793 &spr_read_40x_pit
, &spr_write_40x_pit
,
1795 spr_register(env
, SPR_40x_TCR
, "TCR",
1796 SPR_NOACCESS
, SPR_NOACCESS
,
1797 &spr_read_generic
, &spr_write_booke_tcr
,
1799 spr_register(env
, SPR_40x_TSR
, "TSR",
1800 SPR_NOACCESS
, SPR_NOACCESS
,
1801 &spr_read_generic
, &spr_write_booke_tsr
,
1805 /* SPR specific to PowerPC 405 implementation */
1806 static void gen_spr_405 (CPUPPCState
*env
)
1809 spr_register(env
, SPR_40x_PID
, "PID",
1810 SPR_NOACCESS
, SPR_NOACCESS
,
1811 &spr_read_generic
, &spr_write_generic
,
1813 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1814 SPR_NOACCESS
, SPR_NOACCESS
,
1815 &spr_read_generic
, &spr_write_generic
,
1817 /* Debug interface */
1818 /* XXX : not implemented */
1819 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1820 SPR_NOACCESS
, SPR_NOACCESS
,
1821 &spr_read_generic
, &spr_write_40x_dbcr0
,
1823 /* XXX : not implemented */
1824 spr_register(env
, SPR_405_DBCR1
, "DBCR1",
1825 SPR_NOACCESS
, SPR_NOACCESS
,
1826 &spr_read_generic
, &spr_write_generic
,
1828 /* XXX : not implemented */
1829 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1830 SPR_NOACCESS
, SPR_NOACCESS
,
1831 &spr_read_generic
, &spr_write_clear
,
1832 /* Last reset was system reset */
1834 /* XXX : not implemented */
1835 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1836 SPR_NOACCESS
, SPR_NOACCESS
,
1837 &spr_read_generic
, &spr_write_generic
,
1839 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1840 SPR_NOACCESS
, SPR_NOACCESS
,
1841 &spr_read_generic
, &spr_write_generic
,
1843 /* XXX : not implemented */
1844 spr_register(env
, SPR_405_DVC1
, "DVC1",
1845 SPR_NOACCESS
, SPR_NOACCESS
,
1846 &spr_read_generic
, &spr_write_generic
,
1848 /* XXX : not implemented */
1849 spr_register(env
, SPR_405_DVC2
, "DVC2",
1850 SPR_NOACCESS
, SPR_NOACCESS
,
1851 &spr_read_generic
, &spr_write_generic
,
1853 /* XXX : not implemented */
1854 spr_register(env
, SPR_40x_IAC1
, "IAC1",
1855 SPR_NOACCESS
, SPR_NOACCESS
,
1856 &spr_read_generic
, &spr_write_generic
,
1858 spr_register(env
, SPR_40x_IAC2
, "IAC2",
1859 SPR_NOACCESS
, SPR_NOACCESS
,
1860 &spr_read_generic
, &spr_write_generic
,
1862 /* XXX : not implemented */
1863 spr_register(env
, SPR_405_IAC3
, "IAC3",
1864 SPR_NOACCESS
, SPR_NOACCESS
,
1865 &spr_read_generic
, &spr_write_generic
,
1867 /* XXX : not implemented */
1868 spr_register(env
, SPR_405_IAC4
, "IAC4",
1869 SPR_NOACCESS
, SPR_NOACCESS
,
1870 &spr_read_generic
, &spr_write_generic
,
1872 /* Storage control */
1873 /* XXX: TODO: not implemented */
1874 spr_register(env
, SPR_405_SLER
, "SLER",
1875 SPR_NOACCESS
, SPR_NOACCESS
,
1876 &spr_read_generic
, &spr_write_40x_sler
,
1878 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1879 SPR_NOACCESS
, SPR_NOACCESS
,
1880 &spr_read_generic
, &spr_write_generic
,
1882 /* XXX : not implemented */
1883 spr_register(env
, SPR_405_SU0R
, "SU0R",
1884 SPR_NOACCESS
, SPR_NOACCESS
,
1885 &spr_read_generic
, &spr_write_generic
,
1888 spr_register(env
, SPR_USPRG0
, "USPRG0",
1889 &spr_read_ureg
, SPR_NOACCESS
,
1890 &spr_read_ureg
, SPR_NOACCESS
,
1892 spr_register(env
, SPR_SPRG4
, "SPRG4",
1893 SPR_NOACCESS
, SPR_NOACCESS
,
1894 &spr_read_generic
, &spr_write_generic
,
1896 spr_register(env
, SPR_USPRG4
, "USPRG4",
1897 &spr_read_ureg
, SPR_NOACCESS
,
1898 &spr_read_ureg
, SPR_NOACCESS
,
1900 spr_register(env
, SPR_SPRG5
, "SPRG5",
1901 SPR_NOACCESS
, SPR_NOACCESS
,
1902 spr_read_generic
, &spr_write_generic
,
1904 spr_register(env
, SPR_USPRG5
, "USPRG5",
1905 &spr_read_ureg
, SPR_NOACCESS
,
1906 &spr_read_ureg
, SPR_NOACCESS
,
1908 spr_register(env
, SPR_SPRG6
, "SPRG6",
1909 SPR_NOACCESS
, SPR_NOACCESS
,
1910 spr_read_generic
, &spr_write_generic
,
1912 spr_register(env
, SPR_USPRG6
, "USPRG6",
1913 &spr_read_ureg
, SPR_NOACCESS
,
1914 &spr_read_ureg
, SPR_NOACCESS
,
1916 spr_register(env
, SPR_SPRG7
, "SPRG7",
1917 SPR_NOACCESS
, SPR_NOACCESS
,
1918 spr_read_generic
, &spr_write_generic
,
1920 spr_register(env
, SPR_USPRG7
, "USPRG7",
1921 &spr_read_ureg
, SPR_NOACCESS
,
1922 &spr_read_ureg
, SPR_NOACCESS
,
1926 /* SPR shared between PowerPC 401 & 403 implementations */
1927 static void gen_spr_401_403 (CPUPPCState
*env
)
1930 spr_register(env
, SPR_403_VTBL
, "TBL",
1931 &spr_read_tbl
, SPR_NOACCESS
,
1932 &spr_read_tbl
, SPR_NOACCESS
,
1934 spr_register(env
, SPR_403_TBL
, "TBL",
1935 SPR_NOACCESS
, SPR_NOACCESS
,
1936 SPR_NOACCESS
, &spr_write_tbl
,
1938 spr_register(env
, SPR_403_VTBU
, "TBU",
1939 &spr_read_tbu
, SPR_NOACCESS
,
1940 &spr_read_tbu
, SPR_NOACCESS
,
1942 spr_register(env
, SPR_403_TBU
, "TBU",
1943 SPR_NOACCESS
, SPR_NOACCESS
,
1944 SPR_NOACCESS
, &spr_write_tbu
,
1947 /* not emulated, as Qemu do not emulate caches */
1948 spr_register(env
, SPR_403_CDBCR
, "CDBCR",
1949 SPR_NOACCESS
, SPR_NOACCESS
,
1950 &spr_read_generic
, &spr_write_generic
,
1954 /* SPR specific to PowerPC 401 implementation */
1955 static void gen_spr_401 (CPUPPCState
*env
)
1957 /* Debug interface */
1958 /* XXX : not implemented */
1959 spr_register(env
, SPR_40x_DBCR0
, "DBCR",
1960 SPR_NOACCESS
, SPR_NOACCESS
,
1961 &spr_read_generic
, &spr_write_40x_dbcr0
,
1963 /* XXX : not implemented */
1964 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1965 SPR_NOACCESS
, SPR_NOACCESS
,
1966 &spr_read_generic
, &spr_write_clear
,
1967 /* Last reset was system reset */
1969 /* XXX : not implemented */
1970 spr_register(env
, SPR_40x_DAC1
, "DAC",
1971 SPR_NOACCESS
, SPR_NOACCESS
,
1972 &spr_read_generic
, &spr_write_generic
,
1974 /* XXX : not implemented */
1975 spr_register(env
, SPR_40x_IAC1
, "IAC",
1976 SPR_NOACCESS
, SPR_NOACCESS
,
1977 &spr_read_generic
, &spr_write_generic
,
1979 /* Storage control */
1980 /* XXX: TODO: not implemented */
1981 spr_register(env
, SPR_405_SLER
, "SLER",
1982 SPR_NOACCESS
, SPR_NOACCESS
,
1983 &spr_read_generic
, &spr_write_40x_sler
,
1985 /* not emulated, as Qemu never does speculative access */
1986 spr_register(env
, SPR_40x_SGR
, "SGR",
1987 SPR_NOACCESS
, SPR_NOACCESS
,
1988 &spr_read_generic
, &spr_write_generic
,
1990 /* not emulated, as Qemu do not emulate caches */
1991 spr_register(env
, SPR_40x_DCWR
, "DCWR",
1992 SPR_NOACCESS
, SPR_NOACCESS
,
1993 &spr_read_generic
, &spr_write_generic
,
1997 static void gen_spr_401x2 (CPUPPCState
*env
)
2000 spr_register(env
, SPR_40x_PID
, "PID",
2001 SPR_NOACCESS
, SPR_NOACCESS
,
2002 &spr_read_generic
, &spr_write_generic
,
2004 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2005 SPR_NOACCESS
, SPR_NOACCESS
,
2006 &spr_read_generic
, &spr_write_generic
,
2010 /* SPR specific to PowerPC 403 implementation */
2011 static void gen_spr_403 (CPUPPCState
*env
)
2013 /* Debug interface */
2014 /* XXX : not implemented */
2015 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
2016 SPR_NOACCESS
, SPR_NOACCESS
,
2017 &spr_read_generic
, &spr_write_40x_dbcr0
,
2019 /* XXX : not implemented */
2020 spr_register(env
, SPR_40x_DBSR
, "DBSR",
2021 SPR_NOACCESS
, SPR_NOACCESS
,
2022 &spr_read_generic
, &spr_write_clear
,
2023 /* Last reset was system reset */
2025 /* XXX : not implemented */
2026 spr_register(env
, SPR_40x_DAC1
, "DAC1",
2027 SPR_NOACCESS
, SPR_NOACCESS
,
2028 &spr_read_generic
, &spr_write_generic
,
2030 /* XXX : not implemented */
2031 spr_register(env
, SPR_40x_DAC2
, "DAC2",
2032 SPR_NOACCESS
, SPR_NOACCESS
,
2033 &spr_read_generic
, &spr_write_generic
,
2035 /* XXX : not implemented */
2036 spr_register(env
, SPR_40x_IAC1
, "IAC1",
2037 SPR_NOACCESS
, SPR_NOACCESS
,
2038 &spr_read_generic
, &spr_write_generic
,
2040 /* XXX : not implemented */
2041 spr_register(env
, SPR_40x_IAC2
, "IAC2",
2042 SPR_NOACCESS
, SPR_NOACCESS
,
2043 &spr_read_generic
, &spr_write_generic
,
2047 static void gen_spr_403_real (CPUPPCState
*env
)
2049 spr_register(env
, SPR_403_PBL1
, "PBL1",
2050 SPR_NOACCESS
, SPR_NOACCESS
,
2051 &spr_read_403_pbr
, &spr_write_403_pbr
,
2053 spr_register(env
, SPR_403_PBU1
, "PBU1",
2054 SPR_NOACCESS
, SPR_NOACCESS
,
2055 &spr_read_403_pbr
, &spr_write_403_pbr
,
2057 spr_register(env
, SPR_403_PBL2
, "PBL2",
2058 SPR_NOACCESS
, SPR_NOACCESS
,
2059 &spr_read_403_pbr
, &spr_write_403_pbr
,
2061 spr_register(env
, SPR_403_PBU2
, "PBU2",
2062 SPR_NOACCESS
, SPR_NOACCESS
,
2063 &spr_read_403_pbr
, &spr_write_403_pbr
,
2067 static void gen_spr_403_mmu (CPUPPCState
*env
)
2070 spr_register(env
, SPR_40x_PID
, "PID",
2071 SPR_NOACCESS
, SPR_NOACCESS
,
2072 &spr_read_generic
, &spr_write_generic
,
2074 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2075 SPR_NOACCESS
, SPR_NOACCESS
,
2076 &spr_read_generic
, &spr_write_generic
,
2080 /* SPR specific to PowerPC compression coprocessor extension */
2081 static void gen_spr_compress (CPUPPCState
*env
)
2083 /* XXX : not implemented */
2084 spr_register(env
, SPR_401_SKR
, "SKR",
2085 SPR_NOACCESS
, SPR_NOACCESS
,
2086 &spr_read_generic
, &spr_write_generic
,
2090 #if defined (TARGET_PPC64)
2091 /* SPR specific to PowerPC 620 */
2092 static void gen_spr_620 (CPUPPCState
*env
)
2094 /* XXX : not implemented */
2095 spr_register(env
, SPR_620_PMR0
, "PMR0",
2096 SPR_NOACCESS
, SPR_NOACCESS
,
2097 &spr_read_generic
, &spr_write_generic
,
2099 /* XXX : not implemented */
2100 spr_register(env
, SPR_620_PMR1
, "PMR1",
2101 SPR_NOACCESS
, SPR_NOACCESS
,
2102 &spr_read_generic
, &spr_write_generic
,
2104 /* XXX : not implemented */
2105 spr_register(env
, SPR_620_PMR2
, "PMR2",
2106 SPR_NOACCESS
, SPR_NOACCESS
,
2107 &spr_read_generic
, &spr_write_generic
,
2109 /* XXX : not implemented */
2110 spr_register(env
, SPR_620_PMR3
, "PMR3",
2111 SPR_NOACCESS
, SPR_NOACCESS
,
2112 &spr_read_generic
, &spr_write_generic
,
2114 /* XXX : not implemented */
2115 spr_register(env
, SPR_620_PMR4
, "PMR4",
2116 SPR_NOACCESS
, SPR_NOACCESS
,
2117 &spr_read_generic
, &spr_write_generic
,
2119 /* XXX : not implemented */
2120 spr_register(env
, SPR_620_PMR5
, "PMR5",
2121 SPR_NOACCESS
, SPR_NOACCESS
,
2122 &spr_read_generic
, &spr_write_generic
,
2124 /* XXX : not implemented */
2125 spr_register(env
, SPR_620_PMR6
, "PMR6",
2126 SPR_NOACCESS
, SPR_NOACCESS
,
2127 &spr_read_generic
, &spr_write_generic
,
2129 /* XXX : not implemented */
2130 spr_register(env
, SPR_620_PMR7
, "PMR7",
2131 SPR_NOACCESS
, SPR_NOACCESS
,
2132 &spr_read_generic
, &spr_write_generic
,
2134 /* XXX : not implemented */
2135 spr_register(env
, SPR_620_PMR8
, "PMR8",
2136 SPR_NOACCESS
, SPR_NOACCESS
,
2137 &spr_read_generic
, &spr_write_generic
,
2139 /* XXX : not implemented */
2140 spr_register(env
, SPR_620_PMR9
, "PMR9",
2141 SPR_NOACCESS
, SPR_NOACCESS
,
2142 &spr_read_generic
, &spr_write_generic
,
2144 /* XXX : not implemented */
2145 spr_register(env
, SPR_620_PMRA
, "PMR10",
2146 SPR_NOACCESS
, SPR_NOACCESS
,
2147 &spr_read_generic
, &spr_write_generic
,
2149 /* XXX : not implemented */
2150 spr_register(env
, SPR_620_PMRB
, "PMR11",
2151 SPR_NOACCESS
, SPR_NOACCESS
,
2152 &spr_read_generic
, &spr_write_generic
,
2154 /* XXX : not implemented */
2155 spr_register(env
, SPR_620_PMRC
, "PMR12",
2156 SPR_NOACCESS
, SPR_NOACCESS
,
2157 &spr_read_generic
, &spr_write_generic
,
2159 /* XXX : not implemented */
2160 spr_register(env
, SPR_620_PMRD
, "PMR13",
2161 SPR_NOACCESS
, SPR_NOACCESS
,
2162 &spr_read_generic
, &spr_write_generic
,
2164 /* XXX : not implemented */
2165 spr_register(env
, SPR_620_PMRE
, "PMR14",
2166 SPR_NOACCESS
, SPR_NOACCESS
,
2167 &spr_read_generic
, &spr_write_generic
,
2169 /* XXX : not implemented */
2170 spr_register(env
, SPR_620_PMRF
, "PMR15",
2171 SPR_NOACCESS
, SPR_NOACCESS
,
2172 &spr_read_generic
, &spr_write_generic
,
2174 /* XXX : not implemented */
2175 spr_register(env
, SPR_620_HID8
, "HID8",
2176 SPR_NOACCESS
, SPR_NOACCESS
,
2177 &spr_read_generic
, &spr_write_generic
,
2179 /* XXX : not implemented */
2180 spr_register(env
, SPR_620_HID9
, "HID9",
2181 SPR_NOACCESS
, SPR_NOACCESS
,
2182 &spr_read_generic
, &spr_write_generic
,
2185 #endif /* defined (TARGET_PPC64) */
2189 * AMR => SPR 29 (Power 2.04)
2190 * CTRL => SPR 136 (Power 2.04)
2191 * CTRL => SPR 152 (Power 2.04)
2192 * SCOMC => SPR 276 (64 bits ?)
2193 * SCOMD => SPR 277 (64 bits ?)
2194 * TBU40 => SPR 286 (Power 2.04 hypv)
2195 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2196 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2197 * HDSISR => SPR 306 (Power 2.04 hypv)
2198 * HDAR => SPR 307 (Power 2.04 hypv)
2199 * PURR => SPR 309 (Power 2.04 hypv)
2200 * HDEC => SPR 310 (Power 2.04 hypv)
2201 * HIOR => SPR 311 (hypv)
2202 * RMOR => SPR 312 (970)
2203 * HRMOR => SPR 313 (Power 2.04 hypv)
2204 * HSRR0 => SPR 314 (Power 2.04 hypv)
2205 * HSRR1 => SPR 315 (Power 2.04 hypv)
2206 * LPCR => SPR 316 (970)
2207 * LPIDR => SPR 317 (970)
2208 * SPEFSCR => SPR 512 (Power 2.04 emb)
2209 * EPR => SPR 702 (Power 2.04 emb)
2210 * perf => 768-783 (Power 2.04)
2211 * perf => 784-799 (Power 2.04)
2212 * PPR => SPR 896 (Power 2.04)
2213 * EPLC => SPR 947 (Power 2.04 emb)
2214 * EPSC => SPR 948 (Power 2.04 emb)
2215 * DABRX => 1015 (Power 2.04 hypv)
2216 * FPECR => SPR 1022 (?)
2217 * ... and more (thermal management, performance counters, ...)
2220 /*****************************************************************************/
2221 /* Exception vectors models */
2222 static void init_excp_4xx_real (CPUPPCState
*env
)
2224 #if !defined(CONFIG_USER_ONLY)
2225 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2226 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2227 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2228 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2229 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2230 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2231 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2232 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2233 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2234 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2235 env
->excp_prefix
= 0x00000000;
2236 env
->ivor_mask
= 0x0000FFF0;
2237 env
->ivpr_mask
= 0xFFFF0000;
2241 static void init_excp_4xx_softmmu (CPUPPCState
*env
)
2243 #if !defined(CONFIG_USER_ONLY)
2244 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2245 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2246 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2247 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2248 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2249 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2250 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2251 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2252 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2253 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2254 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2255 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001100;
2256 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001200;
2257 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2258 env
->excp_prefix
= 0x00000000;
2259 env
->ivor_mask
= 0x0000FFF0;
2260 env
->ivpr_mask
= 0xFFFF0000;
2264 static void init_excp_BookE (CPUPPCState
*env
)
2266 #if !defined(CONFIG_USER_ONLY)
2267 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
2268 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
2269 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
2270 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
2271 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
2272 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
2273 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
2274 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
2275 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
2276 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
2277 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
2278 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
2279 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
2280 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
2281 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
2282 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
2283 env
->excp_prefix
= 0x00000000;
2284 env
->ivor_mask
= 0x0000FFE0;
2285 env
->ivpr_mask
= 0xFFFF0000;
2289 static void init_excp_601 (CPUPPCState
*env
)
2291 #if !defined(CONFIG_USER_ONLY)
2292 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2293 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2294 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2295 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2296 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2297 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2298 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2299 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2300 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2301 env
->excp_vectors
[POWERPC_EXCP_IO
] = 0x00000A00;
2302 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2303 env
->excp_vectors
[POWERPC_EXCP_RUNM
] = 0x00002000;
2304 env
->excp_prefix
= 0xFFF00000;
2308 static void init_excp_602 (CPUPPCState
*env
)
2310 #if !defined(CONFIG_USER_ONLY)
2311 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2312 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2313 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2314 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2315 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2316 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2317 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2318 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2319 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2320 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2321 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2322 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2323 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2324 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2325 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2326 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2327 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2328 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001500;
2329 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001600;
2330 env
->excp_prefix
= 0xFFF00000;
2334 static void init_excp_603 (CPUPPCState
*env
)
2336 #if !defined(CONFIG_USER_ONLY)
2337 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2338 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2339 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2340 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2341 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2342 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2343 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2344 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2345 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2346 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2347 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2348 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2349 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2350 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2351 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2352 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2356 static void init_excp_G2 (CPUPPCState
*env
)
2358 #if !defined(CONFIG_USER_ONLY)
2359 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2360 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2361 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2362 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2363 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2364 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2365 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2366 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2367 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2368 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000A00;
2369 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2370 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2371 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2372 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2373 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2374 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2375 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2379 static void init_excp_604 (CPUPPCState
*env
)
2381 #if !defined(CONFIG_USER_ONLY)
2382 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2383 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2384 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2385 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2386 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2387 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2388 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2389 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2390 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2391 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2392 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2393 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2394 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2395 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2399 #if defined(TARGET_PPC64)
2400 static void init_excp_620 (CPUPPCState
*env
)
2402 #if !defined(CONFIG_USER_ONLY)
2403 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2404 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2405 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2406 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2407 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2408 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2409 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2410 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2411 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2412 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2413 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2414 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2415 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2416 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2417 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2420 #endif /* defined(TARGET_PPC64) */
2422 static void init_excp_7x0 (CPUPPCState
*env
)
2424 #if !defined(CONFIG_USER_ONLY)
2425 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2426 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2427 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2428 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2429 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2430 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2431 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2432 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2433 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2434 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2435 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2436 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2437 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2438 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2442 static void init_excp_750FX (CPUPPCState
*env
)
2444 #if !defined(CONFIG_USER_ONLY)
2445 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2446 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2447 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2448 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2449 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2450 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2451 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2452 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2453 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2454 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2455 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2456 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2457 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2458 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2459 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2463 static void init_excp_7400 (CPUPPCState
*env
)
2465 #if !defined(CONFIG_USER_ONLY)
2466 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2467 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2468 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2469 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2470 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2471 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2472 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2473 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2474 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2475 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2476 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2477 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2478 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2479 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2480 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2481 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
2482 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2486 static void init_excp_7450 (CPUPPCState
*env
)
2488 #if !defined(CONFIG_USER_ONLY)
2489 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2490 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2491 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2492 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2493 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2494 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2495 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2496 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2497 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2498 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2499 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2500 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2501 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2502 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2503 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2504 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2505 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2506 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2507 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
2511 #if defined (TARGET_PPC64)
2512 static void init_excp_970 (CPUPPCState
*env
)
2514 #if !defined(CONFIG_USER_ONLY)
2515 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2516 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2517 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2518 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
2519 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2520 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
2521 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2522 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2523 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2524 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2525 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2526 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2527 env
->excp_vectors
[POWERPC_EXCP_HDECR
] = 0x00000980;
2529 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2530 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2531 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2532 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2533 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2534 env
->excp_vectors
[POWERPC_EXCP_MAINT
] = 0x00001600;
2535 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001700;
2536 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001800;
2541 /*****************************************************************************/
2542 /* PowerPC implementations definitions */
2544 /* PowerPC 40x instruction set */
2545 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
2548 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2549 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2550 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2551 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2552 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2553 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2554 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2555 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2557 static void init_proc_401 (CPUPPCState
*env
)
2560 gen_spr_401_403(env
);
2562 init_excp_4xx_real(env
);
2563 /* Allocate hardware IRQ controller */
2564 ppc40x_irq_init(env
);
2568 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2569 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2570 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2571 PPC_CACHE_DCBA | PPC_MFTB | \
2572 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2573 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2574 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2575 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2576 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2577 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2579 static void init_proc_401x2 (CPUPPCState
*env
)
2582 gen_spr_401_403(env
);
2584 gen_spr_compress(env
);
2585 /* Memory management */
2589 init_excp_4xx_softmmu(env
);
2590 /* Allocate hardware IRQ controller */
2591 ppc40x_irq_init(env
);
2595 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2596 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2597 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2598 PPC_CACHE_DCBA | PPC_MFTB | \
2599 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2600 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2601 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2602 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2603 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2604 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2606 __attribute__ (( unused
))
2607 static void init_proc_401x3 (CPUPPCState
*env
)
2610 gen_spr_401_403(env
);
2613 gen_spr_compress(env
);
2614 init_excp_4xx_softmmu(env
);
2615 /* Allocate hardware IRQ controller */
2616 ppc40x_irq_init(env
);
2620 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2621 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2622 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2624 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2625 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2626 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2627 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2628 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2629 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2631 static void init_proc_IOP480 (CPUPPCState
*env
)
2634 gen_spr_401_403(env
);
2636 gen_spr_compress(env
);
2637 /* Memory management */
2641 init_excp_4xx_softmmu(env
);
2642 /* Allocate hardware IRQ controller */
2643 ppc40x_irq_init(env
);
2647 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2648 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2649 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2650 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2651 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2652 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2653 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2654 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2655 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2657 static void init_proc_403 (CPUPPCState
*env
)
2660 gen_spr_401_403(env
);
2662 gen_spr_403_real(env
);
2663 init_excp_4xx_real(env
);
2664 /* Allocate hardware IRQ controller */
2665 ppc40x_irq_init(env
);
2668 /* PowerPC 403 GCX */
2669 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2670 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2671 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2672 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2673 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2674 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2675 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2676 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2677 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2679 static void init_proc_403GCX (CPUPPCState
*env
)
2682 gen_spr_401_403(env
);
2684 gen_spr_403_real(env
);
2685 gen_spr_403_mmu(env
);
2686 /* Bus access control */
2687 /* not emulated, as Qemu never does speculative access */
2688 spr_register(env
, SPR_40x_SGR
, "SGR",
2689 SPR_NOACCESS
, SPR_NOACCESS
,
2690 &spr_read_generic
, &spr_write_generic
,
2692 /* not emulated, as Qemu do not emulate caches */
2693 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2694 SPR_NOACCESS
, SPR_NOACCESS
,
2695 &spr_read_generic
, &spr_write_generic
,
2697 /* Memory management */
2701 init_excp_4xx_softmmu(env
);
2702 /* Allocate hardware IRQ controller */
2703 ppc40x_irq_init(env
);
2707 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2708 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2709 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2710 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2712 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2713 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2714 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2715 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2716 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2718 static void init_proc_405 (CPUPPCState
*env
)
2724 /* Bus access control */
2725 /* not emulated, as Qemu never does speculative access */
2726 spr_register(env
, SPR_40x_SGR
, "SGR",
2727 SPR_NOACCESS
, SPR_NOACCESS
,
2728 &spr_read_generic
, &spr_write_generic
,
2730 /* not emulated, as Qemu do not emulate caches */
2731 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2732 SPR_NOACCESS
, SPR_NOACCESS
,
2733 &spr_read_generic
, &spr_write_generic
,
2735 /* Memory management */
2739 init_excp_4xx_softmmu(env
);
2740 /* Allocate hardware IRQ controller */
2741 ppc40x_irq_init(env
);
2744 /* PowerPC 440 EP */
2745 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2746 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2747 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2748 PPC_440_SPEC | PPC_RFMCI)
2749 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2750 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2751 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2752 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2753 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2755 static void init_proc_440EP (CPUPPCState
*env
)
2761 /* XXX : not implemented */
2762 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2763 SPR_NOACCESS
, SPR_NOACCESS
,
2764 &spr_read_generic
, &spr_write_generic
,
2766 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2767 SPR_NOACCESS
, SPR_NOACCESS
,
2768 &spr_read_generic
, &spr_write_generic
,
2770 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2771 SPR_NOACCESS
, SPR_NOACCESS
,
2772 &spr_read_generic
, &spr_write_generic
,
2774 /* XXX : not implemented */
2775 spr_register(env
, SPR_440_CCR1
, "CCR1",
2776 SPR_NOACCESS
, SPR_NOACCESS
,
2777 &spr_read_generic
, &spr_write_generic
,
2779 /* Memory management */
2783 init_excp_BookE(env
);
2784 /* XXX: TODO: allocate internal IRQ controller */
2787 /* PowerPC 440 GP */
2788 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2789 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2790 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2791 PPC_405_MAC | PPC_440_SPEC)
2792 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2793 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2794 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2795 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2796 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2798 static void init_proc_440GP (CPUPPCState
*env
)
2804 /* Memory management */
2808 init_excp_BookE(env
);
2809 /* XXX: TODO: allocate internal IRQ controller */
2813 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2814 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2815 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2817 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2818 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2819 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2820 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2821 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2823 __attribute__ (( unused
))
2824 static void init_proc_440x4 (CPUPPCState
*env
)
2830 /* Memory management */
2834 init_excp_BookE(env
);
2835 /* XXX: TODO: allocate internal IRQ controller */
2839 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2840 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2841 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2842 PPC_440_SPEC | PPC_RFMCI)
2843 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2844 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2845 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2846 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
2847 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
2849 static void init_proc_440x5 (CPUPPCState
*env
)
2855 /* XXX : not implemented */
2856 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2857 SPR_NOACCESS
, SPR_NOACCESS
,
2858 &spr_read_generic
, &spr_write_generic
,
2860 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2861 SPR_NOACCESS
, SPR_NOACCESS
,
2862 &spr_read_generic
, &spr_write_generic
,
2864 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2865 SPR_NOACCESS
, SPR_NOACCESS
,
2866 &spr_read_generic
, &spr_write_generic
,
2868 /* XXX : not implemented */
2869 spr_register(env
, SPR_440_CCR1
, "CCR1",
2870 SPR_NOACCESS
, SPR_NOACCESS
,
2871 &spr_read_generic
, &spr_write_generic
,
2873 /* Memory management */
2877 init_excp_BookE(env
);
2878 /* XXX: TODO: allocate internal IRQ controller */
2881 /* PowerPC 460 (guessed) */
2882 #define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
2883 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2884 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2885 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2886 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2887 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
2888 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
2889 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
2890 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
2892 __attribute__ (( unused
))
2893 static void init_proc_460 (CPUPPCState
*env
)
2899 /* XXX : not implemented */
2900 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2901 SPR_NOACCESS
, SPR_NOACCESS
,
2902 &spr_read_generic
, &spr_write_generic
,
2904 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2905 SPR_NOACCESS
, SPR_NOACCESS
,
2906 &spr_read_generic
, &spr_write_generic
,
2908 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2909 SPR_NOACCESS
, SPR_NOACCESS
,
2910 &spr_read_generic
, &spr_write_generic
,
2912 /* XXX : not implemented */
2913 spr_register(env
, SPR_440_CCR1
, "CCR1",
2914 SPR_NOACCESS
, SPR_NOACCESS
,
2915 &spr_read_generic
, &spr_write_generic
,
2917 /* XXX : not implemented */
2918 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
2919 &spr_read_generic
, &spr_write_generic
,
2920 &spr_read_generic
, &spr_write_generic
,
2922 /* Memory management */
2926 init_excp_BookE(env
);
2927 /* XXX: TODO: allocate internal IRQ controller */
2930 /* PowerPC 460F (guessed) */
2931 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2932 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2933 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
2934 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
2935 PPC_FLOAT_STFIWX | \
2936 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2937 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2938 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2939 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
2940 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
2941 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
2942 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
2944 __attribute__ (( unused
))
2945 static void init_proc_460F (CPUPPCState
*env
)
2951 /* XXX : not implemented */
2952 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2953 SPR_NOACCESS
, SPR_NOACCESS
,
2954 &spr_read_generic
, &spr_write_generic
,
2956 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2957 SPR_NOACCESS
, SPR_NOACCESS
,
2958 &spr_read_generic
, &spr_write_generic
,
2960 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2961 SPR_NOACCESS
, SPR_NOACCESS
,
2962 &spr_read_generic
, &spr_write_generic
,
2964 /* XXX : not implemented */
2965 spr_register(env
, SPR_440_CCR1
, "CCR1",
2966 SPR_NOACCESS
, SPR_NOACCESS
,
2967 &spr_read_generic
, &spr_write_generic
,
2969 /* XXX : not implemented */
2970 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
2971 &spr_read_generic
, &spr_write_generic
,
2972 &spr_read_generic
, &spr_write_generic
,
2974 /* Memory management */
2978 init_excp_BookE(env
);
2979 /* XXX: TODO: allocate internal IRQ controller */
2982 /* Generic BookE PowerPC */
2983 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
2984 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2986 PPC_FLOAT | PPC_FLOAT_FSQRT | \
2987 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2988 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
2990 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
2991 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
2992 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
2993 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
2994 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
2996 __attribute__ (( unused
))
2997 static void init_proc_BookE (CPUPPCState
*env
)
2999 init_excp_BookE(env
);
3007 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3008 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3010 PPC_BOOKE | PPC_E500_VECTOR)
3011 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3012 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3013 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
3014 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
3016 __attribute__ (( unused
))
3017 static void init_proc_e500 (CPUPPCState
*env
)
3022 /* Memory management */
3023 gen_spr_BookE_FSL(env
);
3027 init_excp_BookE(env
);
3028 /* XXX: TODO: allocate internal IRQ controller */
3033 /* Non-embedded PowerPC */
3034 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3035 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
3036 PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
3037 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3038 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3039 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3040 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3041 PPC_MEM_TLBSYNC | PPC_MFTB)
3043 /* POWER : same as 601, without mfmsr, mfsr */
3045 #define POWERPC_INSNS_POWER (XXX_TODO)
3046 /* POWER RSC (from RAD6000) */
3047 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3051 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_EXTERN | PPC_POWER_BR)
3052 #define POWERPC_MSRM_601 (0x000000000000FE70ULL)
3053 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
3054 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3055 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
3056 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
3058 static void init_proc_601 (CPUPPCState
*env
)
3060 gen_spr_ne_601(env
);
3062 /* Hardware implementation registers */
3063 /* XXX : not implemented */
3064 spr_register(env
, SPR_HID0
, "HID0",
3065 SPR_NOACCESS
, SPR_NOACCESS
,
3066 &spr_read_generic
, &spr_write_generic
,
3068 /* XXX : not implemented */
3069 spr_register(env
, SPR_HID1
, "HID1",
3070 SPR_NOACCESS
, SPR_NOACCESS
,
3071 &spr_read_generic
, &spr_write_generic
,
3073 /* XXX : not implemented */
3074 spr_register(env
, SPR_601_HID2
, "HID2",
3075 SPR_NOACCESS
, SPR_NOACCESS
,
3076 &spr_read_generic
, &spr_write_generic
,
3078 /* XXX : not implemented */
3079 spr_register(env
, SPR_601_HID5
, "HID5",
3080 SPR_NOACCESS
, SPR_NOACCESS
,
3081 &spr_read_generic
, &spr_write_generic
,
3083 /* XXX : not implemented */
3084 spr_register(env
, SPR_601_HID15
, "HID15",
3085 SPR_NOACCESS
, SPR_NOACCESS
,
3086 &spr_read_generic
, &spr_write_generic
,
3088 /* Memory management */
3094 /* XXX: TODO: allocate internal IRQ controller */
3098 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3099 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3100 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3101 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_602_SPEC)
3102 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3103 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3104 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3105 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
3106 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
3108 static void init_proc_602 (CPUPPCState
*env
)
3110 gen_spr_ne_601(env
);
3114 /* hardware implementation registers */
3115 /* XXX : not implemented */
3116 spr_register(env
, SPR_HID0
, "HID0",
3117 SPR_NOACCESS
, SPR_NOACCESS
,
3118 &spr_read_generic
, &spr_write_generic
,
3120 /* XXX : not implemented */
3121 spr_register(env
, SPR_HID1
, "HID1",
3122 SPR_NOACCESS
, SPR_NOACCESS
,
3123 &spr_read_generic
, &spr_write_generic
,
3125 /* Memory management */
3127 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3129 /* Allocate hardware IRQ controller */
3130 ppc6xx_irq_init(env
);
3134 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3135 #define POWERPC_MSRM_603 (0x000000000001FF73ULL)
3136 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3137 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3138 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
3139 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
3141 static void init_proc_603 (CPUPPCState
*env
)
3143 gen_spr_ne_601(env
);
3147 /* hardware implementation registers */
3148 /* XXX : not implemented */
3149 spr_register(env
, SPR_HID0
, "HID0",
3150 SPR_NOACCESS
, SPR_NOACCESS
,
3151 &spr_read_generic
, &spr_write_generic
,
3153 /* XXX : not implemented */
3154 spr_register(env
, SPR_HID1
, "HID1",
3155 SPR_NOACCESS
, SPR_NOACCESS
,
3156 &spr_read_generic
, &spr_write_generic
,
3158 /* Memory management */
3160 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3162 /* Allocate hardware IRQ controller */
3163 ppc6xx_irq_init(env
);
3167 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3168 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3169 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3170 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3171 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
3172 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
3174 static void init_proc_603E (CPUPPCState
*env
)
3176 gen_spr_ne_601(env
);
3180 /* hardware implementation registers */
3181 /* XXX : not implemented */
3182 spr_register(env
, SPR_HID0
, "HID0",
3183 SPR_NOACCESS
, SPR_NOACCESS
,
3184 &spr_read_generic
, &spr_write_generic
,
3186 /* XXX : not implemented */
3187 spr_register(env
, SPR_HID1
, "HID1",
3188 SPR_NOACCESS
, SPR_NOACCESS
,
3189 &spr_read_generic
, &spr_write_generic
,
3191 /* XXX : not implemented */
3192 spr_register(env
, SPR_IABR
, "IABR",
3193 SPR_NOACCESS
, SPR_NOACCESS
,
3194 &spr_read_generic
, &spr_write_generic
,
3196 /* Memory management */
3198 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3200 /* Allocate hardware IRQ controller */
3201 ppc6xx_irq_init(env
);
3205 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3206 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3207 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3208 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3209 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3210 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3212 static void init_proc_G2 (CPUPPCState
*env
)
3214 gen_spr_ne_601(env
);
3215 gen_spr_G2_755(env
);
3219 /* Hardware implementation register */
3220 /* XXX : not implemented */
3221 spr_register(env
, SPR_HID0
, "HID0",
3222 SPR_NOACCESS
, SPR_NOACCESS
,
3223 &spr_read_generic
, &spr_write_generic
,
3225 /* XXX : not implemented */
3226 spr_register(env
, SPR_HID1
, "HID1",
3227 SPR_NOACCESS
, SPR_NOACCESS
,
3228 &spr_read_generic
, &spr_write_generic
,
3230 /* XXX : not implemented */
3231 spr_register(env
, SPR_HID2
, "HID2",
3232 SPR_NOACCESS
, SPR_NOACCESS
,
3233 &spr_read_generic
, &spr_write_generic
,
3235 /* Memory management */
3238 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3240 /* Allocate hardware IRQ controller */
3241 ppc6xx_irq_init(env
);
3245 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3246 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3247 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3248 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3249 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3250 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3252 static void init_proc_G2LE (CPUPPCState
*env
)
3254 gen_spr_ne_601(env
);
3255 gen_spr_G2_755(env
);
3259 /* Hardware implementation register */
3260 /* XXX : not implemented */
3261 spr_register(env
, SPR_HID0
, "HID0",
3262 SPR_NOACCESS
, SPR_NOACCESS
,
3263 &spr_read_generic
, &spr_write_generic
,
3265 /* XXX : not implemented */
3266 spr_register(env
, SPR_HID1
, "HID1",
3267 SPR_NOACCESS
, SPR_NOACCESS
,
3268 &spr_read_generic
, &spr_write_generic
,
3270 /* XXX : not implemented */
3271 spr_register(env
, SPR_HID2
, "HID2",
3272 SPR_NOACCESS
, SPR_NOACCESS
,
3273 &spr_read_generic
, &spr_write_generic
,
3275 /* Memory management */
3278 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3280 /* Allocate hardware IRQ controller */
3281 ppc6xx_irq_init(env
);
3285 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3286 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3287 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
3288 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3289 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
3290 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
3292 static void init_proc_604 (CPUPPCState
*env
)
3294 gen_spr_ne_601(env
);
3298 /* Hardware implementation registers */
3299 /* XXX : not implemented */
3300 spr_register(env
, SPR_HID0
, "HID0",
3301 SPR_NOACCESS
, SPR_NOACCESS
,
3302 &spr_read_generic
, &spr_write_generic
,
3304 /* XXX : not implemented */
3305 spr_register(env
, SPR_HID1
, "HID1",
3306 SPR_NOACCESS
, SPR_NOACCESS
,
3307 &spr_read_generic
, &spr_write_generic
,
3309 /* Memory management */
3312 /* Allocate hardware IRQ controller */
3313 ppc6xx_irq_init(env
);
3316 /* PowerPC 740/750 (aka G3) */
3317 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3318 #define POWERPC_MSRM_7x0 (0x000000000007FF77ULL)
3319 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3320 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3321 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
3322 #define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
3324 static void init_proc_7x0 (CPUPPCState
*env
)
3326 gen_spr_ne_601(env
);
3330 /* Thermal management */
3332 /* Hardware implementation registers */
3333 /* XXX : not implemented */
3334 spr_register(env
, SPR_HID0
, "HID0",
3335 SPR_NOACCESS
, SPR_NOACCESS
,
3336 &spr_read_generic
, &spr_write_generic
,
3338 /* XXX : not implemented */
3339 spr_register(env
, SPR_HID1
, "HID1",
3340 SPR_NOACCESS
, SPR_NOACCESS
,
3341 &spr_read_generic
, &spr_write_generic
,
3343 /* Memory management */
3346 /* Allocate hardware IRQ controller */
3347 ppc6xx_irq_init(env
);
3350 /* PowerPC 750FX/GX */
3351 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3352 #define POWERPC_MSRM_750fx (0x000000000007FF77ULL)
3353 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3354 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3355 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
3356 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
3358 static void init_proc_750fx (CPUPPCState
*env
)
3360 gen_spr_ne_601(env
);
3364 /* Thermal management */
3366 /* Hardware implementation registers */
3367 /* XXX : not implemented */
3368 spr_register(env
, SPR_HID0
, "HID0",
3369 SPR_NOACCESS
, SPR_NOACCESS
,
3370 &spr_read_generic
, &spr_write_generic
,
3372 /* XXX : not implemented */
3373 spr_register(env
, SPR_HID1
, "HID1",
3374 SPR_NOACCESS
, SPR_NOACCESS
,
3375 &spr_read_generic
, &spr_write_generic
,
3377 /* XXX : not implemented */
3378 spr_register(env
, SPR_750_HID2
, "HID2",
3379 SPR_NOACCESS
, SPR_NOACCESS
,
3380 &spr_read_generic
, &spr_write_generic
,
3382 /* Memory management */
3384 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3386 init_excp_750FX(env
);
3387 /* Allocate hardware IRQ controller */
3388 ppc6xx_irq_init(env
);
3391 /* PowerPC 745/755 */
3392 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3393 #define POWERPC_MSRM_7x5 (0x000000000007FF77ULL)
3394 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3395 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3396 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
3397 #define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
3399 static void init_proc_7x5 (CPUPPCState
*env
)
3401 gen_spr_ne_601(env
);
3402 gen_spr_G2_755(env
);
3405 /* L2 cache control */
3406 /* XXX : not implemented */
3407 spr_register(env
, SPR_ICTC
, "ICTC",
3408 SPR_NOACCESS
, SPR_NOACCESS
,
3409 &spr_read_generic
, &spr_write_generic
,
3411 /* XXX : not implemented */
3412 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
3413 SPR_NOACCESS
, SPR_NOACCESS
,
3414 &spr_read_generic
, &spr_write_generic
,
3416 /* Hardware implementation registers */
3417 /* XXX : not implemented */
3418 spr_register(env
, SPR_HID0
, "HID0",
3419 SPR_NOACCESS
, SPR_NOACCESS
,
3420 &spr_read_generic
, &spr_write_generic
,
3422 /* XXX : not implemented */
3423 spr_register(env
, SPR_HID1
, "HID1",
3424 SPR_NOACCESS
, SPR_NOACCESS
,
3425 &spr_read_generic
, &spr_write_generic
,
3427 /* XXX : not implemented */
3428 spr_register(env
, SPR_HID2
, "HID2",
3429 SPR_NOACCESS
, SPR_NOACCESS
,
3430 &spr_read_generic
, &spr_write_generic
,
3432 /* Memory management */
3435 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3436 /* Allocate hardware IRQ controller */
3437 ppc6xx_irq_init(env
);
3440 /* PowerPC 7400 (aka G4) */
3441 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3442 PPC_EXTERN | PPC_MEM_TLBIA | \
3444 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3445 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3446 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3447 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
3448 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
3450 static void init_proc_7400 (CPUPPCState
*env
)
3452 gen_spr_ne_601(env
);
3456 /* 74xx specific SPR */
3458 /* Thermal management */
3460 /* Memory management */
3462 init_excp_7400(env
);
3463 /* Allocate hardware IRQ controller */
3464 ppc6xx_irq_init(env
);
3467 /* PowerPC 7410 (aka G4) */
3468 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3469 PPC_EXTERN | PPC_MEM_TLBIA | \
3471 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3472 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3473 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3474 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3475 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
3477 static void init_proc_7410 (CPUPPCState
*env
)
3479 gen_spr_ne_601(env
);
3483 /* 74xx specific SPR */
3485 /* Thermal management */
3488 /* XXX : not implemented */
3489 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
3490 SPR_NOACCESS
, SPR_NOACCESS
,
3491 &spr_read_generic
, &spr_write_generic
,
3494 /* XXX : not implemented */
3495 spr_register(env
, SPR_LDSTDB
, "LDSTDB",
3496 SPR_NOACCESS
, SPR_NOACCESS
,
3497 &spr_read_generic
, &spr_write_generic
,
3499 /* Memory management */
3501 init_excp_7400(env
);
3502 /* Allocate hardware IRQ controller */
3503 ppc6xx_irq_init(env
);
3506 /* PowerPC 7440 (aka G4) */
3507 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3508 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3510 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3511 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3512 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3513 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3514 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3516 __attribute__ (( unused
))
3517 static void init_proc_7440 (CPUPPCState
*env
)
3519 gen_spr_ne_601(env
);
3523 /* 74xx specific SPR */
3526 /* XXX : not implemented */
3527 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3528 SPR_NOACCESS
, SPR_NOACCESS
,
3529 &spr_read_generic
, &spr_write_generic
,
3532 /* XXX : not implemented */
3533 spr_register(env
, SPR_ICTRL
, "ICTRL",
3534 SPR_NOACCESS
, SPR_NOACCESS
,
3535 &spr_read_generic
, &spr_write_generic
,
3538 /* XXX : not implemented */
3539 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3540 SPR_NOACCESS
, SPR_NOACCESS
,
3541 &spr_read_generic
, &spr_write_generic
,
3544 /* XXX : not implemented */
3545 spr_register(env
, SPR_PMC5
, "PMC5",
3546 SPR_NOACCESS
, SPR_NOACCESS
,
3547 &spr_read_generic
, &spr_write_generic
,
3549 /* XXX : not implemented */
3550 spr_register(env
, SPR_UPMC5
, "UPMC5",
3551 &spr_read_ureg
, SPR_NOACCESS
,
3552 &spr_read_ureg
, SPR_NOACCESS
,
3554 /* XXX : not implemented */
3555 spr_register(env
, SPR_PMC6
, "PMC6",
3556 SPR_NOACCESS
, SPR_NOACCESS
,
3557 &spr_read_generic
, &spr_write_generic
,
3559 /* XXX : not implemented */
3560 spr_register(env
, SPR_UPMC6
, "UPMC6",
3561 &spr_read_ureg
, SPR_NOACCESS
,
3562 &spr_read_ureg
, SPR_NOACCESS
,
3564 /* Memory management */
3566 gen_74xx_soft_tlb(env
, 128, 2);
3567 /* Allocate hardware IRQ controller */
3568 ppc6xx_irq_init(env
);
3571 /* PowerPC 7450 (aka G4) */
3572 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3573 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3575 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3576 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3577 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3578 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3579 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3581 __attribute__ (( unused
))
3582 static void init_proc_7450 (CPUPPCState
*env
)
3584 gen_spr_ne_601(env
);
3588 /* 74xx specific SPR */
3590 /* Level 3 cache control */
3593 /* XXX : not implemented */
3594 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3595 SPR_NOACCESS
, SPR_NOACCESS
,
3596 &spr_read_generic
, &spr_write_generic
,
3599 /* XXX : not implemented */
3600 spr_register(env
, SPR_ICTRL
, "ICTRL",
3601 SPR_NOACCESS
, SPR_NOACCESS
,
3602 &spr_read_generic
, &spr_write_generic
,
3605 /* XXX : not implemented */
3606 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3607 SPR_NOACCESS
, SPR_NOACCESS
,
3608 &spr_read_generic
, &spr_write_generic
,
3611 /* XXX : not implemented */
3612 spr_register(env
, SPR_PMC5
, "PMC5",
3613 SPR_NOACCESS
, SPR_NOACCESS
,
3614 &spr_read_generic
, &spr_write_generic
,
3616 /* XXX : not implemented */
3617 spr_register(env
, SPR_UPMC5
, "UPMC5",
3618 &spr_read_ureg
, SPR_NOACCESS
,
3619 &spr_read_ureg
, SPR_NOACCESS
,
3621 /* XXX : not implemented */
3622 spr_register(env
, SPR_PMC6
, "PMC6",
3623 SPR_NOACCESS
, SPR_NOACCESS
,
3624 &spr_read_generic
, &spr_write_generic
,
3626 /* XXX : not implemented */
3627 spr_register(env
, SPR_UPMC6
, "UPMC6",
3628 &spr_read_ureg
, SPR_NOACCESS
,
3629 &spr_read_ureg
, SPR_NOACCESS
,
3631 /* Memory management */
3633 gen_74xx_soft_tlb(env
, 128, 2);
3634 init_excp_7450(env
);
3635 /* Allocate hardware IRQ controller */
3636 ppc6xx_irq_init(env
);
3639 /* PowerPC 7445 (aka G4) */
3640 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3641 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3643 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3644 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3645 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3646 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3647 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3649 __attribute__ (( unused
))
3650 static void init_proc_7445 (CPUPPCState
*env
)
3652 gen_spr_ne_601(env
);
3656 /* 74xx specific SPR */
3659 /* XXX : not implemented */
3660 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3661 SPR_NOACCESS
, SPR_NOACCESS
,
3662 &spr_read_generic
, &spr_write_generic
,
3665 /* XXX : not implemented */
3666 spr_register(env
, SPR_ICTRL
, "ICTRL",
3667 SPR_NOACCESS
, SPR_NOACCESS
,
3668 &spr_read_generic
, &spr_write_generic
,
3671 /* XXX : not implemented */
3672 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3673 SPR_NOACCESS
, SPR_NOACCESS
,
3674 &spr_read_generic
, &spr_write_generic
,
3677 /* XXX : not implemented */
3678 spr_register(env
, SPR_PMC5
, "PMC5",
3679 SPR_NOACCESS
, SPR_NOACCESS
,
3680 &spr_read_generic
, &spr_write_generic
,
3682 /* XXX : not implemented */
3683 spr_register(env
, SPR_UPMC5
, "UPMC5",
3684 &spr_read_ureg
, SPR_NOACCESS
,
3685 &spr_read_ureg
, SPR_NOACCESS
,
3687 /* XXX : not implemented */
3688 spr_register(env
, SPR_PMC6
, "PMC6",
3689 SPR_NOACCESS
, SPR_NOACCESS
,
3690 &spr_read_generic
, &spr_write_generic
,
3692 /* XXX : not implemented */
3693 spr_register(env
, SPR_UPMC6
, "UPMC6",
3694 &spr_read_ureg
, SPR_NOACCESS
,
3695 &spr_read_ureg
, SPR_NOACCESS
,
3698 spr_register(env
, SPR_SPRG4
, "SPRG4",
3699 SPR_NOACCESS
, SPR_NOACCESS
,
3700 &spr_read_generic
, &spr_write_generic
,
3702 spr_register(env
, SPR_USPRG4
, "USPRG4",
3703 &spr_read_ureg
, SPR_NOACCESS
,
3704 &spr_read_ureg
, SPR_NOACCESS
,
3706 spr_register(env
, SPR_SPRG5
, "SPRG5",
3707 SPR_NOACCESS
, SPR_NOACCESS
,
3708 &spr_read_generic
, &spr_write_generic
,
3710 spr_register(env
, SPR_USPRG5
, "USPRG5",
3711 &spr_read_ureg
, SPR_NOACCESS
,
3712 &spr_read_ureg
, SPR_NOACCESS
,
3714 spr_register(env
, SPR_SPRG6
, "SPRG6",
3715 SPR_NOACCESS
, SPR_NOACCESS
,
3716 &spr_read_generic
, &spr_write_generic
,
3718 spr_register(env
, SPR_USPRG6
, "USPRG6",
3719 &spr_read_ureg
, SPR_NOACCESS
,
3720 &spr_read_ureg
, SPR_NOACCESS
,
3722 spr_register(env
, SPR_SPRG7
, "SPRG7",
3723 SPR_NOACCESS
, SPR_NOACCESS
,
3724 &spr_read_generic
, &spr_write_generic
,
3726 spr_register(env
, SPR_USPRG7
, "USPRG7",
3727 &spr_read_ureg
, SPR_NOACCESS
,
3728 &spr_read_ureg
, SPR_NOACCESS
,
3730 /* Memory management */
3733 gen_74xx_soft_tlb(env
, 128, 2);
3734 init_excp_7450(env
);
3735 /* Allocate hardware IRQ controller */
3736 ppc6xx_irq_init(env
);
3739 /* PowerPC 7455 (aka G4) */
3740 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3741 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3743 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
3744 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
3745 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
3746 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
3747 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
3749 __attribute__ (( unused
))
3750 static void init_proc_7455 (CPUPPCState
*env
)
3752 gen_spr_ne_601(env
);
3756 /* 74xx specific SPR */
3758 /* Level 3 cache control */
3761 /* XXX : not implemented */
3762 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3763 SPR_NOACCESS
, SPR_NOACCESS
,
3764 &spr_read_generic
, &spr_write_generic
,
3767 /* XXX : not implemented */
3768 spr_register(env
, SPR_ICTRL
, "ICTRL",
3769 SPR_NOACCESS
, SPR_NOACCESS
,
3770 &spr_read_generic
, &spr_write_generic
,
3773 /* XXX : not implemented */
3774 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3775 SPR_NOACCESS
, SPR_NOACCESS
,
3776 &spr_read_generic
, &spr_write_generic
,
3779 /* XXX : not implemented */
3780 spr_register(env
, SPR_PMC5
, "PMC5",
3781 SPR_NOACCESS
, SPR_NOACCESS
,
3782 &spr_read_generic
, &spr_write_generic
,
3784 /* XXX : not implemented */
3785 spr_register(env
, SPR_UPMC5
, "UPMC5",
3786 &spr_read_ureg
, SPR_NOACCESS
,
3787 &spr_read_ureg
, SPR_NOACCESS
,
3789 /* XXX : not implemented */
3790 spr_register(env
, SPR_PMC6
, "PMC6",
3791 SPR_NOACCESS
, SPR_NOACCESS
,
3792 &spr_read_generic
, &spr_write_generic
,
3794 /* XXX : not implemented */
3795 spr_register(env
, SPR_UPMC6
, "UPMC6",
3796 &spr_read_ureg
, SPR_NOACCESS
,
3797 &spr_read_ureg
, SPR_NOACCESS
,
3800 spr_register(env
, SPR_SPRG4
, "SPRG4",
3801 SPR_NOACCESS
, SPR_NOACCESS
,
3802 &spr_read_generic
, &spr_write_generic
,
3804 spr_register(env
, SPR_USPRG4
, "USPRG4",
3805 &spr_read_ureg
, SPR_NOACCESS
,
3806 &spr_read_ureg
, SPR_NOACCESS
,
3808 spr_register(env
, SPR_SPRG5
, "SPRG5",
3809 SPR_NOACCESS
, SPR_NOACCESS
,
3810 &spr_read_generic
, &spr_write_generic
,
3812 spr_register(env
, SPR_USPRG5
, "USPRG5",
3813 &spr_read_ureg
, SPR_NOACCESS
,
3814 &spr_read_ureg
, SPR_NOACCESS
,
3816 spr_register(env
, SPR_SPRG6
, "SPRG6",
3817 SPR_NOACCESS
, SPR_NOACCESS
,
3818 &spr_read_generic
, &spr_write_generic
,
3820 spr_register(env
, SPR_USPRG6
, "USPRG6",
3821 &spr_read_ureg
, SPR_NOACCESS
,
3822 &spr_read_ureg
, SPR_NOACCESS
,
3824 spr_register(env
, SPR_SPRG7
, "SPRG7",
3825 SPR_NOACCESS
, SPR_NOACCESS
,
3826 &spr_read_generic
, &spr_write_generic
,
3828 spr_register(env
, SPR_USPRG7
, "USPRG7",
3829 &spr_read_ureg
, SPR_NOACCESS
,
3830 &spr_read_ureg
, SPR_NOACCESS
,
3832 /* Memory management */
3835 gen_74xx_soft_tlb(env
, 128, 2);
3836 init_excp_7450(env
);
3837 /* Allocate hardware IRQ controller */
3838 ppc6xx_irq_init(env
);
3841 #if defined (TARGET_PPC64)
3843 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3844 PPC_64B | PPC_ALTIVEC | \
3845 PPC_64_BRIDGE | PPC_SLBI)
3846 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
3847 #define POWERPC_MMU_970 (POWERPC_MMU_64BRIDGE)
3848 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
3849 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
3850 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
3852 static void init_proc_970 (CPUPPCState
*env
)
3854 gen_spr_ne_601(env
);
3858 /* Hardware implementation registers */
3859 /* XXX : not implemented */
3860 spr_register(env
, SPR_HID0
, "HID0",
3861 SPR_NOACCESS
, SPR_NOACCESS
,
3862 &spr_read_generic
, &spr_write_generic
,
3864 /* XXX : not implemented */
3865 spr_register(env
, SPR_HID1
, "HID1",
3866 SPR_NOACCESS
, SPR_NOACCESS
,
3867 &spr_read_generic
, &spr_write_generic
,
3869 /* XXX : not implemented */
3870 spr_register(env
, SPR_750_HID2
, "HID2",
3871 SPR_NOACCESS
, SPR_NOACCESS
,
3872 &spr_read_generic
, &spr_write_generic
,
3874 /* Memory management */
3875 /* XXX: not correct */
3881 /* Allocate hardware IRQ controller */
3882 ppc970_irq_init(env
);
3885 /* PowerPC 970FX (aka G5) */
3886 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3887 PPC_64B | PPC_ALTIVEC | \
3888 PPC_64_BRIDGE | PPC_SLBI)
3889 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
3890 #define POWERPC_MMU_970FX (POWERPC_MMU_64BRIDGE)
3891 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
3892 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
3893 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
3895 static void init_proc_970FX (CPUPPCState
*env
)
3897 gen_spr_ne_601(env
);
3901 /* Hardware implementation registers */
3902 /* XXX : not implemented */
3903 spr_register(env
, SPR_HID0
, "HID0",
3904 SPR_NOACCESS
, SPR_NOACCESS
,
3905 &spr_read_generic
, &spr_write_generic
,
3907 /* XXX : not implemented */
3908 spr_register(env
, SPR_HID1
, "HID1",
3909 SPR_NOACCESS
, SPR_NOACCESS
,
3910 &spr_read_generic
, &spr_write_generic
,
3912 /* XXX : not implemented */
3913 spr_register(env
, SPR_750_HID2
, "HID2",
3914 SPR_NOACCESS
, SPR_NOACCESS
,
3915 &spr_read_generic
, &spr_write_generic
,
3917 /* Memory management */
3918 /* XXX: not correct */
3924 /* Allocate hardware IRQ controller */
3925 ppc970_irq_init(env
);
3928 /* PowerPC 970 GX */
3929 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3930 PPC_64B | PPC_ALTIVEC | \
3931 PPC_64_BRIDGE | PPC_SLBI)
3932 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
3933 #define POWERPC_MMU_970GX (POWERPC_MMU_64BRIDGE)
3934 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
3935 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
3936 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
3938 static void init_proc_970GX (CPUPPCState
*env
)
3940 gen_spr_ne_601(env
);
3944 /* Hardware implementation registers */
3945 /* XXX : not implemented */
3946 spr_register(env
, SPR_HID0
, "HID0",
3947 SPR_NOACCESS
, SPR_NOACCESS
,
3948 &spr_read_generic
, &spr_write_generic
,
3950 /* XXX : not implemented */
3951 spr_register(env
, SPR_HID1
, "HID1",
3952 SPR_NOACCESS
, SPR_NOACCESS
,
3953 &spr_read_generic
, &spr_write_generic
,
3955 /* XXX : not implemented */
3956 spr_register(env
, SPR_750_HID2
, "HID2",
3957 SPR_NOACCESS
, SPR_NOACCESS
,
3958 &spr_read_generic
, &spr_write_generic
,
3960 /* Memory management */
3961 /* XXX: not correct */
3967 /* Allocate hardware IRQ controller */
3968 ppc970_irq_init(env
);
3972 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3974 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
3975 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
3976 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
3977 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
3978 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
3980 __attribute__ (( unused
))
3981 static void init_proc_620 (CPUPPCState
*env
)
3983 gen_spr_ne_601(env
);
3987 /* Hardware implementation registers */
3988 /* XXX : not implemented */
3989 spr_register(env
, SPR_HID0
, "HID0",
3990 SPR_NOACCESS
, SPR_NOACCESS
,
3991 &spr_read_generic
, &spr_write_generic
,
3993 /* Memory management */
3997 /* XXX: TODO: initialize internal interrupt controller */
3999 #endif /* defined (TARGET_PPC64) */
4001 /* Default 32 bits PowerPC target will be 604 */
4002 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
4003 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4004 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4005 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
4006 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4007 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
4008 #define init_proc_PPC32 init_proc_604
4009 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
4011 /* Default 64 bits PowerPC target will be 970 FX */
4012 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4013 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4014 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4015 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4016 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4017 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
4018 #define init_proc_PPC64 init_proc_970FX
4019 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
4021 /* Default PowerPC target will be PowerPC 32 */
4022 #if defined (TARGET_PPC64) && 0 // XXX: TODO
4023 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4024 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4025 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4026 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4027 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4028 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4029 #define init_proc_DEFAULT init_proc_PPC64
4030 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
4032 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4033 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4034 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4035 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4036 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4037 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4038 #define init_proc_DEFAULT init_proc_PPC32
4039 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
4042 /*****************************************************************************/
4043 /* PVR definitions for most known PowerPC */
4045 /* PowerPC 401 family */
4046 /* Generic PowerPC 401 */
4047 #define CPU_POWERPC_401 CPU_POWERPC_401G2
4048 /* PowerPC 401 cores */
4049 CPU_POWERPC_401A1
= 0x00210000,
4050 CPU_POWERPC_401B2
= 0x00220000,
4052 CPU_POWERPC_401B3
= xxx
,
4054 CPU_POWERPC_401C2
= 0x00230000,
4055 CPU_POWERPC_401D2
= 0x00240000,
4056 CPU_POWERPC_401E2
= 0x00250000,
4057 CPU_POWERPC_401F2
= 0x00260000,
4058 CPU_POWERPC_401G2
= 0x00270000,
4059 /* PowerPC 401 microcontrolers */
4061 CPU_POWERPC_401GF
= xxx
,
4063 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4064 /* IBM Processor for Network Resources */
4065 CPU_POWERPC_COBRA
= 0x10100000, /* XXX: 405 ? */
4067 CPU_POWERPC_XIPCHIP
= xxx
,
4069 /* PowerPC 403 family */
4070 /* Generic PowerPC 403 */
4071 #define CPU_POWERPC_403 CPU_POWERPC_403GC
4072 /* PowerPC 403 microcontrollers */
4073 CPU_POWERPC_403GA
= 0x00200011,
4074 CPU_POWERPC_403GB
= 0x00200100,
4075 CPU_POWERPC_403GC
= 0x00200200,
4076 CPU_POWERPC_403GCX
= 0x00201400,
4078 CPU_POWERPC_403GP
= xxx
,
4080 /* PowerPC 405 family */
4081 /* Generic PowerPC 405 */
4082 #define CPU_POWERPC_405 CPU_POWERPC_405D4
4083 /* PowerPC 405 cores */
4085 CPU_POWERPC_405A3
= xxx
,
4088 CPU_POWERPC_405A4
= xxx
,
4091 CPU_POWERPC_405B3
= xxx
,
4094 CPU_POWERPC_405B4
= xxx
,
4097 CPU_POWERPC_405C3
= xxx
,
4100 CPU_POWERPC_405C4
= xxx
,
4102 CPU_POWERPC_405D2
= 0x20010000,
4104 CPU_POWERPC_405D3
= xxx
,
4106 CPU_POWERPC_405D4
= 0x41810000,
4108 CPU_POWERPC_405D5
= xxx
,
4111 CPU_POWERPC_405E4
= xxx
,
4114 CPU_POWERPC_405F4
= xxx
,
4117 CPU_POWERPC_405F5
= xxx
,
4120 CPU_POWERPC_405F6
= xxx
,
4122 /* PowerPC 405 microcontrolers */
4123 /* XXX: missing 0x200108a0 */
4124 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4125 CPU_POWERPC_405CRa
= 0x40110041,
4126 CPU_POWERPC_405CRb
= 0x401100C5,
4127 CPU_POWERPC_405CRc
= 0x40110145,
4128 CPU_POWERPC_405EP
= 0x51210950,
4130 CPU_POWERPC_405EXr
= xxx
,
4132 CPU_POWERPC_405EZ
= 0x41511460, /* 0x51210950 ? */
4134 CPU_POWERPC_405FX
= xxx
,
4136 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4137 CPU_POWERPC_405GPa
= 0x40110000,
4138 CPU_POWERPC_405GPb
= 0x40110040,
4139 CPU_POWERPC_405GPc
= 0x40110082,
4140 CPU_POWERPC_405GPd
= 0x401100C4,
4141 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4142 CPU_POWERPC_405GPR
= 0x50910951,
4144 CPU_POWERPC_405H
= xxx
,
4147 CPU_POWERPC_405L
= xxx
,
4149 CPU_POWERPC_405LP
= 0x41F10000,
4151 CPU_POWERPC_405PM
= xxx
,
4154 CPU_POWERPC_405PS
= xxx
,
4157 CPU_POWERPC_405S
= xxx
,
4159 /* IBM network processors */
4160 CPU_POWERPC_NPE405H
= 0x414100C0,
4161 CPU_POWERPC_NPE405H2
= 0x41410140,
4162 CPU_POWERPC_NPE405L
= 0x416100C0,
4163 CPU_POWERPC_NPE4GS3
= 0x40B10000,
4165 CPU_POWERPC_NPCxx1
= xxx
,
4168 CPU_POWERPC_NPR161
= xxx
,
4171 CPU_POWERPC_LC77700
= xxx
,
4173 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4175 CPU_POWERPC_STB01000
= xxx
,
4178 CPU_POWERPC_STB01010
= xxx
,
4181 CPU_POWERPC_STB0210
= xxx
, /* 401B3 */
4183 CPU_POWERPC_STB03
= 0x40310000, /* 0x40130000 ? */
4185 CPU_POWERPC_STB043
= xxx
,
4188 CPU_POWERPC_STB045
= xxx
,
4190 CPU_POWERPC_STB04
= 0x41810000,
4191 CPU_POWERPC_STB25
= 0x51510950,
4193 CPU_POWERPC_STB130
= xxx
,
4196 CPU_POWERPC_X2VP4
= 0x20010820,
4197 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4198 CPU_POWERPC_X2VP20
= 0x20010860,
4199 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4201 CPU_POWERPC_ZL10310
= xxx
,
4204 CPU_POWERPC_ZL10311
= xxx
,
4207 CPU_POWERPC_ZL10320
= xxx
,
4210 CPU_POWERPC_ZL10321
= xxx
,
4212 /* PowerPC 440 family */
4213 /* Generic PowerPC 440 */
4214 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
4215 /* PowerPC 440 cores */
4217 CPU_POWERPC_440A4
= xxx
,
4220 CPU_POWERPC_440A5
= xxx
,
4223 CPU_POWERPC_440B4
= xxx
,
4226 CPU_POWERPC_440F5
= xxx
,
4229 CPU_POWERPC_440G5
= xxx
,
4232 CPU_POWERPC_440H4
= xxx
,
4235 CPU_POWERPC_440H6
= xxx
,
4237 /* PowerPC 440 microcontrolers */
4238 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4239 CPU_POWERPC_440EPa
= 0x42221850,
4240 CPU_POWERPC_440EPb
= 0x422218D3,
4241 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4242 CPU_POWERPC_440GPb
= 0x40120440,
4243 CPU_POWERPC_440GPc
= 0x40120481,
4244 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4245 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4246 CPU_POWERPC_440GRX
= 0x200008D0,
4247 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4248 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4249 CPU_POWERPC_440GXa
= 0x51B21850,
4250 CPU_POWERPC_440GXb
= 0x51B21851,
4251 CPU_POWERPC_440GXc
= 0x51B21892,
4252 CPU_POWERPC_440GXf
= 0x51B21894,
4254 CPU_POWERPC_440S
= xxx
,
4256 CPU_POWERPC_440SP
= 0x53221850,
4257 CPU_POWERPC_440SP2
= 0x53221891,
4258 CPU_POWERPC_440SPE
= 0x53421890,
4259 /* PowerPC 460 family */
4261 /* Generic PowerPC 464 */
4262 #define CPU_POWERPC_464 CPU_POWERPC_464H90
4264 /* PowerPC 464 microcontrolers */
4266 CPU_POWERPC_464H90
= xxx
,
4269 CPU_POWERPC_464H90FP
= xxx
,
4271 /* Freescale embedded PowerPC cores */
4273 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4275 CPU_POWERPC_e200z0
= xxx
,
4278 CPU_POWERPC_e200z3
= xxx
,
4280 CPU_POWERPC_e200z5
= 0x81000000,
4281 CPU_POWERPC_e200z6
= 0x81120000,
4283 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4284 CPU_POWERPC_e300c1
= 0x00830000,
4285 CPU_POWERPC_e300c2
= 0x00840000,
4286 CPU_POWERPC_e300c3
= 0x00850000,
4288 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4289 CPU_POWERPC_e500_v11
= 0x80200010,
4290 CPU_POWERPC_e500_v12
= 0x80200020,
4291 CPU_POWERPC_e500_v21
= 0x80210010,
4292 CPU_POWERPC_e500_v22
= 0x80210020,
4294 CPU_POWERPC_e500mc
= xxx
,
4297 CPU_POWERPC_e600
= 0x80040010,
4298 /* PowerPC MPC 5xx cores */
4299 CPU_POWERPC_5xx
= 0x00020020,
4300 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4301 CPU_POWERPC_8xx
= 0x00500000,
4302 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4303 CPU_POWERPC_82xx_HIP3
= 0x00810101,
4304 CPU_POWERPC_82xx_HIP4
= 0x80811014,
4305 CPU_POWERPC_827x
= 0x80822013,
4306 /* PowerPC 6xx cores */
4307 CPU_POWERPC_601
= 0x00010001,
4308 CPU_POWERPC_601a
= 0x00010002,
4309 CPU_POWERPC_602
= 0x00050100,
4310 CPU_POWERPC_603
= 0x00030100,
4311 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4312 CPU_POWERPC_603E_v11
= 0x00060101,
4313 CPU_POWERPC_603E_v12
= 0x00060102,
4314 CPU_POWERPC_603E_v13
= 0x00060103,
4315 CPU_POWERPC_603E_v14
= 0x00060104,
4316 CPU_POWERPC_603E_v22
= 0x00060202,
4317 CPU_POWERPC_603E_v3
= 0x00060300,
4318 CPU_POWERPC_603E_v4
= 0x00060400,
4319 CPU_POWERPC_603E_v41
= 0x00060401,
4320 CPU_POWERPC_603E7t
= 0x00071201,
4321 CPU_POWERPC_603E7v
= 0x00070100,
4322 CPU_POWERPC_603E7v1
= 0x00070101,
4323 CPU_POWERPC_603E7v2
= 0x00070201,
4324 CPU_POWERPC_603E7
= 0x00070200,
4325 CPU_POWERPC_603P
= 0x00070000,
4326 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
4327 CPU_POWERPC_G2
= 0x00810011,
4328 #if 0 // Linux pretends the MSB is zero...
4329 CPU_POWERPC_G2H4
= 0x80811010,
4330 CPU_POWERPC_G2gp
= 0x80821010,
4331 CPU_POWERPC_G2ls
= 0x90810010,
4332 CPU_POWERPC_G2LE
= 0x80820010,
4333 CPU_POWERPC_G2LEgp
= 0x80822010,
4334 CPU_POWERPC_G2LEls
= 0xA0822010,
4336 CPU_POWERPC_G2H4
= 0x00811010,
4337 CPU_POWERPC_G2gp
= 0x00821010,
4338 CPU_POWERPC_G2ls
= 0x10810010,
4339 CPU_POWERPC_G2LE
= 0x00820010,
4340 CPU_POWERPC_G2LEgp
= 0x00822010,
4341 CPU_POWERPC_G2LEls
= 0x20822010,
4343 CPU_POWERPC_604
= 0x00040103,
4344 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4345 CPU_POWERPC_604E_v10
= 0x00090100, /* Also 2110 & 2120 */
4346 CPU_POWERPC_604E_v22
= 0x00090202,
4347 CPU_POWERPC_604E_v24
= 0x00090204,
4348 CPU_POWERPC_604R
= 0x000a0101, /* Also 0x00093102 */
4350 CPU_POWERPC_604EV
= xxx
,
4352 /* PowerPC 740/750 cores (aka G3) */
4353 /* XXX: missing 0x00084202 */
4354 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4355 CPU_POWERPC_7x0_v20
= 0x00080200,
4356 CPU_POWERPC_7x0_v21
= 0x00080201,
4357 CPU_POWERPC_7x0_v22
= 0x00080202,
4358 CPU_POWERPC_7x0_v30
= 0x00080300,
4359 CPU_POWERPC_7x0_v31
= 0x00080301,
4360 CPU_POWERPC_740E
= 0x00080100,
4361 CPU_POWERPC_7x0P
= 0x10080000,
4362 /* XXX: missing 0x00087010 (CL ?) */
4363 CPU_POWERPC_750CL
= 0x00087200,
4364 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4365 CPU_POWERPC_750CX_v21
= 0x00082201,
4366 CPU_POWERPC_750CX_v22
= 0x00082202,
4367 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4368 CPU_POWERPC_750CXE_v21
= 0x00082211,
4369 CPU_POWERPC_750CXE_v22
= 0x00082212,
4370 CPU_POWERPC_750CXE_v23
= 0x00082213,
4371 CPU_POWERPC_750CXE_v24
= 0x00082214,
4372 CPU_POWERPC_750CXE_v24b
= 0x00083214,
4373 CPU_POWERPC_750CXE_v31
= 0x00083211,
4374 CPU_POWERPC_750CXE_v31b
= 0x00083311,
4375 CPU_POWERPC_750CXR
= 0x00083410,
4376 CPU_POWERPC_750E
= 0x00080200,
4377 CPU_POWERPC_750FL
= 0x700A0203,
4378 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4379 CPU_POWERPC_750FX_v10
= 0x70000100,
4380 CPU_POWERPC_750FX_v20
= 0x70000200,
4381 CPU_POWERPC_750FX_v21
= 0x70000201,
4382 CPU_POWERPC_750FX_v22
= 0x70000202,
4383 CPU_POWERPC_750FX_v23
= 0x70000203,
4384 CPU_POWERPC_750GL
= 0x70020102,
4385 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4386 CPU_POWERPC_750GX_v10
= 0x70020100,
4387 CPU_POWERPC_750GX_v11
= 0x70020101,
4388 CPU_POWERPC_750GX_v12
= 0x70020102,
4389 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4390 CPU_POWERPC_750L_v22
= 0x00088202,
4391 CPU_POWERPC_750L_v30
= 0x00088300,
4392 CPU_POWERPC_750L_v32
= 0x00088302,
4393 /* PowerPC 745/755 cores */
4394 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4395 CPU_POWERPC_7x5_v10
= 0x00083100,
4396 CPU_POWERPC_7x5_v11
= 0x00083101,
4397 CPU_POWERPC_7x5_v20
= 0x00083200,
4398 CPU_POWERPC_7x5_v21
= 0x00083201,
4399 CPU_POWERPC_7x5_v22
= 0x00083202, /* aka D */
4400 CPU_POWERPC_7x5_v23
= 0x00083203, /* aka E */
4401 CPU_POWERPC_7x5_v24
= 0x00083204,
4402 CPU_POWERPC_7x5_v25
= 0x00083205,
4403 CPU_POWERPC_7x5_v26
= 0x00083206,
4404 CPU_POWERPC_7x5_v27
= 0x00083207,
4405 CPU_POWERPC_7x5_v28
= 0x00083208,
4407 CPU_POWERPC_7x5P
= xxx
,
4409 /* PowerPC 74xx cores (aka G4) */
4410 /* XXX: missing 0x000C1101 */
4411 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4412 CPU_POWERPC_7400_v10
= 0x000C0100,
4413 CPU_POWERPC_7400_v11
= 0x000C0101,
4414 CPU_POWERPC_7400_v20
= 0x000C0200,
4415 CPU_POWERPC_7400_v22
= 0x000C0202,
4416 CPU_POWERPC_7400_v26
= 0x000C0206,
4417 CPU_POWERPC_7400_v27
= 0x000C0207,
4418 CPU_POWERPC_7400_v28
= 0x000C0208,
4419 CPU_POWERPC_7400_v29
= 0x000C0209,
4420 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4421 CPU_POWERPC_7410_v10
= 0x800C1100,
4422 CPU_POWERPC_7410_v11
= 0x800C1101,
4423 CPU_POWERPC_7410_v12
= 0x800C1102, /* aka C */
4424 CPU_POWERPC_7410_v13
= 0x800C1103, /* aka D */
4425 CPU_POWERPC_7410_v14
= 0x800C1104, /* aka E */
4426 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4427 CPU_POWERPC_7448_v10
= 0x80040100,
4428 CPU_POWERPC_7448_v11
= 0x80040101,
4429 CPU_POWERPC_7448_v20
= 0x80040200,
4430 CPU_POWERPC_7448_v21
= 0x80040201,
4431 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4432 CPU_POWERPC_7450_v10
= 0x80000100,
4433 CPU_POWERPC_7450_v11
= 0x80000101,
4434 CPU_POWERPC_7450_v12
= 0x80000102,
4435 CPU_POWERPC_7450_v20
= 0x80000200, /* aka D: 2.04 */
4436 CPU_POWERPC_7450_v21
= 0x80000201, /* aka E */
4437 CPU_POWERPC_74x1
= 0x80000203,
4438 CPU_POWERPC_74x1G
= 0x80000210, /* aka G: 2.3 */
4439 /* XXX: missing 0x80010200 */
4440 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4441 CPU_POWERPC_74x5_v10
= 0x80010100,
4442 CPU_POWERPC_74x5_v21
= 0x80010201, /* aka C: 2.1 */
4443 CPU_POWERPC_74x5_v32
= 0x80010302,
4444 CPU_POWERPC_74x5_v33
= 0x80010303, /* aka F: 3.3 */
4445 CPU_POWERPC_74x5_v34
= 0x80010304, /* aka G: 3.4 */
4446 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4447 CPU_POWERPC_74x7_v10
= 0x80020100, /* aka A: 1.0 */
4448 CPU_POWERPC_74x7_v11
= 0x80030101, /* aka B: 1.1 */
4449 CPU_POWERPC_74x7_v12
= 0x80020102, /* aka C: 1.2 */
4450 /* 64 bits PowerPC */
4451 CPU_POWERPC_620
= 0x00140000,
4452 CPU_POWERPC_630
= 0x00400000,
4453 CPU_POWERPC_631
= 0x00410104,
4454 CPU_POWERPC_POWER4
= 0x00350000,
4455 CPU_POWERPC_POWER4P
= 0x00380000,
4456 CPU_POWERPC_POWER5
= 0x003A0203,
4457 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4458 CPU_POWERPC_POWER5P
= 0x003B0000,
4459 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4460 CPU_POWERPC_POWER6
= 0x003E0000,
4461 CPU_POWERPC_POWER6_5
= 0x0F000001, /* POWER6 running POWER5 mode */
4462 CPU_POWERPC_POWER6A
= 0x0F000002,
4463 CPU_POWERPC_970
= 0x00390202,
4464 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4465 CPU_POWERPC_970FX_v10
= 0x00391100,
4466 CPU_POWERPC_970FX_v20
= 0x003C0200,
4467 CPU_POWERPC_970FX_v21
= 0x003C0201,
4468 CPU_POWERPC_970FX_v30
= 0x003C0300,
4469 CPU_POWERPC_970FX_v31
= 0x003C0301,
4470 CPU_POWERPC_970GX
= 0x00450000,
4471 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4472 CPU_POWERPC_970MP_v10
= 0x00440100,
4473 CPU_POWERPC_970MP_v11
= 0x00440101,
4474 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4475 CPU_POWERPC_CELL_v10
= 0x00700100,
4476 CPU_POWERPC_CELL_v20
= 0x00700400,
4477 CPU_POWERPC_CELL_v30
= 0x00700500,
4478 CPU_POWERPC_CELL_v31
= 0x00700501,
4479 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4480 CPU_POWERPC_RS64
= 0x00330000,
4481 CPU_POWERPC_RS64II
= 0x00340000,
4482 CPU_POWERPC_RS64III
= 0x00360000,
4483 CPU_POWERPC_RS64IV
= 0x00370000,
4484 /* Original POWER */
4485 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4486 * POWER2 (RIOS2) & RSC2 (P2SC) here
4489 CPU_POWER
= xxx
, /* 0x20000 ? 0x30000 for RSC ? */
4492 CPU_POWER2
= xxx
, /* 0x40000 ? */
4495 CPU_POWERPC_PA6T
= 0x00900000,
4498 /* System version register (used on MPC 8xxx) */
4500 PPC_SVR_8540
= 0x80300000,
4501 PPC_SVR_8541E
= 0x807A0010,
4502 PPC_SVR_8543v10
= 0x80320010,
4503 PPC_SVR_8543v11
= 0x80320011,
4504 PPC_SVR_8543v20
= 0x80320020,
4505 PPC_SVR_8543Ev10
= 0x803A0010,
4506 PPC_SVR_8543Ev11
= 0x803A0011,
4507 PPC_SVR_8543Ev20
= 0x803A0020,
4508 PPC_SVR_8545
= 0x80310220,
4509 PPC_SVR_8545E
= 0x80390220,
4510 PPC_SVR_8547E
= 0x80390120,
4511 PPC_SCR_8548v10
= 0x80310010,
4512 PPC_SCR_8548v11
= 0x80310011,
4513 PPC_SCR_8548v20
= 0x80310020,
4514 PPC_SVR_8548Ev10
= 0x80390010,
4515 PPC_SVR_8548Ev11
= 0x80390011,
4516 PPC_SVR_8548Ev20
= 0x80390020,
4517 PPC_SVR_8555E
= 0x80790010,
4518 PPC_SVR_8560v10
= 0x80700010,
4519 PPC_SVR_8560v20
= 0x80700020,
4522 /*****************************************************************************/
4523 /* PowerPC CPU definitions */
4524 #define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4528 .pvr_mask = _pvr_mask, \
4529 .insns_flags = glue(POWERPC_INSNS_,_type), \
4530 .msr_mask = glue(POWERPC_MSRM_,_type), \
4531 .mmu_model = glue(POWERPC_MMU_,_type), \
4532 .excp_model = glue(POWERPC_EXCP_,_type), \
4533 .bus_model = glue(POWERPC_INPUT_,_type), \
4534 .bfd_mach = glue(POWERPC_BFDM_,_type), \
4535 .init_proc = &glue(init_proc_,_type), \
4538 static ppc_def_t ppc_defs
[] = {
4539 /* Embedded PowerPC */
4540 /* PowerPC 401 family */
4541 /* Generic PowerPC 401 */
4542 POWERPC_DEF("401", CPU_POWERPC_401
, 0xFFFF0000, 401),
4543 /* PowerPC 401 cores */
4545 POWERPC_DEF("401A1", CPU_POWERPC_401A1
, 0xFFFFFFFF, 401),
4547 POWERPC_DEF("401B2", CPU_POWERPC_401B2
, 0xFFFFFFFF, 401x2
),
4550 POWERPC_DEF("401B3", CPU_POWERPC_401B3
, 0xFFFFFFFF, 401x3
),
4553 POWERPC_DEF("401C2", CPU_POWERPC_401C2
, 0xFFFFFFFF, 401x2
),
4555 POWERPC_DEF("401D2", CPU_POWERPC_401D2
, 0xFFFFFFFF, 401x2
),
4557 POWERPC_DEF("401E2", CPU_POWERPC_401E2
, 0xFFFFFFFF, 401x2
),
4559 POWERPC_DEF("401F2", CPU_POWERPC_401F2
, 0xFFFFFFFF, 401x2
),
4561 /* XXX: to be checked */
4562 POWERPC_DEF("401G2", CPU_POWERPC_401G2
, 0xFFFFFFFF, 401x2
),
4563 /* PowerPC 401 microcontrolers */
4566 POWERPC_DEF("401GF", CPU_POWERPC_401GF
, 0xFFFFFFFF, 401),
4568 /* IOP480 (401 microcontroler) */
4569 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480
, 0xFFFFFFFF, IOP480
),
4570 /* IBM Processor for Network Resources */
4571 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA
, 0xFFFFFFFF, 401),
4573 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP
, 0xFFFFFFFF, 401),
4575 /* PowerPC 403 family */
4576 /* Generic PowerPC 403 */
4577 POWERPC_DEF("403", CPU_POWERPC_403
, 0xFFFF0000, 403),
4578 /* PowerPC 403 microcontrolers */
4579 /* PowerPC 403 GA */
4580 POWERPC_DEF("403GA", CPU_POWERPC_403GA
, 0xFFFFFFFF, 403),
4581 /* PowerPC 403 GB */
4582 POWERPC_DEF("403GB", CPU_POWERPC_403GB
, 0xFFFFFFFF, 403),
4583 /* PowerPC 403 GC */
4584 POWERPC_DEF("403GC", CPU_POWERPC_403GC
, 0xFFFFFFFF, 403),
4585 /* PowerPC 403 GCX */
4586 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX
, 0xFFFFFFFF, 403GCX
),
4588 /* PowerPC 403 GP */
4589 POWERPC_DEF("403GP", CPU_POWERPC_403GP
, 0xFFFFFFFF, 403),
4591 /* PowerPC 405 family */
4592 /* Generic PowerPC 405 */
4593 POWERPC_DEF("405", CPU_POWERPC_405
, 0xFFFF0000, 405),
4594 /* PowerPC 405 cores */
4596 /* PowerPC 405 A3 */
4597 POWERPC_DEF("405A3", CPU_POWERPC_405A3
, 0xFFFFFFFF, 405),
4600 /* PowerPC 405 A4 */
4601 POWERPC_DEF("405A4", CPU_POWERPC_405A4
, 0xFFFFFFFF, 405),
4604 /* PowerPC 405 B3 */
4605 POWERPC_DEF("405B3", CPU_POWERPC_405B3
, 0xFFFFFFFF, 405),
4608 /* PowerPC 405 B4 */
4609 POWERPC_DEF("405B4", CPU_POWERPC_405B4
, 0xFFFFFFFF, 405),
4612 /* PowerPC 405 C3 */
4613 POWERPC_DEF("405C3", CPU_POWERPC_405C3
, 0xFFFFFFFF, 405),
4616 /* PowerPC 405 C4 */
4617 POWERPC_DEF("405C4", CPU_POWERPC_405C4
, 0xFFFFFFFF, 405),
4619 /* PowerPC 405 D2 */
4620 POWERPC_DEF("405D2", CPU_POWERPC_405D2
, 0xFFFFFFFF, 405),
4622 /* PowerPC 405 D3 */
4623 POWERPC_DEF("405D3", CPU_POWERPC_405D3
, 0xFFFFFFFF, 405),
4625 /* PowerPC 405 D4 */
4626 POWERPC_DEF("405D4", CPU_POWERPC_405D4
, 0xFFFFFFFF, 405),
4628 /* PowerPC 405 D5 */
4629 POWERPC_DEF("405D5", CPU_POWERPC_405D5
, 0xFFFFFFFF, 405),
4632 /* PowerPC 405 E4 */
4633 POWERPC_DEF("405E4", CPU_POWERPC_405E4
, 0xFFFFFFFF, 405),
4636 /* PowerPC 405 F4 */
4637 POWERPC_DEF("405F4", CPU_POWERPC_405F4
, 0xFFFFFFFF, 405),
4640 /* PowerPC 405 F5 */
4641 POWERPC_DEF("405F5", CPU_POWERPC_405F5
, 0xFFFFFFFF, 405),
4644 /* PowerPC 405 F6 */
4645 POWERPC_DEF("405F6", CPU_POWERPC_405F6
, 0xFFFFFFFF, 405),
4647 /* PowerPC 405 microcontrolers */
4648 /* PowerPC 405 CR */
4649 POWERPC_DEF("405CR", CPU_POWERPC_405CR
, 0xFFFFFFFF, 405),
4650 /* PowerPC 405 CRa */
4651 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa
, 0xFFFFFFFF, 405),
4652 /* PowerPC 405 CRb */
4653 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb
, 0xFFFFFFFF, 405),
4654 /* PowerPC 405 CRc */
4655 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc
, 0xFFFFFFFF, 405),
4656 /* PowerPC 405 EP */
4657 POWERPC_DEF("405EP", CPU_POWERPC_405EP
, 0xFFFFFFFF, 405),
4659 /* PowerPC 405 EXr */
4660 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr
, 0xFFFFFFFF, 405),
4662 /* PowerPC 405 EZ */
4663 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ
, 0xFFFFFFFF, 405),
4665 /* PowerPC 405 FX */
4666 POWERPC_DEF("405FX", CPU_POWERPC_405FX
, 0xFFFFFFFF, 405),
4668 /* PowerPC 405 GP */
4669 POWERPC_DEF("405GP", CPU_POWERPC_405GP
, 0xFFFFFFFF, 405),
4670 /* PowerPC 405 GPa */
4671 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa
, 0xFFFFFFFF, 405),
4672 /* PowerPC 405 GPb */
4673 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb
, 0xFFFFFFFF, 405),
4674 /* PowerPC 405 GPc */
4675 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc
, 0xFFFFFFFF, 405),
4676 /* PowerPC 405 GPd */
4677 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd
, 0xFFFFFFFF, 405),
4678 /* PowerPC 405 GPe */
4679 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe
, 0xFFFFFFFF, 405),
4680 /* PowerPC 405 GPR */
4681 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR
, 0xFFFFFFFF, 405),
4684 POWERPC_DEF("405H", CPU_POWERPC_405H
, 0xFFFFFFFF, 405),
4688 POWERPC_DEF("405L", CPU_POWERPC_405L
, 0xFFFFFFFF, 405),
4690 /* PowerPC 405 LP */
4691 POWERPC_DEF("405LP", CPU_POWERPC_405LP
, 0xFFFFFFFF, 405),
4693 /* PowerPC 405 PM */
4694 POWERPC_DEF("405PM", CPU_POWERPC_405PM
, 0xFFFFFFFF, 405),
4697 /* PowerPC 405 PS */
4698 POWERPC_DEF("405PS", CPU_POWERPC_405PS
, 0xFFFFFFFF, 405),
4702 POWERPC_DEF("405S", CPU_POWERPC_405S
, 0xFFFFFFFF, 405),
4705 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H
, 0xFFFFFFFF, 405),
4707 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2
, 0xFFFFFFFF, 405),
4709 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L
, 0xFFFFFFFF, 405),
4711 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3
, 0xFFFFFFFF, 405),
4713 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1
, 0xFFFFFFFF, 405),
4716 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161
, 0xFFFFFFFF, 405),
4719 /* PowerPC LC77700 (Sanyo) */
4720 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700
, 0xFFFFFFFF, 405),
4722 /* PowerPC 401/403/405 based set-top-box microcontrolers */
4725 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000
, 0xFFFFFFFF, 401x2
),
4729 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010
, 0xFFFFFFFF, 401x2
),
4733 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210
, 0xFFFFFFFF, 401x3
),
4736 POWERPC_DEF("STB03", CPU_POWERPC_STB03
, 0xFFFFFFFF, 405),
4739 POWERPC_DEF("STB043", CPU_POWERPC_STB043
, 0xFFFFFFFF, 405),
4743 POWERPC_DEF("STB045", CPU_POWERPC_STB045
, 0xFFFFFFFF, 405),
4746 POWERPC_DEF("STB04", CPU_POWERPC_STB04
, 0xFFFF0000, 405),
4748 POWERPC_DEF("STB25", CPU_POWERPC_STB25
, 0xFFFFFFFF, 405),
4751 POWERPC_DEF("STB130", CPU_POWERPC_STB130
, 0xFFFFFFFF, 405),
4753 /* Xilinx PowerPC 405 cores */
4754 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4
, 0xFFFFFFFF, 405),
4755 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7
, 0xFFFFFFFF, 405),
4756 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20
, 0xFFFFFFFF, 405),
4757 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50
, 0xFFFFFFFF, 405),
4759 /* Zarlink ZL10310 */
4760 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310
, 0xFFFFFFFF, 405),
4763 /* Zarlink ZL10311 */
4764 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311
, 0xFFFFFFFF, 405),
4767 /* Zarlink ZL10320 */
4768 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320
, 0xFFFFFFFF, 405),
4771 /* Zarlink ZL10321 */
4772 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321
, 0xFFFFFFFF, 405),
4774 /* PowerPC 440 family */
4775 /* Generic PowerPC 440 */
4776 POWERPC_DEF("440", CPU_POWERPC_440
, 0xFFFFFFFF, 440GP
),
4777 /* PowerPC 440 cores */
4779 /* PowerPC 440 A4 */
4780 POWERPC_DEF("440A4", CPU_POWERPC_440A4
, 0xFFFFFFFF, 440x4
),
4783 /* PowerPC 440 A5 */
4784 POWERPC_DEF("440A5", CPU_POWERPC_440A5
, 0xFFFFFFFF, 440x5
),
4787 /* PowerPC 440 B4 */
4788 POWERPC_DEF("440B4", CPU_POWERPC_440B4
, 0xFFFFFFFF, 440x4
),
4791 /* PowerPC 440 G4 */
4792 POWERPC_DEF("440G4", CPU_POWERPC_440G4
, 0xFFFFFFFF, 440x4
),
4795 /* PowerPC 440 F5 */
4796 POWERPC_DEF("440F5", CPU_POWERPC_440F5
, 0xFFFFFFFF, 440x5
),
4799 /* PowerPC 440 G5 */
4800 POWERPC_DEF("440G5", CPU_POWERPC_440G5
, 0xFFFFFFFF, 440x5
),
4804 POWERPC_DEF("440H4", CPU_POWERPC_440H4
, 0xFFFFFFFF, 440x4
),
4808 POWERPC_DEF("440H6", CPU_POWERPC_440H6
, 0xFFFFFFFF, 440Gx5
),
4810 /* PowerPC 440 microcontrolers */
4811 /* PowerPC 440 EP */
4812 POWERPC_DEF("440EP", CPU_POWERPC_440EP
, 0xFFFFFFFF, 440EP
),
4813 /* PowerPC 440 EPa */
4814 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa
, 0xFFFFFFFF, 440EP
),
4815 /* PowerPC 440 EPb */
4816 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb
, 0xFFFFFFFF, 440EP
),
4817 /* PowerPC 440 EPX */
4818 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX
, 0xFFFFFFFF, 440EP
),
4819 /* PowerPC 440 GP */
4820 POWERPC_DEF("440GP", CPU_POWERPC_440GP
, 0xFFFFFFFF, 440GP
),
4821 /* PowerPC 440 GPb */
4822 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb
, 0xFFFFFFFF, 440GP
),
4823 /* PowerPC 440 GPc */
4824 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc
, 0xFFFFFFFF, 440GP
),
4825 /* PowerPC 440 GR */
4826 POWERPC_DEF("440GR", CPU_POWERPC_440GR
, 0xFFFFFFFF, 440x5
),
4827 /* PowerPC 440 GRa */
4828 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa
, 0xFFFFFFFF, 440x5
),
4829 /* PowerPC 440 GRX */
4830 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX
, 0xFFFFFFFF, 440x5
),
4831 /* PowerPC 440 GX */
4832 POWERPC_DEF("440GX", CPU_POWERPC_440GX
, 0xFFFFFFFF, 440EP
),
4833 /* PowerPC 440 GXa */
4834 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa
, 0xFFFFFFFF, 440EP
),
4835 /* PowerPC 440 GXb */
4836 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb
, 0xFFFFFFFF, 440EP
),
4837 /* PowerPC 440 GXc */
4838 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc
, 0xFFFFFFFF, 440EP
),
4839 /* PowerPC 440 GXf */
4840 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf
, 0xFFFFFFFF, 440EP
),
4843 POWERPC_DEF("440S", CPU_POWERPC_440S
, 0xFFFFFFFF, 440),
4845 /* PowerPC 440 SP */
4846 POWERPC_DEF("440SP", CPU_POWERPC_440SP
, 0xFFFFFFFF, 440EP
),
4847 /* PowerPC 440 SP2 */
4848 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2
, 0xFFFFFFFF, 440EP
),
4849 /* PowerPC 440 SPE */
4850 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE
, 0xFFFFFFFF, 440EP
),
4851 /* PowerPC 460 family */
4853 /* Generic PowerPC 464 */
4854 POWERPC_DEF("464", CPU_POWERPC_464
, 0xFFFFFFFF, 460),
4856 /* PowerPC 464 microcontrolers */
4858 /* PowerPC 464H90 */
4859 POWERPC_DEF("464H90", CPU_POWERPC_464H90
, 0xFFFFFFFF, 460),
4862 /* PowerPC 464H90F */
4863 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F
, 0xFFFFFFFF, 460F
),
4865 /* Freescale embedded PowerPC cores */
4868 /* Generic PowerPC e200 core */
4869 POWERPC_DEF("e200", CPU_POWERPC_e200
, 0xFFFFFFFF, e200
),
4872 /* PowerPC e200z5 core */
4873 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5
, 0xFFFFFFFF, e200
),
4876 /* PowerPC e200z6 core */
4877 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6
, 0xFFFFFFFF, e200
),
4881 /* Generic PowerPC e300 core */
4882 POWERPC_DEF("e300", CPU_POWERPC_e300
, 0xFFFFFFFF, e300
),
4885 /* PowerPC e300c1 core */
4886 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1
, 0xFFFFFFFF, e300
),
4889 /* PowerPC e300c2 core */
4890 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2
, 0xFFFFFFFF, e300
),
4893 /* PowerPC e300c3 core */
4894 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3
, 0xFFFFFFFF, e300
),
4898 /* PowerPC e500 core */
4899 POWERPC_DEF("e500", CPU_POWERPC_e500
, 0xFFFFFFFF, e500
),
4902 /* PowerPC e500 v1.1 core */
4903 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11
, 0xFFFFFFFF, e500
),
4906 /* PowerPC e500 v1.2 core */
4907 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12
, 0xFFFFFFFF, e500
),
4910 /* PowerPC e500 v2.1 core */
4911 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21
, 0xFFFFFFFF, e500
),
4914 /* PowerPC e500 v2.2 core */
4915 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22
, 0xFFFFFFFF, e500
),
4919 /* PowerPC e600 core */
4920 POWERPC_DEF("e600", CPU_POWERPC_e600
, 0xFFFFFFFF, e600
),
4922 /* PowerPC MPC 5xx cores */
4924 /* PowerPC MPC 5xx */
4925 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx
, 0xFFFFFFFF, 5xx
),
4927 /* PowerPC MPC 8xx cores */
4929 /* PowerPC MPC 8xx */
4930 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx
, 0xFFFFFFFF, 8xx
),
4932 /* PowerPC MPC 8xxx cores */
4934 /* PowerPC MPC 82xx HIP3 */
4935 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3
, 0xFFFFFFFF, 82xx
),
4938 /* PowerPC MPC 82xx HIP4 */
4939 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4
, 0xFFFFFFFF, 82xx
),
4942 /* PowerPC MPC 827x */
4943 POWERPC_DEF("mpc827x", CPU_POWERPC_827x
, 0xFFFFFFFF, 827x
),
4946 /* 32 bits "classic" PowerPC */
4947 /* PowerPC 6xx family */
4949 POWERPC_DEF("601", CPU_POWERPC_601
, 0xFFFFFFFF, 601),
4951 POWERPC_DEF("601a", CPU_POWERPC_601a
, 0xFFFFFFFF, 601),
4953 POWERPC_DEF("602", CPU_POWERPC_602
, 0xFFFFFFFF, 602),
4955 POWERPC_DEF("603", CPU_POWERPC_603
, 0xFFFFFFFF, 603),
4956 /* Code name for PowerPC 603 */
4957 POWERPC_DEF("Vanilla", CPU_POWERPC_603
, 0xFFFFFFFF, 603),
4959 POWERPC_DEF("603e", CPU_POWERPC_603E
, 0xFFFFFFFF, 603E
),
4960 /* Code name for PowerPC 603e */
4961 POWERPC_DEF("Stretch", CPU_POWERPC_603E
, 0xFFFFFFFF, 603E
),
4962 /* PowerPC 603e v1.1 */
4963 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11
, 0xFFFFFFFF, 603E
),
4964 /* PowerPC 603e v1.2 */
4965 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12
, 0xFFFFFFFF, 603E
),
4966 /* PowerPC 603e v1.3 */
4967 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13
, 0xFFFFFFFF, 603E
),
4968 /* PowerPC 603e v1.4 */
4969 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14
, 0xFFFFFFFF, 603E
),
4970 /* PowerPC 603e v2.2 */
4971 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22
, 0xFFFFFFFF, 603E
),
4972 /* PowerPC 603e v3 */
4973 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3
, 0xFFFFFFFF, 603E
),
4974 /* PowerPC 603e v4 */
4975 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4
, 0xFFFFFFFF, 603E
),
4976 /* PowerPC 603e v4.1 */
4977 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41
, 0xFFFFFFFF, 603E
),
4979 POWERPC_DEF("603e7", CPU_POWERPC_603E7
, 0xFFFFFFFF, 603E
),
4980 /* PowerPC 603e7t */
4981 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t
, 0xFFFFFFFF, 603E
),
4982 /* PowerPC 603e7v */
4983 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v
, 0xFFFFFFFF, 603E
),
4984 /* Code name for PowerPC 603ev */
4985 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v
, 0xFFFFFFFF, 603E
),
4986 /* PowerPC 603e7v1 */
4987 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1
, 0xFFFFFFFF, 603E
),
4988 /* PowerPC 603e7v2 */
4989 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2
, 0xFFFFFFFF, 603E
),
4992 POWERPC_DEF("603p", CPU_POWERPC_603P
, 0xFFFFFFFF, 603),
4994 POWERPC_DEF("603r", CPU_POWERPC_603R
, 0xFFFFFFFF, 603E
),
4995 /* Code name for PowerPC 603r */
4996 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R
, 0xFFFFFFFF, 603E
),
4997 /* PowerPC G2 core */
4998 POWERPC_DEF("G2", CPU_POWERPC_G2
, 0xFFFFFFFF, G2
),
5000 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4
, 0xFFFFFFFF, G2
),
5002 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp
, 0xFFFFFFFF, G2
),
5004 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls
, 0xFFFFFFFF, G2
),
5006 /* Same as G2, with little-endian mode support */
5007 POWERPC_DEF("G2le", CPU_POWERPC_G2LE
, 0xFFFFFFFF, G2LE
),
5008 /* PowerPC G2LE GP */
5009 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp
, 0xFFFFFFFF, G2LE
),
5010 /* PowerPC G2LE LS */
5011 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls
, 0xFFFFFFFF, G2LE
),
5013 POWERPC_DEF("604", CPU_POWERPC_604
, 0xFFFFFFFF, 604),
5015 POWERPC_DEF("604e", CPU_POWERPC_604E
, 0xFFFFFFFF, 604),
5016 /* PowerPC 604e v1.0 */
5017 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10
, 0xFFFFFFFF, 604),
5018 /* PowerPC 604e v2.2 */
5019 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22
, 0xFFFFFFFF, 604),
5020 /* PowerPC 604e v2.4 */
5021 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24
, 0xFFFFFFFF, 604),
5023 POWERPC_DEF("604r", CPU_POWERPC_604R
, 0xFFFFFFFF, 604),
5026 POWERPC_DEF("604ev", CPU_POWERPC_604EV
, 0xFFFFFFFF, 604),
5028 /* PowerPC 7xx family */
5029 /* Generic PowerPC 740 (G3) */
5030 POWERPC_DEF("740", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
5031 /* Generic PowerPC 750 (G3) */
5032 POWERPC_DEF("750", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
5033 /* Code name for generic PowerPC 740/750 (G3) */
5034 POWERPC_DEF("Arthur", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
5035 /* PowerPC 740/750 is also known as G3 */
5036 POWERPC_DEF("G3", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
5037 /* PowerPC 740 v2.0 (G3) */
5038 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20
, 0xFFFFFFFF, 7x0
),
5039 /* PowerPC 750 v2.0 (G3) */
5040 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20
, 0xFFFFFFFF, 7x0
),
5041 /* PowerPC 740 v2.1 (G3) */
5042 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21
, 0xFFFFFFFF, 7x0
),
5043 /* PowerPC 750 v2.1 (G3) */
5044 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21
, 0xFFFFFFFF, 7x0
),
5045 /* PowerPC 740 v2.2 (G3) */
5046 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22
, 0xFFFFFFFF, 7x0
),
5047 /* PowerPC 750 v2.2 (G3) */
5048 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22
, 0xFFFFFFFF, 7x0
),
5049 /* PowerPC 740 v3.0 (G3) */
5050 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30
, 0xFFFFFFFF, 7x0
),
5051 /* PowerPC 750 v3.0 (G3) */
5052 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30
, 0xFFFFFFFF, 7x0
),
5053 /* PowerPC 740 v3.1 (G3) */
5054 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31
, 0xFFFFFFFF, 7x0
),
5055 /* PowerPC 750 v3.1 (G3) */
5056 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31
, 0xFFFFFFFF, 7x0
),
5057 /* PowerPC 740E (G3) */
5058 POWERPC_DEF("740e", CPU_POWERPC_740E
, 0xFFFFFFFF, 7x0
),
5059 /* PowerPC 740P (G3) */
5060 POWERPC_DEF("740p", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
5061 /* PowerPC 750P (G3) */
5062 POWERPC_DEF("750p", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
5063 /* Code name for PowerPC 740P/750P (G3) */
5064 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
5065 /* PowerPC 750CL (G3 embedded) */
5066 POWERPC_DEF("750cl", CPU_POWERPC_750CL
, 0xFFFFFFFF, 7x0
),
5067 /* PowerPC 750CX (G3 embedded) */
5068 POWERPC_DEF("750cx", CPU_POWERPC_750CX
, 0xFFFFFFFF, 7x0
),
5069 /* PowerPC 750CX v2.1 (G3 embedded) */
5070 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21
, 0xFFFFFFFF, 7x0
),
5071 /* PowerPC 750CX v2.2 (G3 embedded) */
5072 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22
, 0xFFFFFFFF, 7x0
),
5073 /* PowerPC 750CXe (G3 embedded) */
5074 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE
, 0xFFFFFFFF, 7x0
),
5075 /* PowerPC 750CXe v2.1 (G3 embedded) */
5076 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21
, 0xFFFFFFFF, 7x0
),
5077 /* PowerPC 750CXe v2.2 (G3 embedded) */
5078 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22
, 0xFFFFFFFF, 7x0
),
5079 /* PowerPC 750CXe v2.3 (G3 embedded) */
5080 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23
, 0xFFFFFFFF, 7x0
),
5081 /* PowerPC 750CXe v2.4 (G3 embedded) */
5082 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24
, 0xFFFFFFFF, 7x0
),
5083 /* PowerPC 750CXe v2.4b (G3 embedded) */
5084 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b
, 0xFFFFFFFF, 7x0
),
5085 /* PowerPC 750CXe v3.1 (G3 embedded) */
5086 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31
, 0xFFFFFFFF, 7x0
),
5087 /* PowerPC 750CXe v3.1b (G3 embedded) */
5088 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b
, 0xFFFFFFFF, 7x0
),
5089 /* PowerPC 750CXr (G3 embedded) */
5090 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR
, 0xFFFFFFFF, 7x0
),
5091 /* PowerPC 750E (G3) */
5092 POWERPC_DEF("750e", CPU_POWERPC_750E
, 0xFFFFFFFF, 7x0
),
5093 /* PowerPC 750FL (G3 embedded) */
5094 POWERPC_DEF("750fl", CPU_POWERPC_750FL
, 0xFFFFFFFF, 750fx
),
5095 /* PowerPC 750FX (G3 embedded) */
5096 POWERPC_DEF("750fx", CPU_POWERPC_750FX
, 0xFFFFFFFF, 750fx
),
5097 /* PowerPC 750FX v1.0 (G3 embedded) */
5098 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10
, 0xFFFFFFFF, 750fx
),
5099 /* PowerPC 750FX v2.0 (G3 embedded) */
5100 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20
, 0xFFFFFFFF, 750fx
),
5101 /* PowerPC 750FX v2.1 (G3 embedded) */
5102 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21
, 0xFFFFFFFF, 750fx
),
5103 /* PowerPC 750FX v2.2 (G3 embedded) */
5104 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22
, 0xFFFFFFFF, 750fx
),
5105 /* PowerPC 750FX v2.3 (G3 embedded) */
5106 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23
, 0xFFFFFFFF, 750fx
),
5107 /* PowerPC 750GL (G3 embedded) */
5108 POWERPC_DEF("750gl", CPU_POWERPC_750GL
, 0xFFFFFFFF, 750fx
),
5109 /* PowerPC 750GX (G3 embedded) */
5110 POWERPC_DEF("750gx", CPU_POWERPC_750GX
, 0xFFFFFFFF, 750fx
),
5111 /* PowerPC 750GX v1.0 (G3 embedded) */
5112 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10
, 0xFFFFFFFF, 750fx
),
5113 /* PowerPC 750GX v1.1 (G3 embedded) */
5114 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11
, 0xFFFFFFFF, 750fx
),
5115 /* PowerPC 750GX v1.2 (G3 embedded) */
5116 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12
, 0xFFFFFFFF, 750fx
),
5117 /* PowerPC 750L (G3 embedded) */
5118 POWERPC_DEF("750l", CPU_POWERPC_750L
, 0xFFFFFFFF, 7x0
),
5119 /* Code name for PowerPC 750L (G3 embedded) */
5120 POWERPC_DEF("LoneStar", CPU_POWERPC_750L
, 0xFFFFFFFF, 7x0
),
5121 /* PowerPC 750L v2.2 (G3 embedded) */
5122 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22
, 0xFFFFFFFF, 7x0
),
5123 /* PowerPC 750L v3.0 (G3 embedded) */
5124 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30
, 0xFFFFFFFF, 7x0
),
5125 /* PowerPC 750L v3.2 (G3 embedded) */
5126 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32
, 0xFFFFFFFF, 7x0
),
5127 /* Generic PowerPC 745 */
5128 POWERPC_DEF("745", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
5129 /* Generic PowerPC 755 */
5130 POWERPC_DEF("755", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
5131 /* Code name for PowerPC 745/755 */
5132 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
5133 /* PowerPC 745 v1.0 */
5134 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10
, 0xFFFFFFFF, 7x5
),
5135 /* PowerPC 755 v1.0 */
5136 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10
, 0xFFFFFFFF, 7x5
),
5137 /* PowerPC 745 v1.1 */
5138 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11
, 0xFFFFFFFF, 7x5
),
5139 /* PowerPC 755 v1.1 */
5140 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11
, 0xFFFFFFFF, 7x5
),
5141 /* PowerPC 745 v2.0 */
5142 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20
, 0xFFFFFFFF, 7x5
),
5143 /* PowerPC 755 v2.0 */
5144 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20
, 0xFFFFFFFF, 7x5
),
5145 /* PowerPC 745 v2.1 */
5146 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21
, 0xFFFFFFFF, 7x5
),
5147 /* PowerPC 755 v2.1 */
5148 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21
, 0xFFFFFFFF, 7x5
),
5149 /* PowerPC 745 v2.2 */
5150 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22
, 0xFFFFFFFF, 7x5
),
5151 /* PowerPC 755 v2.2 */
5152 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22
, 0xFFFFFFFF, 7x5
),
5153 /* PowerPC 745 v2.3 */
5154 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23
, 0xFFFFFFFF, 7x5
),
5155 /* PowerPC 755 v2.3 */
5156 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23
, 0xFFFFFFFF, 7x5
),
5157 /* PowerPC 745 v2.4 */
5158 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24
, 0xFFFFFFFF, 7x5
),
5159 /* PowerPC 755 v2.4 */
5160 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24
, 0xFFFFFFFF, 7x5
),
5161 /* PowerPC 745 v2.5 */
5162 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25
, 0xFFFFFFFF, 7x5
),
5163 /* PowerPC 755 v2.5 */
5164 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25
, 0xFFFFFFFF, 7x5
),
5165 /* PowerPC 745 v2.6 */
5166 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26
, 0xFFFFFFFF, 7x5
),
5167 /* PowerPC 755 v2.6 */
5168 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26
, 0xFFFFFFFF, 7x5
),
5169 /* PowerPC 745 v2.7 */
5170 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27
, 0xFFFFFFFF, 7x5
),
5171 /* PowerPC 755 v2.7 */
5172 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27
, 0xFFFFFFFF, 7x5
),
5173 /* PowerPC 745 v2.8 */
5174 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28
, 0xFFFFFFFF, 7x5
),
5175 /* PowerPC 755 v2.8 */
5176 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28
, 0xFFFFFFFF, 7x5
),
5178 /* PowerPC 745P (G3) */
5179 POWERPC_DEF("745p", CPU_POWERPC_7x5P
, 0xFFFFFFFF, 7x5
),
5180 /* PowerPC 755P (G3) */
5181 POWERPC_DEF("755p", CPU_POWERPC_7x5P
, 0xFFFFFFFF, 7x5
),
5183 /* PowerPC 74xx family */
5184 /* PowerPC 7400 (G4) */
5185 POWERPC_DEF("7400", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
5186 /* Code name for PowerPC 7400 */
5187 POWERPC_DEF("Max", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
5188 /* PowerPC 74xx is also well known as G4 */
5189 POWERPC_DEF("G4", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
5190 /* PowerPC 7400 v1.0 (G4) */
5191 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10
, 0xFFFFFFFF, 7400),
5192 /* PowerPC 7400 v1.1 (G4) */
5193 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11
, 0xFFFFFFFF, 7400),
5194 /* PowerPC 7400 v2.0 (G4) */
5195 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20
, 0xFFFFFFFF, 7400),
5196 /* PowerPC 7400 v2.2 (G4) */
5197 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22
, 0xFFFFFFFF, 7400),
5198 /* PowerPC 7400 v2.6 (G4) */
5199 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26
, 0xFFFFFFFF, 7400),
5200 /* PowerPC 7400 v2.7 (G4) */
5201 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27
, 0xFFFFFFFF, 7400),
5202 /* PowerPC 7400 v2.8 (G4) */
5203 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28
, 0xFFFFFFFF, 7400),
5204 /* PowerPC 7400 v2.9 (G4) */
5205 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29
, 0xFFFFFFFF, 7400),
5206 /* PowerPC 7410 (G4) */
5207 POWERPC_DEF("7410", CPU_POWERPC_7410
, 0xFFFFFFFF, 7410),
5208 /* Code name for PowerPC 7410 */
5209 POWERPC_DEF("Nitro", CPU_POWERPC_7410
, 0xFFFFFFFF, 7410),
5210 /* PowerPC 7410 v1.0 (G4) */
5211 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10
, 0xFFFFFFFF, 7410),
5212 /* PowerPC 7410 v1.1 (G4) */
5213 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11
, 0xFFFFFFFF, 7410),
5214 /* PowerPC 7410 v1.2 (G4) */
5215 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12
, 0xFFFFFFFF, 7410),
5216 /* PowerPC 7410 v1.3 (G4) */
5217 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13
, 0xFFFFFFFF, 7410),
5218 /* PowerPC 7410 v1.4 (G4) */
5219 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14
, 0xFFFFFFFF, 7410),
5220 /* PowerPC 7448 (G4) */
5221 POWERPC_DEF("7448", CPU_POWERPC_7448
, 0xFFFFFFFF, 7400),
5222 /* PowerPC 7448 v1.0 (G4) */
5223 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10
, 0xFFFFFFFF, 7400),
5224 /* PowerPC 7448 v1.1 (G4) */
5225 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11
, 0xFFFFFFFF, 7400),
5226 /* PowerPC 7448 v2.0 (G4) */
5227 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20
, 0xFFFFFFFF, 7400),
5228 /* PowerPC 7448 v2.1 (G4) */
5229 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21
, 0xFFFFFFFF, 7400),
5231 /* PowerPC 7450 (G4) */
5232 POWERPC_DEF("7450", CPU_POWERPC_7450
, 0xFFFFFFFF, 7450),
5233 /* Code name for PowerPC 7450 */
5234 POWERPC_DEF("Vger", CPU_POWERPC_7450
, 0xFFFFFFFF, 7450),
5237 /* PowerPC 7450 v1.0 (G4) */
5238 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10
, 0xFFFFFFFF, 7450),
5241 /* PowerPC 7450 v1.1 (G4) */
5242 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11
, 0xFFFFFFFF, 7450),
5245 /* PowerPC 7450 v1.2 (G4) */
5246 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12
, 0xFFFFFFFF, 7450),
5249 /* PowerPC 7450 v2.0 (G4) */
5250 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20
, 0xFFFFFFFF, 7450),
5253 /* PowerPC 7450 v2.1 (G4) */
5254 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21
, 0xFFFFFFFF, 7450),
5257 /* PowerPC 7441 (G4) */
5258 POWERPC_DEF("7441", CPU_POWERPC_74x1
, 0xFFFFFFFF, 7440),
5259 /* PowerPC 7451 (G4) */
5260 POWERPC_DEF("7451", CPU_POWERPC_74x1
, 0xFFFFFFFF, 7450),
5263 /* PowerPC 7441g (G4) */
5264 POWERPC_DEF("7441g", CPU_POWERPC_74x1G
, 0xFFFFFFFF, 7440),
5265 /* PowerPC 7451g (G4) */
5266 POWERPC_DEF("7451g", CPU_POWERPC_74x1G
, 0xFFFFFFFF, 7450),
5269 /* PowerPC 7445 (G4) */
5270 POWERPC_DEF("7445", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7445),
5271 /* PowerPC 7455 (G4) */
5272 POWERPC_DEF("7455", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7455),
5273 /* Code name for PowerPC 7445/7455 */
5274 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7455),
5277 /* PowerPC 7445 v1.0 (G4) */
5278 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10
, 0xFFFFFFFF, 7445),
5279 /* PowerPC 7455 v1.0 (G4) */
5280 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10
, 0xFFFFFFFF, 7455),
5283 /* PowerPC 7445 v2.1 (G4) */
5284 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21
, 0xFFFFFFFF, 7445),
5285 /* PowerPC 7455 v2.1 (G4) */
5286 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21
, 0xFFFFFFFF, 7455),
5289 /* PowerPC 7445 v3.2 (G4) */
5290 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32
, 0xFFFFFFFF, 7445),
5291 /* PowerPC 7455 v3.2 (G4) */
5292 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32
, 0xFFFFFFFF, 7455),
5295 /* PowerPC 7445 v3.3 (G4) */
5296 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33
, 0xFFFFFFFF, 7445),
5297 /* PowerPC 7455 v3.3 (G4) */
5298 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33
, 0xFFFFFFFF, 7455),
5301 /* PowerPC 7445 v3.4 (G4) */
5302 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34
, 0xFFFFFFFF, 7445),
5303 /* PowerPC 7455 v3.4 (G4) */
5304 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34
, 0xFFFFFFFF, 7455),
5307 /* PowerPC 7447 (G4) */
5308 POWERPC_DEF("7447", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7445),
5309 /* PowerPC 7457 (G4) */
5310 POWERPC_DEF("7457", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7455),
5311 /* Code name for PowerPC 7447/7457 */
5312 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7455),
5315 /* PowerPC 7447 v1.0 (G4) */
5316 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7445),
5317 /* PowerPC 7457 v1.0 (G4) */
5318 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7455),
5319 /* Code name for PowerPC 7447A/7457A */
5320 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7455),
5323 /* PowerPC 7447 v1.1 (G4) */
5324 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11
, 0xFFFFFFFF, 7445),
5325 /* PowerPC 7457 v1.1 (G4) */
5326 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11
, 0xFFFFFFFF, 7455),
5329 /* PowerPC 7447 v1.2 (G4) */
5330 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12
, 0xFFFFFFFF, 7445),
5331 /* PowerPC 7457 v1.2 (G4) */
5332 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12
, 0xFFFFFFFF, 7455),
5334 /* 64 bits PowerPC */
5335 #if defined (TARGET_PPC64)
5338 POWERPC_DEF("620", CPU_POWERPC_620
, 0xFFFFFFFF, 620),
5341 /* PowerPC 630 (POWER3) */
5342 POWERPC_DEF("630", CPU_POWERPC_630
, 0xFFFFFFFF, 630),
5343 POWERPC_DEF("POWER3", CPU_POWERPC_630
, 0xFFFFFFFF, 630),
5346 /* PowerPC 631 (Power 3+) */
5347 POWERPC_DEF("631", CPU_POWERPC_631
, 0xFFFFFFFF, 631),
5348 POWERPC_DEF("POWER3+", CPU_POWERPC_631
, 0xFFFFFFFF, 631),
5352 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4
, 0xFFFFFFFF, POWER4
),
5356 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P
, 0xFFFFFFFF, POWER4P
),
5360 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5
, 0xFFFFFFFF, POWER5
),
5362 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR
, 0xFFFFFFFF, POWER5
),
5366 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P
, 0xFFFFFFFF, POWER5P
),
5368 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS
, 0xFFFFFFFF, POWER5P
),
5372 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6
, 0xFFFFFFFF, POWER6
),
5373 /* POWER6 running in POWER5 mode */
5374 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5
, 0xFFFFFFFF, POWER5
),
5376 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A
, 0xFFFFFFFF, POWER6
),
5379 POWERPC_DEF("970", CPU_POWERPC_970
, 0xFFFFFFFF, 970),
5380 /* PowerPC 970FX (G5) */
5381 POWERPC_DEF("970fx", CPU_POWERPC_970FX
, 0xFFFFFFFF, 970FX
),
5382 /* PowerPC 970FX v1.0 (G5) */
5383 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10
, 0xFFFFFFFF, 970FX
),
5384 /* PowerPC 970FX v2.0 (G5) */
5385 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20
, 0xFFFFFFFF, 970FX
),
5386 /* PowerPC 970FX v2.1 (G5) */
5387 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21
, 0xFFFFFFFF, 970FX
),
5388 /* PowerPC 970FX v3.0 (G5) */
5389 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30
, 0xFFFFFFFF, 970FX
),
5390 /* PowerPC 970FX v3.1 (G5) */
5391 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31
, 0xFFFFFFFF, 970FX
),
5392 /* PowerPC 970GX (G5) */
5393 POWERPC_DEF("970gx", CPU_POWERPC_970GX
, 0xFFFFFFFF, 970GX
),
5395 POWERPC_DEF("970mp", CPU_POWERPC_970MP
, 0xFFFFFFFF, 970),
5396 /* PowerPC 970MP v1.0 */
5397 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10
, 0xFFFFFFFF, 970),
5398 /* PowerPC 970MP v1.1 */
5399 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11
, 0xFFFFFFFF, 970),
5402 POWERPC_DEF("Cell", CPU_POWERPC_CELL
, 0xFFFFFFFF, 970),
5405 /* PowerPC Cell v1.0 */
5406 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10
, 0xFFFFFFFF, 970),
5409 /* PowerPC Cell v2.0 */
5410 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20
, 0xFFFFFFFF, 970),
5413 /* PowerPC Cell v3.0 */
5414 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30
, 0xFFFFFFFF, 970),
5417 /* PowerPC Cell v3.1 */
5418 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31
, 0xFFFFFFFF, 970),
5421 /* PowerPC Cell v3.2 */
5422 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32
, 0xFFFFFFFF, 970),
5425 /* RS64 (Apache/A35) */
5426 /* This one seems to support the whole POWER2 instruction set
5427 * and the PowerPC 64 one.
5429 /* What about A10 & A30 ? */
5430 POWERPC_DEF("RS64", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
5431 POWERPC_DEF("Apache", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
5432 POWERPC_DEF("A35", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
5435 /* RS64-II (NorthStar/A50) */
5436 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
5437 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
5438 POWERPC_DEF("A50", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
5441 /* RS64-III (Pulsar) */
5442 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III
, 0xFFFFFFFF, RS64
),
5443 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III
, 0xFFFFFFFF, RS64
),
5446 /* RS64-IV (IceStar/IStar/SStar) */
5447 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5448 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5449 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5450 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5452 #endif /* defined (TARGET_PPC64) */
5455 /* Original POWER */
5456 POWERPC_DEF("POWER", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5457 POWERPC_DEF("RIOS", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5458 POWERPC_DEF("RSC", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5459 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5460 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5464 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5465 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5466 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5471 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T
, 0xFFFFFFFF, PA6T
),
5473 /* Generic PowerPCs */
5474 #if defined (TARGET_PPC64)
5476 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64
, 0xFFFFFFFF, PPC64
),
5479 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32
, 0xFFFFFFFF, PPC32
),
5480 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT
, 0xFFFFFFFF, DEFAULT
),
5482 POWERPC_DEF("default", CPU_POWERPC_DEFAULT
, 0xFFFFFFFF, DEFAULT
),
5485 /*****************************************************************************/
5486 /* Generic CPU instanciation routine */
5487 static void init_ppc_proc (CPUPPCState
*env
, ppc_def_t
*def
)
5489 #if !defined(CONFIG_USER_ONLY)
5492 env
->irq_inputs
= NULL
;
5493 /* Set all exception vectors to an invalid address */
5494 for (i
= 0; i
< POWERPC_EXCP_NB
; i
++)
5495 env
->excp_vectors
[i
] = (target_ulong
)(-1ULL);
5496 env
->excp_prefix
= 0x00000000;
5497 env
->ivor_mask
= 0x00000000;
5498 env
->ivpr_mask
= 0x00000000;
5500 /* Default MMU definitions */
5504 /* Register SPR common to all PowerPC implementations */
5505 gen_spr_generic(env
);
5506 spr_register(env
, SPR_PVR
, "PVR",
5507 SPR_NOACCESS
, SPR_NOACCESS
,
5508 &spr_read_generic
, SPR_NOACCESS
,
5510 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5511 (*def
->init_proc
)(env
);
5512 /* Allocate TLBs buffer when needed */
5513 if (env
->nb_tlb
!= 0) {
5514 int nb_tlb
= env
->nb_tlb
;
5515 if (env
->id_tlbs
!= 0)
5517 env
->tlb
= qemu_mallocz(nb_tlb
* sizeof(ppc_tlb_t
));
5518 /* Pre-compute some useful values */
5519 env
->tlb_per_way
= env
->nb_tlb
/ env
->nb_ways
;
5521 #if !defined(CONFIG_USER_ONLY)
5522 if (env
->irq_inputs
== NULL
) {
5523 fprintf(stderr
, "WARNING: no internal IRQ controller registered.\n"
5524 " Attempt Qemu to crash very soon !\n");
5529 #if defined(PPC_DUMP_CPU)
5530 static void dump_ppc_sprs (CPUPPCState
*env
)
5533 #if !defined(CONFIG_USER_ONLY)
5539 printf("Special purpose registers:\n");
5540 for (i
= 0; i
< 32; i
++) {
5541 for (j
= 0; j
< 32; j
++) {
5543 spr
= &env
->spr_cb
[n
];
5544 uw
= spr
->uea_write
!= NULL
&& spr
->uea_write
!= SPR_NOACCESS
;
5545 ur
= spr
->uea_read
!= NULL
&& spr
->uea_read
!= SPR_NOACCESS
;
5546 #if !defined(CONFIG_USER_ONLY)
5547 sw
= spr
->oea_write
!= NULL
&& spr
->oea_write
!= SPR_NOACCESS
;
5548 sr
= spr
->oea_read
!= NULL
&& spr
->oea_read
!= SPR_NOACCESS
;
5549 if (sw
|| sr
|| uw
|| ur
) {
5550 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
5551 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
5552 sw
? 'w' : '-', sr
? 'r' : '-',
5553 uw
? 'w' : '-', ur
? 'r' : '-');
5557 printf("SPR: %4d (%03x) %-8s u%c%c\n",
5558 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
5559 uw
? 'w' : '-', ur
? 'r' : '-');
5569 /*****************************************************************************/
5573 int fflush (FILE *stream
);
5577 PPC_DIRECT
= 0, /* Opcode routine */
5578 PPC_INDIRECT
= 1, /* Indirect opcode table */
5581 static inline int is_indirect_opcode (void *handler
)
5583 return ((unsigned long)handler
& 0x03) == PPC_INDIRECT
;
5586 static inline opc_handler_t
**ind_table(void *handler
)
5588 return (opc_handler_t
**)((unsigned long)handler
& ~3);
5591 /* Instruction table creation */
5592 /* Opcodes tables creation */
5593 static void fill_new_table (opc_handler_t
**table
, int len
)
5597 for (i
= 0; i
< len
; i
++)
5598 table
[i
] = &invalid_handler
;
5601 static int create_new_table (opc_handler_t
**table
, unsigned char idx
)
5603 opc_handler_t
**tmp
;
5605 tmp
= malloc(0x20 * sizeof(opc_handler_t
));
5608 fill_new_table(tmp
, 0x20);
5609 table
[idx
] = (opc_handler_t
*)((unsigned long)tmp
| PPC_INDIRECT
);
5614 static int insert_in_table (opc_handler_t
**table
, unsigned char idx
,
5615 opc_handler_t
*handler
)
5617 if (table
[idx
] != &invalid_handler
)
5619 table
[idx
] = handler
;
5624 static int register_direct_insn (opc_handler_t
**ppc_opcodes
,
5625 unsigned char idx
, opc_handler_t
*handler
)
5627 if (insert_in_table(ppc_opcodes
, idx
, handler
) < 0) {
5628 printf("*** ERROR: opcode %02x already assigned in main "
5629 "opcode table\n", idx
);
5636 static int register_ind_in_table (opc_handler_t
**table
,
5637 unsigned char idx1
, unsigned char idx2
,
5638 opc_handler_t
*handler
)
5640 if (table
[idx1
] == &invalid_handler
) {
5641 if (create_new_table(table
, idx1
) < 0) {
5642 printf("*** ERROR: unable to create indirect table "
5643 "idx=%02x\n", idx1
);
5647 if (!is_indirect_opcode(table
[idx1
])) {
5648 printf("*** ERROR: idx %02x already assigned to a direct "
5653 if (handler
!= NULL
&&
5654 insert_in_table(ind_table(table
[idx1
]), idx2
, handler
) < 0) {
5655 printf("*** ERROR: opcode %02x already assigned in "
5656 "opcode table %02x\n", idx2
, idx1
);
5663 static int register_ind_insn (opc_handler_t
**ppc_opcodes
,
5664 unsigned char idx1
, unsigned char idx2
,
5665 opc_handler_t
*handler
)
5669 ret
= register_ind_in_table(ppc_opcodes
, idx1
, idx2
, handler
);
5674 static int register_dblind_insn (opc_handler_t
**ppc_opcodes
,
5675 unsigned char idx1
, unsigned char idx2
,
5676 unsigned char idx3
, opc_handler_t
*handler
)
5678 if (register_ind_in_table(ppc_opcodes
, idx1
, idx2
, NULL
) < 0) {
5679 printf("*** ERROR: unable to join indirect table idx "
5680 "[%02x-%02x]\n", idx1
, idx2
);
5683 if (register_ind_in_table(ind_table(ppc_opcodes
[idx1
]), idx2
, idx3
,
5685 printf("*** ERROR: unable to insert opcode "
5686 "[%02x-%02x-%02x]\n", idx1
, idx2
, idx3
);
5693 static int register_insn (opc_handler_t
**ppc_opcodes
, opcode_t
*insn
)
5695 if (insn
->opc2
!= 0xFF) {
5696 if (insn
->opc3
!= 0xFF) {
5697 if (register_dblind_insn(ppc_opcodes
, insn
->opc1
, insn
->opc2
,
5698 insn
->opc3
, &insn
->handler
) < 0)
5701 if (register_ind_insn(ppc_opcodes
, insn
->opc1
,
5702 insn
->opc2
, &insn
->handler
) < 0)
5706 if (register_direct_insn(ppc_opcodes
, insn
->opc1
, &insn
->handler
) < 0)
5713 static int test_opcode_table (opc_handler_t
**table
, int len
)
5717 for (i
= 0, count
= 0; i
< len
; i
++) {
5718 /* Consistency fixup */
5719 if (table
[i
] == NULL
)
5720 table
[i
] = &invalid_handler
;
5721 if (table
[i
] != &invalid_handler
) {
5722 if (is_indirect_opcode(table
[i
])) {
5723 tmp
= test_opcode_table(ind_table(table
[i
]), 0x20);
5726 table
[i
] = &invalid_handler
;
5739 static void fix_opcode_tables (opc_handler_t
**ppc_opcodes
)
5741 if (test_opcode_table(ppc_opcodes
, 0x40) == 0)
5742 printf("*** WARNING: no opcode defined !\n");
5745 /*****************************************************************************/
5746 static int create_ppc_opcodes (CPUPPCState
*env
, ppc_def_t
*def
)
5748 opcode_t
*opc
, *start
, *end
;
5750 fill_new_table(env
->opcodes
, 0x40);
5751 if (&opc_start
< &opc_end
) {
5758 for (opc
= start
+ 1; opc
!= end
; opc
++) {
5759 if ((opc
->handler
.type
& def
->insns_flags
) != 0) {
5760 if (register_insn(env
->opcodes
, opc
) < 0) {
5761 printf("*** ERROR initializing PowerPC instruction "
5762 "0x%02x 0x%02x 0x%02x\n", opc
->opc1
, opc
->opc2
,
5768 fix_opcode_tables(env
->opcodes
);
5775 #if defined(PPC_DUMP_CPU)
5776 static int dump_ppc_insns (CPUPPCState
*env
)
5778 opc_handler_t
**table
, *handler
;
5779 uint8_t opc1
, opc2
, opc3
;
5781 printf("Instructions set:\n");
5782 /* opc1 is 6 bits long */
5783 for (opc1
= 0x00; opc1
< 0x40; opc1
++) {
5784 table
= env
->opcodes
;
5785 handler
= table
[opc1
];
5786 if (is_indirect_opcode(handler
)) {
5787 /* opc2 is 5 bits long */
5788 for (opc2
= 0; opc2
< 0x20; opc2
++) {
5789 table
= env
->opcodes
;
5790 handler
= env
->opcodes
[opc1
];
5791 table
= ind_table(handler
);
5792 handler
= table
[opc2
];
5793 if (is_indirect_opcode(handler
)) {
5794 table
= ind_table(handler
);
5795 /* opc3 is 5 bits long */
5796 for (opc3
= 0; opc3
< 0x20; opc3
++) {
5797 handler
= table
[opc3
];
5798 if (handler
->handler
!= &gen_invalid
) {
5799 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
5800 opc1
, opc2
, opc3
, opc1
, (opc3
<< 5) | opc2
,
5805 if (handler
->handler
!= &gen_invalid
) {
5806 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
5807 opc1
, opc2
, opc1
, opc2
, handler
->oname
);
5812 if (handler
->handler
!= &gen_invalid
) {
5813 printf("INSN: %02x -- -- (%02d ----) : %s\n",
5814 opc1
, opc1
, handler
->oname
);
5821 int cpu_ppc_register (CPUPPCState
*env
, ppc_def_t
*def
)
5823 env
->msr_mask
= def
->msr_mask
;
5824 env
->mmu_model
= def
->mmu_model
;
5825 env
->excp_model
= def
->excp_model
;
5826 env
->bus_model
= def
->bus_model
;
5827 env
->bfd_mach
= def
->bfd_mach
;
5828 if (create_ppc_opcodes(env
, def
) < 0)
5830 init_ppc_proc(env
, def
);
5831 #if defined(PPC_DUMP_CPU)
5833 const unsigned char *mmu_model
, *excp_model
, *bus_model
;
5834 switch (env
->mmu_model
) {
5835 case POWERPC_MMU_32B
:
5836 mmu_model
= "PowerPC 32";
5838 case POWERPC_MMU_64B
:
5839 mmu_model
= "PowerPC 64";
5841 case POWERPC_MMU_601
:
5842 mmu_model
= "PowerPC 601";
5844 case POWERPC_MMU_SOFT_6xx
:
5845 mmu_model
= "PowerPC 6xx/7xx with software driven TLBs";
5847 case POWERPC_MMU_SOFT_74xx
:
5848 mmu_model
= "PowerPC 74xx with software driven TLBs";
5850 case POWERPC_MMU_SOFT_4xx
:
5851 mmu_model
= "PowerPC 4xx with software driven TLBs";
5853 case POWERPC_MMU_SOFT_4xx_Z
:
5854 mmu_model
= "PowerPC 4xx with software driven TLBs "
5855 "and zones protections";
5857 case POWERPC_MMU_REAL_4xx
:
5858 mmu_model
= "PowerPC 4xx real mode only";
5860 case POWERPC_MMU_BOOKE
:
5861 mmu_model
= "PowerPC BookE";
5863 case POWERPC_MMU_BOOKE_FSL
:
5864 mmu_model
= "PowerPC BookE FSL";
5866 case POWERPC_MMU_64BRIDGE
:
5867 mmu_model
= "PowerPC 64 bridge";
5870 mmu_model
= "Unknown or invalid";
5873 switch (env
->excp_model
) {
5874 case POWERPC_EXCP_STD
:
5875 excp_model
= "PowerPC";
5877 case POWERPC_EXCP_40x
:
5878 excp_model
= "PowerPC 40x";
5880 case POWERPC_EXCP_601
:
5881 excp_model
= "PowerPC 601";
5883 case POWERPC_EXCP_602
:
5884 excp_model
= "PowerPC 602";
5886 case POWERPC_EXCP_603
:
5887 excp_model
= "PowerPC 603";
5889 case POWERPC_EXCP_603E
:
5890 excp_model
= "PowerPC 603e";
5892 case POWERPC_EXCP_604
:
5893 excp_model
= "PowerPC 604";
5895 case POWERPC_EXCP_7x0
:
5896 excp_model
= "PowerPC 740/750";
5898 case POWERPC_EXCP_7x5
:
5899 excp_model
= "PowerPC 745/755";
5901 case POWERPC_EXCP_74xx
:
5902 excp_model
= "PowerPC 74xx";
5904 case POWERPC_EXCP_970
:
5905 excp_model
= "PowerPC 970";
5907 case POWERPC_EXCP_BOOKE
:
5908 excp_model
= "PowerPC BookE";
5911 excp_model
= "Unknown or invalid";
5914 switch (env
->bus_model
) {
5915 case PPC_FLAGS_INPUT_6xx
:
5916 bus_model
= "PowerPC 6xx";
5918 case PPC_FLAGS_INPUT_BookE
:
5919 bus_model
= "PowerPC BookE";
5921 case PPC_FLAGS_INPUT_405
:
5922 bus_model
= "PowerPC 405";
5924 case PPC_FLAGS_INPUT_970
:
5925 bus_model
= "PowerPC 970";
5927 case PPC_FLAGS_INPUT_401
:
5928 bus_model
= "PowerPC 401/403";
5931 bus_model
= "Unknown or invalid";
5934 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64
"\n"
5935 " MMU model : %s\n",
5936 def
->name
, def
->pvr
, def
->msr_mask
, mmu_model
);
5937 if (env
->tlb
!= NULL
) {
5938 printf(" %d %s TLB in %d ways\n",
5939 env
->nb_tlb
, env
->id_tlbs
? "splitted" : "merged",
5942 printf(" Exceptions model : %s\n"
5943 " Bus model : %s\n",
5944 excp_model
, bus_model
);
5946 dump_ppc_insns(env
);
5954 int ppc_find_by_name (const unsigned char *name
, ppc_def_t
**def
)
5960 max
= sizeof(ppc_defs
) / sizeof(ppc_def_t
);
5961 for (i
= 0; i
< max
; i
++) {
5962 if (strcasecmp(name
, ppc_defs
[i
].name
) == 0) {
5963 *def
= &ppc_defs
[i
];
5972 int ppc_find_by_pvr (uint32_t pvr
, ppc_def_t
**def
)
5978 max
= sizeof(ppc_defs
) / sizeof(ppc_def_t
);
5979 for (i
= 0; i
< max
; i
++) {
5980 if ((pvr
& ppc_defs
[i
].pvr_mask
) ==
5981 (ppc_defs
[i
].pvr
& ppc_defs
[i
].pvr_mask
)) {
5982 *def
= &ppc_defs
[i
];
5991 void ppc_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
5995 max
= sizeof(ppc_defs
) / sizeof(ppc_def_t
);
5996 for (i
= 0; i
< max
; i
++) {
5997 (*cpu_fprintf
)(f
, "PowerPC %-16s PVR %08x\n",
5998 ppc_defs
[i
].name
, ppc_defs
[i
].pvr
);