target-ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if !defined (__CPU_PPC_H__)
  21 #define __CPU_PPC_H__
  22
  23 #include "config.h"
  24 #include <inttypes.h>
  25
  26 #if defined (TARGET_PPC64)
  27 typedef uint64_t ppc_gpr_t;
  28 #define TARGET_GPR_BITS  64
  29 #define TARGET_LONG_BITS 64
  30 #define REGX "%016" PRIx64
  31 #define TARGET_PAGE_BITS 12
  32 #elif defined(TARGET_PPCEMB)
  33 /* BookE have 36 bits physical address space */
  34 #define TARGET_PHYS_ADDR_BITS 64
  35 /* GPR are 64 bits: used by vector extension */
  36 typedef uint64_t ppc_gpr_t;
  37 #define TARGET_GPR_BITS  64
  38 #define TARGET_LONG_BITS 32
  39 #define REGX "%016" PRIx64
  40 #if defined(CONFIG_USER_ONLY)
  41 /* It looks like a lot of Linux programs assume page size
  42  * is 4kB long. This is evil, but we have to deal with it...
  43  */
  44 #define TARGET_PAGE_BITS 12
  45 #else
  46 /* Pages can be 1 kB small */
  47 #define TARGET_PAGE_BITS 10
  48 #endif
  49 #else
  50 #if (HOST_LONG_BITS >= 64)
  51 /* When using 64 bits temporary registers,
  52  * we can use 64 bits GPR with no extra cost
  53  * It's even an optimization as it will prevent
  54  * the compiler to do unuseful masking in the micro-ops.
  55  */
  56 typedef uint64_t ppc_gpr_t;
  57 #define TARGET_GPR_BITS  64
  58 #define REGX "%08" PRIx64
  59 #else
  60 typedef uint32_t ppc_gpr_t;
  61 #define TARGET_GPR_BITS  32
  62 #define REGX "%08" PRIx32
  63 #endif
  64 #define TARGET_LONG_BITS 32
  65 #define TARGET_PAGE_BITS 12
  66 #endif
  67
  68 #include "cpu-defs.h"
  69
  70 #define ADDRX TARGET_FMT_lx
  71 #define PADDRX TARGET_FMT_plx
  72
  73 #include <setjmp.h>
  74
  75 #include "softfloat.h"
  76
  77 #define TARGET_HAS_ICE 1
  78
  79 #if defined (TARGET_PPC64)
  80 #define ELF_MACHINE     EM_PPC64
  81 #else
  82 #define ELF_MACHINE     EM_PPC
  83 #endif
  84
  85 /* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
  86  *                              have different cache line sizes
  87  */
  88 #define ICACHE_LINE_SIZE 32
  89 #define DCACHE_LINE_SIZE 32
  90
  91 /*****************************************************************************/
  92 /* MMU model                                                                 */
  93 enum {
  94     POWERPC_MMU_UNKNOWN    = 0,
  95     /* Standard 32 bits PowerPC MMU                            */
  96     POWERPC_MMU_32B,
  97     /* Standard 64 bits PowerPC MMU                            */
  98     POWERPC_MMU_64B,
  99     /* PowerPC 601 MMU                                         */
 100     POWERPC_MMU_601,
 101     /* PowerPC 6xx MMU with software TLB                       */
 102     POWERPC_MMU_SOFT_6xx,
 103     /* PowerPC 74xx MMU with software TLB                      */
 104     POWERPC_MMU_SOFT_74xx,
 105     /* PowerPC 4xx MMU with software TLB                       */
 106     POWERPC_MMU_SOFT_4xx,
 107     /* PowerPC 4xx MMU with software TLB and zones protections */
 108     POWERPC_MMU_SOFT_4xx_Z,
 109     /* PowerPC 4xx MMU in real mode only                       */
 110     POWERPC_MMU_REAL_4xx,
 111     /* BookE MMU model                                         */
 112     POWERPC_MMU_BOOKE,
 113     /* BookE FSL MMU model                                     */
 114     POWERPC_MMU_BOOKE_FSL,
 115     /* 64 bits "bridge" PowerPC MMU                            */
 116     POWERPC_MMU_64BRIDGE,
 117 };
 118
 119 /*****************************************************************************/
 120 /* Exception model                                                           */
 121 enum {
 122     POWERPC_EXCP_UNKNOWN   = 0,
 123     /* Standard PowerPC exception model */
 124     POWERPC_EXCP_STD,
 125     /* PowerPC 40x exception model      */
 126     POWERPC_EXCP_40x,
 127     /* PowerPC 601 exception model      */
 128     POWERPC_EXCP_601,
 129     /* PowerPC 602 exception model      */
 130     POWERPC_EXCP_602,
 131     /* PowerPC 603 exception model      */
 132     POWERPC_EXCP_603,
 133     /* PowerPC 603e exception model     */
 134     POWERPC_EXCP_603E,
 135     /* PowerPC G2 exception model       */
 136     POWERPC_EXCP_G2,
 137     /* PowerPC 604 exception model      */
 138     POWERPC_EXCP_604,
 139     /* PowerPC 7x0 exception model      */
 140     POWERPC_EXCP_7x0,
 141     /* PowerPC 7x5 exception model      */
 142     POWERPC_EXCP_7x5,
 143     /* PowerPC 74xx exception model     */
 144     POWERPC_EXCP_74xx,
 145     /* PowerPC 970 exception model      */
 146     POWERPC_EXCP_970,
 147     /* BookE exception model            */
 148     POWERPC_EXCP_BOOKE,
 149 };
 150
 151 /*****************************************************************************/
 152 /* Exception vectors definitions                                             */
 153 enum {
 154     POWERPC_EXCP_NONE    = -1,
 155     /* The 64 first entries are used by the PowerPC embedded specification   */
 156     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
 157     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
 158     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
 159     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
 160     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
 161     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
 162     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
 163     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
 164     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 165     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 166     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 167     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 168     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 169     POWERPC_EXCP_DTLB     = 13, /* Data TLB error                            */
 170     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB error                     */
 171     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 172     /* Vectors 16 to 31 are reserved                                         */
 173 #if defined(TARGET_PPCEMB)
 174     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 175     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 176     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 177     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 178     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 179     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 180 #endif /* defined(TARGET_PPCEMB) */
 181     /* Vectors 38 to 63 are reserved                                         */
 182     /* Exceptions defined in the PowerPC server specification                */
 183     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 184 #if defined(TARGET_PPC64) /* PowerPC 64 */
 185     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 186     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 187 #endif /* defined(TARGET_PPC64) */
 188 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
 189     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 190 #endif /* defined(TARGET_PPC64H) */
 191     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 192 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
 193     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 194     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 195     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 196     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 197 #endif /* defined(TARGET_PPC64H) */
 198     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 199     /* 40x specific exceptions                                               */
 200     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 201     /* 601 specific exceptions                                               */
 202     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 203     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 204     /* 602 specific exceptions                                               */
 205     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 206     /* 602/603 specific exceptions                                           */
 207     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB error               */
 208     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 209     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 210     /* Exceptions available on most PowerPC                                  */
 211     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 212     POWERPC_EXCP_IABR     = 82, /* Instruction address breakpoint            */
 213     POWERPC_EXCP_SMI      = 83, /* System management interrupt               */
 214     POWERPC_EXCP_PERFM    = 84, /* Embedded performance monitor interrupt    */
 215     /* 7xx/74xx specific exceptions                                          */
 216     POWERPC_EXCP_THERM    = 85, /* Thermal interrupt                         */
 217     /* 74xx specific exceptions                                              */
 218     POWERPC_EXCP_VPUA     = 86, /* Vector assist exception                   */
 219     /* 970FX specific exceptions                                             */
 220     POWERPC_EXCP_SOFTP    = 87, /* Soft patch exception                      */
 221     POWERPC_EXCP_MAINT    = 88, /* Maintenance exception                     */
 222     /* EOL                                                                   */
 223     POWERPC_EXCP_NB       = 96,
 224     /* Qemu exceptions: used internally during code translation              */
 225     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 226     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 227     /* Qemu exceptions: special cases we want to stop translation            */
 228     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 229     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 230 };
 231
 232
 233 /* Exceptions error codes                                                    */
 234 enum {
 235     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 236     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 237     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 238     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 239     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 240     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 241     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 242     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 243     /* FP exceptions                                                         */
 244     POWERPC_EXCP_FP            = 0x10,
 245     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 246     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 247     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 248     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 249     POWERPC_EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op                */
 250     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 251     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 252     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 253     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 254     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 255     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 256     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 257     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 258     /* Invalid instruction                                                   */
 259     POWERPC_EXCP_INVAL         = 0x20,
 260     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 261     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 262     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 263     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 264     /* Privileged instruction                                                */
 265     POWERPC_EXCP_PRIV          = 0x30,
 266     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 267     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 268     /* Trap                                                                  */
 269     POWERPC_EXCP_TRAP          = 0x40,
 270 };
 271
 272 /*****************************************************************************/
 273 /* Input pins model                                                          */
 274 enum {
 275     PPC_FLAGS_INPUT_UNKNOWN = 0,
 276     /* PowerPC 6xx bus                  */
 277     PPC_FLAGS_INPUT_6xx,
 278     /* BookE bus                        */
 279     PPC_FLAGS_INPUT_BookE,
 280     /* PowerPC 405 bus                  */
 281     PPC_FLAGS_INPUT_405,
 282     /* PowerPC 970 bus                  */
 283     PPC_FLAGS_INPUT_970,
 284     /* PowerPC 401 bus                  */
 285     PPC_FLAGS_INPUT_401,
 286 };
 287
 288 #define PPC_INPUT(env) (env->bus_model)
 289
 290 /*****************************************************************************/
 291 typedef struct ppc_def_t ppc_def_t;
 292 typedef struct opc_handler_t opc_handler_t;
 293
 294 /*****************************************************************************/
 295 /* Types used to describe some PowerPC registers */
 296 typedef struct CPUPPCState CPUPPCState;
 297 typedef struct ppc_tb_t ppc_tb_t;
 298 typedef struct ppc_spr_t ppc_spr_t;
 299 typedef struct ppc_dcr_t ppc_dcr_t;
 300 typedef struct ppc_avr_t ppc_avr_t;
 301 typedef union ppc_tlb_t ppc_tlb_t;
 302
 303 /* SPR access micro-ops generations callbacks */
 304 struct ppc_spr_t {
 305     void (*uea_read)(void *opaque, int spr_num);
 306     void (*uea_write)(void *opaque, int spr_num);
 307 #if !defined(CONFIG_USER_ONLY)
 308     void (*oea_read)(void *opaque, int spr_num);
 309     void (*oea_write)(void *opaque, int spr_num);
 310 #if defined(TARGET_PPC64H)
 311     void (*hea_read)(void *opaque, int spr_num);
 312     void (*hea_write)(void *opaque, int spr_num);
 313 #endif
 314 #endif
 315     const unsigned char *name;
 316 };
 317
 318 /* Altivec registers (128 bits) */
 319 struct ppc_avr_t {
 320     uint32_t u[4];
 321 };
 322
 323 /* Software TLB cache */
 324 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 325 struct ppc6xx_tlb_t {
 326     target_ulong pte0;
 327     target_ulong pte1;
 328     target_ulong EPN;
 329 };
 330
 331 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 332 struct ppcemb_tlb_t {
 333     target_phys_addr_t RPN;
 334     target_ulong EPN;
 335     target_ulong PID;
 336     target_ulong size;
 337     uint32_t prot;
 338     uint32_t attr; /* Storage attributes */
 339 };
 340
 341 union ppc_tlb_t {
 342     ppc6xx_tlb_t tlb6;
 343     ppcemb_tlb_t tlbe;
 344 };
 345
 346 /*****************************************************************************/
 347 /* Machine state register bits definition                                    */
 348 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 349 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 350 #define MSR_HV   60 /* hypervisor state                               hflags */
 351 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 352 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 353 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 354 #define MSR_VR   25 /* altivec available                              hflags */
 355 #define MSR_SPE  25 /* SPE enable for BookE                           hflags */
 356 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 357 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 358 #define MSR_KEY  19 /* key bit on 603e                                       */
 359 #define MSR_POW  18 /* Power management                                      */
 360 #define MSR_WE   18 /* Wait state enable on embedded PowerPC                 */
 361 #define MSR_TGPR 17 /* TGPR usage on 602/603                                 */
 362 #define MSR_TLB  17 /* TLB update on ?                                       */
 363 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC         */
 364 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 365 #define MSR_EE   15 /* External interrupt enable                             */
 366 #define MSR_PR   14 /* Problem state                                  hflags */
 367 #define MSR_FP   13 /* Floating point available                       hflags */
 368 #define MSR_ME   12 /* Machine check interrupt enable                        */
 369 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 370 #define MSR_SE   10 /* Single-step trace enable                       hflags */
 371 #define MSR_DWE  10 /* Debug wait enable on 405                              */
 372 #define MSR_UBLE 10 /* User BTB lock enable on e500                          */
 373 #define MSR_BE   9  /* Branch trace enable                            hflags */
 374 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC           */
 375 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 376 #define MSR_AL   7  /* AL bit on POWER                                       */
 377 #define MSR_IP   6  /* Interrupt prefix                                      */
 378 #define MSR_IR   5  /* Instruction relocate                                  */
 379 #define MSR_IS   5  /* Instruction address space on embedded PowerPC         */
 380 #define MSR_DR   4  /* Data relocate                                         */
 381 #define MSR_DS   4  /* Data address space on embedded PowerPC                */
 382 #define MSR_PE   3  /* Protection enable on 403                              */
 383 #define MSR_EP   3  /* Exception prefix on 601                               */
 384 #define MSR_PX   2  /* Protection exclusive on 403                           */
 385 #define MSR_PMM  2  /* Performance monitor mark on POWER                     */
 386 #define MSR_RI   1  /* Recoverable interrupt                                 */
 387 #define MSR_LE   0  /* Little-endian mode                             hflags */
 388 #define msr_sf   env->msr[MSR_SF]
 389 #define msr_isf  env->msr[MSR_ISF]
 390 #define msr_hv   env->msr[MSR_HV]
 391 #define msr_cm   env->msr[MSR_CM]
 392 #define msr_icm  env->msr[MSR_ICM]
 393 #define msr_ucle env->msr[MSR_UCLE]
 394 #define msr_vr   env->msr[MSR_VR]
 395 #define msr_spe  env->msr[MSR_SPE]
 396 #define msr_ap   env->msr[MSR_AP]
 397 #define msr_sa   env->msr[MSR_SA]
 398 #define msr_key  env->msr[MSR_KEY]
 399 #define msr_pow  env->msr[MSR_POW]
 400 #define msr_we   env->msr[MSR_WE]
 401 #define msr_tgpr env->msr[MSR_TGPR]
 402 #define msr_tlb  env->msr[MSR_TLB]
 403 #define msr_ce   env->msr[MSR_CE]
 404 #define msr_ile  env->msr[MSR_ILE]
 405 #define msr_ee   env->msr[MSR_EE]
 406 #define msr_pr   env->msr[MSR_PR]
 407 #define msr_fp   env->msr[MSR_FP]
 408 #define msr_me   env->msr[MSR_ME]
 409 #define msr_fe0  env->msr[MSR_FE0]
 410 #define msr_se   env->msr[MSR_SE]
 411 #define msr_dwe  env->msr[MSR_DWE]
 412 #define msr_uble env->msr[MSR_UBLE]
 413 #define msr_be   env->msr[MSR_BE]
 414 #define msr_de   env->msr[MSR_DE]
 415 #define msr_fe1  env->msr[MSR_FE1]
 416 #define msr_al   env->msr[MSR_AL]
 417 #define msr_ip   env->msr[MSR_IP]
 418 #define msr_ir   env->msr[MSR_IR]
 419 #define msr_is   env->msr[MSR_IS]
 420 #define msr_dr   env->msr[MSR_DR]
 421 #define msr_ds   env->msr[MSR_DS]
 422 #define msr_pe   env->msr[MSR_PE]
 423 #define msr_ep   env->msr[MSR_EP]
 424 #define msr_px   env->msr[MSR_PX]
 425 #define msr_pmm  env->msr[MSR_PMM]
 426 #define msr_ri   env->msr[MSR_RI]
 427 #define msr_le   env->msr[MSR_LE]
 428
 429 /*****************************************************************************/
 430 /* The whole PowerPC CPU context */
 431 struct CPUPPCState {
 432     /* First are the most commonly used resources
 433      * during translated code execution
 434      */
 435 #if TARGET_GPR_BITS > HOST_LONG_BITS
 436     /* temporary fixed-point registers
 437      * used to emulate 64 bits target on 32 bits hosts
 438      */
 439     ppc_gpr_t t0, t1, t2;
 440 #endif
 441     ppc_avr_t t0_avr, t1_avr, t2_avr;
 442
 443     /* general purpose registers */
 444     ppc_gpr_t gpr[32];
 445     /* LR */
 446     target_ulong lr;
 447     /* CTR */
 448     target_ulong ctr;
 449     /* condition register */
 450     uint8_t crf[8];
 451     /* XER */
 452     /* XXX: We use only 5 fields, but we want to keep the structure aligned */
 453     uint8_t xer[8];
 454     /* Reservation address */
 455     target_ulong reserve;
 456
 457     /* Those ones are used in supervisor mode only */
 458     /* machine state register */
 459     uint8_t msr[64];
 460     /* temporary general purpose registers */
 461     ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
 462
 463     /* Floating point execution context */
 464     /* temporary float registers */
 465     float64 ft0;
 466     float64 ft1;
 467     float64 ft2;
 468     float_status fp_status;
 469     /* floating point registers */
 470     float64 fpr[32];
 471     /* floating point status and control register */
 472     uint8_t fpscr[8];
 473
 474     CPU_COMMON
 475
 476     int halted; /* TRUE if the CPU is in suspend state */
 477
 478     int access_type; /* when a memory exception occurs, the access
 479                         type is stored here */
 480
 481     /* MMU context */
 482     /* Address space register */
 483     target_ulong asr;
 484     /* segment registers */
 485     target_ulong sdr1;
 486     target_ulong sr[16];
 487     /* BATs */
 488     int nb_BATs;
 489     target_ulong DBAT[2][8];
 490     target_ulong IBAT[2][8];
 491
 492     /* Other registers */
 493     /* Special purpose registers */
 494     target_ulong spr[1024];
 495     /* Altivec registers */
 496     ppc_avr_t avr[32];
 497     uint32_t vscr;
 498     /* SPE registers */
 499     ppc_gpr_t spe_acc;
 500     float_status spe_status;
 501     uint32_t spe_fscr;
 502
 503     /* Internal devices resources */
 504     /* Time base and decrementer */
 505     ppc_tb_t *tb_env;
 506     /* Device control registers */
 507     ppc_dcr_t *dcr_env;
 508
 509     /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
 510     int nb_tlb;      /* Total number of TLB                                  */
 511     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
 512     int nb_ways;     /* Number of ways in the TLB set                        */
 513     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
 514     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
 515     int nb_pids;     /* Number of available PID registers                    */
 516     ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
 517     /* 403 dedicated access protection registers */
 518     target_ulong pb[4];
 519
 520     /* Those resources are used during exception processing */
 521     /* CPU model definition */
 522     target_ulong msr_mask;
 523     uint8_t mmu_model;
 524     uint8_t excp_model;
 525     uint8_t bus_model;
 526     uint8_t pad;
 527     int bfd_mach;
 528     uint32_t flags;
 529
 530     int exception_index;
 531     int error_code;
 532     int interrupt_request;
 533     uint32_t pending_interrupts;
 534 #if !defined(CONFIG_USER_ONLY)
 535     /* This is the IRQ controller, which is implementation dependant
 536      * and only relevant when emulating a complete machine.
 537      */
 538     uint32_t irq_input_state;
 539     void **irq_inputs;
 540     /* Exception vectors */
 541     target_ulong excp_vectors[POWERPC_EXCP_NB];
 542     target_ulong excp_prefix;
 543     target_ulong ivor_mask;
 544     target_ulong ivpr_mask;
 545 #endif
 546
 547     /* Those resources are used only during code translation */
 548     /* Next instruction pointer */
 549     target_ulong nip;
 550     /* SPR translation callbacks */
 551     ppc_spr_t spr_cb[1024];
 552     /* opcode handlers */
 553     opc_handler_t *opcodes[0x40];
 554
 555     /* Those resources are used only in Qemu core */
 556     jmp_buf jmp_env;
 557     int user_mode_only; /* user mode only simulation */
 558     target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
 559
 560     /* Power management */
 561     int power_mode;
 562
 563     /* temporary hack to handle OSI calls (only used if non NULL) */
 564     int (*osi_call)(struct CPUPPCState *env);
 565 };
 566
 567 /* Context used internally during MMU translations */
 568 typedef struct mmu_ctx_t mmu_ctx_t;
 569 struct mmu_ctx_t {
 570     target_phys_addr_t raddr;      /* Real address              */
 571     int prot;                      /* Protection bits           */
 572     target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
 573     target_ulong ptem;             /* Virtual segment ID | API  */
 574     int key;                       /* Access key                */
 575 };
 576
 577 /*****************************************************************************/
 578 CPUPPCState *cpu_ppc_init (void);
 579 int cpu_ppc_exec (CPUPPCState *s);
 580 void cpu_ppc_close (CPUPPCState *s);
 581 /* you can call this signal handler from your SIGBUS and SIGSEGV
 582    signal handlers to inform the virtual CPU of exceptions. non zero
 583    is returned if the signal was handled by the virtual CPU.  */
 584 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
 585                             void *puc);
 586
 587 void do_interrupt (CPUPPCState *env);
 588 void ppc_hw_interrupt (CPUPPCState *env);
 589 void cpu_loop_exit (void);
 590
 591 void dump_stack (CPUPPCState *env);
 592
 593 #if !defined(CONFIG_USER_ONLY)
 594 target_ulong do_load_ibatu (CPUPPCState *env, int nr);
 595 target_ulong do_load_ibatl (CPUPPCState *env, int nr);
 596 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
 597 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
 598 target_ulong do_load_dbatu (CPUPPCState *env, int nr);
 599 target_ulong do_load_dbatl (CPUPPCState *env, int nr);
 600 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
 601 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
 602 target_ulong do_load_sdr1 (CPUPPCState *env);
 603 void do_store_sdr1 (CPUPPCState *env, target_ulong value);
 604 #if defined(TARGET_PPC64)
 605 target_ulong ppc_load_asr (CPUPPCState *env);
 606 void ppc_store_asr (CPUPPCState *env, target_ulong value);
 607 #endif
 608 target_ulong do_load_sr (CPUPPCState *env, int srnum);
 609 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
 610 #endif
 611 target_ulong ppc_load_xer (CPUPPCState *env);
 612 void ppc_store_xer (CPUPPCState *env, target_ulong value);
 613 target_ulong do_load_msr (CPUPPCState *env);
 614 void do_store_msr (CPUPPCState *env, target_ulong value);
 615 #if defined(TARGET_PPC64)
 616 void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
 617 #endif
 618
 619 void do_compute_hflags (CPUPPCState *env);
 620 void cpu_ppc_reset (void *opaque);
 621 CPUPPCState *cpu_ppc_init (void);
 622 void cpu_ppc_close(CPUPPCState *env);
 623
 624 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
 625 int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
 626 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 627 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
 628
 629 /* Time-base and decrementer management */
 630 #ifndef NO_CPU_IO_DEFS
 631 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
 632 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
 633 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
 634 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
 635 uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
 636 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
 637 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
 638 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
 639 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
 640 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
 641 #if defined(TARGET_PPC64H)
 642 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
 643 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
 644 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
 645 void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
 646 #endif
 647 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
 648 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
 649 #if !defined(CONFIG_USER_ONLY)
 650 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
 651 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
 652 target_ulong load_40x_pit (CPUPPCState *env);
 653 void store_40x_pit (CPUPPCState *env, target_ulong val);
 654 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
 655 void store_40x_sler (CPUPPCState *env, uint32_t val);
 656 void store_booke_tcr (CPUPPCState *env, target_ulong val);
 657 void store_booke_tsr (CPUPPCState *env, target_ulong val);
 658 void ppc_tlb_invalidate_all (CPUPPCState *env);
 659 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
 660 #if defined(TARGET_PPC64)
 661 void ppc_slb_invalidate_all (CPUPPCState *env);
 662 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
 663 #endif
 664 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
 665 #endif
 666 #endif
 667
 668 /* Device control registers */
 669 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
 670 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
 671
 672 #define CPUState CPUPPCState
 673 #define cpu_init cpu_ppc_init
 674 #define cpu_exec cpu_ppc_exec
 675 #define cpu_gen_code cpu_ppc_gen_code
 676 #define cpu_signal_handler cpu_ppc_signal_handler
 677
 678 #include "cpu-all.h"
 679
 680 /*****************************************************************************/
 681 /* Registers definitions */
 682 #define XER_SO 31
 683 #define XER_OV 30
 684 #define XER_CA 29
 685 #define XER_CMP 8
 686 #define XER_BC  0
 687 #define xer_so  env->xer[4]
 688 #define xer_ov  env->xer[6]
 689 #define xer_ca  env->xer[2]
 690 #define xer_cmp env->xer[1]
 691 #define xer_bc  env->xer[0]
 692
 693 /* SPR definitions */
 694 #define SPR_MQ           (0x000)
 695 #define SPR_XER          (0x001)
 696 #define SPR_601_VRTCU    (0x004)
 697 #define SPR_601_VRTCL    (0x005)
 698 #define SPR_601_UDECR    (0x006)
 699 #define SPR_LR           (0x008)
 700 #define SPR_CTR          (0x009)
 701 #define SPR_DSISR        (0x012)
 702 #define SPR_DAR          (0x013) /* DAE for PowerPC 601 */
 703 #define SPR_601_RTCU     (0x014)
 704 #define SPR_601_RTCL     (0x015)
 705 #define SPR_DECR         (0x016)
 706 #define SPR_SDR1         (0x019)
 707 #define SPR_SRR0         (0x01A)
 708 #define SPR_SRR1         (0x01B)
 709 #define SPR_AMR          (0x01D)
 710 #define SPR_BOOKE_PID    (0x030)
 711 #define SPR_BOOKE_DECAR  (0x036)
 712 #define SPR_BOOKE_CSRR0  (0x03A)
 713 #define SPR_BOOKE_CSRR1  (0x03B)
 714 #define SPR_BOOKE_DEAR   (0x03D)
 715 #define SPR_BOOKE_ESR    (0x03E)
 716 #define SPR_BOOKE_IVPR   (0x03F)
 717 #define SPR_8xx_EIE      (0x050)
 718 #define SPR_8xx_EID      (0x051)
 719 #define SPR_8xx_NRE      (0x052)
 720 #define SPR_CTRL         (0x088)
 721 #define SPR_58x_CMPA     (0x090)
 722 #define SPR_58x_CMPB     (0x091)
 723 #define SPR_58x_CMPC     (0x092)
 724 #define SPR_58x_CMPD     (0x093)
 725 #define SPR_58x_ICR      (0x094)
 726 #define SPR_58x_DER      (0x094)
 727 #define SPR_58x_COUNTA   (0x096)
 728 #define SPR_58x_COUNTB   (0x097)
 729 #define SPR_UCTRL        (0x098)
 730 #define SPR_58x_CMPE     (0x098)
 731 #define SPR_58x_CMPF     (0x099)
 732 #define SPR_58x_CMPG     (0x09A)
 733 #define SPR_58x_CMPH     (0x09B)
 734 #define SPR_58x_LCTRL1   (0x09C)
 735 #define SPR_58x_LCTRL2   (0x09D)
 736 #define SPR_58x_ICTRL    (0x09E)
 737 #define SPR_58x_BAR      (0x09F)
 738 #define SPR_VRSAVE       (0x100)
 739 #define SPR_USPRG0       (0x100)
 740 #define SPR_USPRG1       (0x101)
 741 #define SPR_USPRG2       (0x102)
 742 #define SPR_USPRG3       (0x103)
 743 #define SPR_USPRG4       (0x104)
 744 #define SPR_USPRG5       (0x105)
 745 #define SPR_USPRG6       (0x106)
 746 #define SPR_USPRG7       (0x107)
 747 #define SPR_VTBL         (0x10C)
 748 #define SPR_VTBU         (0x10D)
 749 #define SPR_SPRG0        (0x110)
 750 #define SPR_SPRG1        (0x111)
 751 #define SPR_SPRG2        (0x112)
 752 #define SPR_SPRG3        (0x113)
 753 #define SPR_SPRG4        (0x114)
 754 #define SPR_SCOMC        (0x114)
 755 #define SPR_SPRG5        (0x115)
 756 #define SPR_SCOMD        (0x115)
 757 #define SPR_SPRG6        (0x116)
 758 #define SPR_SPRG7        (0x117)
 759 #define SPR_ASR          (0x118)
 760 #define SPR_EAR          (0x11A)
 761 #define SPR_TBL          (0x11C)
 762 #define SPR_TBU          (0x11D)
 763 #define SPR_TBU40        (0x11E)
 764 #define SPR_SVR          (0x11E)
 765 #define SPR_BOOKE_PIR    (0x11E)
 766 #define SPR_PVR          (0x11F)
 767 #define SPR_HSPRG0       (0x130)
 768 #define SPR_BOOKE_DBSR   (0x130)
 769 #define SPR_HSPRG1       (0x131)
 770 #define SPR_HDSISR       (0x132)
 771 #define SPR_HDAR         (0x133)
 772 #define SPR_BOOKE_DBCR0  (0x134)
 773 #define SPR_IBCR         (0x135)
 774 #define SPR_PURR         (0x135)
 775 #define SPR_BOOKE_DBCR1  (0x135)
 776 #define SPR_DBCR         (0x136)
 777 #define SPR_HDEC         (0x136)
 778 #define SPR_BOOKE_DBCR2  (0x136)
 779 #define SPR_HIOR         (0x137)
 780 #define SPR_MBAR         (0x137)
 781 #define SPR_RMOR         (0x138)
 782 #define SPR_BOOKE_IAC1   (0x138)
 783 #define SPR_HRMOR        (0x139)
 784 #define SPR_BOOKE_IAC2   (0x139)
 785 #define SPR_HSRR0        (0x13A)
 786 #define SPR_BOOKE_IAC3   (0x13A)
 787 #define SPR_HSRR1        (0x13B)
 788 #define SPR_BOOKE_IAC4   (0x13B)
 789 #define SPR_LPCR         (0x13C)
 790 #define SPR_BOOKE_DAC1   (0x13C)
 791 #define SPR_LPIDR        (0x13D)
 792 #define SPR_DABR2        (0x13D)
 793 #define SPR_BOOKE_DAC2   (0x13D)
 794 #define SPR_BOOKE_DVC1   (0x13E)
 795 #define SPR_BOOKE_DVC2   (0x13F)
 796 #define SPR_BOOKE_TSR    (0x150)
 797 #define SPR_BOOKE_TCR    (0x154)
 798 #define SPR_BOOKE_IVOR0  (0x190)
 799 #define SPR_BOOKE_IVOR1  (0x191)
 800 #define SPR_BOOKE_IVOR2  (0x192)
 801 #define SPR_BOOKE_IVOR3  (0x193)
 802 #define SPR_BOOKE_IVOR4  (0x194)
 803 #define SPR_BOOKE_IVOR5  (0x195)
 804 #define SPR_BOOKE_IVOR6  (0x196)
 805 #define SPR_BOOKE_IVOR7  (0x197)
 806 #define SPR_BOOKE_IVOR8  (0x198)
 807 #define SPR_BOOKE_IVOR9  (0x199)
 808 #define SPR_BOOKE_IVOR10 (0x19A)
 809 #define SPR_BOOKE_IVOR11 (0x19B)
 810 #define SPR_BOOKE_IVOR12 (0x19C)
 811 #define SPR_BOOKE_IVOR13 (0x19D)
 812 #define SPR_BOOKE_IVOR14 (0x19E)
 813 #define SPR_BOOKE_IVOR15 (0x19F)
 814 #define SPR_BOOKE_SPEFSCR (0x200)
 815 #define SPR_E500_BBEAR   (0x201)
 816 #define SPR_E500_BBTAR   (0x202)
 817 #define SPR_ATBL         (0x20E)
 818 #define SPR_ATBU         (0x20F)
 819 #define SPR_IBAT0U       (0x210)
 820 #define SPR_BOOKE_IVOR32 (0x210)
 821 #define SPR_IBAT0L       (0x211)
 822 #define SPR_BOOKE_IVOR33 (0x211)
 823 #define SPR_IBAT1U       (0x212)
 824 #define SPR_BOOKE_IVOR34 (0x212)
 825 #define SPR_IBAT1L       (0x213)
 826 #define SPR_BOOKE_IVOR35 (0x213)
 827 #define SPR_IBAT2U       (0x214)
 828 #define SPR_BOOKE_IVOR36 (0x214)
 829 #define SPR_IBAT2L       (0x215)
 830 #define SPR_E500_L1CFG0  (0x215)
 831 #define SPR_BOOKE_IVOR37 (0x215)
 832 #define SPR_IBAT3U       (0x216)
 833 #define SPR_E500_L1CFG1  (0x216)
 834 #define SPR_IBAT3L       (0x217)
 835 #define SPR_DBAT0U       (0x218)
 836 #define SPR_DBAT0L       (0x219)
 837 #define SPR_DBAT1U       (0x21A)
 838 #define SPR_DBAT1L       (0x21B)
 839 #define SPR_DBAT2U       (0x21C)
 840 #define SPR_DBAT2L       (0x21D)
 841 #define SPR_DBAT3U       (0x21E)
 842 #define SPR_DBAT3L       (0x21F)
 843 #define SPR_IBAT4U       (0x230)
 844 #define SPR_IBAT4L       (0x231)
 845 #define SPR_IBAT5U       (0x232)
 846 #define SPR_IBAT5L       (0x233)
 847 #define SPR_IBAT6U       (0x234)
 848 #define SPR_IBAT6L       (0x235)
 849 #define SPR_IBAT7U       (0x236)
 850 #define SPR_IBAT7L       (0x237)
 851 #define SPR_DBAT4U       (0x238)
 852 #define SPR_DBAT4L       (0x239)
 853 #define SPR_DBAT5U       (0x23A)
 854 #define SPR_BOOKE_MCSRR0 (0x23A)
 855 #define SPR_DBAT5L       (0x23B)
 856 #define SPR_BOOKE_MCSRR1 (0x23B)
 857 #define SPR_DBAT6U       (0x23C)
 858 #define SPR_BOOKE_MCSR   (0x23C)
 859 #define SPR_DBAT6L       (0x23D)
 860 #define SPR_E500_MCAR    (0x23D)
 861 #define SPR_DBAT7U       (0x23E)
 862 #define SPR_BOOKE_DSRR0  (0x23E)
 863 #define SPR_DBAT7L       (0x23F)
 864 #define SPR_BOOKE_DSRR1  (0x23F)
 865 #define SPR_BOOKE_SPRG8  (0x25C)
 866 #define SPR_BOOKE_SPRG9  (0x25D)
 867 #define SPR_BOOKE_MAS0   (0x270)
 868 #define SPR_BOOKE_MAS1   (0x271)
 869 #define SPR_BOOKE_MAS2   (0x272)
 870 #define SPR_BOOKE_MAS3   (0x273)
 871 #define SPR_BOOKE_MAS4   (0x274)
 872 #define SPR_BOOKE_MAS6   (0x276)
 873 #define SPR_BOOKE_PID1   (0x279)
 874 #define SPR_BOOKE_PID2   (0x27A)
 875 #define SPR_BOOKE_TLB0CFG (0x2B0)
 876 #define SPR_BOOKE_TLB1CFG (0x2B1)
 877 #define SPR_BOOKE_TLB2CFG (0x2B2)
 878 #define SPR_BOOKE_TLB3CFG (0x2B3)
 879 #define SPR_BOOKE_EPR    (0x2BE)
 880 #define SPR_PERF0        (0x300)
 881 #define SPR_PERF1        (0x301)
 882 #define SPR_PERF2        (0x302)
 883 #define SPR_PERF3        (0x303)
 884 #define SPR_PERF4        (0x304)
 885 #define SPR_PERF5        (0x305)
 886 #define SPR_PERF6        (0x306)
 887 #define SPR_PERF7        (0x307)
 888 #define SPR_PERF8        (0x308)
 889 #define SPR_PERF9        (0x309)
 890 #define SPR_PERFA        (0x30A)
 891 #define SPR_PERFB        (0x30B)
 892 #define SPR_PERFC        (0x30C)
 893 #define SPR_PERFD        (0x30D)
 894 #define SPR_PERFE        (0x30E)
 895 #define SPR_PERFF        (0x30F)
 896 #define SPR_UPERF0       (0x310)
 897 #define SPR_UPERF1       (0x311)
 898 #define SPR_UPERF2       (0x312)
 899 #define SPR_UPERF3       (0x313)
 900 #define SPR_UPERF4       (0x314)
 901 #define SPR_UPERF5       (0x315)
 902 #define SPR_UPERF6       (0x316)
 903 #define SPR_UPERF7       (0x317)
 904 #define SPR_UPERF8       (0x318)
 905 #define SPR_UPERF9       (0x319)
 906 #define SPR_UPERFA       (0x31A)
 907 #define SPR_UPERFB       (0x31B)
 908 #define SPR_UPERFC       (0x31C)
 909 #define SPR_UPERFD       (0x31D)
 910 #define SPR_UPERFE       (0x31E)
 911 #define SPR_UPERFF       (0x31F)
 912 #define SPR_440_INV0     (0x370)
 913 #define SPR_440_INV1     (0x371)
 914 #define SPR_440_INV2     (0x372)
 915 #define SPR_440_INV3     (0x373)
 916 #define SPR_440_ITV0     (0x374)
 917 #define SPR_440_ITV1     (0x375)
 918 #define SPR_440_ITV2     (0x376)
 919 #define SPR_440_ITV3     (0x377)
 920 #define SPR_440_CCR1     (0x378)
 921 #define SPR_DCRIPR       (0x37B)
 922 #define SPR_PPR          (0x380)
 923 #define SPR_440_DNV0     (0x390)
 924 #define SPR_440_DNV1     (0x391)
 925 #define SPR_440_DNV2     (0x392)
 926 #define SPR_440_DNV3     (0x393)
 927 #define SPR_440_DTV0     (0x394)
 928 #define SPR_440_DTV1     (0x395)
 929 #define SPR_440_DTV2     (0x396)
 930 #define SPR_440_DTV3     (0x397)
 931 #define SPR_440_DVLIM    (0x398)
 932 #define SPR_440_IVLIM    (0x399)
 933 #define SPR_440_RSTCFG   (0x39B)
 934 #define SPR_BOOKE_DCDBTRL (0x39C)
 935 #define SPR_BOOKE_DCDBTRH (0x39D)
 936 #define SPR_BOOKE_ICDBTRL (0x39E)
 937 #define SPR_BOOKE_ICDBTRH (0x39F)
 938 #define SPR_UMMCR2       (0x3A0)
 939 #define SPR_UPMC5        (0x3A1)
 940 #define SPR_UPMC6        (0x3A2)
 941 #define SPR_UBAMR        (0x3A7)
 942 #define SPR_UMMCR0       (0x3A8)
 943 #define SPR_UPMC1        (0x3A9)
 944 #define SPR_UPMC2        (0x3AA)
 945 #define SPR_USIAR        (0x3AB)
 946 #define SPR_UMMCR1       (0x3AC)
 947 #define SPR_UPMC3        (0x3AD)
 948 #define SPR_UPMC4        (0x3AE)
 949 #define SPR_USDA         (0x3AF)
 950 #define SPR_40x_ZPR      (0x3B0)
 951 #define SPR_BOOKE_MAS7   (0x3B0)
 952 #define SPR_620_PMR0     (0x3B0)
 953 #define SPR_MMCR2        (0x3B0)
 954 #define SPR_PMC5         (0x3B1)
 955 #define SPR_40x_PID      (0x3B1)
 956 #define SPR_620_PMR1     (0x3B1)
 957 #define SPR_PMC6         (0x3B2)
 958 #define SPR_440_MMUCR    (0x3B2)
 959 #define SPR_620_PMR2     (0x3B2)
 960 #define SPR_4xx_CCR0     (0x3B3)
 961 #define SPR_BOOKE_EPLC   (0x3B3)
 962 #define SPR_620_PMR3     (0x3B3)
 963 #define SPR_405_IAC3     (0x3B4)
 964 #define SPR_BOOKE_EPSC   (0x3B4)
 965 #define SPR_620_PMR4     (0x3B4)
 966 #define SPR_405_IAC4     (0x3B5)
 967 #define SPR_620_PMR5     (0x3B5)
 968 #define SPR_405_DVC1     (0x3B6)
 969 #define SPR_620_PMR6     (0x3B6)
 970 #define SPR_405_DVC2     (0x3B7)
 971 #define SPR_620_PMR7     (0x3B7)
 972 #define SPR_BAMR         (0x3B7)
 973 #define SPR_MMCR0        (0x3B8)
 974 #define SPR_620_PMR8     (0x3B8)
 975 #define SPR_PMC1         (0x3B9)
 976 #define SPR_40x_SGR      (0x3B9)
 977 #define SPR_620_PMR9     (0x3B9)
 978 #define SPR_PMC2         (0x3BA)
 979 #define SPR_40x_DCWR     (0x3BA)
 980 #define SPR_620_PMRA     (0x3BA)
 981 #define SPR_SIAR         (0x3BB)
 982 #define SPR_405_SLER     (0x3BB)
 983 #define SPR_620_PMRB     (0x3BB)
 984 #define SPR_MMCR1        (0x3BC)
 985 #define SPR_405_SU0R     (0x3BC)
 986 #define SPR_620_PMRC     (0x3BC)
 987 #define SPR_401_SKR      (0x3BC)
 988 #define SPR_PMC3         (0x3BD)
 989 #define SPR_405_DBCR1    (0x3BD)
 990 #define SPR_620_PMRD     (0x3BD)
 991 #define SPR_PMC4         (0x3BE)
 992 #define SPR_620_PMRE     (0x3BE)
 993 #define SPR_SDA          (0x3BF)
 994 #define SPR_620_PMRF     (0x3BF)
 995 #define SPR_403_VTBL     (0x3CC)
 996 #define SPR_403_VTBU     (0x3CD)
 997 #define SPR_DMISS        (0x3D0)
 998 #define SPR_DCMP         (0x3D1)
 999 #define SPR_HASH1        (0x3D2)
1000 #define SPR_HASH2        (0x3D3)
1001 #define SPR_BOOKE_ICDBDR (0x3D3)
1002 #define SPR_TLBMISS      (0x3D4)
1003 #define SPR_IMISS        (0x3D4)
1004 #define SPR_40x_ESR      (0x3D4)
1005 #define SPR_PTEHI        (0x3D5)
1006 #define SPR_ICMP         (0x3D5)
1007 #define SPR_40x_DEAR     (0x3D5)
1008 #define SPR_PTELO        (0x3D6)
1009 #define SPR_RPA          (0x3D6)
1010 #define SPR_40x_EVPR     (0x3D6)
1011 #define SPR_L3PM         (0x3D7)
1012 #define SPR_403_CDBCR    (0x3D7)
1013 #define SPR_L3OHCR       (0x3D8)
1014 #define SPR_TCR          (0x3D8)
1015 #define SPR_40x_TSR      (0x3D8)
1016 #define SPR_IBR          (0x3DA)
1017 #define SPR_40x_TCR      (0x3DA)
1018 #define SPR_ESASRR       (0x3DB)
1019 #define SPR_40x_PIT      (0x3DB)
1020 #define SPR_403_TBL      (0x3DC)
1021 #define SPR_403_TBU      (0x3DD)
1022 #define SPR_SEBR         (0x3DE)
1023 #define SPR_40x_SRR2     (0x3DE)
1024 #define SPR_SER          (0x3DF)
1025 #define SPR_40x_SRR3     (0x3DF)
1026 #define SPR_L3ITCR0      (0x3E8)
1027 #define SPR_L3ITCR1      (0x3E9)
1028 #define SPR_L3ITCR2      (0x3EA)
1029 #define SPR_L3ITCR3      (0x3EB)
1030 #define SPR_HID0         (0x3F0)
1031 #define SPR_40x_DBSR     (0x3F0)
1032 #define SPR_HID1         (0x3F1)
1033 #define SPR_IABR         (0x3F2)
1034 #define SPR_40x_DBCR0    (0x3F2)
1035 #define SPR_601_HID2     (0x3F2)
1036 #define SPR_E500_L1CSR0  (0x3F2)
1037 #define SPR_ICTRL        (0x3F3)
1038 #define SPR_HID2         (0x3F3)
1039 #define SPR_E500_L1CSR1  (0x3F3)
1040 #define SPR_440_DBDR     (0x3F3)
1041 #define SPR_LDSTDB       (0x3F4)
1042 #define SPR_40x_IAC1     (0x3F4)
1043 #define SPR_BOOKE_MMUCSR0 (0x3F4)
1044 #define SPR_DABR         (0x3F5)
1045 #define DABR_MASK (~(target_ulong)0x7)
1046 #define SPR_E500_BUCSR   (0x3F5)
1047 #define SPR_40x_IAC2     (0x3F5)
1048 #define SPR_601_HID5     (0x3F5)
1049 #define SPR_40x_DAC1     (0x3F6)
1050 #define SPR_MSSCR0       (0x3F6)
1051 #define SPR_MSSSR0       (0x3F7)
1052 #define SPR_DABRX        (0x3F7)
1053 #define SPR_40x_DAC2     (0x3F7)
1054 #define SPR_BOOKE_MMUCFG (0x3F7)
1055 #define SPR_LDSTCR       (0x3F8)
1056 #define SPR_L2PMCR       (0x3F8)
1057 #define SPR_750_HID2     (0x3F8)
1058 #define SPR_620_HID8     (0x3F8)
1059 #define SPR_L2CR         (0x3F9)
1060 #define SPR_620_HID9     (0x3F9)
1061 #define SPR_L3CR         (0x3FA)
1062 #define SPR_IABR2        (0x3FA)
1063 #define SPR_40x_DCCR     (0x3FA)
1064 #define SPR_ICTC         (0x3FB)
1065 #define SPR_40x_ICCR     (0x3FB)
1066 #define SPR_THRM1        (0x3FC)
1067 #define SPR_403_PBL1     (0x3FC)
1068 #define SPR_SP           (0x3FD)
1069 #define SPR_THRM2        (0x3FD)
1070 #define SPR_403_PBU1     (0x3FD)
1071 #define SPR_604_HID13    (0x3FD)
1072 #define SPR_LT           (0x3FE)
1073 #define SPR_THRM3        (0x3FE)
1074 #define SPR_FPECR        (0x3FE)
1075 #define SPR_403_PBL2     (0x3FE)
1076 #define SPR_PIR          (0x3FF)
1077 #define SPR_403_PBU2     (0x3FF)
1078 #define SPR_601_HID15    (0x3FF)
1079 #define SPR_604_HID15    (0x3FF)
1080 #define SPR_E500_SVR     (0x3FF)
1081
1082 /*****************************************************************************/
1083 /* Memory access type :
1084  * may be needed for precise access rights control and precise exceptions.
1085  */
1086 enum {
1087     /* 1 bit to define user level / supervisor access */
1088     ACCESS_USER  = 0x00,
1089     ACCESS_SUPER = 0x01,
1090     /* Type of instruction that generated the access */
1091     ACCESS_CODE  = 0x10, /* Code fetch access                */
1092     ACCESS_INT   = 0x20, /* Integer load/store access        */
1093     ACCESS_FLOAT = 0x30, /* floating point load/store access */
1094     ACCESS_RES   = 0x40, /* load/store with reservation      */
1095     ACCESS_EXT   = 0x50, /* external access                  */
1096     ACCESS_CACHE = 0x60, /* Cache manipulation               */
1097 };
1098
1099 /* Hardware interruption sources:
1100  * all those exception can be raised simulteaneously
1101  */
1102 /* Input pins definitions */
1103 enum {
1104     /* 6xx bus input pins */
1105     PPC6xx_INPUT_HRESET     = 0,
1106     PPC6xx_INPUT_SRESET     = 1,
1107     PPC6xx_INPUT_CKSTP_IN   = 2,
1108     PPC6xx_INPUT_MCP        = 3,
1109     PPC6xx_INPUT_SMI        = 4,
1110     PPC6xx_INPUT_INT        = 5,
1111 };
1112
1113 enum {
1114     /* Embedded PowerPC input pins */
1115     PPCBookE_INPUT_HRESET     = 0,
1116     PPCBookE_INPUT_SRESET     = 1,
1117     PPCBookE_INPUT_CKSTP_IN   = 2,
1118     PPCBookE_INPUT_MCP        = 3,
1119     PPCBookE_INPUT_SMI        = 4,
1120     PPCBookE_INPUT_INT        = 5,
1121     PPCBookE_INPUT_CINT       = 6,
1122 };
1123
1124 enum {
1125     /* PowerPC 40x input pins */
1126     PPC40x_INPUT_RESET_CORE = 0,
1127     PPC40x_INPUT_RESET_CHIP = 1,
1128     PPC40x_INPUT_RESET_SYS  = 2,
1129     PPC40x_INPUT_CINT       = 3,
1130     PPC40x_INPUT_INT        = 4,
1131     PPC40x_INPUT_HALT       = 5,
1132     PPC40x_INPUT_DEBUG      = 6,
1133     PPC40x_INPUT_NB,
1134 };
1135
1136 enum {
1137     /* PowerPC 620 (and probably others) input pins */
1138     PPC620_INPUT_HRESET     = 0,
1139     PPC620_INPUT_SRESET     = 1,
1140     PPC620_INPUT_CKSTP      = 2,
1141     PPC620_INPUT_TBEN       = 3,
1142     PPC620_INPUT_WAKEUP     = 4,
1143     PPC620_INPUT_MCP        = 5,
1144     PPC620_INPUT_SMI        = 6,
1145     PPC620_INPUT_INT        = 7,
1146 };
1147
1148 enum {
1149     /* PowerPC 970 input pins */
1150     PPC970_INPUT_HRESET     = 0,
1151     PPC970_INPUT_SRESET     = 1,
1152     PPC970_INPUT_CKSTP      = 2,
1153     PPC970_INPUT_TBEN       = 3,
1154     PPC970_INPUT_MCP        = 4,
1155     PPC970_INPUT_INT        = 5,
1156     PPC970_INPUT_THINT      = 6,
1157 };
1158
1159 /* Hardware exceptions definitions */
1160 enum {
1161     /* External hardware exception sources */
1162     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
1163     PPC_INTERRUPT_MCK       = 1,  /* Machine check exception              */
1164     PPC_INTERRUPT_EXT       = 2,  /* External interrupt                   */
1165     PPC_INTERRUPT_SMI       = 3,  /* System management interrupt          */
1166     PPC_INTERRUPT_CEXT      = 4,  /* Critical external interrupt          */
1167     PPC_INTERRUPT_DEBUG     = 5,  /* External debug exception             */
1168     PPC_INTERRUPT_THERM     = 6,  /* Thermal exception                    */
1169     /* Internal hardware exception sources */
1170     PPC_INTERRUPT_DECR      = 7,  /* Decrementer exception                */
1171     PPC_INTERRUPT_HDECR     = 8,  /* Hypervisor decrementer exception     */
1172     PPC_INTERRUPT_PIT       = 9,  /* Programmable inteval timer interrupt */
1173     PPC_INTERRUPT_FIT       = 10, /* Fixed interval timer interrupt       */
1174     PPC_INTERRUPT_WDT       = 11, /* Watchdog timer interrupt             */
1175     PPC_INTERRUPT_CDOORBELL = 12, /* Critical doorbell interrupt          */
1176     PPC_INTERRUPT_DOORBELL  = 13, /* Doorbell interrupt                   */
1177     PPC_INTERRUPT_PERFM     = 14, /* Performance monitor interrupt        */
1178 };
1179
1180 /*****************************************************************************/
1181
1182 #endif /* !defined (__CPU_PPC_H__) */