qemu/virtio: virtio support for many interrupt vectors
[qemu-kvm/fedora.git] / hw / virtio-pci.c
blobcc2304861df31fdc3b3297fe9b6aaaea6bfbd85f
1 /*
2 * Virtio PCI Bindings
4 * Copyright IBM, Corp. 2007
5 * Copyright (c) 2009 CodeSourcery
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 * Paul Brook <paul@codesourcery.com>
11 * This work is licensed under the terms of the GNU GPL, version 2. See
12 * the COPYING file in the top-level directory.
16 #include <inttypes.h>
18 #include "virtio.h"
19 #include "pci.h"
20 //#include "sysemu.h"
22 /* from Linux's linux/virtio_pci.h */
24 /* A 32-bit r/o bitmask of the features supported by the host */
25 #define VIRTIO_PCI_HOST_FEATURES 0
27 /* A 32-bit r/w bitmask of features activated by the guest */
28 #define VIRTIO_PCI_GUEST_FEATURES 4
30 /* A 32-bit r/w PFN for the currently selected queue */
31 #define VIRTIO_PCI_QUEUE_PFN 8
33 /* A 16-bit r/o queue size for the currently selected queue */
34 #define VIRTIO_PCI_QUEUE_NUM 12
36 /* A 16-bit r/w queue selector */
37 #define VIRTIO_PCI_QUEUE_SEL 14
39 /* A 16-bit r/w queue notifier */
40 #define VIRTIO_PCI_QUEUE_NOTIFY 16
42 /* An 8-bit device status register. */
43 #define VIRTIO_PCI_STATUS 18
45 /* An 8-bit r/o interrupt status register. Reading the value will return the
46 * current contents of the ISR and will also clear it. This is effectively
47 * a read-and-acknowledge. */
48 #define VIRTIO_PCI_ISR 19
50 #define VIRTIO_PCI_CONFIG 20
52 /* Virtio ABI version, if we increment this, we break the guest driver. */
53 #define VIRTIO_PCI_ABI_VERSION 0
55 /* How many bits to shift physical queue address written to QUEUE_PFN.
56 * 12 is historical, and due to x86 page size. */
57 #define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12
59 /* QEMU doesn't strictly need write barriers since everything runs in
60 * lock-step. We'll leave the calls to wmb() in though to make it obvious for
61 * KVM or if kqemu gets SMP support.
63 #define wmb() do { } while (0)
65 /* PCI bindings. */
67 typedef struct {
68 PCIDevice pci_dev;
69 VirtIODevice *vdev;
70 uint32_t addr;
72 uint16_t vendor;
73 uint16_t device;
74 uint16_t subvendor;
75 uint16_t class_code;
76 uint8_t pif;
77 } VirtIOPCIProxy;
79 /* virtio device */
81 static void virtio_pci_notify(void *opaque, uint16_t vector)
83 VirtIOPCIProxy *proxy = opaque;
85 qemu_set_irq(proxy->pci_dev.irq[0], proxy->vdev->isr & 1);
88 static void virtio_pci_reset(void *opaque)
90 VirtIOPCIProxy *proxy = opaque;
91 virtio_reset(proxy->vdev);
94 static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val)
96 VirtIOPCIProxy *proxy = opaque;
97 VirtIODevice *vdev = proxy->vdev;
98 target_phys_addr_t pa;
100 addr -= proxy->addr;
102 switch (addr) {
103 case VIRTIO_PCI_GUEST_FEATURES:
104 /* Guest does not negotiate properly? We have to assume nothing. */
105 if (val & (1 << VIRTIO_F_BAD_FEATURE)) {
106 if (vdev->bad_features)
107 val = vdev->bad_features(vdev);
108 else
109 val = 0;
111 if (vdev->set_features)
112 vdev->set_features(vdev, val);
113 vdev->features = val;
114 break;
115 case VIRTIO_PCI_QUEUE_PFN:
116 pa = (target_phys_addr_t)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
117 if (pa == 0)
118 virtio_pci_reset(proxy);
119 else
120 virtio_queue_set_addr(vdev, vdev->queue_sel, pa);
121 break;
122 case VIRTIO_PCI_QUEUE_SEL:
123 if (val < VIRTIO_PCI_QUEUE_MAX)
124 vdev->queue_sel = val;
125 break;
126 case VIRTIO_PCI_QUEUE_NOTIFY:
127 virtio_queue_notify(vdev, val);
128 break;
129 case VIRTIO_PCI_STATUS:
130 vdev->status = val & 0xFF;
131 if (vdev->status == 0)
132 virtio_pci_reset(proxy);
133 break;
137 static uint32_t virtio_ioport_read(void *opaque, uint32_t addr)
139 VirtIOPCIProxy *proxy = opaque;
140 VirtIODevice *vdev = proxy->vdev;
141 uint32_t ret = 0xFFFFFFFF;
143 addr -= proxy->addr;
145 switch (addr) {
146 case VIRTIO_PCI_HOST_FEATURES:
147 ret = vdev->get_features(vdev);
148 ret |= (1 << VIRTIO_F_NOTIFY_ON_EMPTY);
149 ret |= (1 << VIRTIO_RING_F_INDIRECT_DESC);
150 ret |= (1 << VIRTIO_F_BAD_FEATURE);
151 break;
152 case VIRTIO_PCI_GUEST_FEATURES:
153 ret = vdev->features;
154 break;
155 case VIRTIO_PCI_QUEUE_PFN:
156 ret = virtio_queue_get_addr(vdev, vdev->queue_sel)
157 >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
158 break;
159 case VIRTIO_PCI_QUEUE_NUM:
160 ret = virtio_queue_get_num(vdev, vdev->queue_sel);
161 break;
162 case VIRTIO_PCI_QUEUE_SEL:
163 ret = vdev->queue_sel;
164 break;
165 case VIRTIO_PCI_STATUS:
166 ret = vdev->status;
167 break;
168 case VIRTIO_PCI_ISR:
169 /* reading from the ISR also clears it. */
170 ret = vdev->isr;
171 vdev->isr = 0;
172 qemu_set_irq(proxy->pci_dev.irq[0], 0);
173 break;
174 default:
175 break;
178 return ret;
181 static uint32_t virtio_pci_config_readb(void *opaque, uint32_t addr)
183 VirtIOPCIProxy *proxy = opaque;
184 addr -= proxy->addr + VIRTIO_PCI_CONFIG;
185 return virtio_config_readb(proxy->vdev, addr);
188 static uint32_t virtio_pci_config_readw(void *opaque, uint32_t addr)
190 VirtIOPCIProxy *proxy = opaque;
191 addr -= proxy->addr + VIRTIO_PCI_CONFIG;
192 return virtio_config_readw(proxy->vdev, addr);
195 static uint32_t virtio_pci_config_readl(void *opaque, uint32_t addr)
197 VirtIOPCIProxy *proxy = opaque;
198 addr -= proxy->addr + VIRTIO_PCI_CONFIG;
199 return virtio_config_readl(proxy->vdev, addr);
202 static void virtio_pci_config_writeb(void *opaque, uint32_t addr, uint32_t val)
204 VirtIOPCIProxy *proxy = opaque;
205 addr -= proxy->addr + VIRTIO_PCI_CONFIG;
206 virtio_config_writeb(proxy->vdev, addr, val);
209 static void virtio_pci_config_writew(void *opaque, uint32_t addr, uint32_t val)
211 VirtIOPCIProxy *proxy = opaque;
212 addr -= proxy->addr + VIRTIO_PCI_CONFIG;
213 virtio_config_writew(proxy->vdev, addr, val);
216 static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val)
218 VirtIOPCIProxy *proxy = opaque;
219 addr -= proxy->addr + VIRTIO_PCI_CONFIG;
220 virtio_config_writel(proxy->vdev, addr, val);
223 static void virtio_map(PCIDevice *pci_dev, int region_num,
224 uint32_t addr, uint32_t size, int type)
226 VirtIOPCIProxy *proxy = container_of(pci_dev, VirtIOPCIProxy, pci_dev);
227 VirtIODevice *vdev = proxy->vdev;
228 int i;
230 proxy->addr = addr;
231 for (i = 0; i < 3; i++) {
232 register_ioport_write(addr, VIRTIO_PCI_CONFIG, 1 << i,
233 virtio_ioport_write, proxy);
234 register_ioport_read(addr, VIRTIO_PCI_CONFIG, 1 << i,
235 virtio_ioport_read, proxy);
238 if (vdev->config_len) {
239 register_ioport_write(addr + VIRTIO_PCI_CONFIG, vdev->config_len, 1,
240 virtio_pci_config_writeb, proxy);
241 register_ioport_write(addr + VIRTIO_PCI_CONFIG, vdev->config_len, 2,
242 virtio_pci_config_writew, proxy);
243 register_ioport_write(addr + VIRTIO_PCI_CONFIG, vdev->config_len, 4,
244 virtio_pci_config_writel, proxy);
245 register_ioport_read(addr + VIRTIO_PCI_CONFIG, vdev->config_len, 1,
246 virtio_pci_config_readb, proxy);
247 register_ioport_read(addr + VIRTIO_PCI_CONFIG, vdev->config_len, 2,
248 virtio_pci_config_readw, proxy);
249 register_ioport_read(addr + VIRTIO_PCI_CONFIG, vdev->config_len, 4,
250 virtio_pci_config_readl, proxy);
252 vdev->get_config(vdev, vdev->config);
256 static const VirtIOBindings virtio_pci_bindings = {
257 .notify = virtio_pci_notify
260 static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev,
261 uint16_t vendor, uint16_t device,
262 uint16_t class_code, uint8_t pif)
264 uint8_t *config;
265 uint32_t size;
267 proxy->vdev = vdev;
269 /* No support for multiple vectors yet. */
270 proxy->vdev->nvectors = 0;
272 config = proxy->pci_dev.config;
273 pci_config_set_vendor_id(config, vendor);
274 pci_config_set_device_id(config, device);
276 config[0x08] = VIRTIO_PCI_ABI_VERSION;
278 config[0x09] = pif;
279 pci_config_set_class(config, class_code);
280 config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
282 config[0x2c] = vendor & 0xFF;
283 config[0x2d] = (vendor >> 8) & 0xFF;
284 config[0x2e] = vdev->device_id & 0xFF;
285 config[0x2f] = (vdev->device_id >> 8) & 0xFF;
287 config[0x3d] = 1;
289 size = 20 + vdev->config_len;
290 if (size & (size-1))
291 size = 1 << qemu_fls(size);
293 pci_register_bar(&proxy->pci_dev, 0, size, PCI_ADDRESS_SPACE_IO,
294 virtio_map);
296 qemu_register_reset(virtio_pci_reset, 0, proxy);
298 virtio_bind_device(vdev, &virtio_pci_bindings, proxy);
301 static void virtio_blk_init_pci(PCIDevice *pci_dev)
303 VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
304 VirtIODevice *vdev;
306 vdev = virtio_blk_init(&pci_dev->qdev);
307 virtio_init_pci(proxy, vdev,
308 PCI_VENDOR_ID_REDHAT_QUMRANET,
309 PCI_DEVICE_ID_VIRTIO_BLOCK,
310 PCI_CLASS_STORAGE_OTHER,
311 0x00);
314 static void virtio_console_init_pci(PCIDevice *pci_dev)
316 VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
317 VirtIODevice *vdev;
319 vdev = virtio_console_init(&pci_dev->qdev);
320 virtio_init_pci(proxy, vdev,
321 PCI_VENDOR_ID_REDHAT_QUMRANET,
322 PCI_DEVICE_ID_VIRTIO_CONSOLE,
323 PCI_CLASS_DISPLAY_OTHER,
324 0x00);
327 static void virtio_net_init_pci(PCIDevice *pci_dev)
329 VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
330 VirtIODevice *vdev;
332 vdev = virtio_net_init(&pci_dev->qdev);
333 virtio_init_pci(proxy, vdev,
334 PCI_VENDOR_ID_REDHAT_QUMRANET,
335 PCI_DEVICE_ID_VIRTIO_NET,
336 PCI_CLASS_NETWORK_ETHERNET,
337 0x00);
340 static void virtio_balloon_init_pci(PCIDevice *pci_dev)
342 VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
343 VirtIODevice *vdev;
345 vdev = virtio_balloon_init(&pci_dev->qdev);
346 virtio_init_pci(proxy, vdev,
347 PCI_VENDOR_ID_REDHAT_QUMRANET,
348 PCI_DEVICE_ID_VIRTIO_BALLOON,
349 PCI_CLASS_MEMORY_RAM,
350 0x00);
353 static void virtio_pci_register_devices(void)
355 pci_qdev_register("virtio-blk-pci", sizeof(VirtIOPCIProxy),
356 virtio_blk_init_pci);
357 pci_qdev_register("virtio-net-pci", sizeof(VirtIOPCIProxy),
358 virtio_net_init_pci);
359 pci_qdev_register("virtio-console-pci", sizeof(VirtIOPCIProxy),
360 virtio_console_init_pci);
361 pci_qdev_register("virtio-balloon-pci", sizeof(VirtIOPCIProxy),
362 virtio_balloon_init_pci);
365 device_init(virtio_pci_register_devices)