target-arm/op_helper.c

   1 /*
   2  *  ARM helper routines
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery, LLC
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "exec.h"
  21
  22 void raise_exception(int tt)
  23 {
  24     env->exception_index = tt;
  25     cpu_loop_exit();
  26 }
  27
  28 /* thread support */
  29
  30 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
  31
  32 void cpu_lock(void)
  33 {
  34     spin_lock(&global_cpu_lock);
  35 }
  36
  37 void cpu_unlock(void)
  38 {
  39     spin_unlock(&global_cpu_lock);
  40 }
  41
  42 /* VFP support.  */
  43
  44 void do_vfp_abss(void)
  45 {
  46     FT0s = float32_abs(FT0s);
  47 }
  48
  49 void do_vfp_absd(void)
  50 {
  51     FT0d = float64_abs(FT0d);
  52 }
  53
  54 void do_vfp_sqrts(void)
  55 {
  56     FT0s = float32_sqrt(FT0s, &env->vfp.fp_status);
  57 }
  58
  59 void do_vfp_sqrtd(void)
  60 {
  61     FT0d = float64_sqrt(FT0d, &env->vfp.fp_status);
  62 }
  63
  64 /* XXX: check quiet/signaling case */
  65 #define DO_VFP_cmp(p, size)               \
  66 void do_vfp_cmp##p(void)                  \
  67 {                                         \
  68     uint32_t flags;                       \
  69     switch(float ## size ## _compare_quiet(FT0##p, FT1##p, &env->vfp.fp_status)) {\
  70     case 0: flags = 0x6; break;\
  71     case -1: flags = 0x8; break;\
  72     case 1: flags = 0x2; break;\
  73     default: case 2: flags = 0x3; break;\
  74     }\
  75     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28)\
  76         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
  77     FORCE_RET();                          \
  78 }\
  79 \
  80 void do_vfp_cmpe##p(void)                   \
  81 {                                           \
  82     uint32_t flags;                       \
  83     switch(float ## size ## _compare(FT0##p, FT1##p, &env->vfp.fp_status)) {\
  84     case 0: flags = 0x6; break;\
  85     case -1: flags = 0x8; break;\
  86     case 1: flags = 0x2; break;\
  87     default: case 2: flags = 0x3; break;\
  88     }\
  89     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28)\
  90         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
  91     FORCE_RET();                          \
  92 }
  93 DO_VFP_cmp(s, 32)
  94 DO_VFP_cmp(d, 64)
  95 #undef DO_VFP_cmp
  96
  97 /* Convert host exception flags to vfp form.  */
  98 static inline int vfp_exceptbits_from_host(int host_bits)
  99 {
 100     int target_bits = 0;
 101
 102     if (host_bits & float_flag_invalid)
 103         target_bits |= 1;
 104     if (host_bits & float_flag_divbyzero)
 105         target_bits |= 2;
 106     if (host_bits & float_flag_overflow)
 107         target_bits |= 4;
 108     if (host_bits & float_flag_underflow)
 109         target_bits |= 8;
 110     if (host_bits & float_flag_inexact)
 111         target_bits |= 0x10;
 112     return target_bits;
 113 }
 114
 115 /* Convert vfp exception flags to target form.  */
 116 static inline int vfp_exceptbits_to_host(int target_bits)
 117 {
 118     int host_bits = 0;
 119
 120     if (target_bits & 1)
 121         host_bits |= float_flag_invalid;
 122     if (target_bits & 2)
 123         host_bits |= float_flag_divbyzero;
 124     if (target_bits & 4)
 125         host_bits |= float_flag_overflow;
 126     if (target_bits & 8)
 127         host_bits |= float_flag_underflow;
 128     if (target_bits & 0x10)
 129         host_bits |= float_flag_inexact;
 130     return host_bits;
 131 }
 132
 133 void do_vfp_set_fpscr(void)
 134 {
 135     int i;
 136     uint32_t changed;
 137
 138     changed = env->vfp.xregs[ARM_VFP_FPSCR];
 139     env->vfp.xregs[ARM_VFP_FPSCR] = (T0 & 0xffc8ffff);
 140     env->vfp.vec_len = (T0 >> 16) & 7;
 141     env->vfp.vec_stride = (T0 >> 20) & 3;
 142
 143     changed ^= T0;
 144     if (changed & (3 << 22)) {
 145         i = (T0 >> 22) & 3;
 146         switch (i) {
 147         case 0:
 148             i = float_round_nearest_even;
 149             break;
 150         case 1:
 151             i = float_round_up;
 152             break;
 153         case 2:
 154             i = float_round_down;
 155             break;
 156         case 3:
 157             i = float_round_to_zero;
 158             break;
 159         }
 160         set_float_rounding_mode(i, &env->vfp.fp_status);
 161     }
 162
 163     i = vfp_exceptbits_to_host((T0 >> 8) & 0x1f);
 164     set_float_exception_flags(i, &env->vfp.fp_status);
 165     /* XXX: FZ and DN are not implemented.  */
 166 }
 167
 168 void do_vfp_get_fpscr(void)
 169 {
 170     int i;
 171
 172     T0 = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | (env->vfp.vec_len << 16)
 173           | (env->vfp.vec_stride << 20);
 174     i = get_float_exception_flags(&env->vfp.fp_status);
 175     T0 |= vfp_exceptbits_from_host(i);
 176 }
 177
 178 float32 helper_recps_f32(float32 a, float32 b)
 179 {
 180     float_status *s = &env->vfp.fp_status;
 181     float32 two = int32_to_float32(2, s);
 182     return float32_sub(two, float32_mul(a, b, s), s);
 183 }
 184
 185 float32 helper_rsqrts_f32(float32 a, float32 b)
 186 {
 187     float_status *s = &env->vfp.fp_status;
 188     float32 three = int32_to_float32(3, s);
 189     return float32_sub(three, float32_mul(a, b, s), s);
 190 }
 191
 192 /* TODO: The architecture specifies the value that the estimate functions
 193    should return.  We return the exact reciprocal/root instead.  */
 194 float32 helper_recpe_f32(float32 a)
 195 {
 196     float_status *s = &env->vfp.fp_status;
 197     float32 one = int32_to_float32(1, s);
 198     return float32_div(one, a, s);
 199 }
 200
 201 float32 helper_rsqrte_f32(float32 a)
 202 {
 203     float_status *s = &env->vfp.fp_status;
 204     float32 one = int32_to_float32(1, s);
 205     return float32_div(one, float32_sqrt(a, s), s);
 206 }
 207
 208 uint32_t helper_recpe_u32(uint32_t a)
 209 {
 210     float_status *s = &env->vfp.fp_status;
 211     float32 tmp;
 212     tmp = int32_to_float32(a, s);
 213     tmp = float32_scalbn(tmp, -32, s);
 214     tmp = helper_recpe_f32(tmp);
 215     tmp = float32_scalbn(tmp, 31, s);
 216     return float32_to_int32(tmp, s);
 217 }
 218
 219 uint32_t helper_rsqrte_u32(uint32_t a)
 220 {
 221     float_status *s = &env->vfp.fp_status;
 222     float32 tmp;
 223     tmp = int32_to_float32(a, s);
 224     tmp = float32_scalbn(tmp, -32, s);
 225     tmp = helper_rsqrte_f32(tmp);
 226     tmp = float32_scalbn(tmp, 31, s);
 227     return float32_to_int32(tmp, s);
 228 }
 229
 230 void helper_neon_tbl(int rn, int maxindex)
 231 {
 232     uint32_t val;
 233     uint32_t mask;
 234     uint32_t tmp;
 235     int index;
 236     int shift;
 237     uint64_t *table;
 238     table = (uint64_t *)&env->vfp.regs[rn];
 239     val = 0;
 240     mask = 0;
 241     for (shift = 0; shift < 32; shift += 8) {
 242         index = (T1 >> shift) & 0xff;
 243         if (index <= maxindex) {
 244             tmp = (table[index >> 3] >> (index & 7)) & 0xff;
 245             val |= tmp << shift;
 246         } else {
 247             val |= T0 & (0xff << shift);
 248         }
 249     }
 250     T0 = val;
 251 }
 252
 253 #if !defined(CONFIG_USER_ONLY)
 254
 255 #define MMUSUFFIX _mmu
 256 #ifdef __s390__
 257 # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
 258 #else
 259 # define GETPC() (__builtin_return_address(0))
 260 #endif
 261
 262 #define SHIFT 0
 263 #include "softmmu_template.h"
 264
 265 #define SHIFT 1
 266 #include "softmmu_template.h"
 267
 268 #define SHIFT 2
 269 #include "softmmu_template.h"
 270
 271 #define SHIFT 3
 272 #include "softmmu_template.h"
 273
 274 /* try to fill the TLB and return an exception if error. If retaddr is
 275    NULL, it means that the function was called in C code (i.e. not
 276    from generated code or from helper.c) */
 277 /* XXX: fix it to restore all registers */
 278 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
 279 {
 280     TranslationBlock *tb;
 281     CPUState *saved_env;
 282     unsigned long pc;
 283     int ret;
 284
 285     /* XXX: hack to restore env in all cases, even if not called from
 286        generated code */
 287     saved_env = env;
 288     env = cpu_single_env;
 289     ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
 290     if (__builtin_expect(ret, 0)) {
 291         if (retaddr) {
 292             /* now we have a real cpu fault */
 293             pc = (unsigned long)retaddr;
 294             tb = tb_find_pc(pc);
 295             if (tb) {
 296                 /* the PC is inside the translated code. It means that we have
 297                    a virtual CPU fault */
 298                 cpu_restore_state(tb, env, pc, NULL);
 299             }
 300         }
 301         raise_exception(env->exception_index);
 302     }
 303     env = saved_env;
 304 }
 305 #endif