qemu-kvm-x86.c

   1 /*
   2  * qemu/kvm integration, x86 specific code
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  *
   6  * Licensed under the terms of the GNU GPL version 2 or higher.
   7  */
   8
   9 #include "config.h"
  10 #include "config-host.h"
  11
  12 #include <string.h>
  13 #include "hw/hw.h"
  14
  15 #include "qemu-kvm.h"
  16 #include <libkvm.h>
  17 #include <pthread.h>
  18 #include <sys/utsname.h>
  19 #include <linux/kvm_para.h>
  20
  21 #define MSR_IA32_TSC            0x10
  22
  23 #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
  24
  25 static struct kvm_msr_list *kvm_msr_list;
  26 extern unsigned int kvm_shadow_memory;
  27 extern kvm_context_t kvm_context;
  28 static int kvm_has_msr_star;
  29
  30 static int lm_capable_kernel;
  31
  32 int kvm_arch_qemu_create_context(void)
  33 {
  34     int i;
  35     struct utsname utsname;
  36
  37     uname(&utsname);
  38     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
  39
  40     if (kvm_shadow_memory)
  41         kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
  42
  43     kvm_msr_list = kvm_get_msr_list(kvm_context);
  44     if (!kvm_msr_list)
  45                 return -1;
  46     for (i = 0; i < kvm_msr_list->nmsrs; ++i)
  47         if (kvm_msr_list->indices[i] == MSR_STAR)
  48             kvm_has_msr_star = 1;
  49         return 0;
  50 }
  51
  52 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
  53                           uint64_t data)
  54 {
  55     entry->index = index;
  56     entry->data  = data;
  57 }
  58
  59 /* returns 0 on success, non-0 on failure */
  60 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
  61 {
  62         switch (entry->index) {
  63         case MSR_IA32_SYSENTER_CS:
  64             env->sysenter_cs  = entry->data;
  65             break;
  66         case MSR_IA32_SYSENTER_ESP:
  67             env->sysenter_esp = entry->data;
  68             break;
  69         case MSR_IA32_SYSENTER_EIP:
  70             env->sysenter_eip = entry->data;
  71             break;
  72         case MSR_STAR:
  73             env->star         = entry->data;
  74             break;
  75 #ifdef TARGET_X86_64
  76         case MSR_CSTAR:
  77             env->cstar        = entry->data;
  78             break;
  79         case MSR_KERNELGSBASE:
  80             env->kernelgsbase = entry->data;
  81             break;
  82         case MSR_FMASK:
  83             env->fmask        = entry->data;
  84             break;
  85         case MSR_LSTAR:
  86             env->lstar        = entry->data;
  87             break;
  88 #endif
  89         case MSR_IA32_TSC:
  90             env->tsc          = entry->data;
  91             break;
  92         default:
  93             printf("Warning unknown msr index 0x%x\n", entry->index);
  94             return 1;
  95         }
  96         return 0;
  97 }
  98
  99 #ifdef TARGET_X86_64
 100 #define MSR_COUNT 9
 101 #else
 102 #define MSR_COUNT 5
 103 #endif
 104
 105 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 106 {
 107     lhs->selector = rhs->selector;
 108     lhs->base = rhs->base;
 109     lhs->limit = rhs->limit;
 110     lhs->type = 3;
 111     lhs->present = 1;
 112     lhs->dpl = 3;
 113     lhs->db = 0;
 114     lhs->s = 1;
 115     lhs->l = 0;
 116     lhs->g = 0;
 117     lhs->avl = 0;
 118     lhs->unusable = 0;
 119 }
 120
 121 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 122 {
 123     unsigned flags = rhs->flags;
 124     lhs->selector = rhs->selector;
 125     lhs->base = rhs->base;
 126     lhs->limit = rhs->limit;
 127     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 128     lhs->present = (flags & DESC_P_MASK) != 0;
 129     lhs->dpl = rhs->selector & 3;
 130     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 131     lhs->s = (flags & DESC_S_MASK) != 0;
 132     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 133     lhs->g = (flags & DESC_G_MASK) != 0;
 134     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 135     lhs->unusable = 0;
 136 }
 137
 138 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 139 {
 140     lhs->selector = rhs->selector;
 141     lhs->base = rhs->base;
 142     lhs->limit = rhs->limit;
 143     lhs->flags =
 144         (rhs->type << DESC_TYPE_SHIFT)
 145         | (rhs->present * DESC_P_MASK)
 146         | (rhs->dpl << DESC_DPL_SHIFT)
 147         | (rhs->db << DESC_B_SHIFT)
 148         | (rhs->s * DESC_S_MASK)
 149         | (rhs->l << DESC_L_SHIFT)
 150         | (rhs->g * DESC_G_MASK)
 151         | (rhs->avl * DESC_AVL_MASK);
 152 }
 153
 154 /* the reset values of qemu are not compatible to SVM
 155  * this function is used to fix the segment descriptor values */
 156 static void fix_realmode_dataseg(struct kvm_segment *seg)
 157 {
 158         seg->type = 0x02;
 159         seg->present = 1;
 160         seg->s = 1;
 161 }
 162
 163 void kvm_arch_load_regs(CPUState *env)
 164 {
 165     struct kvm_regs regs;
 166     struct kvm_fpu fpu;
 167     struct kvm_sregs sregs;
 168     struct kvm_msr_entry msrs[MSR_COUNT];
 169     int rc, n, i;
 170
 171     regs.rax = env->regs[R_EAX];
 172     regs.rbx = env->regs[R_EBX];
 173     regs.rcx = env->regs[R_ECX];
 174     regs.rdx = env->regs[R_EDX];
 175     regs.rsi = env->regs[R_ESI];
 176     regs.rdi = env->regs[R_EDI];
 177     regs.rsp = env->regs[R_ESP];
 178     regs.rbp = env->regs[R_EBP];
 179 #ifdef TARGET_X86_64
 180     regs.r8 = env->regs[8];
 181     regs.r9 = env->regs[9];
 182     regs.r10 = env->regs[10];
 183     regs.r11 = env->regs[11];
 184     regs.r12 = env->regs[12];
 185     regs.r13 = env->regs[13];
 186     regs.r14 = env->regs[14];
 187     regs.r15 = env->regs[15];
 188 #endif
 189
 190     regs.rflags = env->eflags;
 191     regs.rip = env->eip;
 192
 193     kvm_set_regs(kvm_context, env->cpu_index, &regs);
 194
 195     memset(&fpu, 0, sizeof fpu);
 196     fpu.fsw = env->fpus & ~(7 << 11);
 197     fpu.fsw |= (env->fpstt & 7) << 11;
 198     fpu.fcw = env->fpuc;
 199     for (i = 0; i < 8; ++i)
 200         fpu.ftwx |= (!env->fptags[i]) << i;
 201     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 202     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 203     fpu.mxcsr = env->mxcsr;
 204     kvm_set_fpu(kvm_context, env->cpu_index, &fpu);
 205
 206     memcpy(sregs.interrupt_bitmap, env->kvm_interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
 207
 208     if ((env->eflags & VM_MASK)) {
 209             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 210             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 211             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 212             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 213             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 214             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 215     } else {
 216             set_seg(&sregs.cs, &env->segs[R_CS]);
 217             set_seg(&sregs.ds, &env->segs[R_DS]);
 218             set_seg(&sregs.es, &env->segs[R_ES]);
 219             set_seg(&sregs.fs, &env->segs[R_FS]);
 220             set_seg(&sregs.gs, &env->segs[R_GS]);
 221             set_seg(&sregs.ss, &env->segs[R_SS]);
 222
 223             if (env->cr[0] & CR0_PE_MASK) {
 224                 /* force ss cpl to cs cpl */
 225                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 226                         (sregs.cs.selector & 3);
 227                 sregs.ss.dpl = sregs.ss.selector & 3;
 228             }
 229
 230             if (!(env->cr[0] & CR0_PG_MASK)) {
 231                     fix_realmode_dataseg(&sregs.cs);
 232                     fix_realmode_dataseg(&sregs.ds);
 233                     fix_realmode_dataseg(&sregs.es);
 234                     fix_realmode_dataseg(&sregs.fs);
 235                     fix_realmode_dataseg(&sregs.gs);
 236                     fix_realmode_dataseg(&sregs.ss);
 237             }
 238     }
 239
 240     set_seg(&sregs.tr, &env->tr);
 241     set_seg(&sregs.ldt, &env->ldt);
 242
 243     sregs.idt.limit = env->idt.limit;
 244     sregs.idt.base = env->idt.base;
 245     sregs.gdt.limit = env->gdt.limit;
 246     sregs.gdt.base = env->gdt.base;
 247
 248     sregs.cr0 = env->cr[0];
 249     sregs.cr2 = env->cr[2];
 250     sregs.cr3 = env->cr[3];
 251     sregs.cr4 = env->cr[4];
 252
 253     sregs.apic_base = cpu_get_apic_base(env);
 254     sregs.efer = env->efer;
 255     sregs.cr8 = cpu_get_apic_tpr(env);
 256
 257     kvm_set_sregs(kvm_context, env->cpu_index, &sregs);
 258
 259     /* msrs */
 260     n = 0;
 261     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS,  env->sysenter_cs);
 262     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 263     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 264     if (kvm_has_msr_star)
 265         set_msr_entry(&msrs[n++], MSR_STAR,              env->star);
 266     set_msr_entry(&msrs[n++], MSR_IA32_TSC, env->tsc);
 267 #ifdef TARGET_X86_64
 268     if (lm_capable_kernel) {
 269         set_msr_entry(&msrs[n++], MSR_CSTAR,             env->cstar);
 270         set_msr_entry(&msrs[n++], MSR_KERNELGSBASE,      env->kernelgsbase);
 271         set_msr_entry(&msrs[n++], MSR_FMASK,             env->fmask);
 272         set_msr_entry(&msrs[n++], MSR_LSTAR  ,           env->lstar);
 273     }
 274 #endif
 275
 276     rc = kvm_set_msrs(kvm_context, env->cpu_index, msrs, n);
 277     if (rc == -1)
 278         perror("kvm_set_msrs FAILED");
 279 }
 280
 281
 282 void kvm_arch_save_regs(CPUState *env)
 283 {
 284     struct kvm_regs regs;
 285     struct kvm_fpu fpu;
 286     struct kvm_sregs sregs;
 287     struct kvm_msr_entry msrs[MSR_COUNT];
 288     uint32_t hflags;
 289     uint32_t i, n, rc;
 290
 291     kvm_get_regs(kvm_context, env->cpu_index, &regs);
 292
 293     env->regs[R_EAX] = regs.rax;
 294     env->regs[R_EBX] = regs.rbx;
 295     env->regs[R_ECX] = regs.rcx;
 296     env->regs[R_EDX] = regs.rdx;
 297     env->regs[R_ESI] = regs.rsi;
 298     env->regs[R_EDI] = regs.rdi;
 299     env->regs[R_ESP] = regs.rsp;
 300     env->regs[R_EBP] = regs.rbp;
 301 #ifdef TARGET_X86_64
 302     env->regs[8] = regs.r8;
 303     env->regs[9] = regs.r9;
 304     env->regs[10] = regs.r10;
 305     env->regs[11] = regs.r11;
 306     env->regs[12] = regs.r12;
 307     env->regs[13] = regs.r13;
 308     env->regs[14] = regs.r14;
 309     env->regs[15] = regs.r15;
 310 #endif
 311
 312     env->eflags = regs.rflags;
 313     env->eip = regs.rip;
 314
 315     kvm_get_fpu(kvm_context, env->cpu_index, &fpu);
 316     env->fpstt = (fpu.fsw >> 11) & 7;
 317     env->fpus = fpu.fsw;
 318     env->fpuc = fpu.fcw;
 319     for (i = 0; i < 8; ++i)
 320         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 321     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 322     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 323     env->mxcsr = fpu.mxcsr;
 324
 325     kvm_get_sregs(kvm_context, env->cpu_index, &sregs);
 326
 327     memcpy(env->kvm_interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->kvm_interrupt_bitmap));
 328
 329     get_seg(&env->segs[R_CS], &sregs.cs);
 330     get_seg(&env->segs[R_DS], &sregs.ds);
 331     get_seg(&env->segs[R_ES], &sregs.es);
 332     get_seg(&env->segs[R_FS], &sregs.fs);
 333     get_seg(&env->segs[R_GS], &sregs.gs);
 334     get_seg(&env->segs[R_SS], &sregs.ss);
 335
 336     get_seg(&env->tr, &sregs.tr);
 337     get_seg(&env->ldt, &sregs.ldt);
 338
 339     env->idt.limit = sregs.idt.limit;
 340     env->idt.base = sregs.idt.base;
 341     env->gdt.limit = sregs.gdt.limit;
 342     env->gdt.base = sregs.gdt.base;
 343
 344     env->cr[0] = sregs.cr0;
 345     env->cr[2] = sregs.cr2;
 346     env->cr[3] = sregs.cr3;
 347     env->cr[4] = sregs.cr4;
 348
 349     cpu_set_apic_base(env, sregs.apic_base);
 350
 351     env->efer = sregs.efer;
 352     //cpu_set_apic_tpr(env, sregs.cr8);
 353
 354 #define HFLAG_COPY_MASK ~( \
 355                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 356                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 357                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 358                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 359
 360
 361
 362     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 363     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 364     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 365             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 366     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 367     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 368             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 369
 370     if (env->efer & MSR_EFER_LMA) {
 371         hflags |= HF_LMA_MASK;
 372     }
 373
 374     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 375         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 376     } else {
 377         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 378                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 379         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 380                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 381         if (!(env->cr[0] & CR0_PE_MASK) ||
 382                    (env->eflags & VM_MASK) ||
 383                    !(hflags & HF_CS32_MASK)) {
 384                 hflags |= HF_ADDSEG_MASK;
 385             } else {
 386                 hflags |= ((env->segs[R_DS].base |
 387                                 env->segs[R_ES].base |
 388                                 env->segs[R_SS].base) != 0) <<
 389                     HF_ADDSEG_SHIFT;
 390             }
 391     }
 392     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 393     env->cc_src = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 394     env->df = 1 - (2 * ((env->eflags >> 10) & 1));
 395     env->cc_op = CC_OP_EFLAGS;
 396     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 397
 398     /* msrs */
 399     n = 0;
 400     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 401     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 402     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 403     if (kvm_has_msr_star)
 404         msrs[n++].index = MSR_STAR;
 405     msrs[n++].index = MSR_IA32_TSC;
 406 #ifdef TARGET_X86_64
 407     if (lm_capable_kernel) {
 408         msrs[n++].index = MSR_CSTAR;
 409         msrs[n++].index = MSR_KERNELGSBASE;
 410         msrs[n++].index = MSR_FMASK;
 411         msrs[n++].index = MSR_LSTAR;
 412     }
 413 #endif
 414     rc = kvm_get_msrs(kvm_context, env->cpu_index, msrs, n);
 415     if (rc == -1) {
 416         perror("kvm_get_msrs FAILED");
 417     }
 418     else {
 419         n = rc; /* actual number of MSRs */
 420         for (i=0 ; i<n; i++) {
 421             if (get_msr_entry(&msrs[i], env))
 422                 return;
 423         }
 424     }
 425 }
 426
 427 static void host_cpuid(uint32_t function, uint32_t *eax, uint32_t *ebx,
 428                        uint32_t *ecx, uint32_t *edx)
 429 {
 430     uint32_t vec[4];
 431
 432 #ifdef __x86_64__
 433     asm volatile("cpuid"
 434                  : "=a"(vec[0]), "=b"(vec[1]),
 435                    "=c"(vec[2]), "=d"(vec[3])
 436                  : "0"(function) : "cc");
 437 #else
 438     asm volatile("pusha \n\t"
 439                  "cpuid \n\t"
 440                  "mov %%eax, 0(%1) \n\t"
 441                  "mov %%ebx, 4(%1) \n\t"
 442                  "mov %%ecx, 8(%1) \n\t"
 443                  "mov %%edx, 12(%1) \n\t"
 444                  "popa"
 445                  : : "a"(function), "S"(vec)
 446                  : "memory", "cc");
 447 #endif
 448
 449     if (eax)
 450         *eax = vec[0];
 451     if (ebx)
 452         *ebx = vec[1];
 453     if (ecx)
 454         *ecx = vec[2];
 455     if (edx)
 456         *edx = vec[3];
 457 }
 458
 459
 460 static void do_cpuid_ent(struct kvm_cpuid_entry *e, uint32_t function,
 461                          CPUState *env)
 462 {
 463     env->regs[R_EAX] = function;
 464     qemu_kvm_cpuid_on_env(env);
 465     e->function = function;
 466     e->eax = env->regs[R_EAX];
 467     e->ebx = env->regs[R_EBX];
 468     e->ecx = env->regs[R_ECX];
 469     e->edx = env->regs[R_EDX];
 470     if (function == 0x80000001) {
 471         uint32_t h_eax, h_edx;
 472
 473         host_cpuid(function, &h_eax, NULL, NULL, &h_edx);
 474
 475         // long mode
 476         if ((h_edx & 0x20000000) == 0 || !lm_capable_kernel)
 477             e->edx &= ~0x20000000u;
 478         // syscall
 479         if ((h_edx & 0x00000800) == 0)
 480             e->edx &= ~0x00000800u;
 481         // nx
 482         if ((h_edx & 0x00100000) == 0)
 483             e->edx &= ~0x00100000u;
 484         // svm
 485         if (e->ecx & 4)
 486             e->ecx &= ~4u;
 487     }
 488     // sysenter isn't supported on compatibility mode on AMD.  and syscall
 489     // isn't supported in compatibility mode on Intel.  so advertise the
 490     // actuall cpu, and say goodbye to migration between different vendors
 491     // is you use compatibility mode.
 492     if (function == 0) {
 493         uint32_t bcd[3];
 494
 495         host_cpuid(0, NULL, &bcd[0], &bcd[1], &bcd[2]);
 496         e->ebx = bcd[0];
 497         e->ecx = bcd[1];
 498         e->edx = bcd[2];
 499     }
 500 }
 501
 502 struct kvm_para_features {
 503         int cap;
 504         int feature;
 505 } para_features[] = {
 506 #ifdef KVM_CAP_CLOCKSOURCE
 507         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 508 #endif
 509 #ifdef KVM_CAP_NOP_IO_DELAY
 510         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 511 #endif
 512 #ifdef KVM_CAP_PV_MMU
 513         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 514 #endif
 515 #ifdef KVM_CAP_CR3_CACHE
 516         { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
 517 #endif
 518         { -1, -1 }
 519 };
 520
 521 static int get_para_features(kvm_context_t kvm_context)
 522 {
 523         int i, features = 0;
 524
 525         for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
 526                 if (kvm_check_extension(kvm_context, para_features[i].cap))
 527                         features |= (1 << para_features[i].feature);
 528         }
 529
 530         return features;
 531 }
 532
 533 int kvm_arch_qemu_init_env(CPUState *cenv)
 534 {
 535     struct kvm_cpuid_entry cpuid_ent[100];
 536 #ifdef KVM_CPUID_SIGNATURE
 537     struct kvm_cpuid_entry *pv_ent;
 538     uint32_t signature[3];
 539 #endif
 540     int cpuid_nent = 0;
 541     CPUState copy;
 542     uint32_t i, limit;
 543
 544     copy = *cenv;
 545
 546 #ifdef KVM_CPUID_SIGNATURE
 547     /* Paravirtualization CPUIDs */
 548     memcpy(signature, "KVMKVMKVM", 12);
 549     pv_ent = &cpuid_ent[cpuid_nent++];
 550     memset(pv_ent, 0, sizeof(*pv_ent));
 551     pv_ent->function = KVM_CPUID_SIGNATURE;
 552     pv_ent->eax = 0;
 553     pv_ent->ebx = signature[0];
 554     pv_ent->ecx = signature[1];
 555     pv_ent->edx = signature[2];
 556
 557     pv_ent = &cpuid_ent[cpuid_nent++];
 558     memset(pv_ent, 0, sizeof(*pv_ent));
 559     pv_ent->function = KVM_CPUID_FEATURES;
 560     pv_ent->eax = get_para_features(kvm_context);
 561 #endif
 562
 563     copy.regs[R_EAX] = 0;
 564     qemu_kvm_cpuid_on_env(&copy);
 565     limit = copy.regs[R_EAX];
 566
 567     for (i = 0; i <= limit; ++i)
 568         do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, &copy);
 569
 570     copy.regs[R_EAX] = 0x80000000;
 571     qemu_kvm_cpuid_on_env(&copy);
 572     limit = copy.regs[R_EAX];
 573
 574     for (i = 0x80000000; i <= limit; ++i)
 575         do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, &copy);
 576
 577     kvm_setup_cpuid(kvm_context, cenv->cpu_index, cpuid_nent, cpuid_ent);
 578     return 0;
 579 }
 580
 581 int kvm_arch_halt(void *opaque, int vcpu)
 582 {
 583     CPUState *env = cpu_single_env;
 584
 585     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 586           (env->eflags & IF_MASK))) {
 587             env->hflags |= HF_HALTED_MASK;
 588             env->exception_index = EXCP_HLT;
 589     }
 590     return 1;
 591 }
 592
 593 void kvm_arch_pre_kvm_run(void *opaque, int vcpu)
 594 {
 595     CPUState *env = cpu_single_env;
 596
 597     if (!kvm_irqchip_in_kernel(kvm_context))
 598         kvm_set_cr8(kvm_context, vcpu, cpu_get_apic_tpr(env));
 599 }
 600
 601 void kvm_arch_post_kvm_run(void *opaque, int vcpu)
 602 {
 603     CPUState *env = qemu_kvm_cpu_env(vcpu);
 604     cpu_single_env = env;
 605
 606     env->eflags = kvm_get_interrupt_flag(kvm_context, vcpu)
 607         ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
 608     env->ready_for_interrupt_injection
 609         = kvm_is_ready_for_interrupt_injection(kvm_context, vcpu);
 610
 611     cpu_set_apic_tpr(env, kvm_get_cr8(kvm_context, vcpu));
 612     cpu_set_apic_base(env, kvm_get_apic_base(kvm_context, vcpu));
 613 }
 614
 615 int kvm_arch_has_work(CPUState *env)
 616 {
 617     if ((env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT)) &&
 618         (env->eflags & IF_MASK))
 619         return 1;
 620     return 0;
 621 }
 622
 623 int kvm_arch_try_push_interrupts(void *opaque)
 624 {
 625     CPUState *env = cpu_single_env;
 626     int r, irq;
 627
 628     if (env->ready_for_interrupt_injection &&
 629         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 630         (env->eflags & IF_MASK)) {
 631             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 632             irq = cpu_get_pic_interrupt(env);
 633             if (irq >= 0) {
 634                 r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
 635                 if (r < 0)
 636                     printf("cpu %d fail inject %x\n", env->cpu_index, irq);
 637             }
 638     }
 639
 640     return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
 641 }
 642
 643 void kvm_arch_update_regs_for_sipi(CPUState *env)
 644 {
 645     SegmentCache cs = env->segs[R_CS];
 646
 647     kvm_arch_save_regs(env);
 648     env->segs[R_CS] = cs;
 649     env->eip = 0;
 650     kvm_arch_load_regs(env);
 651 }
 652
 653 int handle_tpr_access(void *opaque, int vcpu,
 654                              uint64_t rip, int is_write)
 655 {
 656     kvm_tpr_access_report(cpu_single_env, rip, is_write);
 657     return 0;
 658 }