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Ignore -Waddress for alsaaudio.c
[qemu-kvm/fedora.git] / hw / fdc.c
blobfa154a30cbbb9e82d63e26d7ab23c8d501ce8d74
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "block.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36
37 /********************************************************/
38 /* debug Floppy devices */
39 //#define DEBUG_FLOPPY
40
41 #ifdef DEBUG_FLOPPY
42 #define FLOPPY_DPRINTF(fmt, ...) \
43 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
44 #else
45 #define FLOPPY_DPRINTF(fmt, ...)
46 #endif
47
48 #define FLOPPY_ERROR(fmt, ...) \
49 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
50
51 /********************************************************/
52 /* Floppy drive emulation */
53
54 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
55 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
56
57 /* Will always be a fixed parameter for us */
58 #define FD_SECTOR_LEN 512
59 #define FD_SECTOR_SC 2 /* Sector size code */
60 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
61
62 /* Floppy disk drive emulation */
63 typedef enum fdisk_type_t {
64 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
65 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
66 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
67 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
68 FDRIVE_DISK_NONE = 0x05, /* No disk */
69 } fdisk_type_t;
70
71 typedef enum fdrive_type_t {
72 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
73 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
74 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
75 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
76 } fdrive_type_t;
77
78 typedef enum fdisk_flags_t {
79 FDISK_DBL_SIDES = 0x01,
80 } fdisk_flags_t;
81
82 typedef struct fdrive_t {
83 BlockDriverState *bs;
84 /* Drive status */
85 fdrive_type_t drive;
86 uint8_t perpendicular; /* 2.88 MB access mode */
87 /* Position */
88 uint8_t head;
89 uint8_t track;
90 uint8_t sect;
91 /* Media */
92 fdisk_flags_t flags;
93 uint8_t last_sect; /* Nb sector per track */
94 uint8_t max_track; /* Nb of tracks */
95 uint16_t bps; /* Bytes per sector */
96 uint8_t ro; /* Is read-only */
97 } fdrive_t;
98
99 static void fd_init (fdrive_t *drv, BlockDriverState *bs)
100 {
101 /* Drive */
102 drv->bs = bs;
103 drv->drive = FDRIVE_DRV_NONE;
104 drv->perpendicular = 0;
105 /* Disk */
106 drv->last_sect = 0;
107 drv->max_track = 0;
108 }
109
110 static int _fd_sector (uint8_t head, uint8_t track,
111 uint8_t sect, uint8_t last_sect)
112 {
113 return (((track * 2) + head) * last_sect) + sect - 1;
114 }
115
116 /* Returns current position, in sectors, for given drive */
117 static int fd_sector (fdrive_t *drv)
118 {
119 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
120 }
121
122 /* Seek to a new position:
123 * returns 0 if already on right track
124 * returns 1 if track changed
125 * returns 2 if track is invalid
126 * returns 3 if sector is invalid
127 * returns 4 if seek is disabled
128 */
129 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
130 int enable_seek)
131 {
132 uint32_t sector;
133 int ret;
134
135 if (track > drv->max_track ||
136 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
137 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
138 head, track, sect, 1,
139 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
140 drv->max_track, drv->last_sect);
141 return 2;
142 }
143 if (sect > drv->last_sect) {
144 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
145 head, track, sect, 1,
146 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
147 drv->max_track, drv->last_sect);
148 return 3;
149 }
150 sector = _fd_sector(head, track, sect, drv->last_sect);
151 ret = 0;
152 if (sector != fd_sector(drv)) {
153 #if 0
154 if (!enable_seek) {
155 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
156 head, track, sect, 1, drv->max_track, drv->last_sect);
157 return 4;
158 }
159 #endif
160 drv->head = head;
161 if (drv->track != track)
162 ret = 1;
163 drv->track = track;
164 drv->sect = sect;
165 }
166
167 return ret;
168 }
169
170 /* Set drive back to track 0 */
171 static void fd_recalibrate (fdrive_t *drv)
172 {
173 FLOPPY_DPRINTF("recalibrate\n");
174 drv->head = 0;
175 drv->track = 0;
176 drv->sect = 1;
177 }
178
179 /* Recognize floppy formats */
180 typedef struct fd_format_t {
181 fdrive_type_t drive;
182 fdisk_type_t disk;
183 uint8_t last_sect;
184 uint8_t max_track;
185 uint8_t max_head;
186 const char *str;
187 } fd_format_t;
188
189 static const fd_format_t fd_formats[] = {
190 /* First entry is default format */
191 /* 1.44 MB 3"1/2 floppy disks */
192 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
193 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
198 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
199 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
200 /* 2.88 MB 3"1/2 floppy disks */
201 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
202 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
204 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
205 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
206 /* 720 kB 3"1/2 floppy disks */
207 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
208 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
211 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
212 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
213 /* 1.2 MB 5"1/4 floppy disks */
214 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
215 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
219 /* 720 kB 5"1/4 floppy disks */
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
221 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
222 /* 360 kB 5"1/4 floppy disks */
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
224 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
227 /* 320 kB 5"1/4 floppy disks */
228 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
229 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
230 /* 360 kB must match 5"1/4 better than 3"1/2... */
231 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
232 /* end */
233 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
234 };
235
236 /* Revalidate a disk drive after a disk change */
237 static void fd_revalidate (fdrive_t *drv)
238 {
239 const fd_format_t *parse;
240 uint64_t nb_sectors, size;
241 int i, first_match, match;
242 int nb_heads, max_track, last_sect, ro;
243
244 FLOPPY_DPRINTF("revalidate\n");
245 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
246 ro = bdrv_is_read_only(drv->bs);
247 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
248 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
249 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
250 nb_heads - 1, max_track, last_sect);
251 } else {
252 bdrv_get_geometry(drv->bs, &nb_sectors);
253 match = -1;
254 first_match = -1;
255 for (i = 0;; i++) {
256 parse = &fd_formats[i];
257 if (parse->drive == FDRIVE_DRV_NONE)
258 break;
259 if (drv->drive == parse->drive ||
260 drv->drive == FDRIVE_DRV_NONE) {
261 size = (parse->max_head + 1) * parse->max_track *
262 parse->last_sect;
263 if (nb_sectors == size) {
264 match = i;
265 break;
266 }
267 if (first_match == -1)
268 first_match = i;
269 }
270 }
271 if (match == -1) {
272 if (first_match == -1)
273 match = 1;
274 else
275 match = first_match;
276 parse = &fd_formats[match];
277 }
278 nb_heads = parse->max_head + 1;
279 max_track = parse->max_track;
280 last_sect = parse->last_sect;
281 drv->drive = parse->drive;
282 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
283 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
284 }
285 if (nb_heads == 1) {
286 drv->flags &= ~FDISK_DBL_SIDES;
287 } else {
288 drv->flags |= FDISK_DBL_SIDES;
289 }
290 drv->max_track = max_track;
291 drv->last_sect = last_sect;
292 drv->ro = ro;
293 } else {
294 FLOPPY_DPRINTF("No disk in drive\n");
295 drv->last_sect = 0;
296 drv->max_track = 0;
297 drv->flags &= ~FDISK_DBL_SIDES;
298 }
299 }
300
301 /********************************************************/
302 /* Intel 82078 floppy disk controller emulation */
303
304 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
305 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
306 static int fdctrl_transfer_handler (void *opaque, int nchan,
307 int dma_pos, int dma_len);
308 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
309
310 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
311 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
312 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
313 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
314 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
315 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
316 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
317 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
318 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
319 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
320 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
321
322 enum {
323 FD_DIR_WRITE = 0,
324 FD_DIR_READ = 1,
325 FD_DIR_SCANE = 2,
326 FD_DIR_SCANL = 3,
327 FD_DIR_SCANH = 4,
328 };
329
330 enum {
331 FD_STATE_MULTI = 0x01, /* multi track flag */
332 FD_STATE_FORMAT = 0x02, /* format flag */
333 FD_STATE_SEEK = 0x04, /* seek flag */
334 };
335
336 enum {
337 FD_REG_SRA = 0x00,
338 FD_REG_SRB = 0x01,
339 FD_REG_DOR = 0x02,
340 FD_REG_TDR = 0x03,
341 FD_REG_MSR = 0x04,
342 FD_REG_DSR = 0x04,
343 FD_REG_FIFO = 0x05,
344 FD_REG_DIR = 0x07,
345 };
346
347 enum {
348 FD_CMD_READ_TRACK = 0x02,
349 FD_CMD_SPECIFY = 0x03,
350 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
351 FD_CMD_WRITE = 0x05,
352 FD_CMD_READ = 0x06,
353 FD_CMD_RECALIBRATE = 0x07,
354 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
355 FD_CMD_WRITE_DELETED = 0x09,
356 FD_CMD_READ_ID = 0x0a,
357 FD_CMD_READ_DELETED = 0x0c,
358 FD_CMD_FORMAT_TRACK = 0x0d,
359 FD_CMD_DUMPREG = 0x0e,
360 FD_CMD_SEEK = 0x0f,
361 FD_CMD_VERSION = 0x10,
362 FD_CMD_SCAN_EQUAL = 0x11,
363 FD_CMD_PERPENDICULAR_MODE = 0x12,
364 FD_CMD_CONFIGURE = 0x13,
365 FD_CMD_LOCK = 0x14,
366 FD_CMD_VERIFY = 0x16,
367 FD_CMD_POWERDOWN_MODE = 0x17,
368 FD_CMD_PART_ID = 0x18,
369 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
370 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
371 FD_CMD_SAVE = 0x2c,
372 FD_CMD_OPTION = 0x33,
373 FD_CMD_RESTORE = 0x4c,
374 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
375 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
376 FD_CMD_FORMAT_AND_WRITE = 0xcd,
377 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
378 };
379
380 enum {
381 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
382 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
383 FD_CONFIG_POLL = 0x10, /* Poll enabled */
384 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
385 FD_CONFIG_EIS = 0x40, /* No implied seeks */
386 };
387
388 enum {
389 FD_SR0_EQPMT = 0x10,
390 FD_SR0_SEEK = 0x20,
391 FD_SR0_ABNTERM = 0x40,
392 FD_SR0_INVCMD = 0x80,
393 FD_SR0_RDYCHG = 0xc0,
394 };
395
396 enum {
397 FD_SR1_EC = 0x80, /* End of cylinder */
398 };
399
400 enum {
401 FD_SR2_SNS = 0x04, /* Scan not satisfied */
402 FD_SR2_SEH = 0x08, /* Scan equal hit */
403 };
404
405 enum {
406 FD_SRA_DIR = 0x01,
407 FD_SRA_nWP = 0x02,
408 FD_SRA_nINDX = 0x04,
409 FD_SRA_HDSEL = 0x08,
410 FD_SRA_nTRK0 = 0x10,
411 FD_SRA_STEP = 0x20,
412 FD_SRA_nDRV2 = 0x40,
413 FD_SRA_INTPEND = 0x80,
414 };
415
416 enum {
417 FD_SRB_MTR0 = 0x01,
418 FD_SRB_MTR1 = 0x02,
419 FD_SRB_WGATE = 0x04,
420 FD_SRB_RDATA = 0x08,
421 FD_SRB_WDATA = 0x10,
422 FD_SRB_DR0 = 0x20,
423 };
424
425 enum {
426 #if MAX_FD == 4
427 FD_DOR_SELMASK = 0x03,
428 #else
429 FD_DOR_SELMASK = 0x01,
430 #endif
431 FD_DOR_nRESET = 0x04,
432 FD_DOR_DMAEN = 0x08,
433 FD_DOR_MOTEN0 = 0x10,
434 FD_DOR_MOTEN1 = 0x20,
435 FD_DOR_MOTEN2 = 0x40,
436 FD_DOR_MOTEN3 = 0x80,
437 };
438
439 enum {
440 #if MAX_FD == 4
441 FD_TDR_BOOTSEL = 0x0c,
442 #else
443 FD_TDR_BOOTSEL = 0x04,
444 #endif
445 };
446
447 enum {
448 FD_DSR_DRATEMASK= 0x03,
449 FD_DSR_PWRDOWN = 0x40,
450 FD_DSR_SWRESET = 0x80,
451 };
452
453 enum {
454 FD_MSR_DRV0BUSY = 0x01,
455 FD_MSR_DRV1BUSY = 0x02,
456 FD_MSR_DRV2BUSY = 0x04,
457 FD_MSR_DRV3BUSY = 0x08,
458 FD_MSR_CMDBUSY = 0x10,
459 FD_MSR_NONDMA = 0x20,
460 FD_MSR_DIO = 0x40,
461 FD_MSR_RQM = 0x80,
462 };
463
464 enum {
465 FD_DIR_DSKCHG = 0x80,
466 };
467
468 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
469 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
470 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
471
472 struct fdctrl_t {
473 SysBusDevice busdev;
474 /* Controller's identification */
475 uint8_t version;
476 /* HW */
477 qemu_irq irq;
478 int dma_chann;
479 target_phys_addr_t io_base;
480 /* Controller state */
481 QEMUTimer *result_timer;
482 uint8_t sra;
483 uint8_t srb;
484 uint8_t dor;
485 uint8_t tdr;
486 uint8_t dsr;
487 uint8_t msr;
488 uint8_t cur_drv;
489 uint8_t status0;
490 uint8_t status1;
491 uint8_t status2;
492 /* Command FIFO */
493 uint8_t *fifo;
494 uint32_t data_pos;
495 uint32_t data_len;
496 uint8_t data_state;
497 uint8_t data_dir;
498 uint8_t eot; /* last wanted sector */
499 /* States kept only to be returned back */
500 /* Timers state */
501 uint8_t timer0;
502 uint8_t timer1;
503 /* precompensation */
504 uint8_t precomp_trk;
505 uint8_t config;
506 uint8_t lock;
507 /* Power down config (also with status regB access mode */
508 uint8_t pwrd;
509 /* Sun4m quirks? */
510 int sun4m;
511 /* Floppy drives */
512 fdrive_t drives[MAX_FD];
513 int reset_sensei;
514 uint32_t strict_io;
515 uint32_t mem_mapped;
516 };
517
518 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
519 {
520 fdctrl_t *fdctrl = opaque;
521 uint32_t retval;
522
523 switch (reg) {
524 case FD_REG_SRA:
525 retval = fdctrl_read_statusA(fdctrl);
526 break;
527 case FD_REG_SRB:
528 retval = fdctrl_read_statusB(fdctrl);
529 break;
530 case FD_REG_DOR:
531 retval = fdctrl_read_dor(fdctrl);
532 break;
533 case FD_REG_TDR:
534 retval = fdctrl_read_tape(fdctrl);
535 break;
536 case FD_REG_MSR:
537 retval = fdctrl_read_main_status(fdctrl);
538 break;
539 case FD_REG_FIFO:
540 retval = fdctrl_read_data(fdctrl);
541 break;
542 case FD_REG_DIR:
543 retval = fdctrl_read_dir(fdctrl);
544 break;
545 default:
546 retval = (uint32_t)(-1);
547 break;
548 }
549 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
550
551 return retval;
552 }
553
554 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
555 {
556 fdctrl_t *fdctrl = opaque;
557
558 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
559
560 switch (reg) {
561 case FD_REG_DOR:
562 fdctrl_write_dor(fdctrl, value);
563 break;
564 case FD_REG_TDR:
565 fdctrl_write_tape(fdctrl, value);
566 break;
567 case FD_REG_DSR:
568 fdctrl_write_rate(fdctrl, value);
569 break;
570 case FD_REG_FIFO:
571 fdctrl_write_data(fdctrl, value);
572 break;
573 default:
574 break;
575 }
576 }
577
578 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
579 {
580 return fdctrl_read(opaque, reg & 7);
581 }
582
583 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
584 {
585 fdctrl_write(opaque, reg & 7, value);
586 }
587
588 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
589 {
590 return fdctrl_read(opaque, (uint32_t)reg);
591 }
592
593 static void fdctrl_write_mem (void *opaque,
594 target_phys_addr_t reg, uint32_t value)
595 {
596 fdctrl_write(opaque, (uint32_t)reg, value);
597 }
598
599 static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
600 fdctrl_read_mem,
601 fdctrl_read_mem,
602 fdctrl_read_mem,
603 };
604
605 static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
606 fdctrl_write_mem,
607 fdctrl_write_mem,
608 fdctrl_write_mem,
609 };
610
611 static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
612 fdctrl_read_mem,
613 NULL,
614 NULL,
615 };
616
617 static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
618 fdctrl_write_mem,
619 NULL,
620 NULL,
621 };
622
623 static void fd_save (QEMUFile *f, fdrive_t *fd)
624 {
625 qemu_put_8s(f, &fd->head);
626 qemu_put_8s(f, &fd->track);
627 qemu_put_8s(f, &fd->sect);
628 }
629
630 static void fdc_save (QEMUFile *f, void *opaque)
631 {
632 fdctrl_t *s = opaque;
633 uint8_t tmp;
634 int i;
635 uint8_t dor = s->dor | GET_CUR_DRV(s);
636
637 /* Controller state */
638 qemu_put_8s(f, &s->sra);
639 qemu_put_8s(f, &s->srb);
640 qemu_put_8s(f, &dor);
641 qemu_put_8s(f, &s->tdr);
642 qemu_put_8s(f, &s->dsr);
643 qemu_put_8s(f, &s->msr);
644 qemu_put_8s(f, &s->status0);
645 qemu_put_8s(f, &s->status1);
646 qemu_put_8s(f, &s->status2);
647 /* Command FIFO */
648 qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
649 qemu_put_be32s(f, &s->data_pos);
650 qemu_put_be32s(f, &s->data_len);
651 qemu_put_8s(f, &s->data_state);
652 qemu_put_8s(f, &s->data_dir);
653 qemu_put_8s(f, &s->eot);
654 /* States kept only to be returned back */
655 qemu_put_8s(f, &s->timer0);
656 qemu_put_8s(f, &s->timer1);
657 qemu_put_8s(f, &s->precomp_trk);
658 qemu_put_8s(f, &s->config);
659 qemu_put_8s(f, &s->lock);
660 qemu_put_8s(f, &s->pwrd);
661
662 tmp = MAX_FD;
663 qemu_put_8s(f, &tmp);
664 for (i = 0; i < MAX_FD; i++)
665 fd_save(f, &s->drives[i]);
666 }
667
668 static int fd_load (QEMUFile *f, fdrive_t *fd)
669 {
670 qemu_get_8s(f, &fd->head);
671 qemu_get_8s(f, &fd->track);
672 qemu_get_8s(f, &fd->sect);
673
674 return 0;
675 }
676
677 static int fdc_load (QEMUFile *f, void *opaque, int version_id)
678 {
679 fdctrl_t *s = opaque;
680 int i, ret = 0;
681 uint8_t n;
682
683 if (version_id != 2)
684 return -EINVAL;
685
686 /* Controller state */
687 qemu_get_8s(f, &s->sra);
688 qemu_get_8s(f, &s->srb);
689 qemu_get_8s(f, &s->dor);
690 SET_CUR_DRV(s, s->dor & FD_DOR_SELMASK);
691 s->dor &= ~FD_DOR_SELMASK;
692 qemu_get_8s(f, &s->tdr);
693 qemu_get_8s(f, &s->dsr);
694 qemu_get_8s(f, &s->msr);
695 qemu_get_8s(f, &s->status0);
696 qemu_get_8s(f, &s->status1);
697 qemu_get_8s(f, &s->status2);
698 /* Command FIFO */
699 qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
700 qemu_get_be32s(f, &s->data_pos);
701 qemu_get_be32s(f, &s->data_len);
702 qemu_get_8s(f, &s->data_state);
703 qemu_get_8s(f, &s->data_dir);
704 qemu_get_8s(f, &s->eot);
705 /* States kept only to be returned back */
706 qemu_get_8s(f, &s->timer0);
707 qemu_get_8s(f, &s->timer1);
708 qemu_get_8s(f, &s->precomp_trk);
709 qemu_get_8s(f, &s->config);
710 qemu_get_8s(f, &s->lock);
711 qemu_get_8s(f, &s->pwrd);
712 qemu_get_8s(f, &n);
713
714 if (n > MAX_FD)
715 return -EINVAL;
716
717 for (i = 0; i < n; i++) {
718 ret = fd_load(f, &s->drives[i]);
719 if (ret != 0)
720 break;
721 }
722
723 return ret;
724 }
725
726 static void fdctrl_external_reset(void *opaque)
727 {
728 fdctrl_t *s = opaque;
729
730 fdctrl_reset(s, 0);
731 }
732
733 static void fdctrl_handle_tc(void *opaque, int irq, int level)
734 {
735 //fdctrl_t *s = opaque;
736
737 if (level) {
738 // XXX
739 FLOPPY_DPRINTF("TC pulsed\n");
740 }
741 }
742
743 /* XXX: may change if moved to bdrv */
744 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
745 {
746 return fdctrl->drives[drive_num].drive;
747 }
748
749 /* Change IRQ state */
750 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
751 {
752 if (!(fdctrl->sra & FD_SRA_INTPEND))
753 return;
754 FLOPPY_DPRINTF("Reset interrupt\n");
755 qemu_set_irq(fdctrl->irq, 0);
756 fdctrl->sra &= ~FD_SRA_INTPEND;
757 }
758
759 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
760 {
761 /* Sparc mutation */
762 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
763 /* XXX: not sure */
764 fdctrl->msr &= ~FD_MSR_CMDBUSY;
765 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
766 fdctrl->status0 = status0;
767 return;
768 }
769 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
770 qemu_set_irq(fdctrl->irq, 1);
771 fdctrl->sra |= FD_SRA_INTPEND;
772 }
773 fdctrl->reset_sensei = 0;
774 fdctrl->status0 = status0;
775 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
776 }
777
778 /* Reset controller */
779 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
780 {
781 int i;
782
783 FLOPPY_DPRINTF("reset controller\n");
784 fdctrl_reset_irq(fdctrl);
785 /* Initialise controller */
786 fdctrl->sra = 0;
787 fdctrl->srb = 0xc0;
788 if (!fdctrl->drives[1].bs)
789 fdctrl->sra |= FD_SRA_nDRV2;
790 fdctrl->cur_drv = 0;
791 fdctrl->dor = FD_DOR_nRESET;
792 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
793 fdctrl->msr = FD_MSR_RQM;
794 /* FIFO state */
795 fdctrl->data_pos = 0;
796 fdctrl->data_len = 0;
797 fdctrl->data_state = 0;
798 fdctrl->data_dir = FD_DIR_WRITE;
799 for (i = 0; i < MAX_FD; i++)
800 fd_recalibrate(&fdctrl->drives[i]);
801 fdctrl_reset_fifo(fdctrl);
802 if (do_irq) {
803 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
804 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
805 }
806 }
807
808 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
809 {
810 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
811 }
812
813 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
814 {
815 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
816 return &fdctrl->drives[1];
817 else
818 return &fdctrl->drives[0];
819 }
820
821 #if MAX_FD == 4
822 static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
823 {
824 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
825 return &fdctrl->drives[2];
826 else
827 return &fdctrl->drives[1];
828 }
829
830 static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
831 {
832 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
833 return &fdctrl->drives[3];
834 else
835 return &fdctrl->drives[2];
836 }
837 #endif
838
839 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
840 {
841 switch (fdctrl->cur_drv) {
842 case 0: return drv0(fdctrl);
843 case 1: return drv1(fdctrl);
844 #if MAX_FD == 4
845 case 2: return drv2(fdctrl);
846 case 3: return drv3(fdctrl);
847 #endif
848 default: return NULL;
849 }
850 }
851
852 /* Status A register : 0x00 (read-only) */
853 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
854 {
855 uint32_t retval = fdctrl->sra;
856
857 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
858
859 return retval;
860 }
861
862 /* Status B register : 0x01 (read-only) */
863 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
864 {
865 uint32_t retval = fdctrl->srb;
866
867 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
868
869 return retval;
870 }
871
872 /* Digital output register : 0x02 */
873 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
874 {
875 uint32_t retval = fdctrl->dor;
876
877 /* Selected drive */
878 retval |= fdctrl->cur_drv;
879 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
880
881 return retval;
882 }
883
884 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
885 {
886 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
887
888 /* Motors */
889 if (value & FD_DOR_MOTEN0)
890 fdctrl->srb |= FD_SRB_MTR0;
891 else
892 fdctrl->srb &= ~FD_SRB_MTR0;
893 if (value & FD_DOR_MOTEN1)
894 fdctrl->srb |= FD_SRB_MTR1;
895 else
896 fdctrl->srb &= ~FD_SRB_MTR1;
897
898 /* Drive */
899 if (value & 1)
900 fdctrl->srb |= FD_SRB_DR0;
901 else
902 fdctrl->srb &= ~FD_SRB_DR0;
903
904 /* Reset */
905 if (!(value & FD_DOR_nRESET)) {
906 if (fdctrl->dor & FD_DOR_nRESET) {
907 FLOPPY_DPRINTF("controller enter RESET state\n");
908 }
909 } else {
910 if (!(fdctrl->dor & FD_DOR_nRESET)) {
911 FLOPPY_DPRINTF("controller out of RESET state\n");
912 fdctrl_reset(fdctrl, 1);
913 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
914 }
915 }
916 /* Selected drive */
917 fdctrl->cur_drv = value & FD_DOR_SELMASK;
918
919 fdctrl->dor = value;
920 }
921
922 /* Tape drive register : 0x03 */
923 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
924 {
925 uint32_t retval = fdctrl->tdr;
926
927 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
928
929 return retval;
930 }
931
932 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
933 {
934 /* Reset mode */
935 if (!(fdctrl->dor & FD_DOR_nRESET)) {
936 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
937 return;
938 }
939 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
940 /* Disk boot selection indicator */
941 fdctrl->tdr = value & FD_TDR_BOOTSEL;
942 /* Tape indicators: never allow */
943 }
944
945 /* Main status register : 0x04 (read) */
946 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
947 {
948 uint32_t retval = fdctrl->msr;
949
950 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
951 fdctrl->dor |= FD_DOR_nRESET;
952
953 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
954
955 return retval;
956 }
957
958 /* Data select rate register : 0x04 (write) */
959 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
960 {
961 /* Reset mode */
962 if (!(fdctrl->dor & FD_DOR_nRESET)) {
963 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
964 return;
965 }
966 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
967 /* Reset: autoclear */
968 if (value & FD_DSR_SWRESET) {
969 fdctrl->dor &= ~FD_DOR_nRESET;
970 fdctrl_reset(fdctrl, 1);
971 fdctrl->dor |= FD_DOR_nRESET;
972 }
973 if (value & FD_DSR_PWRDOWN) {
974 fdctrl_reset(fdctrl, 1);
975 }
976 fdctrl->dsr = value;
977 }
978
979 static int fdctrl_media_changed(fdrive_t *drv)
980 {
981 int ret;
982
983 if (!drv->bs)
984 return 0;
985 ret = bdrv_media_changed(drv->bs);
986 if (ret) {
987 fd_revalidate(drv);
988 }
989 return ret;
990 }
991
992 /* Digital input register : 0x07 (read-only) */
993 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
994 {
995 uint32_t retval = 0;
996
997 if (fdctrl_media_changed(drv0(fdctrl))
998 || fdctrl_media_changed(drv1(fdctrl))
999 #if MAX_FD == 4
1000 || fdctrl_media_changed(drv2(fdctrl))
1001 || fdctrl_media_changed(drv3(fdctrl))
1002 #endif
1003 )
1004 retval |= FD_DIR_DSKCHG;
1005 if (retval != 0)
1006 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1007
1008 return retval;
1009 }
1010
1011 /* FIFO state control */
1012 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
1013 {
1014 fdctrl->data_dir = FD_DIR_WRITE;
1015 fdctrl->data_pos = 0;
1016 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1017 }
1018
1019 /* Set FIFO status for the host to read */
1020 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1021 {
1022 fdctrl->data_dir = FD_DIR_READ;
1023 fdctrl->data_len = fifo_len;
1024 fdctrl->data_pos = 0;
1025 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1026 if (do_irq)
1027 fdctrl_raise_irq(fdctrl, 0x00);
1028 }
1029
1030 /* Set an error: unimplemented/unknown command */
1031 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1032 {
1033 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1034 fdctrl->fifo[0] = FD_SR0_INVCMD;
1035 fdctrl_set_fifo(fdctrl, 1, 0);
1036 }
1037
1038 /* Seek to next sector */
1039 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1040 {
1041 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1042 cur_drv->head, cur_drv->track, cur_drv->sect,
1043 fd_sector(cur_drv));
1044 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1045 error in fact */
1046 if (cur_drv->sect >= cur_drv->last_sect ||
1047 cur_drv->sect == fdctrl->eot) {
1048 cur_drv->sect = 1;
1049 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1050 if (cur_drv->head == 0 &&
1051 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1052 cur_drv->head = 1;
1053 } else {
1054 cur_drv->head = 0;
1055 cur_drv->track++;
1056 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1057 return 0;
1058 }
1059 } else {
1060 cur_drv->track++;
1061 return 0;
1062 }
1063 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1064 cur_drv->head, cur_drv->track,
1065 cur_drv->sect, fd_sector(cur_drv));
1066 } else {
1067 cur_drv->sect++;
1068 }
1069 return 1;
1070 }
1071
1072 /* Callback for transfer end (stop or abort) */
1073 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1074 uint8_t status1, uint8_t status2)
1075 {
1076 fdrive_t *cur_drv;
1077
1078 cur_drv = get_cur_drv(fdctrl);
1079 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1080 status0, status1, status2,
1081 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1082 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1083 fdctrl->fifo[1] = status1;
1084 fdctrl->fifo[2] = status2;
1085 fdctrl->fifo[3] = cur_drv->track;
1086 fdctrl->fifo[4] = cur_drv->head;
1087 fdctrl->fifo[5] = cur_drv->sect;
1088 fdctrl->fifo[6] = FD_SECTOR_SC;
1089 fdctrl->data_dir = FD_DIR_READ;
1090 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1091 DMA_release_DREQ(fdctrl->dma_chann);
1092 }
1093 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1094 fdctrl->msr &= ~FD_MSR_NONDMA;
1095 fdctrl_set_fifo(fdctrl, 7, 1);
1096 }
1097
1098 /* Prepare a data transfer (either DMA or FIFO) */
1099 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1100 {
1101 fdrive_t *cur_drv;
1102 uint8_t kh, kt, ks;
1103 int did_seek = 0;
1104
1105 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1106 cur_drv = get_cur_drv(fdctrl);
1107 kt = fdctrl->fifo[2];
1108 kh = fdctrl->fifo[3];
1109 ks = fdctrl->fifo[4];
1110 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1111 GET_CUR_DRV(fdctrl), kh, kt, ks,
1112 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1113 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1114 case 2:
1115 /* sect too big */
1116 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1117 fdctrl->fifo[3] = kt;
1118 fdctrl->fifo[4] = kh;
1119 fdctrl->fifo[5] = ks;
1120 return;
1121 case 3:
1122 /* track too big */
1123 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1124 fdctrl->fifo[3] = kt;
1125 fdctrl->fifo[4] = kh;
1126 fdctrl->fifo[5] = ks;
1127 return;
1128 case 4:
1129 /* No seek enabled */
1130 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1131 fdctrl->fifo[3] = kt;
1132 fdctrl->fifo[4] = kh;
1133 fdctrl->fifo[5] = ks;
1134 return;
1135 case 1:
1136 did_seek = 1;
1137 break;
1138 default:
1139 break;
1140 }
1141
1142 /* Set the FIFO state */
1143 fdctrl->data_dir = direction;
1144 fdctrl->data_pos = 0;
1145 fdctrl->msr |= FD_MSR_CMDBUSY;
1146 if (fdctrl->fifo[0] & 0x80)
1147 fdctrl->data_state |= FD_STATE_MULTI;
1148 else
1149 fdctrl->data_state &= ~FD_STATE_MULTI;
1150 if (did_seek)
1151 fdctrl->data_state |= FD_STATE_SEEK;
1152 else
1153 fdctrl->data_state &= ~FD_STATE_SEEK;
1154 if (fdctrl->fifo[5] == 00) {
1155 fdctrl->data_len = fdctrl->fifo[8];
1156 } else {
1157 int tmp;
1158 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1159 tmp = (fdctrl->fifo[6] - ks + 1);
1160 if (fdctrl->fifo[0] & 0x80)
1161 tmp += fdctrl->fifo[6];
1162 fdctrl->data_len *= tmp;
1163 }
1164 fdctrl->eot = fdctrl->fifo[6];
1165 if (fdctrl->dor & FD_DOR_DMAEN) {
1166 int dma_mode;
1167 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1168 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1169 dma_mode = (dma_mode >> 2) & 3;
1170 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1171 dma_mode, direction,
1172 (128 << fdctrl->fifo[5]) *
1173 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1174 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1175 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1176 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1177 (direction == FD_DIR_READ && dma_mode == 1)) {
1178 /* No access is allowed until DMA transfer has completed */
1179 fdctrl->msr &= ~FD_MSR_RQM;
1180 /* Now, we just have to wait for the DMA controller to
1181 * recall us...
1182 */
1183 DMA_hold_DREQ(fdctrl->dma_chann);
1184 DMA_schedule(fdctrl->dma_chann);
1185 return;
1186 } else {
1187 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1188 }
1189 }
1190 FLOPPY_DPRINTF("start non-DMA transfer\n");
1191 fdctrl->msr |= FD_MSR_NONDMA;
1192 if (direction != FD_DIR_WRITE)
1193 fdctrl->msr |= FD_MSR_DIO;
1194 /* IO based transfer: calculate len */
1195 fdctrl_raise_irq(fdctrl, 0x00);
1196
1197 return;
1198 }
1199
1200 /* Prepare a transfer of deleted data */
1201 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1202 {
1203 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1204
1205 /* We don't handle deleted data,
1206 * so we don't return *ANYTHING*
1207 */
1208 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1209 }
1210
1211 /* handlers for DMA transfers */
1212 static int fdctrl_transfer_handler (void *opaque, int nchan,
1213 int dma_pos, int dma_len)
1214 {
1215 fdctrl_t *fdctrl;
1216 fdrive_t *cur_drv;
1217 int len, start_pos, rel_pos;
1218 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1219
1220 fdctrl = opaque;
1221 if (fdctrl->msr & FD_MSR_RQM) {
1222 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1223 return 0;
1224 }
1225 cur_drv = get_cur_drv(fdctrl);
1226 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1227 fdctrl->data_dir == FD_DIR_SCANH)
1228 status2 = FD_SR2_SNS;
1229 if (dma_len > fdctrl->data_len)
1230 dma_len = fdctrl->data_len;
1231 if (cur_drv->bs == NULL) {
1232 if (fdctrl->data_dir == FD_DIR_WRITE)
1233 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1234 else
1235 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1236 len = 0;
1237 goto transfer_error;
1238 }
1239 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1240 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1241 len = dma_len - fdctrl->data_pos;
1242 if (len + rel_pos > FD_SECTOR_LEN)
1243 len = FD_SECTOR_LEN - rel_pos;
1244 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1245 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1246 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1247 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1248 fd_sector(cur_drv) * FD_SECTOR_LEN);
1249 if (fdctrl->data_dir != FD_DIR_WRITE ||
1250 len < FD_SECTOR_LEN || rel_pos != 0) {
1251 /* READ & SCAN commands and realign to a sector for WRITE */
1252 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1253 fdctrl->fifo, 1) < 0) {
1254 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1255 fd_sector(cur_drv));
1256 /* Sure, image size is too small... */
1257 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1258 }
1259 }
1260 switch (fdctrl->data_dir) {
1261 case FD_DIR_READ:
1262 /* READ commands */
1263 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1264 fdctrl->data_pos, len);
1265 break;
1266 case FD_DIR_WRITE:
1267 /* WRITE commands */
1268 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1269 fdctrl->data_pos, len);
1270 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1271 fdctrl->fifo, 1) < 0) {
1272 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1273 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1274 goto transfer_error;
1275 }
1276 break;
1277 default:
1278 /* SCAN commands */
1279 {
1280 uint8_t tmpbuf[FD_SECTOR_LEN];
1281 int ret;
1282 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1283 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1284 if (ret == 0) {
1285 status2 = FD_SR2_SEH;
1286 goto end_transfer;
1287 }
1288 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1289 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1290 status2 = 0x00;
1291 goto end_transfer;
1292 }
1293 }
1294 break;
1295 }
1296 fdctrl->data_pos += len;
1297 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1298 if (rel_pos == 0) {
1299 /* Seek to next sector */
1300 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1301 break;
1302 }
1303 }
1304 end_transfer:
1305 len = fdctrl->data_pos - start_pos;
1306 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1307 fdctrl->data_pos, len, fdctrl->data_len);
1308 if (fdctrl->data_dir == FD_DIR_SCANE ||
1309 fdctrl->data_dir == FD_DIR_SCANL ||
1310 fdctrl->data_dir == FD_DIR_SCANH)
1311 status2 = FD_SR2_SEH;
1312 if (FD_DID_SEEK(fdctrl->data_state))
1313 status0 |= FD_SR0_SEEK;
1314 fdctrl->data_len -= len;
1315 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1316 transfer_error:
1317
1318 return len;
1319 }
1320
1321 /* Data register : 0x05 */
1322 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1323 {
1324 fdrive_t *cur_drv;
1325 uint32_t retval = 0;
1326 int pos;
1327
1328 cur_drv = get_cur_drv(fdctrl);
1329 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1330 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1331 FLOPPY_ERROR("controller not ready for reading\n");
1332 return 0;
1333 }
1334 pos = fdctrl->data_pos;
1335 if (fdctrl->msr & FD_MSR_NONDMA) {
1336 pos %= FD_SECTOR_LEN;
1337 if (pos == 0) {
1338 if (fdctrl->data_pos != 0)
1339 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1340 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1341 fd_sector(cur_drv));
1342 return 0;
1343 }
1344 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1345 FLOPPY_DPRINTF("error getting sector %d\n",
1346 fd_sector(cur_drv));
1347 /* Sure, image size is too small... */
1348 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1349 }
1350 }
1351 }
1352 retval = fdctrl->fifo[pos];
1353 if (++fdctrl->data_pos == fdctrl->data_len) {
1354 fdctrl->data_pos = 0;
1355 /* Switch from transfer mode to status mode
1356 * then from status mode to command mode
1357 */
1358 if (fdctrl->msr & FD_MSR_NONDMA) {
1359 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1360 } else {
1361 fdctrl_reset_fifo(fdctrl);
1362 fdctrl_reset_irq(fdctrl);
1363 }
1364 }
1365 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1366
1367 return retval;
1368 }
1369
1370 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1371 {
1372 fdrive_t *cur_drv;
1373 uint8_t kh, kt, ks;
1374
1375 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1376 cur_drv = get_cur_drv(fdctrl);
1377 kt = fdctrl->fifo[6];
1378 kh = fdctrl->fifo[7];
1379 ks = fdctrl->fifo[8];
1380 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1381 GET_CUR_DRV(fdctrl), kh, kt, ks,
1382 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1383 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1384 case 2:
1385 /* sect too big */
1386 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1387 fdctrl->fifo[3] = kt;
1388 fdctrl->fifo[4] = kh;
1389 fdctrl->fifo[5] = ks;
1390 return;
1391 case 3:
1392 /* track too big */
1393 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1394 fdctrl->fifo[3] = kt;
1395 fdctrl->fifo[4] = kh;
1396 fdctrl->fifo[5] = ks;
1397 return;
1398 case 4:
1399 /* No seek enabled */
1400 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1401 fdctrl->fifo[3] = kt;
1402 fdctrl->fifo[4] = kh;
1403 fdctrl->fifo[5] = ks;
1404 return;
1405 case 1:
1406 fdctrl->data_state |= FD_STATE_SEEK;
1407 break;
1408 default:
1409 break;
1410 }
1411 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1412 if (cur_drv->bs == NULL ||
1413 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1414 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1415 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1416 } else {
1417 if (cur_drv->sect == cur_drv->last_sect) {
1418 fdctrl->data_state &= ~FD_STATE_FORMAT;
1419 /* Last sector done */
1420 if (FD_DID_SEEK(fdctrl->data_state))
1421 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1422 else
1423 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1424 } else {
1425 /* More to do */
1426 fdctrl->data_pos = 0;
1427 fdctrl->data_len = 4;
1428 }
1429 }
1430 }
1431
1432 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1433 {
1434 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1435 fdctrl->fifo[0] = fdctrl->lock << 4;
1436 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1437 }
1438
1439 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1440 {
1441 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1442
1443 /* Drives position */
1444 fdctrl->fifo[0] = drv0(fdctrl)->track;
1445 fdctrl->fifo[1] = drv1(fdctrl)->track;
1446 #if MAX_FD == 4
1447 fdctrl->fifo[2] = drv2(fdctrl)->track;
1448 fdctrl->fifo[3] = drv3(fdctrl)->track;
1449 #else
1450 fdctrl->fifo[2] = 0;
1451 fdctrl->fifo[3] = 0;
1452 #endif
1453 /* timers */
1454 fdctrl->fifo[4] = fdctrl->timer0;
1455 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1456 fdctrl->fifo[6] = cur_drv->last_sect;
1457 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1458 (cur_drv->perpendicular << 2);
1459 fdctrl->fifo[8] = fdctrl->config;
1460 fdctrl->fifo[9] = fdctrl->precomp_trk;
1461 fdctrl_set_fifo(fdctrl, 10, 0);
1462 }
1463
1464 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1465 {
1466 /* Controller's version */
1467 fdctrl->fifo[0] = fdctrl->version;
1468 fdctrl_set_fifo(fdctrl, 1, 1);
1469 }
1470
1471 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1472 {
1473 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1474 fdctrl_set_fifo(fdctrl, 1, 0);
1475 }
1476
1477 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1478 {
1479 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1480
1481 /* Drives position */
1482 drv0(fdctrl)->track = fdctrl->fifo[3];
1483 drv1(fdctrl)->track = fdctrl->fifo[4];
1484 #if MAX_FD == 4
1485 drv2(fdctrl)->track = fdctrl->fifo[5];
1486 drv3(fdctrl)->track = fdctrl->fifo[6];
1487 #endif
1488 /* timers */
1489 fdctrl->timer0 = fdctrl->fifo[7];
1490 fdctrl->timer1 = fdctrl->fifo[8];
1491 cur_drv->last_sect = fdctrl->fifo[9];
1492 fdctrl->lock = fdctrl->fifo[10] >> 7;
1493 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1494 fdctrl->config = fdctrl->fifo[11];
1495 fdctrl->precomp_trk = fdctrl->fifo[12];
1496 fdctrl->pwrd = fdctrl->fifo[13];
1497 fdctrl_reset_fifo(fdctrl);
1498 }
1499
1500 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1501 {
1502 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1503
1504 fdctrl->fifo[0] = 0;
1505 fdctrl->fifo[1] = 0;
1506 /* Drives position */
1507 fdctrl->fifo[2] = drv0(fdctrl)->track;
1508 fdctrl->fifo[3] = drv1(fdctrl)->track;
1509 #if MAX_FD == 4
1510 fdctrl->fifo[4] = drv2(fdctrl)->track;
1511 fdctrl->fifo[5] = drv3(fdctrl)->track;
1512 #else
1513 fdctrl->fifo[4] = 0;
1514 fdctrl->fifo[5] = 0;
1515 #endif
1516 /* timers */
1517 fdctrl->fifo[6] = fdctrl->timer0;
1518 fdctrl->fifo[7] = fdctrl->timer1;
1519 fdctrl->fifo[8] = cur_drv->last_sect;
1520 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1521 (cur_drv->perpendicular << 2);
1522 fdctrl->fifo[10] = fdctrl->config;
1523 fdctrl->fifo[11] = fdctrl->precomp_trk;
1524 fdctrl->fifo[12] = fdctrl->pwrd;
1525 fdctrl->fifo[13] = 0;
1526 fdctrl->fifo[14] = 0;
1527 fdctrl_set_fifo(fdctrl, 15, 1);
1528 }
1529
1530 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1531 {
1532 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1533
1534 /* XXX: should set main status register to busy */
1535 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1536 qemu_mod_timer(fdctrl->result_timer,
1537 qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
1538 }
1539
1540 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1541 {
1542 fdrive_t *cur_drv;
1543
1544 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1545 cur_drv = get_cur_drv(fdctrl);
1546 fdctrl->data_state |= FD_STATE_FORMAT;
1547 if (fdctrl->fifo[0] & 0x80)
1548 fdctrl->data_state |= FD_STATE_MULTI;
1549 else
1550 fdctrl->data_state &= ~FD_STATE_MULTI;
1551 fdctrl->data_state &= ~FD_STATE_SEEK;
1552 cur_drv->bps =
1553 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1554 #if 0
1555 cur_drv->last_sect =
1556 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1557 fdctrl->fifo[3] / 2;
1558 #else
1559 cur_drv->last_sect = fdctrl->fifo[3];
1560 #endif
1561 /* TODO: implement format using DMA expected by the Bochs BIOS
1562 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1563 * the sector with the specified fill byte
1564 */
1565 fdctrl->data_state &= ~FD_STATE_FORMAT;
1566 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1567 }
1568
1569 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1570 {
1571 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1572 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1573 if (fdctrl->fifo[2] & 1)
1574 fdctrl->dor &= ~FD_DOR_DMAEN;
1575 else
1576 fdctrl->dor |= FD_DOR_DMAEN;
1577 /* No result back */
1578 fdctrl_reset_fifo(fdctrl);
1579 }
1580
1581 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1582 {
1583 fdrive_t *cur_drv;
1584
1585 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1586 cur_drv = get_cur_drv(fdctrl);
1587 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1588 /* 1 Byte status back */
1589 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1590 (cur_drv->track == 0 ? 0x10 : 0x00) |
1591 (cur_drv->head << 2) |
1592 GET_CUR_DRV(fdctrl) |
1593 0x28;
1594 fdctrl_set_fifo(fdctrl, 1, 0);
1595 }
1596
1597 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1598 {
1599 fdrive_t *cur_drv;
1600
1601 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1602 cur_drv = get_cur_drv(fdctrl);
1603 fd_recalibrate(cur_drv);
1604 fdctrl_reset_fifo(fdctrl);
1605 /* Raise Interrupt */
1606 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1607 }
1608
1609 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1610 {
1611 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1612
1613 if(fdctrl->reset_sensei > 0) {
1614 fdctrl->fifo[0] =
1615 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1616 fdctrl->reset_sensei--;
1617 } else {
1618 /* XXX: status0 handling is broken for read/write
1619 commands, so we do this hack. It should be suppressed
1620 ASAP */
1621 fdctrl->fifo[0] =
1622 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1623 }
1624
1625 fdctrl->fifo[1] = cur_drv->track;
1626 fdctrl_set_fifo(fdctrl, 2, 0);
1627 fdctrl_reset_irq(fdctrl);
1628 fdctrl->status0 = FD_SR0_RDYCHG;
1629 }
1630
1631 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1632 {
1633 fdrive_t *cur_drv;
1634
1635 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1636 cur_drv = get_cur_drv(fdctrl);
1637 fdctrl_reset_fifo(fdctrl);
1638 if (fdctrl->fifo[2] > cur_drv->max_track) {
1639 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1640 } else {
1641 cur_drv->track = fdctrl->fifo[2];
1642 /* Raise Interrupt */
1643 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1644 }
1645 }
1646
1647 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1648 {
1649 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1650
1651 if (fdctrl->fifo[1] & 0x80)
1652 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1653 /* No result back */
1654 fdctrl_reset_fifo(fdctrl);
1655 }
1656
1657 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1658 {
1659 fdctrl->config = fdctrl->fifo[2];
1660 fdctrl->precomp_trk = fdctrl->fifo[3];
1661 /* No result back */
1662 fdctrl_reset_fifo(fdctrl);
1663 }
1664
1665 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1666 {
1667 fdctrl->pwrd = fdctrl->fifo[1];
1668 fdctrl->fifo[0] = fdctrl->fifo[1];
1669 fdctrl_set_fifo(fdctrl, 1, 1);
1670 }
1671
1672 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1673 {
1674 /* No result back */
1675 fdctrl_reset_fifo(fdctrl);
1676 }
1677
1678 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1679 {
1680 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1681
1682 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1683 /* Command parameters done */
1684 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1685 fdctrl->fifo[0] = fdctrl->fifo[1];
1686 fdctrl->fifo[2] = 0;
1687 fdctrl->fifo[3] = 0;
1688 fdctrl_set_fifo(fdctrl, 4, 1);
1689 } else {
1690 fdctrl_reset_fifo(fdctrl);
1691 }
1692 } else if (fdctrl->data_len > 7) {
1693 /* ERROR */
1694 fdctrl->fifo[0] = 0x80 |
1695 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1696 fdctrl_set_fifo(fdctrl, 1, 1);
1697 }
1698 }
1699
1700 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1701 {
1702 fdrive_t *cur_drv;
1703
1704 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1705 cur_drv = get_cur_drv(fdctrl);
1706 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1707 cur_drv->track = cur_drv->max_track - 1;
1708 } else {
1709 cur_drv->track += fdctrl->fifo[2];
1710 }
1711 fdctrl_reset_fifo(fdctrl);
1712 /* Raise Interrupt */
1713 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1714 }
1715
1716 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1717 {
1718 fdrive_t *cur_drv;
1719
1720 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1721 cur_drv = get_cur_drv(fdctrl);
1722 if (fdctrl->fifo[2] > cur_drv->track) {
1723 cur_drv->track = 0;
1724 } else {
1725 cur_drv->track -= fdctrl->fifo[2];
1726 }
1727 fdctrl_reset_fifo(fdctrl);
1728 /* Raise Interrupt */
1729 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1730 }
1731
1732 static const struct {
1733 uint8_t value;
1734 uint8_t mask;
1735 const char* name;
1736 int parameters;
1737 void (*handler)(fdctrl_t *fdctrl, int direction);
1738 int direction;
1739 } handlers[] = {
1740 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1741 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1742 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1743 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1744 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1745 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1746 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1747 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1748 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1749 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1750 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1751 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1752 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1753 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1754 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1755 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1756 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1757 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1758 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1759 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1760 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1761 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1762 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1763 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1764 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1765 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1766 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1767 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1768 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1769 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1770 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1771 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1772 };
1773 /* Associate command to an index in the 'handlers' array */
1774 static uint8_t command_to_handler[256];
1775
1776 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1777 {
1778 fdrive_t *cur_drv;
1779 int pos;
1780
1781 /* Reset mode */
1782 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1783 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1784 return;
1785 }
1786 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1787 FLOPPY_ERROR("controller not ready for writing\n");
1788 return;
1789 }
1790 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1791 /* Is it write command time ? */
1792 if (fdctrl->msr & FD_MSR_NONDMA) {
1793 /* FIFO data write */
1794 pos = fdctrl->data_pos++;
1795 pos %= FD_SECTOR_LEN;
1796 fdctrl->fifo[pos] = value;
1797 if (pos == FD_SECTOR_LEN - 1 ||
1798 fdctrl->data_pos == fdctrl->data_len) {
1799 cur_drv = get_cur_drv(fdctrl);
1800 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1801 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1802 return;
1803 }
1804 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1805 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1806 fd_sector(cur_drv));
1807 return;
1808 }
1809 }
1810 /* Switch from transfer mode to status mode
1811 * then from status mode to command mode
1812 */
1813 if (fdctrl->data_pos == fdctrl->data_len)
1814 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1815 return;
1816 }
1817 if (fdctrl->data_pos == 0) {
1818 /* Command */
1819 pos = command_to_handler[value & 0xff];
1820 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1821 fdctrl->data_len = handlers[pos].parameters + 1;
1822 }
1823
1824 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1825 fdctrl->fifo[fdctrl->data_pos++] = value;
1826 if (fdctrl->data_pos == fdctrl->data_len) {
1827 /* We now have all parameters
1828 * and will be able to treat the command
1829 */
1830 if (fdctrl->data_state & FD_STATE_FORMAT) {
1831 fdctrl_format_sector(fdctrl);
1832 return;
1833 }
1834
1835 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1836 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1837 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1838 }
1839 }
1840
1841 static void fdctrl_result_timer(void *opaque)
1842 {
1843 fdctrl_t *fdctrl = opaque;
1844 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1845
1846 /* Pretend we are spinning.
1847 * This is needed for Coherent, which uses READ ID to check for
1848 * sector interleaving.
1849 */
1850 if (cur_drv->last_sect != 0) {
1851 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1852 }
1853 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1854 }
1855
1856 /* Init functions */
1857 static void fdctrl_init_common (fdctrl_t *fdctrl, int dma_chann,
1858 target_phys_addr_t io_base,
1859 BlockDriverState **fds)
1860 {
1861 int i, j;
1862
1863 /* Fill 'command_to_handler' lookup table */
1864 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1865 for (j = 0; j < sizeof(command_to_handler); j++) {
1866 if ((j & handlers[i].mask) == handlers[i].value)
1867 command_to_handler[j] = i;
1868 }
1869 }
1870
1871 FLOPPY_DPRINTF("init controller\n");
1872 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1873 fdctrl->result_timer = qemu_new_timer(vm_clock,
1874 fdctrl_result_timer, fdctrl);
1875
1876 fdctrl->version = 0x90; /* Intel 82078 controller */
1877 fdctrl->dma_chann = dma_chann;
1878 fdctrl->io_base = io_base;
1879 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1880 if (fdctrl->dma_chann != -1) {
1881 DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1882 }
1883 for (i = 0; i < MAX_FD; i++) {
1884 fd_init(&fdctrl->drives[i], fds[i]);
1885 }
1886 fdctrl_external_reset(fdctrl);
1887 register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
1888 qemu_register_reset(fdctrl_external_reset, fdctrl);
1889 for (i = 0; i < MAX_FD; i++) {
1890 fd_revalidate(&fdctrl->drives[i]);
1891 }
1892 }
1893
1894 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1895 target_phys_addr_t io_base,
1896 BlockDriverState **fds)
1897 {
1898 DeviceState *dev;
1899 SysBusDevice *s;
1900 fdctrl_t *fdctrl;
1901
1902 dev = qdev_create(NULL, "fdc");
1903 qdev_prop_set_uint32(dev, "strict_io", 0);
1904 qdev_prop_set_uint32(dev, "mem_mapped", mem_mapped);
1905 qdev_prop_set_uint32(dev, "sun4m", 0);
1906 qdev_init(dev);
1907 s = sysbus_from_qdev(dev);
1908 sysbus_connect_irq(s, 0, irq);
1909 fdctrl = FROM_SYSBUS(fdctrl_t, s);
1910 if (mem_mapped) {
1911 sysbus_mmio_map(s, 0, io_base);
1912 } else {
1913 register_ioport_read((uint32_t)io_base + 0x01, 5, 1,
1914 &fdctrl_read_port, fdctrl);
1915 register_ioport_read((uint32_t)io_base + 0x07, 1, 1,
1916 &fdctrl_read_port, fdctrl);
1917 register_ioport_write((uint32_t)io_base + 0x01, 5, 1,
1918 &fdctrl_write_port, fdctrl);
1919 register_ioport_write((uint32_t)io_base + 0x07, 1, 1,
1920 &fdctrl_write_port, fdctrl);
1921 }
1922
1923 fdctrl_init_common(fdctrl, dma_chann, io_base, fds);
1924
1925 return fdctrl;
1926 }
1927
1928 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1929 BlockDriverState **fds, qemu_irq *fdc_tc)
1930 {
1931 DeviceState *dev;
1932 SysBusDevice *s;
1933 fdctrl_t *fdctrl;
1934
1935 dev = qdev_create(NULL, "fdc");
1936 qdev_prop_set_uint32(dev, "strict_io", 1);
1937 qdev_prop_set_uint32(dev, "mem_mapped", 1);
1938 qdev_prop_set_uint32(dev, "sun4m", 1);
1939 qdev_init(dev);
1940 s = sysbus_from_qdev(dev);
1941 sysbus_connect_irq(s, 0, irq);
1942 sysbus_mmio_map(s, 0, io_base);
1943 *fdc_tc = qdev_get_gpio_in(dev, 0);
1944
1945 fdctrl = FROM_SYSBUS(fdctrl_t, s);
1946 fdctrl_init_common(fdctrl, -1, io_base, fds);
1947
1948 return fdctrl;
1949 }
1950
1951 static void fdc_init1(SysBusDevice *dev)
1952 {
1953 fdctrl_t *s = FROM_SYSBUS(fdctrl_t, dev);
1954 int io;
1955
1956 sysbus_init_irq(dev, &s->irq);
1957 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1958 if (s->strict_io) {
1959 io = cpu_register_io_memory(fdctrl_mem_read_strict,
1960 fdctrl_mem_write_strict, s);
1961 } else {
1962 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, s);
1963 }
1964 sysbus_init_mmio(dev, 0x08, io);
1965 }
1966
1967
1968 static SysBusDeviceInfo fdc_info = {
1969 .init = fdc_init1,
1970 .qdev.name = "fdc",
1971 .qdev.size = sizeof(fdctrl_t),
1972 .qdev.props = (Property[]) {
1973 {
1974 .name = "io_base",
1975 .info = &qdev_prop_uint32,
1976 .offset = offsetof(fdctrl_t, io_base),
1977 },
1978 {
1979 .name = "strict_io",
1980 .info = &qdev_prop_uint32,
1981 .offset = offsetof(fdctrl_t, strict_io),
1982 },
1983 {
1984 .name = "mem_mapped",
1985 .info = &qdev_prop_uint32,
1986 .offset = offsetof(fdctrl_t, mem_mapped),
1987 },
1988 {
1989 .name = "sun4m",
1990 .info = &qdev_prop_uint32,
1991 .offset = offsetof(fdctrl_t, sun4m),
1992 },
1993 {/* end of properties */}
1994 }
1995 };
1996
1997 static void fdc_register_devices(void)
1998 {
1999 sysbus_register_withprop(&fdc_info);
2000 }
2001
2002 device_init(fdc_register_devices)
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