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Sync ia64 instruction cache after DMA memory access
[qemu-kvm/fedora.git] / cpu-exec.c
blob2cfefbfabc75a9275717d2b346e985605d354c00
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 #ifdef USE_KVM
39 #include "qemu-kvm.h"
40 extern int kvm_allowed;
41 #endif
42
43 int tb_invalidated_flag;
44
45 //#define DEBUG_EXEC
46 //#define DEBUG_SIGNAL
47
48 void cpu_loop_exit(void)
49 {
50 /* NOTE: the register at this point must be saved by hand because
51 longjmp restore them */
52 regs_to_env();
53 longjmp(env->jmp_env, 1);
54 }
55
56 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
57 #define reg_T2
58 #endif
59
60 /* exit the current TB from a signal handler. The host registers are
61 restored in a state compatible with the CPU emulator
62 */
63 void cpu_resume_from_signal(CPUState *env1, void *puc)
64 {
65 #if !defined(CONFIG_SOFTMMU)
66 struct ucontext *uc = puc;
67 #endif
68
69 env = env1;
70
71 /* XXX: restore cpu registers saved in host registers */
72
73 #if !defined(CONFIG_SOFTMMU)
74 if (puc) {
75 /* XXX: use siglongjmp ? */
76 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
77 }
78 #endif
79 longjmp(env->jmp_env, 1);
80 }
81
82
83 static TranslationBlock *tb_find_slow(target_ulong pc,
84 target_ulong cs_base,
85 uint64_t flags)
86 {
87 TranslationBlock *tb, **ptb1;
88 int code_gen_size;
89 unsigned int h;
90 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
91 uint8_t *tc_ptr;
92
93 spin_lock(&tb_lock);
94
95 tb_invalidated_flag = 0;
96
97 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
98
99 /* find translated block using physical mappings */
100 phys_pc = get_phys_addr_code(env, pc);
101 phys_page1 = phys_pc & TARGET_PAGE_MASK;
102 phys_page2 = -1;
103 h = tb_phys_hash_func(phys_pc);
104 ptb1 = &tb_phys_hash[h];
105 for(;;) {
106 tb = *ptb1;
107 if (!tb)
108 goto not_found;
109 if (tb->pc == pc &&
110 tb->page_addr[0] == phys_page1 &&
111 tb->cs_base == cs_base &&
112 tb->flags == flags) {
113 /* check next page if needed */
114 if (tb->page_addr[1] != -1) {
115 virt_page2 = (pc & TARGET_PAGE_MASK) +
116 TARGET_PAGE_SIZE;
117 phys_page2 = get_phys_addr_code(env, virt_page2);
118 if (tb->page_addr[1] == phys_page2)
119 goto found;
120 } else {
121 goto found;
122 }
123 }
124 ptb1 = &tb->phys_hash_next;
125 }
126 not_found:
127 /* if no translated code available, then translate it now */
128 tb = tb_alloc(pc);
129 if (!tb) {
130 /* flush must be done */
131 tb_flush(env);
132 /* cannot fail at this point */
133 tb = tb_alloc(pc);
134 /* don't forget to invalidate previous TB info */
135 tb_invalidated_flag = 1;
136 }
137 tc_ptr = code_gen_ptr;
138 tb->tc_ptr = tc_ptr;
139 tb->cs_base = cs_base;
140 tb->flags = flags;
141 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
142 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
143
144 /* check next page if needed */
145 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
146 phys_page2 = -1;
147 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
148 phys_page2 = get_phys_addr_code(env, virt_page2);
149 }
150 tb_link_phys(tb, phys_pc, phys_page2);
151
152 found:
153 /* we add the TB in the virtual pc hash table */
154 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
155 spin_unlock(&tb_lock);
156 return tb;
157 }
158
159 static inline TranslationBlock *tb_find_fast(void)
160 {
161 TranslationBlock *tb;
162 target_ulong cs_base, pc;
163 uint64_t flags;
164
165 /* we record a subset of the CPU state. It will
166 always be the same before a given translated block
167 is executed. */
168 #if defined(TARGET_I386)
169 flags = env->hflags;
170 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
171 flags |= env->intercept;
172 cs_base = env->segs[R_CS].base;
173 pc = cs_base + env->eip;
174 #elif defined(TARGET_ARM)
175 flags = env->thumb | (env->vfp.vec_len << 1)
176 | (env->vfp.vec_stride << 4);
177 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
178 flags |= (1 << 6);
179 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
180 flags |= (1 << 7);
181 cs_base = 0;
182 pc = env->regs[15];
183 #elif defined(TARGET_SPARC)
184 #ifdef TARGET_SPARC64
185 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
186 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
187 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
188 #else
189 // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor
190 flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3)
191 | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
192 | env->psrs;
193 #endif
194 cs_base = env->npc;
195 pc = env->pc;
196 #elif defined(TARGET_PPC)
197 flags = env->hflags;
198 cs_base = 0;
199 pc = env->nip;
200 #elif defined(TARGET_MIPS)
201 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
202 cs_base = 0;
203 pc = env->PC[env->current_tc];
204 #elif defined(TARGET_M68K)
205 flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
206 | (env->sr & SR_S) /* Bit 13 */
207 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
208 cs_base = 0;
209 pc = env->pc;
210 #elif defined(TARGET_SH4)
211 flags = env->sr & (SR_MD | SR_RB);
212 cs_base = 0; /* XXXXX */
213 pc = env->pc;
214 #elif defined(TARGET_ALPHA)
215 flags = env->ps;
216 cs_base = 0;
217 pc = env->pc;
218 #elif defined(TARGET_IA64)
219 flags = 0;
220 cs_base = 0; /* XXXXX */
221 pc = 0;
222 #else
223 #error unsupported CPU
224 #endif
225 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
226 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
227 tb->flags != flags, 0)) {
228 tb = tb_find_slow(pc, cs_base, flags);
229 /* Note: we do it here to avoid a gcc bug on Mac OS X when
230 doing it in tb_find_slow */
231 if (tb_invalidated_flag) {
232 /* as some TB could have been invalidated because
233 of memory exceptions while generating the code, we
234 must recompute the hash index here */
235 T0 = 0;
236 }
237 }
238 return tb;
239 }
240
241
242 /* main execution loop */
243
244 int cpu_exec(CPUState *env1)
245 {
246 #define DECLARE_HOST_REGS 1
247 #include "hostregs_helper.h"
248 #if defined(TARGET_SPARC)
249 #if defined(reg_REGWPTR)
250 uint32_t *saved_regwptr;
251 #endif
252 #endif
253 #if defined(__sparc__) && !defined(HOST_SOLARIS)
254 int saved_i7;
255 target_ulong tmp_T0;
256 #endif
257 int ret, interrupt_request;
258 void (*gen_func)(void);
259 TranslationBlock *tb;
260 uint8_t *tc_ptr;
261
262 if (cpu_halted(env1) == EXCP_HALTED)
263 return EXCP_HALTED;
264
265 cpu_single_env = env1;
266
267 /* first we save global registers */
268 #define SAVE_HOST_REGS 1
269 #include "hostregs_helper.h"
270 env = env1;
271 #if defined(__sparc__) && !defined(HOST_SOLARIS)
272 /* we also save i7 because longjmp may not restore it */
273 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
274 #endif
275
276 env_to_regs();
277 #if defined(TARGET_I386)
278 /* put eflags in CPU temporary format */
279 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
280 DF = 1 - (2 * ((env->eflags >> 10) & 1));
281 CC_OP = CC_OP_EFLAGS;
282 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
283 #elif defined(TARGET_SPARC)
284 #if defined(reg_REGWPTR)
285 saved_regwptr = REGWPTR;
286 #endif
287 #elif defined(TARGET_M68K)
288 env->cc_op = CC_OP_FLAGS;
289 env->cc_dest = env->sr & 0xf;
290 env->cc_x = (env->sr >> 4) & 1;
291 #elif defined(TARGET_ALPHA)
292 #elif defined(TARGET_ARM)
293 #elif defined(TARGET_PPC)
294 #elif defined(TARGET_MIPS)
295 #elif defined(TARGET_SH4)
296 #elif defined(TARGET_IA64)
297 /* XXXXX */
298 #else
299 #error unsupported target CPU
300 #endif
301 env->exception_index = -1;
302
303 /* prepare setjmp context for exception handling */
304 for(;;) {
305 if (setjmp(env->jmp_env) == 0) {
306 env->current_tb = NULL;
307 /* if an exception is pending, we execute it here */
308 if (env->exception_index >= 0) {
309 if (env->exception_index >= EXCP_INTERRUPT) {
310 /* exit request from the cpu execution loop */
311 ret = env->exception_index;
312 break;
313 } else if (env->user_mode_only) {
314 /* if user mode only, we simulate a fake exception
315 which will be handled outside the cpu execution
316 loop */
317 #if defined(TARGET_I386)
318 do_interrupt_user(env->exception_index,
319 env->exception_is_int,
320 env->error_code,
321 env->exception_next_eip);
322 #endif
323 ret = env->exception_index;
324 break;
325 } else {
326 #if defined(TARGET_I386)
327 /* simulate a real cpu exception. On i386, it can
328 trigger new exceptions, but we do not handle
329 double or triple faults yet. */
330 do_interrupt(env->exception_index,
331 env->exception_is_int,
332 env->error_code,
333 env->exception_next_eip, 0);
334 /* successfully delivered */
335 env->old_exception = -1;
336 #elif defined(TARGET_PPC)
337 do_interrupt(env);
338 #elif defined(TARGET_MIPS)
339 do_interrupt(env);
340 #elif defined(TARGET_SPARC)
341 do_interrupt(env->exception_index);
342 #elif defined(TARGET_ARM)
343 do_interrupt(env);
344 #elif defined(TARGET_SH4)
345 do_interrupt(env);
346 #elif defined(TARGET_ALPHA)
347 do_interrupt(env);
348 #elif defined(TARGET_M68K)
349 do_interrupt(0);
350 #elif defined(TARGET_IA64)
351 do_interrupt(env);
352 #endif
353 }
354 env->exception_index = -1;
355 }
356 #ifdef USE_KQEMU
357 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
358 int ret;
359 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
360 ret = kqemu_cpu_exec(env);
361 /* put eflags in CPU temporary format */
362 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
363 DF = 1 - (2 * ((env->eflags >> 10) & 1));
364 CC_OP = CC_OP_EFLAGS;
365 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
366 if (ret == 1) {
367 /* exception */
368 longjmp(env->jmp_env, 1);
369 } else if (ret == 2) {
370 /* softmmu execution needed */
371 } else {
372 if (env->interrupt_request != 0) {
373 /* hardware interrupt will be executed just after */
374 } else {
375 /* otherwise, we restart */
376 longjmp(env->jmp_env, 1);
377 }
378 }
379 }
380 #endif
381
382 #ifdef USE_KVM
383 if (kvm_allowed) {
384 kvm_cpu_exec(env);
385 longjmp(env->jmp_env, 1);
386 }
387 #endif
388 T0 = 0; /* force lookup of first TB */
389 for(;;) {
390 #if defined(__sparc__) && !defined(HOST_SOLARIS)
391 /* g1 can be modified by some libc? functions */
392 tmp_T0 = T0;
393 #endif
394 interrupt_request = env->interrupt_request;
395 if (__builtin_expect(interrupt_request, 0)
396 #if defined(TARGET_I386)
397 && env->hflags & HF_GIF_MASK
398 #endif
399 ) {
400 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
401 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
402 env->exception_index = EXCP_DEBUG;
403 cpu_loop_exit();
404 }
405 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
406 defined(TARGET_PPC) || defined(TARGET_ALPHA)
407 if (interrupt_request & CPU_INTERRUPT_HALT) {
408 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
409 env->halted = 1;
410 env->exception_index = EXCP_HLT;
411 cpu_loop_exit();
412 }
413 #endif
414 #if defined(TARGET_I386)
415 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
416 !(env->hflags & HF_SMM_MASK)) {
417 svm_check_intercept(SVM_EXIT_SMI);
418 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
419 do_smm_enter();
420 #if defined(__sparc__) && !defined(HOST_SOLARIS)
421 tmp_T0 = 0;
422 #else
423 T0 = 0;
424 #endif
425 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
426 (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) &&
427 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
428 int intno;
429 svm_check_intercept(SVM_EXIT_INTR);
430 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
431 intno = cpu_get_pic_interrupt(env);
432 if (loglevel & CPU_LOG_TB_IN_ASM) {
433 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
434 }
435 do_interrupt(intno, 0, 0, 0, 1);
436 /* ensure that no TB jump will be modified as
437 the program flow was changed */
438 #if defined(__sparc__) && !defined(HOST_SOLARIS)
439 tmp_T0 = 0;
440 #else
441 T0 = 0;
442 #endif
443 #if !defined(CONFIG_USER_ONLY)
444 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
445 (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
446 int intno;
447 /* FIXME: this should respect TPR */
448 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
449 svm_check_intercept(SVM_EXIT_VINTR);
450 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
451 if (loglevel & CPU_LOG_TB_IN_ASM)
452 fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno);
453 do_interrupt(intno, 0, 0, -1, 1);
454 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
455 ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK);
456 #if defined(__sparc__) && !defined(HOST_SOLARIS)
457 tmp_T0 = 0;
458 #else
459 T0 = 0;
460 #endif
461 #endif
462 }
463 #elif defined(TARGET_PPC)
464 #if 0
465 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
466 cpu_ppc_reset(env);
467 }
468 #endif
469 if (interrupt_request & CPU_INTERRUPT_HARD) {
470 ppc_hw_interrupt(env);
471 if (env->pending_interrupts == 0)
472 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
473 #if defined(__sparc__) && !defined(HOST_SOLARIS)
474 tmp_T0 = 0;
475 #else
476 T0 = 0;
477 #endif
478 }
479 #elif defined(TARGET_MIPS)
480 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
481 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
482 (env->CP0_Status & (1 << CP0St_IE)) &&
483 !(env->CP0_Status & (1 << CP0St_EXL)) &&
484 !(env->CP0_Status & (1 << CP0St_ERL)) &&
485 !(env->hflags & MIPS_HFLAG_DM)) {
486 /* Raise it */
487 env->exception_index = EXCP_EXT_INTERRUPT;
488 env->error_code = 0;
489 do_interrupt(env);
490 #if defined(__sparc__) && !defined(HOST_SOLARIS)
491 tmp_T0 = 0;
492 #else
493 T0 = 0;
494 #endif
495 }
496 #elif defined(TARGET_SPARC)
497 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
498 (env->psret != 0)) {
499 int pil = env->interrupt_index & 15;
500 int type = env->interrupt_index & 0xf0;
501
502 if (((type == TT_EXTINT) &&
503 (pil == 15 || pil > env->psrpil)) ||
504 type != TT_EXTINT) {
505 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
506 do_interrupt(env->interrupt_index);
507 env->interrupt_index = 0;
508 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
509 cpu_check_irqs(env);
510 #endif
511 #if defined(__sparc__) && !defined(HOST_SOLARIS)
512 tmp_T0 = 0;
513 #else
514 T0 = 0;
515 #endif
516 }
517 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
518 //do_interrupt(0, 0, 0, 0, 0);
519 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
520 }
521 #elif defined(TARGET_ARM)
522 if (interrupt_request & CPU_INTERRUPT_FIQ
523 && !(env->uncached_cpsr & CPSR_F)) {
524 env->exception_index = EXCP_FIQ;
525 do_interrupt(env);
526 }
527 if (interrupt_request & CPU_INTERRUPT_HARD
528 && !(env->uncached_cpsr & CPSR_I)) {
529 env->exception_index = EXCP_IRQ;
530 do_interrupt(env);
531 }
532 #elif defined(TARGET_SH4)
533 /* XXXXX */
534 #elif defined(TARGET_ALPHA)
535 if (interrupt_request & CPU_INTERRUPT_HARD) {
536 do_interrupt(env);
537 }
538 #elif defined(TARGET_M68K)
539 if (interrupt_request & CPU_INTERRUPT_HARD
540 && ((env->sr & SR_I) >> SR_I_SHIFT)
541 < env->pending_level) {
542 /* Real hardware gets the interrupt vector via an
543 IACK cycle at this point. Current emulated
544 hardware doesn't rely on this, so we
545 provide/save the vector when the interrupt is
546 first signalled. */
547 env->exception_index = env->pending_vector;
548 do_interrupt(1);
549 }
550 #endif
551 /* Don't use the cached interupt_request value,
552 do_interrupt may have updated the EXITTB flag. */
553 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
554 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
555 /* ensure that no TB jump will be modified as
556 the program flow was changed */
557 #if defined(__sparc__) && !defined(HOST_SOLARIS)
558 tmp_T0 = 0;
559 #else
560 T0 = 0;
561 #endif
562 }
563 if (interrupt_request & CPU_INTERRUPT_EXIT) {
564 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
565 env->exception_index = EXCP_INTERRUPT;
566 cpu_loop_exit();
567 }
568 }
569 #ifdef DEBUG_EXEC
570 if ((loglevel & CPU_LOG_TB_CPU)) {
571 /* restore flags in standard format */
572 regs_to_env();
573 #if defined(TARGET_I386)
574 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
575 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
576 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
577 #elif defined(TARGET_ARM)
578 cpu_dump_state(env, logfile, fprintf, 0);
579 #elif defined(TARGET_SPARC)
580 REGWPTR = env->regbase + (env->cwp * 16);
581 env->regwptr = REGWPTR;
582 cpu_dump_state(env, logfile, fprintf, 0);
583 #elif defined(TARGET_PPC)
584 cpu_dump_state(env, logfile, fprintf, 0);
585 #elif defined(TARGET_M68K)
586 cpu_m68k_flush_flags(env, env->cc_op);
587 env->cc_op = CC_OP_FLAGS;
588 env->sr = (env->sr & 0xffe0)
589 | env->cc_dest | (env->cc_x << 4);
590 cpu_dump_state(env, logfile, fprintf, 0);
591 #elif defined(TARGET_MIPS)
592 cpu_dump_state(env, logfile, fprintf, 0);
593 #elif defined(TARGET_SH4)
594 cpu_dump_state(env, logfile, fprintf, 0);
595 #elif defined(TARGET_ALPHA)
596 cpu_dump_state(env, logfile, fprintf, 0);
597 #else
598 #error unsupported target CPU
599 #endif
600 }
601 #endif
602 tb = tb_find_fast();
603 #ifdef DEBUG_EXEC
604 if ((loglevel & CPU_LOG_EXEC)) {
605 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
606 (long)tb->tc_ptr, tb->pc,
607 lookup_symbol(tb->pc));
608 }
609 #endif
610 #if defined(__sparc__) && !defined(HOST_SOLARIS)
611 T0 = tmp_T0;
612 #endif
613 /* see if we can patch the calling TB. When the TB
614 spans two pages, we cannot safely do a direct
615 jump. */
616 {
617 if (T0 != 0 &&
618 #if USE_KQEMU
619 (env->kqemu_enabled != 2) &&
620 #endif
621 tb->page_addr[1] == -1
622 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
623 && (tb->cflags & CF_CODE_COPY) ==
624 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
625 #endif
626 ) {
627 spin_lock(&tb_lock);
628 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
629 #if defined(USE_CODE_COPY)
630 /* propagates the FP use info */
631 ((TranslationBlock *)(T0 & ~3))->cflags |=
632 (tb->cflags & CF_FP_USED);
633 #endif
634 spin_unlock(&tb_lock);
635 }
636 }
637 tc_ptr = tb->tc_ptr;
638 env->current_tb = tb;
639 /* execute the generated code */
640 gen_func = (void *)tc_ptr;
641 #if defined(__sparc__)
642 __asm__ __volatile__("call %0\n\t"
643 "mov %%o7,%%i0"
644 : /* no outputs */
645 : "r" (gen_func)
646 : "i0", "i1", "i2", "i3", "i4", "i5",
647 "o0", "o1", "o2", "o3", "o4", "o5",
648 "l0", "l1", "l2", "l3", "l4", "l5",
649 "l6", "l7");
650 #elif defined(__arm__)
651 asm volatile ("mov pc, %0\n\t"
652 ".global exec_loop\n\t"
653 "exec_loop:\n\t"
654 : /* no outputs */
655 : "r" (gen_func)
656 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
657 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
658 {
659 if (!(tb->cflags & CF_CODE_COPY)) {
660 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
661 save_native_fp_state(env);
662 }
663 gen_func();
664 } else {
665 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
666 restore_native_fp_state(env);
667 }
668 /* we work with native eflags */
669 CC_SRC = cc_table[CC_OP].compute_all();
670 CC_OP = CC_OP_EFLAGS;
671 asm(".globl exec_loop\n"
672 "\n"
673 "debug1:\n"
674 " pushl %%ebp\n"
675 " fs movl %10, %9\n"
676 " fs movl %11, %%eax\n"
677 " andl $0x400, %%eax\n"
678 " fs orl %8, %%eax\n"
679 " pushl %%eax\n"
680 " popf\n"
681 " fs movl %%esp, %12\n"
682 " fs movl %0, %%eax\n"
683 " fs movl %1, %%ecx\n"
684 " fs movl %2, %%edx\n"
685 " fs movl %3, %%ebx\n"
686 " fs movl %4, %%esp\n"
687 " fs movl %5, %%ebp\n"
688 " fs movl %6, %%esi\n"
689 " fs movl %7, %%edi\n"
690 " fs jmp *%9\n"
691 "exec_loop:\n"
692 " fs movl %%esp, %4\n"
693 " fs movl %12, %%esp\n"
694 " fs movl %%eax, %0\n"
695 " fs movl %%ecx, %1\n"
696 " fs movl %%edx, %2\n"
697 " fs movl %%ebx, %3\n"
698 " fs movl %%ebp, %5\n"
699 " fs movl %%esi, %6\n"
700 " fs movl %%edi, %7\n"
701 " pushf\n"
702 " popl %%eax\n"
703 " movl %%eax, %%ecx\n"
704 " andl $0x400, %%ecx\n"
705 " shrl $9, %%ecx\n"
706 " andl $0x8d5, %%eax\n"
707 " fs movl %%eax, %8\n"
708 " movl $1, %%eax\n"
709 " subl %%ecx, %%eax\n"
710 " fs movl %%eax, %11\n"
711 " fs movl %9, %%ebx\n" /* get T0 value */
712 " popl %%ebp\n"
713 :
714 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
715 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
716 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
717 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
718 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
719 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
720 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
721 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
722 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
723 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
724 "a" (gen_func),
725 "m" (*(uint8_t *)offsetof(CPUState, df)),
726 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
727 : "%ecx", "%edx"
728 );
729 }
730 }
731 #elif defined(__ia64)
732 struct fptr {
733 void *ip;
734 void *gp;
735 } fp;
736
737 fp.ip = tc_ptr;
738 fp.gp = code_gen_buffer + 2 * (1 << 20);
739 (*(void (*)(void)) &fp)();
740 #else
741 gen_func();
742 #endif
743 env->current_tb = NULL;
744 /* reset soft MMU for next block (it can currently
745 only be set by a memory fault) */
746 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
747 if (env->hflags & HF_SOFTMMU_MASK) {
748 env->hflags &= ~HF_SOFTMMU_MASK;
749 /* do not allow linking to another block */
750 T0 = 0;
751 }
752 #endif
753 #if defined(USE_KQEMU)
754 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
755 if (kqemu_is_ok(env) &&
756 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
757 cpu_loop_exit();
758 }
759 #endif
760 } /* for(;;) */
761 } else {
762 env_to_regs();
763 }
764 } /* for(;;) */
765
766
767 #if defined(TARGET_I386)
768 #if defined(USE_CODE_COPY)
769 if (env->native_fp_regs) {
770 save_native_fp_state(env);
771 }
772 #endif
773 /* restore flags in standard format */
774 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
775 #elif defined(TARGET_ARM)
776 /* XXX: Save/restore host fpu exception state?. */
777 #elif defined(TARGET_SPARC)
778 #if defined(reg_REGWPTR)
779 REGWPTR = saved_regwptr;
780 #endif
781 #elif defined(TARGET_PPC)
782 #elif defined(TARGET_M68K)
783 cpu_m68k_flush_flags(env, env->cc_op);
784 env->cc_op = CC_OP_FLAGS;
785 env->sr = (env->sr & 0xffe0)
786 | env->cc_dest | (env->cc_x << 4);
787 #elif defined(TARGET_MIPS)
788 #elif defined(TARGET_SH4)
789 #elif defined(TARGET_IA64)
790 #elif defined(TARGET_ALPHA)
791 /* XXXXX */
792 #else
793 #error unsupported target CPU
794 #endif
795
796 /* restore global registers */
797 #if defined(__sparc__) && !defined(HOST_SOLARIS)
798 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
799 #endif
800 #include "hostregs_helper.h"
801
802 /* fail safe : never use cpu_single_env outside cpu_exec() */
803 cpu_single_env = NULL;
804 return ret;
805 }
806
807 /* must only be called from the generated code as an exception can be
808 generated */
809 void tb_invalidate_page_range(target_ulong start, target_ulong end)
810 {
811 /* XXX: cannot enable it yet because it yields to MMU exception
812 where NIP != read address on PowerPC */
813 #if 0
814 target_ulong phys_addr;
815 phys_addr = get_phys_addr_code(env, start);
816 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
817 #endif
818 }
819
820 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
821
822 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
823 {
824 CPUX86State *saved_env;
825
826 saved_env = env;
827 env = s;
828 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
829 selector &= 0xffff;
830 cpu_x86_load_seg_cache(env, seg_reg, selector,
831 (selector << 4), 0xffff, 0);
832 } else {
833 load_seg(seg_reg, selector);
834 }
835 env = saved_env;
836 }
837
838 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
839 {
840 CPUX86State *saved_env;
841
842 saved_env = env;
843 env = s;
844
845 helper_fsave((target_ulong)ptr, data32);
846
847 env = saved_env;
848 }
849
850 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
851 {
852 CPUX86State *saved_env;
853
854 saved_env = env;
855 env = s;
856
857 helper_frstor((target_ulong)ptr, data32);
858
859 env = saved_env;
860 }
861
862 #endif /* TARGET_I386 */
863
864 #if !defined(CONFIG_SOFTMMU)
865
866 #if defined(TARGET_I386)
867
868 /* 'pc' is the host PC at which the exception was raised. 'address' is
869 the effective address of the memory exception. 'is_write' is 1 if a
870 write caused the exception and otherwise 0'. 'old_set' is the
871 signal set which should be restored */
872 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
873 int is_write, sigset_t *old_set,
874 void *puc)
875 {
876 TranslationBlock *tb;
877 int ret;
878
879 if (cpu_single_env)
880 env = cpu_single_env; /* XXX: find a correct solution for multithread */
881 #if defined(DEBUG_SIGNAL)
882 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
883 pc, address, is_write, *(unsigned long *)old_set);
884 #endif
885 /* XXX: locking issue */
886 if (is_write && page_unprotect(h2g(address), pc, puc)) {
887 return 1;
888 }
889
890 /* see if it is an MMU fault */
891 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
892 ((env->hflags & HF_CPL_MASK) == 3), 0);
893 if (ret < 0)
894 return 0; /* not an MMU fault */
895 if (ret == 0)
896 return 1; /* the MMU fault was handled without causing real CPU fault */
897 /* now we have a real cpu fault */
898 tb = tb_find_pc(pc);
899 if (tb) {
900 /* the PC is inside the translated code. It means that we have
901 a virtual CPU fault */
902 cpu_restore_state(tb, env, pc, puc);
903 }
904 if (ret == 1) {
905 #if 0
906 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
907 env->eip, env->cr[2], env->error_code);
908 #endif
909 /* we restore the process signal mask as the sigreturn should
910 do it (XXX: use sigsetjmp) */
911 sigprocmask(SIG_SETMASK, old_set, NULL);
912 raise_exception_err(env->exception_index, env->error_code);
913 } else {
914 /* activate soft MMU for this block */
915 env->hflags |= HF_SOFTMMU_MASK;
916 cpu_resume_from_signal(env, puc);
917 }
918 /* never comes here */
919 return 1;
920 }
921
922 #elif defined(TARGET_ARM)
923 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
924 int is_write, sigset_t *old_set,
925 void *puc)
926 {
927 TranslationBlock *tb;
928 int ret;
929
930 if (cpu_single_env)
931 env = cpu_single_env; /* XXX: find a correct solution for multithread */
932 #if defined(DEBUG_SIGNAL)
933 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
934 pc, address, is_write, *(unsigned long *)old_set);
935 #endif
936 /* XXX: locking issue */
937 if (is_write && page_unprotect(h2g(address), pc, puc)) {
938 return 1;
939 }
940 /* see if it is an MMU fault */
941 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
942 if (ret < 0)
943 return 0; /* not an MMU fault */
944 if (ret == 0)
945 return 1; /* the MMU fault was handled without causing real CPU fault */
946 /* now we have a real cpu fault */
947 tb = tb_find_pc(pc);
948 if (tb) {
949 /* the PC is inside the translated code. It means that we have
950 a virtual CPU fault */
951 cpu_restore_state(tb, env, pc, puc);
952 }
953 /* we restore the process signal mask as the sigreturn should
954 do it (XXX: use sigsetjmp) */
955 sigprocmask(SIG_SETMASK, old_set, NULL);
956 cpu_loop_exit();
957 }
958 #elif defined(TARGET_SPARC)
959 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
960 int is_write, sigset_t *old_set,
961 void *puc)
962 {
963 TranslationBlock *tb;
964 int ret;
965
966 if (cpu_single_env)
967 env = cpu_single_env; /* XXX: find a correct solution for multithread */
968 #if defined(DEBUG_SIGNAL)
969 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
970 pc, address, is_write, *(unsigned long *)old_set);
971 #endif
972 /* XXX: locking issue */
973 if (is_write && page_unprotect(h2g(address), pc, puc)) {
974 return 1;
975 }
976 /* see if it is an MMU fault */
977 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
978 if (ret < 0)
979 return 0; /* not an MMU fault */
980 if (ret == 0)
981 return 1; /* the MMU fault was handled without causing real CPU fault */
982 /* now we have a real cpu fault */
983 tb = tb_find_pc(pc);
984 if (tb) {
985 /* the PC is inside the translated code. It means that we have
986 a virtual CPU fault */
987 cpu_restore_state(tb, env, pc, puc);
988 }
989 /* we restore the process signal mask as the sigreturn should
990 do it (XXX: use sigsetjmp) */
991 sigprocmask(SIG_SETMASK, old_set, NULL);
992 cpu_loop_exit();
993 }
994 #elif defined (TARGET_PPC)
995 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
996 int is_write, sigset_t *old_set,
997 void *puc)
998 {
999 TranslationBlock *tb;
1000 int ret;
1001
1002 if (cpu_single_env)
1003 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1004 #if defined(DEBUG_SIGNAL)
1005 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1006 pc, address, is_write, *(unsigned long *)old_set);
1007 #endif
1008 /* XXX: locking issue */
1009 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1010 return 1;
1011 }
1012
1013 /* see if it is an MMU fault */
1014 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1015 if (ret < 0)
1016 return 0; /* not an MMU fault */
1017 if (ret == 0)
1018 return 1; /* the MMU fault was handled without causing real CPU fault */
1019
1020 /* now we have a real cpu fault */
1021 tb = tb_find_pc(pc);
1022 if (tb) {
1023 /* the PC is inside the translated code. It means that we have
1024 a virtual CPU fault */
1025 cpu_restore_state(tb, env, pc, puc);
1026 }
1027 if (ret == 1) {
1028 #if 0
1029 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1030 env->nip, env->error_code, tb);
1031 #endif
1032 /* we restore the process signal mask as the sigreturn should
1033 do it (XXX: use sigsetjmp) */
1034 sigprocmask(SIG_SETMASK, old_set, NULL);
1035 do_raise_exception_err(env->exception_index, env->error_code);
1036 } else {
1037 /* activate soft MMU for this block */
1038 cpu_resume_from_signal(env, puc);
1039 }
1040 /* never comes here */
1041 return 1;
1042 }
1043
1044 #elif defined(TARGET_M68K)
1045 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1046 int is_write, sigset_t *old_set,
1047 void *puc)
1048 {
1049 TranslationBlock *tb;
1050 int ret;
1051
1052 if (cpu_single_env)
1053 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1054 #if defined(DEBUG_SIGNAL)
1055 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1056 pc, address, is_write, *(unsigned long *)old_set);
1057 #endif
1058 /* XXX: locking issue */
1059 if (is_write && page_unprotect(address, pc, puc)) {
1060 return 1;
1061 }
1062 /* see if it is an MMU fault */
1063 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1064 if (ret < 0)
1065 return 0; /* not an MMU fault */
1066 if (ret == 0)
1067 return 1; /* the MMU fault was handled without causing real CPU fault */
1068 /* now we have a real cpu fault */
1069 tb = tb_find_pc(pc);
1070 if (tb) {
1071 /* the PC is inside the translated code. It means that we have
1072 a virtual CPU fault */
1073 cpu_restore_state(tb, env, pc, puc);
1074 }
1075 /* we restore the process signal mask as the sigreturn should
1076 do it (XXX: use sigsetjmp) */
1077 sigprocmask(SIG_SETMASK, old_set, NULL);
1078 cpu_loop_exit();
1079 /* never comes here */
1080 return 1;
1081 }
1082
1083 #elif defined (TARGET_MIPS)
1084 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1085 int is_write, sigset_t *old_set,
1086 void *puc)
1087 {
1088 TranslationBlock *tb;
1089 int ret;
1090
1091 if (cpu_single_env)
1092 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1093 #if defined(DEBUG_SIGNAL)
1094 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1095 pc, address, is_write, *(unsigned long *)old_set);
1096 #endif
1097 /* XXX: locking issue */
1098 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1099 return 1;
1100 }
1101
1102 /* see if it is an MMU fault */
1103 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1104 if (ret < 0)
1105 return 0; /* not an MMU fault */
1106 if (ret == 0)
1107 return 1; /* the MMU fault was handled without causing real CPU fault */
1108
1109 /* now we have a real cpu fault */
1110 tb = tb_find_pc(pc);
1111 if (tb) {
1112 /* the PC is inside the translated code. It means that we have
1113 a virtual CPU fault */
1114 cpu_restore_state(tb, env, pc, puc);
1115 }
1116 if (ret == 1) {
1117 #if 0
1118 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1119 env->PC, env->error_code, tb);
1120 #endif
1121 /* we restore the process signal mask as the sigreturn should
1122 do it (XXX: use sigsetjmp) */
1123 sigprocmask(SIG_SETMASK, old_set, NULL);
1124 do_raise_exception_err(env->exception_index, env->error_code);
1125 } else {
1126 /* activate soft MMU for this block */
1127 cpu_resume_from_signal(env, puc);
1128 }
1129 /* never comes here */
1130 return 1;
1131 }
1132
1133 #elif defined (TARGET_SH4)
1134 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1135 int is_write, sigset_t *old_set,
1136 void *puc)
1137 {
1138 TranslationBlock *tb;
1139 int ret;
1140
1141 if (cpu_single_env)
1142 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1143 #if defined(DEBUG_SIGNAL)
1144 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1145 pc, address, is_write, *(unsigned long *)old_set);
1146 #endif
1147 /* XXX: locking issue */
1148 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1149 return 1;
1150 }
1151
1152 /* see if it is an MMU fault */
1153 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1154 if (ret < 0)
1155 return 0; /* not an MMU fault */
1156 if (ret == 0)
1157 return 1; /* the MMU fault was handled without causing real CPU fault */
1158
1159 /* now we have a real cpu fault */
1160 tb = tb_find_pc(pc);
1161 if (tb) {
1162 /* the PC is inside the translated code. It means that we have
1163 a virtual CPU fault */
1164 cpu_restore_state(tb, env, pc, puc);
1165 }
1166 #if 0
1167 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1168 env->nip, env->error_code, tb);
1169 #endif
1170 /* we restore the process signal mask as the sigreturn should
1171 do it (XXX: use sigsetjmp) */
1172 sigprocmask(SIG_SETMASK, old_set, NULL);
1173 cpu_loop_exit();
1174 /* never comes here */
1175 return 1;
1176 }
1177
1178 #elif defined (TARGET_ALPHA)
1179 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1180 int is_write, sigset_t *old_set,
1181 void *puc)
1182 {
1183 TranslationBlock *tb;
1184 int ret;
1185
1186 if (cpu_single_env)
1187 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1188 #if defined(DEBUG_SIGNAL)
1189 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1190 pc, address, is_write, *(unsigned long *)old_set);
1191 #endif
1192 /* XXX: locking issue */
1193 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1194 return 1;
1195 }
1196
1197 /* see if it is an MMU fault */
1198 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0);
1199 if (ret < 0)
1200 return 0; /* not an MMU fault */
1201 if (ret == 0)
1202 return 1; /* the MMU fault was handled without causing real CPU fault */
1203
1204 /* now we have a real cpu fault */
1205 tb = tb_find_pc(pc);
1206 if (tb) {
1207 /* the PC is inside the translated code. It means that we have
1208 a virtual CPU fault */
1209 cpu_restore_state(tb, env, pc, puc);
1210 }
1211 #if 0
1212 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1213 env->nip, env->error_code, tb);
1214 #endif
1215 /* we restore the process signal mask as the sigreturn should
1216 do it (XXX: use sigsetjmp) */
1217 sigprocmask(SIG_SETMASK, old_set, NULL);
1218 cpu_loop_exit();
1219 /* never comes here */
1220 return 1;
1221 }
1222 #else
1223 #error unsupported target CPU
1224 #endif
1225
1226 #if defined(__i386__)
1227
1228 #if defined(__APPLE__)
1229 # include <sys/ucontext.h>
1230
1231 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1232 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1233 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1234 #else
1235 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1236 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1237 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1238 #endif
1239
1240 #if defined(USE_CODE_COPY)
1241 static void cpu_send_trap(unsigned long pc, int trap,
1242 struct ucontext *uc)
1243 {
1244 TranslationBlock *tb;
1245
1246 if (cpu_single_env)
1247 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1248 /* now we have a real cpu fault */
1249 tb = tb_find_pc(pc);
1250 if (tb) {
1251 /* the PC is inside the translated code. It means that we have
1252 a virtual CPU fault */
1253 cpu_restore_state(tb, env, pc, uc);
1254 }
1255 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1256 raise_exception_err(trap, env->error_code);
1257 }
1258 #endif
1259
1260 int cpu_signal_handler(int host_signum, void *pinfo,
1261 void *puc)
1262 {
1263 siginfo_t *info = pinfo;
1264 struct ucontext *uc = puc;
1265 unsigned long pc;
1266 int trapno;
1267
1268 #ifndef REG_EIP
1269 /* for glibc 2.1 */
1270 #define REG_EIP EIP
1271 #define REG_ERR ERR
1272 #define REG_TRAPNO TRAPNO
1273 #endif
1274 pc = EIP_sig(uc);
1275 trapno = TRAP_sig(uc);
1276 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1277 if (trapno == 0x00 || trapno == 0x05) {
1278 /* send division by zero or bound exception */
1279 cpu_send_trap(pc, trapno, uc);
1280 return 1;
1281 } else
1282 #endif
1283 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1284 trapno == 0xe ?
1285 (ERROR_sig(uc) >> 1) & 1 : 0,
1286 &uc->uc_sigmask, puc);
1287 }
1288
1289 #elif defined(__x86_64__)
1290
1291 int cpu_signal_handler(int host_signum, void *pinfo,
1292 void *puc)
1293 {
1294 siginfo_t *info = pinfo;
1295 struct ucontext *uc = puc;
1296 unsigned long pc;
1297
1298 pc = uc->uc_mcontext.gregs[REG_RIP];
1299 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1300 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1301 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1302 &uc->uc_sigmask, puc);
1303 }
1304
1305 #elif defined(__powerpc__)
1306
1307 /***********************************************************************
1308 * signal context platform-specific definitions
1309 * From Wine
1310 */
1311 #ifdef linux
1312 /* All Registers access - only for local access */
1313 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1314 /* Gpr Registers access */
1315 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1316 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1317 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1318 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1319 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1320 # define LR_sig(context) REG_sig(link, context) /* Link register */
1321 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1322 /* Float Registers access */
1323 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1324 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1325 /* Exception Registers access */
1326 # define DAR_sig(context) REG_sig(dar, context)
1327 # define DSISR_sig(context) REG_sig(dsisr, context)
1328 # define TRAP_sig(context) REG_sig(trap, context)
1329 #endif /* linux */
1330
1331 #ifdef __APPLE__
1332 # include <sys/ucontext.h>
1333 typedef struct ucontext SIGCONTEXT;
1334 /* All Registers access - only for local access */
1335 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1336 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1337 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1338 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1339 /* Gpr Registers access */
1340 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1341 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1342 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1343 # define CTR_sig(context) REG_sig(ctr, context)
1344 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1345 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1346 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1347 /* Float Registers access */
1348 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1349 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1350 /* Exception Registers access */
1351 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1352 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1353 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1354 #endif /* __APPLE__ */
1355
1356 int cpu_signal_handler(int host_signum, void *pinfo,
1357 void *puc)
1358 {
1359 siginfo_t *info = pinfo;
1360 struct ucontext *uc = puc;
1361 unsigned long pc;
1362 int is_write;
1363
1364 pc = IAR_sig(uc);
1365 is_write = 0;
1366 #if 0
1367 /* ppc 4xx case */
1368 if (DSISR_sig(uc) & 0x00800000)
1369 is_write = 1;
1370 #else
1371 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1372 is_write = 1;
1373 #endif
1374 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1375 is_write, &uc->uc_sigmask, puc);
1376 }
1377
1378 #elif defined(__alpha__)
1379
1380 int cpu_signal_handler(int host_signum, void *pinfo,
1381 void *puc)
1382 {
1383 siginfo_t *info = pinfo;
1384 struct ucontext *uc = puc;
1385 uint32_t *pc = uc->uc_mcontext.sc_pc;
1386 uint32_t insn = *pc;
1387 int is_write = 0;
1388
1389 /* XXX: need kernel patch to get write flag faster */
1390 switch (insn >> 26) {
1391 case 0x0d: // stw
1392 case 0x0e: // stb
1393 case 0x0f: // stq_u
1394 case 0x24: // stf
1395 case 0x25: // stg
1396 case 0x26: // sts
1397 case 0x27: // stt
1398 case 0x2c: // stl
1399 case 0x2d: // stq
1400 case 0x2e: // stl_c
1401 case 0x2f: // stq_c
1402 is_write = 1;
1403 }
1404
1405 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1406 is_write, &uc->uc_sigmask, puc);
1407 }
1408 #elif defined(__sparc__)
1409
1410 int cpu_signal_handler(int host_signum, void *pinfo,
1411 void *puc)
1412 {
1413 siginfo_t *info = pinfo;
1414 uint32_t *regs = (uint32_t *)(info + 1);
1415 void *sigmask = (regs + 20);
1416 unsigned long pc;
1417 int is_write;
1418 uint32_t insn;
1419
1420 /* XXX: is there a standard glibc define ? */
1421 pc = regs[1];
1422 /* XXX: need kernel patch to get write flag faster */
1423 is_write = 0;
1424 insn = *(uint32_t *)pc;
1425 if ((insn >> 30) == 3) {
1426 switch((insn >> 19) & 0x3f) {
1427 case 0x05: // stb
1428 case 0x06: // sth
1429 case 0x04: // st
1430 case 0x07: // std
1431 case 0x24: // stf
1432 case 0x27: // stdf
1433 case 0x25: // stfsr
1434 is_write = 1;
1435 break;
1436 }
1437 }
1438 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1439 is_write, sigmask, NULL);
1440 }
1441
1442 #elif defined(__arm__)
1443
1444 int cpu_signal_handler(int host_signum, void *pinfo,
1445 void *puc)
1446 {
1447 siginfo_t *info = pinfo;
1448 struct ucontext *uc = puc;
1449 unsigned long pc;
1450 int is_write;
1451
1452 pc = uc->uc_mcontext.gregs[R15];
1453 /* XXX: compute is_write */
1454 is_write = 0;
1455 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1456 is_write,
1457 &uc->uc_sigmask, puc);
1458 }
1459
1460 #elif defined(__mc68000)
1461
1462 int cpu_signal_handler(int host_signum, void *pinfo,
1463 void *puc)
1464 {
1465 siginfo_t *info = pinfo;
1466 struct ucontext *uc = puc;
1467 unsigned long pc;
1468 int is_write;
1469
1470 pc = uc->uc_mcontext.gregs[16];
1471 /* XXX: compute is_write */
1472 is_write = 0;
1473 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1474 is_write,
1475 &uc->uc_sigmask, puc);
1476 }
1477
1478 #elif defined(__ia64)
1479
1480 #ifndef __ISR_VALID
1481 /* This ought to be in <bits/siginfo.h>... */
1482 # define __ISR_VALID 1
1483 #endif
1484
1485 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1486 {
1487 siginfo_t *info = pinfo;
1488 struct ucontext *uc = puc;
1489 unsigned long ip;
1490 int is_write = 0;
1491
1492 ip = uc->uc_mcontext.sc_ip;
1493 switch (host_signum) {
1494 case SIGILL:
1495 case SIGFPE:
1496 case SIGSEGV:
1497 case SIGBUS:
1498 case SIGTRAP:
1499 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1500 /* ISR.W (write-access) is bit 33: */
1501 is_write = (info->si_isr >> 33) & 1;
1502 break;
1503
1504 default:
1505 break;
1506 }
1507 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1508 is_write,
1509 &uc->uc_sigmask, puc);
1510 }
1511
1512 #elif defined(__s390__)
1513
1514 int cpu_signal_handler(int host_signum, void *pinfo,
1515 void *puc)
1516 {
1517 siginfo_t *info = pinfo;
1518 struct ucontext *uc = puc;
1519 unsigned long pc;
1520 int is_write;
1521
1522 pc = uc->uc_mcontext.psw.addr;
1523 /* XXX: compute is_write */
1524 is_write = 0;
1525 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1526 is_write, &uc->uc_sigmask, puc);
1527 }
1528
1529 #elif defined(__mips__)
1530
1531 int cpu_signal_handler(int host_signum, void *pinfo,
1532 void *puc)
1533 {
1534 siginfo_t *info = pinfo;
1535 struct ucontext *uc = puc;
1536 greg_t pc = uc->uc_mcontext.pc;
1537 int is_write;
1538
1539 /* XXX: compute is_write */
1540 is_write = 0;
1541 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1542 is_write, &uc->uc_sigmask, puc);
1543 }
1544
1545 #else
1546
1547 #error host CPU specific signal handler needed
1548
1549 #endif
1550
1551 #endif /* !defined(CONFIG_SOFTMMU) */
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