2 * qemu/kvm integration, x86 specific code
4 * Copyright (C) 2006-2008 Qumranet Technologies
6 * Licensed under the terms of the GNU GPL version 2 or higher.
10 #include "config-host.h"
18 #include <sys/utsname.h>
19 #include <linux/kvm_para.h>
21 #define MSR_IA32_TSC 0x10
23 static struct kvm_msr_list
*kvm_msr_list
;
24 extern unsigned int kvm_shadow_memory
;
25 extern kvm_context_t kvm_context
;
26 static int kvm_has_msr_star
;
28 static int lm_capable_kernel
;
30 int kvm_arch_qemu_create_context(void)
33 struct utsname utsname
;
36 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
38 if (kvm_shadow_memory
)
39 kvm_set_shadow_pages(kvm_context
, kvm_shadow_memory
);
41 kvm_msr_list
= kvm_get_msr_list(kvm_context
);
44 for (i
= 0; i
< kvm_msr_list
->nmsrs
; ++i
)
45 if (kvm_msr_list
->indices
[i
] == MSR_STAR
)
50 static void set_msr_entry(struct kvm_msr_entry
*entry
, uint32_t index
,
57 /* returns 0 on success, non-0 on failure */
58 static int get_msr_entry(struct kvm_msr_entry
*entry
, CPUState
*env
)
60 switch (entry
->index
) {
61 case MSR_IA32_SYSENTER_CS
:
62 env
->sysenter_cs
= entry
->data
;
64 case MSR_IA32_SYSENTER_ESP
:
65 env
->sysenter_esp
= entry
->data
;
67 case MSR_IA32_SYSENTER_EIP
:
68 env
->sysenter_eip
= entry
->data
;
71 env
->star
= entry
->data
;
75 env
->cstar
= entry
->data
;
77 case MSR_KERNELGSBASE
:
78 env
->kernelgsbase
= entry
->data
;
81 env
->fmask
= entry
->data
;
84 env
->lstar
= entry
->data
;
88 env
->tsc
= entry
->data
;
91 printf("Warning unknown msr index 0x%x\n", entry
->index
);
103 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
105 lhs
->selector
= rhs
->selector
;
106 lhs
->base
= rhs
->base
;
107 lhs
->limit
= rhs
->limit
;
119 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
121 unsigned flags
= rhs
->flags
;
122 lhs
->selector
= rhs
->selector
;
123 lhs
->base
= rhs
->base
;
124 lhs
->limit
= rhs
->limit
;
125 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
126 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
127 lhs
->dpl
= rhs
->selector
& 3;
128 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
129 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
130 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
131 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
132 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
136 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
138 lhs
->selector
= rhs
->selector
;
139 lhs
->base
= rhs
->base
;
140 lhs
->limit
= rhs
->limit
;
142 (rhs
->type
<< DESC_TYPE_SHIFT
)
143 | (rhs
->present
* DESC_P_MASK
)
144 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
145 | (rhs
->db
<< DESC_B_SHIFT
)
146 | (rhs
->s
* DESC_S_MASK
)
147 | (rhs
->l
<< DESC_L_SHIFT
)
148 | (rhs
->g
* DESC_G_MASK
)
149 | (rhs
->avl
* DESC_AVL_MASK
);
152 void kvm_arch_load_regs(CPUState
*env
)
154 struct kvm_regs regs
;
156 struct kvm_sregs sregs
;
157 struct kvm_msr_entry msrs
[MSR_COUNT
];
160 regs
.rax
= env
->regs
[R_EAX
];
161 regs
.rbx
= env
->regs
[R_EBX
];
162 regs
.rcx
= env
->regs
[R_ECX
];
163 regs
.rdx
= env
->regs
[R_EDX
];
164 regs
.rsi
= env
->regs
[R_ESI
];
165 regs
.rdi
= env
->regs
[R_EDI
];
166 regs
.rsp
= env
->regs
[R_ESP
];
167 regs
.rbp
= env
->regs
[R_EBP
];
169 regs
.r8
= env
->regs
[8];
170 regs
.r9
= env
->regs
[9];
171 regs
.r10
= env
->regs
[10];
172 regs
.r11
= env
->regs
[11];
173 regs
.r12
= env
->regs
[12];
174 regs
.r13
= env
->regs
[13];
175 regs
.r14
= env
->regs
[14];
176 regs
.r15
= env
->regs
[15];
179 regs
.rflags
= env
->eflags
;
182 kvm_set_regs(kvm_context
, env
->cpu_index
, ®s
);
184 memset(&fpu
, 0, sizeof fpu
);
185 fpu
.fsw
= env
->fpus
& ~(7 << 11);
186 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
188 for (i
= 0; i
< 8; ++i
)
189 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
190 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
191 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
192 fpu
.mxcsr
= env
->mxcsr
;
193 kvm_set_fpu(kvm_context
, env
->cpu_index
, &fpu
);
195 memcpy(sregs
.interrupt_bitmap
, env
->kvm_interrupt_bitmap
, sizeof(sregs
.interrupt_bitmap
));
197 if ((env
->eflags
& VM_MASK
)) {
198 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
199 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
200 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
201 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
202 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
203 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
205 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
206 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
207 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
208 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
209 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
210 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
212 if (env
->cr
[0] & CR0_PE_MASK
) {
213 /* force ss cpl to cs cpl */
214 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
215 (sregs
.cs
.selector
& 3);
216 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
220 set_seg(&sregs
.tr
, &env
->tr
);
221 set_seg(&sregs
.ldt
, &env
->ldt
);
223 sregs
.idt
.limit
= env
->idt
.limit
;
224 sregs
.idt
.base
= env
->idt
.base
;
225 sregs
.gdt
.limit
= env
->gdt
.limit
;
226 sregs
.gdt
.base
= env
->gdt
.base
;
228 sregs
.cr0
= env
->cr
[0];
229 sregs
.cr2
= env
->cr
[2];
230 sregs
.cr3
= env
->cr
[3];
231 sregs
.cr4
= env
->cr
[4];
233 sregs
.cr8
= cpu_get_apic_tpr(env
);
234 sregs
.apic_base
= cpu_get_apic_base(env
);
236 sregs
.efer
= env
->efer
;
238 kvm_set_sregs(kvm_context
, env
->cpu_index
, &sregs
);
242 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
243 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
244 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
245 if (kvm_has_msr_star
)
246 set_msr_entry(&msrs
[n
++], MSR_STAR
, env
->star
);
247 set_msr_entry(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
249 if (lm_capable_kernel
) {
250 set_msr_entry(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
251 set_msr_entry(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
252 set_msr_entry(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
253 set_msr_entry(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
257 rc
= kvm_set_msrs(kvm_context
, env
->cpu_index
, msrs
, n
);
259 perror("kvm_set_msrs FAILED");
262 void kvm_save_mpstate(CPUState
*env
)
264 #ifdef KVM_CAP_MP_STATE
266 struct kvm_mp_state mp_state
;
268 r
= kvm_get_mpstate(kvm_context
, env
->cpu_index
, &mp_state
);
272 env
->mp_state
= mp_state
.mp_state
;
276 void kvm_load_mpstate(CPUState
*env
)
278 #ifdef KVM_CAP_MP_STATE
279 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
282 * -1 indicates that the host did not support GET_MP_STATE ioctl,
285 if (env
->mp_state
!= -1)
286 kvm_set_mpstate(kvm_context
, env
->cpu_index
, &mp_state
);
290 void kvm_arch_save_regs(CPUState
*env
)
292 struct kvm_regs regs
;
294 struct kvm_sregs sregs
;
295 struct kvm_msr_entry msrs
[MSR_COUNT
];
299 kvm_get_regs(kvm_context
, env
->cpu_index
, ®s
);
301 env
->regs
[R_EAX
] = regs
.rax
;
302 env
->regs
[R_EBX
] = regs
.rbx
;
303 env
->regs
[R_ECX
] = regs
.rcx
;
304 env
->regs
[R_EDX
] = regs
.rdx
;
305 env
->regs
[R_ESI
] = regs
.rsi
;
306 env
->regs
[R_EDI
] = regs
.rdi
;
307 env
->regs
[R_ESP
] = regs
.rsp
;
308 env
->regs
[R_EBP
] = regs
.rbp
;
310 env
->regs
[8] = regs
.r8
;
311 env
->regs
[9] = regs
.r9
;
312 env
->regs
[10] = regs
.r10
;
313 env
->regs
[11] = regs
.r11
;
314 env
->regs
[12] = regs
.r12
;
315 env
->regs
[13] = regs
.r13
;
316 env
->regs
[14] = regs
.r14
;
317 env
->regs
[15] = regs
.r15
;
320 env
->eflags
= regs
.rflags
;
323 kvm_get_fpu(kvm_context
, env
->cpu_index
, &fpu
);
324 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
327 for (i
= 0; i
< 8; ++i
)
328 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
329 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
330 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
331 env
->mxcsr
= fpu
.mxcsr
;
333 kvm_get_sregs(kvm_context
, env
->cpu_index
, &sregs
);
335 memcpy(env
->kvm_interrupt_bitmap
, sregs
.interrupt_bitmap
, sizeof(env
->kvm_interrupt_bitmap
));
337 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
338 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
339 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
340 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
341 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
342 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
344 get_seg(&env
->tr
, &sregs
.tr
);
345 get_seg(&env
->ldt
, &sregs
.ldt
);
347 env
->idt
.limit
= sregs
.idt
.limit
;
348 env
->idt
.base
= sregs
.idt
.base
;
349 env
->gdt
.limit
= sregs
.gdt
.limit
;
350 env
->gdt
.base
= sregs
.gdt
.base
;
352 env
->cr
[0] = sregs
.cr0
;
353 env
->cr
[2] = sregs
.cr2
;
354 env
->cr
[3] = sregs
.cr3
;
355 env
->cr
[4] = sregs
.cr4
;
357 cpu_set_apic_base(env
, sregs
.apic_base
);
359 env
->efer
= sregs
.efer
;
360 //cpu_set_apic_tpr(env, sregs.cr8);
362 #define HFLAG_COPY_MASK ~( \
363 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
364 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
365 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
366 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
370 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
371 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
372 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
373 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
374 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
375 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
376 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
378 if (env
->efer
& MSR_EFER_LMA
) {
379 hflags
|= HF_LMA_MASK
;
382 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
383 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
385 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
386 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
387 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
388 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
389 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
390 (env
->eflags
& VM_MASK
) ||
391 !(hflags
& HF_CS32_MASK
)) {
392 hflags
|= HF_ADDSEG_MASK
;
394 hflags
|= ((env
->segs
[R_DS
].base
|
395 env
->segs
[R_ES
].base
|
396 env
->segs
[R_SS
].base
) != 0) <<
400 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
401 env
->cc_src
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
402 env
->df
= 1 - (2 * ((env
->eflags
>> 10) & 1));
403 env
->cc_op
= CC_OP_EFLAGS
;
404 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
408 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
409 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
410 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
411 if (kvm_has_msr_star
)
412 msrs
[n
++].index
= MSR_STAR
;
413 msrs
[n
++].index
= MSR_IA32_TSC
;
415 if (lm_capable_kernel
) {
416 msrs
[n
++].index
= MSR_CSTAR
;
417 msrs
[n
++].index
= MSR_KERNELGSBASE
;
418 msrs
[n
++].index
= MSR_FMASK
;
419 msrs
[n
++].index
= MSR_LSTAR
;
422 rc
= kvm_get_msrs(kvm_context
, env
->cpu_index
, msrs
, n
);
424 perror("kvm_get_msrs FAILED");
427 n
= rc
; /* actual number of MSRs */
428 for (i
=0 ; i
<n
; i
++) {
429 if (get_msr_entry(&msrs
[i
], env
))
435 static void host_cpuid(uint32_t function
, uint32_t *eax
, uint32_t *ebx
,
436 uint32_t *ecx
, uint32_t *edx
)
442 : "=a"(vec
[0]), "=b"(vec
[1]),
443 "=c"(vec
[2]), "=d"(vec
[3])
444 : "0"(function
) : "cc");
446 asm volatile("pusha \n\t"
448 "mov %%eax, 0(%1) \n\t"
449 "mov %%ebx, 4(%1) \n\t"
450 "mov %%ecx, 8(%1) \n\t"
451 "mov %%edx, 12(%1) \n\t"
453 : : "a"(function
), "S"(vec
)
468 static void do_cpuid_ent(struct kvm_cpuid_entry
*e
, uint32_t function
,
471 env
->regs
[R_EAX
] = function
;
472 qemu_kvm_cpuid_on_env(env
);
473 e
->function
= function
;
474 e
->eax
= env
->regs
[R_EAX
];
475 e
->ebx
= env
->regs
[R_EBX
];
476 e
->ecx
= env
->regs
[R_ECX
];
477 e
->edx
= env
->regs
[R_EDX
];
478 if (function
== 0x80000001) {
479 uint32_t h_eax
, h_edx
;
481 host_cpuid(function
, &h_eax
, NULL
, NULL
, &h_edx
);
484 if ((h_edx
& 0x20000000) == 0 || !lm_capable_kernel
)
485 e
->edx
&= ~0x20000000u
;
487 if ((h_edx
& 0x00000800) == 0)
488 e
->edx
&= ~0x00000800u
;
490 if ((h_edx
& 0x00100000) == 0)
491 e
->edx
&= ~0x00100000u
;
496 // sysenter isn't supported on compatibility mode on AMD. and syscall
497 // isn't supported in compatibility mode on Intel. so advertise the
498 // actuall cpu, and say goodbye to migration between different vendors
499 // is you use compatibility mode.
503 host_cpuid(0, NULL
, &bcd
[0], &bcd
[1], &bcd
[2]);
508 // "Hypervisor present" bit for Microsoft guests
510 e
->ecx
|= (1u << 31);
512 // 3dnow isn't properly emulated yet
513 if (function
== 0x80000001)
514 e
->edx
&= ~0xc0000000;
517 struct kvm_para_features
{
520 } para_features
[] = {
521 #ifdef KVM_CAP_CLOCKSOURCE
522 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
524 #ifdef KVM_CAP_NOP_IO_DELAY
525 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
527 #ifdef KVM_CAP_PV_MMU
528 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
530 #ifdef KVM_CAP_CR3_CACHE
531 { KVM_CAP_CR3_CACHE
, KVM_FEATURE_CR3_CACHE
},
536 static int get_para_features(kvm_context_t kvm_context
)
540 for (i
= 0; i
< ARRAY_SIZE(para_features
)-1; i
++) {
541 if (kvm_check_extension(kvm_context
, para_features
[i
].cap
))
542 features
|= (1 << para_features
[i
].feature
);
548 int kvm_arch_qemu_init_env(CPUState
*cenv
)
550 struct kvm_cpuid_entry cpuid_ent
[100];
551 #ifdef KVM_CPUID_SIGNATURE
552 struct kvm_cpuid_entry
*pv_ent
;
553 uint32_t signature
[3];
561 #ifdef KVM_CPUID_SIGNATURE
562 /* Paravirtualization CPUIDs */
563 memcpy(signature
, "KVMKVMKVM", 12);
564 pv_ent
= &cpuid_ent
[cpuid_nent
++];
565 memset(pv_ent
, 0, sizeof(*pv_ent
));
566 pv_ent
->function
= KVM_CPUID_SIGNATURE
;
568 pv_ent
->ebx
= signature
[0];
569 pv_ent
->ecx
= signature
[1];
570 pv_ent
->edx
= signature
[2];
572 pv_ent
= &cpuid_ent
[cpuid_nent
++];
573 memset(pv_ent
, 0, sizeof(*pv_ent
));
574 pv_ent
->function
= KVM_CPUID_FEATURES
;
575 pv_ent
->eax
= get_para_features(kvm_context
);
578 copy
.regs
[R_EAX
] = 0;
579 qemu_kvm_cpuid_on_env(©
);
580 limit
= copy
.regs
[R_EAX
];
582 for (i
= 0; i
<= limit
; ++i
)
583 do_cpuid_ent(&cpuid_ent
[cpuid_nent
++], i
, ©
);
585 copy
.regs
[R_EAX
] = 0x80000000;
586 qemu_kvm_cpuid_on_env(©
);
587 limit
= copy
.regs
[R_EAX
];
589 for (i
= 0x80000000; i
<= limit
; ++i
)
590 do_cpuid_ent(&cpuid_ent
[cpuid_nent
++], i
, ©
);
592 kvm_setup_cpuid(kvm_context
, cenv
->cpu_index
, cpuid_nent
, cpuid_ent
);
596 int kvm_arch_halt(void *opaque
, int vcpu
)
598 CPUState
*env
= cpu_single_env
;
600 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
601 (env
->eflags
& IF_MASK
))) {
602 env
->hflags
|= HF_HALTED_MASK
;
603 env
->exception_index
= EXCP_HLT
;
608 void kvm_arch_pre_kvm_run(void *opaque
, int vcpu
)
610 CPUState
*env
= cpu_single_env
;
612 if (!kvm_irqchip_in_kernel(kvm_context
))
613 kvm_set_cr8(kvm_context
, vcpu
, cpu_get_apic_tpr(env
));
616 void kvm_arch_post_kvm_run(void *opaque
, int vcpu
)
618 CPUState
*env
= qemu_kvm_cpu_env(vcpu
);
619 cpu_single_env
= env
;
621 env
->eflags
= kvm_get_interrupt_flag(kvm_context
, vcpu
)
622 ? env
->eflags
| IF_MASK
: env
->eflags
& ~IF_MASK
;
623 env
->ready_for_interrupt_injection
624 = kvm_is_ready_for_interrupt_injection(kvm_context
, vcpu
);
626 cpu_set_apic_tpr(env
, kvm_get_cr8(kvm_context
, vcpu
));
627 cpu_set_apic_base(env
, kvm_get_apic_base(kvm_context
, vcpu
));
630 int kvm_arch_has_work(CPUState
*env
)
632 if ((env
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_EXIT
)) &&
633 (env
->eflags
& IF_MASK
))
638 int kvm_arch_try_push_interrupts(void *opaque
)
640 CPUState
*env
= cpu_single_env
;
643 if (env
->ready_for_interrupt_injection
&&
644 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
645 (env
->eflags
& IF_MASK
)) {
646 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
647 irq
= cpu_get_pic_interrupt(env
);
649 r
= kvm_inject_irq(kvm_context
, env
->cpu_index
, irq
);
651 printf("cpu %d fail inject %x\n", env
->cpu_index
, irq
);
655 return (env
->interrupt_request
& CPU_INTERRUPT_HARD
) != 0;
658 void kvm_arch_update_regs_for_sipi(CPUState
*env
)
660 SegmentCache cs
= env
->segs
[R_CS
];
662 kvm_arch_save_regs(env
);
663 env
->segs
[R_CS
] = cs
;
665 kvm_arch_load_regs(env
);
668 int handle_tpr_access(void *opaque
, int vcpu
,
669 uint64_t rip
, int is_write
)
671 kvm_tpr_access_report(cpu_single_env
, rip
, is_write
);
675 void kvm_arch_cpu_reset(CPUState
*env
)
677 struct kvm_mp_state mp_state
= { .mp_state
= KVM_MP_STATE_UNINITIALIZED
};
679 kvm_arch_load_regs(env
);
680 if (env
->cpu_index
!= 0) {
681 if (kvm_irqchip_in_kernel(kvm_context
))
682 kvm_set_mpstate(kvm_context
, env
->cpu_index
, &mp_state
);
684 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
685 env
->hflags
|= HF_HALTED_MASK
;
686 env
->exception_index
= EXCP_HLT
;