cpu-all.h

   1 /*
   2  * defines common to all virtual CPUs
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ALL_H
  21 #define CPU_ALL_H
  22
  23 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
  24 #define WORDS_ALIGNED
  25 #endif
  26
  27 /* some important defines:
  28  *
  29  * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
  30  * memory accesses.
  31  *
  32  * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
  33  * otherwise little endian.
  34  *
  35  * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
  36  *
  37  * TARGET_WORDS_BIGENDIAN : same for target cpu
  38  */
  39
  40 #include "bswap.h"
  41 #include "softfloat.h"
  42
  43 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
  44 #define BSWAP_NEEDED
  45 #endif
  46
  47 #ifdef BSWAP_NEEDED
  48
  49 static inline uint16_t tswap16(uint16_t s)
  50 {
  51     return bswap16(s);
  52 }
  53
  54 static inline uint32_t tswap32(uint32_t s)
  55 {
  56     return bswap32(s);
  57 }
  58
  59 static inline uint64_t tswap64(uint64_t s)
  60 {
  61     return bswap64(s);
  62 }
  63
  64 static inline void tswap16s(uint16_t *s)
  65 {
  66     *s = bswap16(*s);
  67 }
  68
  69 static inline void tswap32s(uint32_t *s)
  70 {
  71     *s = bswap32(*s);
  72 }
  73
  74 static inline void tswap64s(uint64_t *s)
  75 {
  76     *s = bswap64(*s);
  77 }
  78
  79 #else
  80
  81 static inline uint16_t tswap16(uint16_t s)
  82 {
  83     return s;
  84 }
  85
  86 static inline uint32_t tswap32(uint32_t s)
  87 {
  88     return s;
  89 }
  90
  91 static inline uint64_t tswap64(uint64_t s)
  92 {
  93     return s;
  94 }
  95
  96 static inline void tswap16s(uint16_t *s)
  97 {
  98 }
  99
 100 static inline void tswap32s(uint32_t *s)
 101 {
 102 }
 103
 104 static inline void tswap64s(uint64_t *s)
 105 {
 106 }
 107
 108 #endif
 109
 110 #if TARGET_LONG_SIZE == 4
 111 #define tswapl(s) tswap32(s)
 112 #define tswapls(s) tswap32s((uint32_t *)(s))
 113 #define bswaptls(s) bswap32s(s)
 114 #else
 115 #define tswapl(s) tswap64(s)
 116 #define tswapls(s) tswap64s((uint64_t *)(s))
 117 #define bswaptls(s) bswap64s(s)
 118 #endif
 119
 120 typedef union {
 121     float32 f;
 122     uint32_t l;
 123 } CPU_FloatU;
 124
 125 /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
 126    endian ! */
 127 typedef union {
 128     float64 d;
 129 #if defined(WORDS_BIGENDIAN) \
 130     || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
 131     struct {
 132         uint32_t upper;
 133         uint32_t lower;
 134     } l;
 135 #else
 136     struct {
 137         uint32_t lower;
 138         uint32_t upper;
 139     } l;
 140 #endif
 141     uint64_t ll;
 142 } CPU_DoubleU;
 143
 144 #ifdef TARGET_SPARC
 145 typedef union {
 146     float128 q;
 147 #if defined(WORDS_BIGENDIAN) \
 148     || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
 149     struct {
 150         uint32_t upmost;
 151         uint32_t upper;
 152         uint32_t lower;
 153         uint32_t lowest;
 154     } l;
 155     struct {
 156         uint64_t upper;
 157         uint64_t lower;
 158     } ll;
 159 #else
 160     struct {
 161         uint32_t lowest;
 162         uint32_t lower;
 163         uint32_t upper;
 164         uint32_t upmost;
 165     } l;
 166     struct {
 167         uint64_t lower;
 168         uint64_t upper;
 169     } ll;
 170 #endif
 171 } CPU_QuadU;
 172 #endif
 173
 174 /* CPU memory access without any memory or io remapping */
 175
 176 /*
 177  * the generic syntax for the memory accesses is:
 178  *
 179  * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
 180  *
 181  * store: st{type}{size}{endian}_{access_type}(ptr, val)
 182  *
 183  * type is:
 184  * (empty): integer access
 185  *   f    : float access
 186  *
 187  * sign is:
 188  * (empty): for floats or 32 bit size
 189  *   u    : unsigned
 190  *   s    : signed
 191  *
 192  * size is:
 193  *   b: 8 bits
 194  *   w: 16 bits
 195  *   l: 32 bits
 196  *   q: 64 bits
 197  *
 198  * endian is:
 199  * (empty): target cpu endianness or 8 bit access
 200  *   r    : reversed target cpu endianness (not implemented yet)
 201  *   be   : big endian (not implemented yet)
 202  *   le   : little endian (not implemented yet)
 203  *
 204  * access_type is:
 205  *   raw    : host memory access
 206  *   user   : user mode access using soft MMU
 207  *   kernel : kernel mode access using soft MMU
 208  */
 209 static inline int ldub_p(void *ptr)
 210 {
 211     return *(uint8_t *)ptr;
 212 }
 213
 214 static inline int ldsb_p(void *ptr)
 215 {
 216     return *(int8_t *)ptr;
 217 }
 218
 219 static inline void stb_p(void *ptr, int v)
 220 {
 221     *(uint8_t *)ptr = v;
 222 }
 223
 224 /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
 225    kernel handles unaligned load/stores may give better results, but
 226    it is a system wide setting : bad */
 227 #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
 228
 229 /* conservative code for little endian unaligned accesses */
 230 static inline int lduw_le_p(void *ptr)
 231 {
 232 #ifdef __powerpc__
 233     int val;
 234     __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
 235     return val;
 236 #elif defined(__sparc__)
 237 #ifndef ASI_PRIMARY_LITTLE
 238 #define ASI_PRIMARY_LITTLE 0x88
 239 #endif
 240
 241     int val;
 242     __asm__ __volatile__ ("lduha [%1] %2, %0" : "=r" (val) : "r" (ptr),
 243                           "i" (ASI_PRIMARY_LITTLE));
 244     return val;
 245 #else
 246     uint8_t *p = ptr;
 247     return p[0] | (p[1] << 8);
 248 #endif
 249 }
 250
 251 static inline int ldsw_le_p(void *ptr)
 252 {
 253 #ifdef __powerpc__
 254     int val;
 255     __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
 256     return (int16_t)val;
 257 #elif defined(__sparc__)
 258     int val;
 259     __asm__ __volatile__ ("ldsha [%1] %2, %0" : "=r" (val) : "r" (ptr),
 260                           "i" (ASI_PRIMARY_LITTLE));
 261     return val;
 262 #else
 263     uint8_t *p = ptr;
 264     return (int16_t)(p[0] | (p[1] << 8));
 265 #endif
 266 }
 267
 268 static inline int ldl_le_p(void *ptr)
 269 {
 270 #ifdef __powerpc__
 271     int val;
 272     __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
 273     return val;
 274 #elif defined(__sparc__)
 275     int val;
 276     __asm__ __volatile__ ("lduwa [%1] %2, %0" : "=r" (val) : "r" (ptr),
 277                           "i" (ASI_PRIMARY_LITTLE));
 278     return val;
 279 #else
 280     uint8_t *p = ptr;
 281     return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
 282 #endif
 283 }
 284
 285 static inline uint64_t ldq_le_p(void *ptr)
 286 {
 287 #if defined(__sparc__)
 288     uint64_t val;
 289     __asm__ __volatile__ ("ldxa [%1] %2, %0" : "=r" (val) : "r" (ptr),
 290                           "i" (ASI_PRIMARY_LITTLE));
 291     return val;
 292 #else
 293     uint8_t *p = ptr;
 294     uint32_t v1, v2;
 295     v1 = ldl_le_p(p);
 296     v2 = ldl_le_p(p + 4);
 297     return v1 | ((uint64_t)v2 << 32);
 298 #endif
 299 }
 300
 301 static inline void stw_le_p(void *ptr, int v)
 302 {
 303 #ifdef __powerpc__
 304     __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
 305 #elif defined(__sparc__)
 306     __asm__ __volatile__ ("stha %1, [%2] %3" : "=m" (*(uint16_t *)ptr) : "r" (v),
 307                           "r" (ptr), "i" (ASI_PRIMARY_LITTLE));
 308 #else
 309     uint8_t *p = ptr;
 310     p[0] = v;
 311     p[1] = v >> 8;
 312 #endif
 313 }
 314
 315 static inline void stl_le_p(void *ptr, int v)
 316 {
 317 #ifdef __powerpc__
 318     __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
 319 #elif defined(__sparc__)
 320     __asm__ __volatile__ ("stwa %1, [%2] %3" : "=m" (*(uint32_t *)ptr) : "r" (v),
 321                           "r" (ptr), "i" (ASI_PRIMARY_LITTLE));
 322 #else
 323     uint8_t *p = ptr;
 324     p[0] = v;
 325     p[1] = v >> 8;
 326     p[2] = v >> 16;
 327     p[3] = v >> 24;
 328 #endif
 329 }
 330
 331 static inline void stq_le_p(void *ptr, uint64_t v)
 332 {
 333 #if defined(__sparc__)
 334     __asm__ __volatile__ ("stxa %1, [%2] %3" : "=m" (*(uint64_t *)ptr) : "r" (v),
 335                           "r" (ptr), "i" (ASI_PRIMARY_LITTLE));
 336 #undef ASI_PRIMARY_LITTLE
 337 #else
 338     uint8_t *p = ptr;
 339     stl_le_p(p, (uint32_t)v);
 340     stl_le_p(p + 4, v >> 32);
 341 #endif
 342 }
 343
 344 /* float access */
 345
 346 static inline float32 ldfl_le_p(void *ptr)
 347 {
 348     union {
 349         float32 f;
 350         uint32_t i;
 351     } u;
 352     u.i = ldl_le_p(ptr);
 353     return u.f;
 354 }
 355
 356 static inline void stfl_le_p(void *ptr, float32 v)
 357 {
 358     union {
 359         float32 f;
 360         uint32_t i;
 361     } u;
 362     u.f = v;
 363     stl_le_p(ptr, u.i);
 364 }
 365
 366 static inline float64 ldfq_le_p(void *ptr)
 367 {
 368     CPU_DoubleU u;
 369     u.l.lower = ldl_le_p(ptr);
 370     u.l.upper = ldl_le_p(ptr + 4);
 371     return u.d;
 372 }
 373
 374 static inline void stfq_le_p(void *ptr, float64 v)
 375 {
 376     CPU_DoubleU u;
 377     u.d = v;
 378     stl_le_p(ptr, u.l.lower);
 379     stl_le_p(ptr + 4, u.l.upper);
 380 }
 381
 382 #else
 383
 384 static inline int lduw_le_p(void *ptr)
 385 {
 386     return *(uint16_t *)ptr;
 387 }
 388
 389 static inline int ldsw_le_p(void *ptr)
 390 {
 391     return *(int16_t *)ptr;
 392 }
 393
 394 static inline int ldl_le_p(void *ptr)
 395 {
 396     return *(uint32_t *)ptr;
 397 }
 398
 399 static inline uint64_t ldq_le_p(void *ptr)
 400 {
 401     return *(uint64_t *)ptr;
 402 }
 403
 404 static inline void stw_le_p(void *ptr, int v)
 405 {
 406     *(uint16_t *)ptr = v;
 407 }
 408
 409 static inline void stl_le_p(void *ptr, int v)
 410 {
 411     *(uint32_t *)ptr = v;
 412 }
 413
 414 static inline void stq_le_p(void *ptr, uint64_t v)
 415 {
 416     *(uint64_t *)ptr = v;
 417 }
 418
 419 /* float access */
 420
 421 static inline float32 ldfl_le_p(void *ptr)
 422 {
 423     return *(float32 *)ptr;
 424 }
 425
 426 static inline float64 ldfq_le_p(void *ptr)
 427 {
 428     return *(float64 *)ptr;
 429 }
 430
 431 static inline void stfl_le_p(void *ptr, float32 v)
 432 {
 433     *(float32 *)ptr = v;
 434 }
 435
 436 static inline void stfq_le_p(void *ptr, float64 v)
 437 {
 438     *(float64 *)ptr = v;
 439 }
 440 #endif
 441
 442 #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
 443
 444 static inline int lduw_be_p(void *ptr)
 445 {
 446 #if defined(__i386__)
 447     int val;
 448     asm volatile ("movzwl %1, %0\n"
 449                   "xchgb %b0, %h0\n"
 450                   : "=q" (val)
 451                   : "m" (*(uint16_t *)ptr));
 452     return val;
 453 #else
 454     uint8_t *b = (uint8_t *) ptr;
 455     return ((b[0] << 8) | b[1]);
 456 #endif
 457 }
 458
 459 static inline int ldsw_be_p(void *ptr)
 460 {
 461 #if defined(__i386__)
 462     int val;
 463     asm volatile ("movzwl %1, %0\n"
 464                   "xchgb %b0, %h0\n"
 465                   : "=q" (val)
 466                   : "m" (*(uint16_t *)ptr));
 467     return (int16_t)val;
 468 #else
 469     uint8_t *b = (uint8_t *) ptr;
 470     return (int16_t)((b[0] << 8) | b[1]);
 471 #endif
 472 }
 473
 474 static inline int ldl_be_p(void *ptr)
 475 {
 476 #if defined(__i386__) || defined(__x86_64__)
 477     int val;
 478     asm volatile ("movl %1, %0\n"
 479                   "bswap %0\n"
 480                   : "=r" (val)
 481                   : "m" (*(uint32_t *)ptr));
 482     return val;
 483 #else
 484     uint8_t *b = (uint8_t *) ptr;
 485     return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
 486 #endif
 487 }
 488
 489 static inline uint64_t ldq_be_p(void *ptr)
 490 {
 491     uint32_t a,b;
 492     a = ldl_be_p(ptr);
 493     b = ldl_be_p((uint8_t *)ptr + 4);
 494     return (((uint64_t)a<<32)|b);
 495 }
 496
 497 static inline void stw_be_p(void *ptr, int v)
 498 {
 499 #if defined(__i386__)
 500     asm volatile ("xchgb %b0, %h0\n"
 501                   "movw %w0, %1\n"
 502                   : "=q" (v)
 503                   : "m" (*(uint16_t *)ptr), "0" (v));
 504 #else
 505     uint8_t *d = (uint8_t *) ptr;
 506     d[0] = v >> 8;
 507     d[1] = v;
 508 #endif
 509 }
 510
 511 static inline void stl_be_p(void *ptr, int v)
 512 {
 513 #if defined(__i386__) || defined(__x86_64__)
 514     asm volatile ("bswap %0\n"
 515                   "movl %0, %1\n"
 516                   : "=r" (v)
 517                   : "m" (*(uint32_t *)ptr), "0" (v));
 518 #else
 519     uint8_t *d = (uint8_t *) ptr;
 520     d[0] = v >> 24;
 521     d[1] = v >> 16;
 522     d[2] = v >> 8;
 523     d[3] = v;
 524 #endif
 525 }
 526
 527 static inline void stq_be_p(void *ptr, uint64_t v)
 528 {
 529     stl_be_p(ptr, v >> 32);
 530     stl_be_p((uint8_t *)ptr + 4, v);
 531 }
 532
 533 /* float access */
 534
 535 static inline float32 ldfl_be_p(void *ptr)
 536 {
 537     union {
 538         float32 f;
 539         uint32_t i;
 540     } u;
 541     u.i = ldl_be_p(ptr);
 542     return u.f;
 543 }
 544
 545 static inline void stfl_be_p(void *ptr, float32 v)
 546 {
 547     union {
 548         float32 f;
 549         uint32_t i;
 550     } u;
 551     u.f = v;
 552     stl_be_p(ptr, u.i);
 553 }
 554
 555 static inline float64 ldfq_be_p(void *ptr)
 556 {
 557     CPU_DoubleU u;
 558     u.l.upper = ldl_be_p(ptr);
 559     u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
 560     return u.d;
 561 }
 562
 563 static inline void stfq_be_p(void *ptr, float64 v)
 564 {
 565     CPU_DoubleU u;
 566     u.d = v;
 567     stl_be_p(ptr, u.l.upper);
 568     stl_be_p((uint8_t *)ptr + 4, u.l.lower);
 569 }
 570
 571 #else
 572
 573 static inline int lduw_be_p(void *ptr)
 574 {
 575     return *(uint16_t *)ptr;
 576 }
 577
 578 static inline int ldsw_be_p(void *ptr)
 579 {
 580     return *(int16_t *)ptr;
 581 }
 582
 583 static inline int ldl_be_p(void *ptr)
 584 {
 585     return *(uint32_t *)ptr;
 586 }
 587
 588 static inline uint64_t ldq_be_p(void *ptr)
 589 {
 590     return *(uint64_t *)ptr;
 591 }
 592
 593 static inline void stw_be_p(void *ptr, int v)
 594 {
 595     *(uint16_t *)ptr = v;
 596 }
 597
 598 static inline void stl_be_p(void *ptr, int v)
 599 {
 600     *(uint32_t *)ptr = v;
 601 }
 602
 603 static inline void stq_be_p(void *ptr, uint64_t v)
 604 {
 605     *(uint64_t *)ptr = v;
 606 }
 607
 608 /* float access */
 609
 610 static inline float32 ldfl_be_p(void *ptr)
 611 {
 612     return *(float32 *)ptr;
 613 }
 614
 615 static inline float64 ldfq_be_p(void *ptr)
 616 {
 617     return *(float64 *)ptr;
 618 }
 619
 620 static inline void stfl_be_p(void *ptr, float32 v)
 621 {
 622     *(float32 *)ptr = v;
 623 }
 624
 625 static inline void stfq_be_p(void *ptr, float64 v)
 626 {
 627     *(float64 *)ptr = v;
 628 }
 629
 630 #endif
 631
 632 /* target CPU memory access functions */
 633 #if defined(TARGET_WORDS_BIGENDIAN)
 634 #define lduw_p(p) lduw_be_p(p)
 635 #define ldsw_p(p) ldsw_be_p(p)
 636 #define ldl_p(p) ldl_be_p(p)
 637 #define ldq_p(p) ldq_be_p(p)
 638 #define ldfl_p(p) ldfl_be_p(p)
 639 #define ldfq_p(p) ldfq_be_p(p)
 640 #define stw_p(p, v) stw_be_p(p, v)
 641 #define stl_p(p, v) stl_be_p(p, v)
 642 #define stq_p(p, v) stq_be_p(p, v)
 643 #define stfl_p(p, v) stfl_be_p(p, v)
 644 #define stfq_p(p, v) stfq_be_p(p, v)
 645 #else
 646 #define lduw_p(p) lduw_le_p(p)
 647 #define ldsw_p(p) ldsw_le_p(p)
 648 #define ldl_p(p) ldl_le_p(p)
 649 #define ldq_p(p) ldq_le_p(p)
 650 #define ldfl_p(p) ldfl_le_p(p)
 651 #define ldfq_p(p) ldfq_le_p(p)
 652 #define stw_p(p, v) stw_le_p(p, v)
 653 #define stl_p(p, v) stl_le_p(p, v)
 654 #define stq_p(p, v) stq_le_p(p, v)
 655 #define stfl_p(p, v) stfl_le_p(p, v)
 656 #define stfq_p(p, v) stfq_le_p(p, v)
 657 #endif
 658
 659 /* MMU memory access macros */
 660
 661 #if defined(CONFIG_USER_ONLY)
 662 /* On some host systems the guest address space is reserved on the host.
 663  * This allows the guest address space to be offset to a convenient location.
 664  */
 665 //#define GUEST_BASE 0x20000000
 666 #define GUEST_BASE 0
 667
 668 /* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
 669 #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
 670 #define h2g(x) ((target_ulong)(x - GUEST_BASE))
 671
 672 #define saddr(x) g2h(x)
 673 #define laddr(x) g2h(x)
 674
 675 #else /* !CONFIG_USER_ONLY */
 676 /* NOTE: we use double casts if pointers and target_ulong have
 677    different sizes */
 678 #define saddr(x) (uint8_t *)(long)(x)
 679 #define laddr(x) (uint8_t *)(long)(x)
 680 #endif
 681
 682 #define ldub_raw(p) ldub_p(laddr((p)))
 683 #define ldsb_raw(p) ldsb_p(laddr((p)))
 684 #define lduw_raw(p) lduw_p(laddr((p)))
 685 #define ldsw_raw(p) ldsw_p(laddr((p)))
 686 #define ldl_raw(p) ldl_p(laddr((p)))
 687 #define ldq_raw(p) ldq_p(laddr((p)))
 688 #define ldfl_raw(p) ldfl_p(laddr((p)))
 689 #define ldfq_raw(p) ldfq_p(laddr((p)))
 690 #define stb_raw(p, v) stb_p(saddr((p)), v)
 691 #define stw_raw(p, v) stw_p(saddr((p)), v)
 692 #define stl_raw(p, v) stl_p(saddr((p)), v)
 693 #define stq_raw(p, v) stq_p(saddr((p)), v)
 694 #define stfl_raw(p, v) stfl_p(saddr((p)), v)
 695 #define stfq_raw(p, v) stfq_p(saddr((p)), v)
 696
 697
 698 #if defined(CONFIG_USER_ONLY)
 699
 700 /* if user mode, no other memory access functions */
 701 #define ldub(p) ldub_raw(p)
 702 #define ldsb(p) ldsb_raw(p)
 703 #define lduw(p) lduw_raw(p)
 704 #define ldsw(p) ldsw_raw(p)
 705 #define ldl(p) ldl_raw(p)
 706 #define ldq(p) ldq_raw(p)
 707 #define ldfl(p) ldfl_raw(p)
 708 #define ldfq(p) ldfq_raw(p)
 709 #define stb(p, v) stb_raw(p, v)
 710 #define stw(p, v) stw_raw(p, v)
 711 #define stl(p, v) stl_raw(p, v)
 712 #define stq(p, v) stq_raw(p, v)
 713 #define stfl(p, v) stfl_raw(p, v)
 714 #define stfq(p, v) stfq_raw(p, v)
 715
 716 #define ldub_code(p) ldub_raw(p)
 717 #define ldsb_code(p) ldsb_raw(p)
 718 #define lduw_code(p) lduw_raw(p)
 719 #define ldsw_code(p) ldsw_raw(p)
 720 #define ldl_code(p) ldl_raw(p)
 721 #define ldq_code(p) ldq_raw(p)
 722
 723 #define ldub_kernel(p) ldub_raw(p)
 724 #define ldsb_kernel(p) ldsb_raw(p)
 725 #define lduw_kernel(p) lduw_raw(p)
 726 #define ldsw_kernel(p) ldsw_raw(p)
 727 #define ldl_kernel(p) ldl_raw(p)
 728 #define ldq_kernel(p) ldq_raw(p)
 729 #define ldfl_kernel(p) ldfl_raw(p)
 730 #define ldfq_kernel(p) ldfq_raw(p)
 731 #define stb_kernel(p, v) stb_raw(p, v)
 732 #define stw_kernel(p, v) stw_raw(p, v)
 733 #define stl_kernel(p, v) stl_raw(p, v)
 734 #define stq_kernel(p, v) stq_raw(p, v)
 735 #define stfl_kernel(p, v) stfl_raw(p, v)
 736 #define stfq_kernel(p, vt) stfq_raw(p, v)
 737
 738 #endif /* defined(CONFIG_USER_ONLY) */
 739
 740 /* page related stuff */
 741
 742 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
 743 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
 744 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
 745
 746 /* ??? These should be the larger of unsigned long and target_ulong.  */
 747 extern unsigned long qemu_real_host_page_size;
 748 extern unsigned long qemu_host_page_bits;
 749 extern unsigned long qemu_host_page_size;
 750 extern unsigned long qemu_host_page_mask;
 751
 752 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
 753
 754 /* same as PROT_xxx */
 755 #define PAGE_READ      0x0001
 756 #define PAGE_WRITE     0x0002
 757 #define PAGE_EXEC      0x0004
 758 #define PAGE_BITS      (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
 759 #define PAGE_VALID     0x0008
 760 /* original state of the write flag (used when tracking self-modifying
 761    code */
 762 #define PAGE_WRITE_ORG 0x0010
 763 #define PAGE_RESERVED  0x0020
 764
 765 void page_dump(FILE *f);
 766 int page_get_flags(target_ulong address);
 767 void page_set_flags(target_ulong start, target_ulong end, int flags);
 768 int page_check_range(target_ulong start, target_ulong len, int flags);
 769
 770 void cpu_exec_init_all(unsigned long tb_size);
 771 CPUState *cpu_copy(CPUState *env);
 772
 773 void cpu_dump_state(CPUState *env, FILE *f,
 774                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
 775                     int flags);
 776 void cpu_dump_statistics (CPUState *env, FILE *f,
 777                           int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
 778                           int flags);
 779
 780 void cpu_abort(CPUState *env, const char *fmt, ...)
 781     __attribute__ ((__format__ (__printf__, 2, 3)))
 782     __attribute__ ((__noreturn__));
 783 extern CPUState *first_cpu;
 784 extern CPUState *cpu_single_env;
 785 extern int64_t qemu_icount;
 786 extern int use_icount;
 787
 788 #define CPU_INTERRUPT_EXIT   0x01 /* wants exit from main loop */
 789 #define CPU_INTERRUPT_HARD   0x02 /* hardware interrupt pending */
 790 #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
 791 #define CPU_INTERRUPT_TIMER  0x08 /* internal timer exception pending */
 792 #define CPU_INTERRUPT_FIQ    0x10 /* Fast interrupt pending.  */
 793 #define CPU_INTERRUPT_HALT   0x20 /* CPU halt wanted */
 794 #define CPU_INTERRUPT_SMI    0x40 /* (x86 only) SMI interrupt pending */
 795 #define CPU_INTERRUPT_DEBUG  0x80 /* Debug event occured.  */
 796 #define CPU_INTERRUPT_VIRQ   0x100 /* virtual interrupt pending.  */
 797 #define CPU_INTERRUPT_NMI    0x200 /* NMI pending. */
 798
 799 void cpu_interrupt(CPUState *s, int mask);
 800 void cpu_reset_interrupt(CPUState *env, int mask);
 801
 802 int cpu_watchpoint_insert(CPUState *env, target_ulong addr, int type);
 803 int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
 804 void cpu_watchpoint_remove_all(CPUState *env);
 805 int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
 806 int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
 807 void cpu_breakpoint_remove_all(CPUState *env);
 808
 809 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 810 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 811 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 812
 813 void cpu_single_step(CPUState *env, int enabled);
 814 void cpu_reset(CPUState *s);
 815
 816 /* Return the physical page corresponding to a virtual one. Use it
 817    only for debugging because no protection checks are done. Return -1
 818    if no page found. */
 819 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
 820
 821 #define CPU_LOG_TB_OUT_ASM (1 << 0)
 822 #define CPU_LOG_TB_IN_ASM  (1 << 1)
 823 #define CPU_LOG_TB_OP      (1 << 2)
 824 #define CPU_LOG_TB_OP_OPT  (1 << 3)
 825 #define CPU_LOG_INT        (1 << 4)
 826 #define CPU_LOG_EXEC       (1 << 5)
 827 #define CPU_LOG_PCALL      (1 << 6)
 828 #define CPU_LOG_IOPORT     (1 << 7)
 829 #define CPU_LOG_TB_CPU     (1 << 8)
 830
 831 /* define log items */
 832 typedef struct CPULogItem {
 833     int mask;
 834     const char *name;
 835     const char *help;
 836 } CPULogItem;
 837
 838 extern CPULogItem cpu_log_items[];
 839
 840 void cpu_set_log(int log_flags);
 841 void cpu_set_log_filename(const char *filename);
 842 int cpu_str_to_log_mask(const char *str);
 843
 844 /* IO ports API */
 845
 846 /* NOTE: as these functions may be even used when there is an isa
 847    brige on non x86 targets, we always defined them */
 848 #ifndef NO_CPU_IO_DEFS
 849 void cpu_outb(CPUState *env, int addr, int val);
 850 void cpu_outw(CPUState *env, int addr, int val);
 851 void cpu_outl(CPUState *env, int addr, int val);
 852 int cpu_inb(CPUState *env, int addr);
 853 int cpu_inw(CPUState *env, int addr);
 854 int cpu_inl(CPUState *env, int addr);
 855 #endif
 856
 857 /* address in the RAM (different from a physical address) */
 858 #ifdef USE_KQEMU
 859 typedef uint32_t ram_addr_t;
 860 #else
 861 typedef unsigned long ram_addr_t;
 862 #endif
 863
 864 /* memory API */
 865
 866 extern ram_addr_t phys_ram_size;
 867 extern int phys_ram_fd;
 868 extern uint8_t *phys_ram_base;
 869 extern uint8_t *phys_ram_dirty;
 870 extern ram_addr_t ram_size;
 871
 872 /* physical memory access */
 873
 874 /* MMIO pages are identified by a combination of an IO device index and
 875    3 flags.  The ROMD code stores the page ram offset in iotlb entry,
 876    so only a limited number of ids are avaiable.  */
 877
 878 #define IO_MEM_SHIFT       3
 879 #define IO_MEM_NB_ENTRIES  (1 << (TARGET_PAGE_BITS  - IO_MEM_SHIFT))
 880
 881 #define IO_MEM_RAM         (0 << IO_MEM_SHIFT) /* hardcoded offset */
 882 #define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */
 883 #define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
 884 #define IO_MEM_NOTDIRTY    (3 << IO_MEM_SHIFT)
 885
 886 /* Acts like a ROM when read and like a device when written.  */
 887 #define IO_MEM_ROMD        (1)
 888 #define IO_MEM_SUBPAGE     (2)
 889 #define IO_MEM_SUBWIDTH    (4)
 890
 891 /* Flags stored in the low bits of the TLB virtual address.  These are
 892    defined so that fast path ram access is all zeros.  */
 893 /* Zero if TLB entry is valid.  */
 894 #define TLB_INVALID_MASK   (1 << 3)
 895 /* Set if TLB entry references a clean RAM page.  The iotlb entry will
 896    contain the page physical address.  */
 897 #define TLB_NOTDIRTY    (1 << 4)
 898 /* Set if TLB entry is an IO callback.  */
 899 #define TLB_MMIO        (1 << 5)
 900
 901 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
 902 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
 903
 904 void cpu_register_physical_memory(target_phys_addr_t start_addr,
 905                                   ram_addr_t size,
 906                                   ram_addr_t phys_offset);
 907 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
 908 ram_addr_t qemu_ram_alloc(ram_addr_t);
 909 void qemu_ram_free(ram_addr_t addr);
 910 int cpu_register_io_memory(int io_index,
 911                            CPUReadMemoryFunc **mem_read,
 912                            CPUWriteMemoryFunc **mem_write,
 913                            void *opaque);
 914 CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
 915 CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
 916
 917 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
 918                             int len, int is_write);
 919 static inline void cpu_physical_memory_read(target_phys_addr_t addr,
 920                                             uint8_t *buf, int len)
 921 {
 922     cpu_physical_memory_rw(addr, buf, len, 0);
 923 }
 924 static inline void cpu_physical_memory_write(target_phys_addr_t addr,
 925                                              const uint8_t *buf, int len)
 926 {
 927     cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
 928 }
 929 uint32_t ldub_phys(target_phys_addr_t addr);
 930 uint32_t lduw_phys(target_phys_addr_t addr);
 931 uint32_t ldl_phys(target_phys_addr_t addr);
 932 uint64_t ldq_phys(target_phys_addr_t addr);
 933 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
 934 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
 935 void stb_phys(target_phys_addr_t addr, uint32_t val);
 936 void stw_phys(target_phys_addr_t addr, uint32_t val);
 937 void stl_phys(target_phys_addr_t addr, uint32_t val);
 938 void stq_phys(target_phys_addr_t addr, uint64_t val);
 939
 940 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
 941                                    const uint8_t *buf, int len);
 942 int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
 943                         uint8_t *buf, int len, int is_write);
 944
 945 #define VGA_DIRTY_FLAG  0x01
 946 #define CODE_DIRTY_FLAG 0x02
 947
 948 /* read dirty bit (return 0 or 1) */
 949 static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
 950 {
 951     return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
 952 }
 953
 954 static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
 955                                                 int dirty_flags)
 956 {
 957     return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
 958 }
 959
 960 static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
 961 {
 962     phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
 963 }
 964
 965 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
 966                                      int dirty_flags);
 967 void cpu_tlb_update_dirty(CPUState *env);
 968
 969 void dump_exec_info(FILE *f,
 970                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 971
 972 /*******************************************/
 973 /* host CPU ticks (if available) */
 974
 975 #if defined(__powerpc__)
 976
 977 static inline uint32_t get_tbl(void)
 978 {
 979     uint32_t tbl;
 980     asm volatile("mftb %0" : "=r" (tbl));
 981     return tbl;
 982 }
 983
 984 static inline uint32_t get_tbu(void)
 985 {
 986         uint32_t tbl;
 987         asm volatile("mftbu %0" : "=r" (tbl));
 988         return tbl;
 989 }
 990
 991 static inline int64_t cpu_get_real_ticks(void)
 992 {
 993     uint32_t l, h, h1;
 994     /* NOTE: we test if wrapping has occurred */
 995     do {
 996         h = get_tbu();
 997         l = get_tbl();
 998         h1 = get_tbu();
 999     } while (h != h1);
1000     return ((int64_t)h << 32) | l;
1001 }
1002
1003 #elif defined(__i386__)
1004
1005 static inline int64_t cpu_get_real_ticks(void)
1006 {
1007     int64_t val;
1008     asm volatile ("rdtsc" : "=A" (val));
1009     return val;
1010 }
1011
1012 #elif defined(__x86_64__)
1013
1014 static inline int64_t cpu_get_real_ticks(void)
1015 {
1016     uint32_t low,high;
1017     int64_t val;
1018     asm volatile("rdtsc" : "=a" (low), "=d" (high));
1019     val = high;
1020     val <<= 32;
1021     val |= low;
1022     return val;
1023 }
1024
1025 #elif defined(__hppa__)
1026
1027 static inline int64_t cpu_get_real_ticks(void)
1028 {
1029     int val;
1030     asm volatile ("mfctl %%cr16, %0" : "=r"(val));
1031     return val;
1032 }
1033
1034 #elif defined(__ia64)
1035
1036 static inline int64_t cpu_get_real_ticks(void)
1037 {
1038         int64_t val;
1039         asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1040         return val;
1041 }
1042
1043 #elif defined(__s390__)
1044
1045 static inline int64_t cpu_get_real_ticks(void)
1046 {
1047     int64_t val;
1048     asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1049     return val;
1050 }
1051
1052 #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
1053
1054 static inline int64_t cpu_get_real_ticks (void)
1055 {
1056 #if     defined(_LP64)
1057         uint64_t        rval;
1058         asm volatile("rd %%tick,%0" : "=r"(rval));
1059         return rval;
1060 #else
1061         union {
1062                 uint64_t i64;
1063                 struct {
1064                         uint32_t high;
1065                         uint32_t low;
1066                 }       i32;
1067         } rval;
1068         asm volatile("rd %%tick,%1; srlx %1,32,%0"
1069                 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1070         return rval.i64;
1071 #endif
1072 }
1073
1074 #elif defined(__mips__)
1075
1076 static inline int64_t cpu_get_real_ticks(void)
1077 {
1078 #if __mips_isa_rev >= 2
1079     uint32_t count;
1080     static uint32_t cyc_per_count = 0;
1081
1082     if (!cyc_per_count)
1083         __asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count));
1084
1085     __asm__ __volatile__("rdhwr %1, $2" : "=r" (count));
1086     return (int64_t)(count * cyc_per_count);
1087 #else
1088     /* FIXME */
1089     static int64_t ticks = 0;
1090     return ticks++;
1091 #endif
1092 }
1093
1094 #else
1095 /* The host CPU doesn't have an easily accessible cycle counter.
1096    Just return a monotonically increasing value.  This will be
1097    totally wrong, but hopefully better than nothing.  */
1098 static inline int64_t cpu_get_real_ticks (void)
1099 {
1100     static int64_t ticks = 0;
1101     return ticks++;
1102 }
1103 #endif
1104
1105 /* profiling */
1106 #ifdef CONFIG_PROFILER
1107 static inline int64_t profile_getclock(void)
1108 {
1109     return cpu_get_real_ticks();
1110 }
1111
1112 extern int64_t kqemu_time, kqemu_time_start;
1113 extern int64_t qemu_time, qemu_time_start;
1114 extern int64_t tlb_flush_time;
1115 extern int64_t kqemu_exec_count;
1116 extern int64_t dev_time;
1117 extern int64_t kqemu_ret_int_count;
1118 extern int64_t kqemu_ret_excp_count;
1119 extern int64_t kqemu_ret_intr_count;
1120 #endif
1121
1122 #endif /* CPU_ALL_H */