hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33
  34 #define BIOS_FILENAME "ppc405_rom.bin"
  35 #undef BIOS_SIZE
  36 #define BIOS_SIZE (2048 * 1024)
  37
  38 #define KERNEL_LOAD_ADDR 0x00000000
  39 #define INITRD_LOAD_ADDR 0x01800000
  40
  41 #define USE_FLASH_BIOS
  42
  43 #define DEBUG_BOARD_INIT
  44
  45 /*****************************************************************************/
  46 /* PPC405EP reference board (IBM) */
  47 /* Standalone board with:
  48  * - PowerPC 405EP CPU
  49  * - SDRAM (0x00000000)
  50  * - Flash (0xFFF80000)
  51  * - SRAM  (0xFFF00000)
  52  * - NVRAM (0xF0000000)
  53  * - FPGA  (0xF0300000)
  54  */
  55 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  56 struct ref405ep_fpga_t {
  57     uint8_t reg0;
  58     uint8_t reg1;
  59 };
  60
  61 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  62 {
  63     ref405ep_fpga_t *fpga;
  64     uint32_t ret;
  65
  66     fpga = opaque;
  67     switch (addr) {
  68     case 0x0:
  69         ret = fpga->reg0;
  70         break;
  71     case 0x1:
  72         ret = fpga->reg1;
  73         break;
  74     default:
  75         ret = 0;
  76         break;
  77     }
  78
  79     return ret;
  80 }
  81
  82 static void ref405ep_fpga_writeb (void *opaque,
  83                                   target_phys_addr_t addr, uint32_t value)
  84 {
  85     ref405ep_fpga_t *fpga;
  86
  87     fpga = opaque;
  88     switch (addr) {
  89     case 0x0:
  90         /* Read only */
  91         break;
  92     case 0x1:
  93         fpga->reg1 = value;
  94         break;
  95     default:
  96         break;
  97     }
  98 }
  99
 100 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 101 {
 102     uint32_t ret;
 103
 104     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 105     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 106
 107     return ret;
 108 }
 109
 110 static void ref405ep_fpga_writew (void *opaque,
 111                                   target_phys_addr_t addr, uint32_t value)
 112 {
 113     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 114     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 115 }
 116
 117 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 118 {
 119     uint32_t ret;
 120
 121     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 122     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 123     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 124     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 125
 126     return ret;
 127 }
 128
 129 static void ref405ep_fpga_writel (void *opaque,
 130                                   target_phys_addr_t addr, uint32_t value)
 131 {
 132     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 133     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 134     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 135     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 136 }
 137
 138 static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
 139     &ref405ep_fpga_readb,
 140     &ref405ep_fpga_readw,
 141     &ref405ep_fpga_readl,
 142 };
 143
 144 static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
 145     &ref405ep_fpga_writeb,
 146     &ref405ep_fpga_writew,
 147     &ref405ep_fpga_writel,
 148 };
 149
 150 static void ref405ep_fpga_reset (void *opaque)
 151 {
 152     ref405ep_fpga_t *fpga;
 153
 154     fpga = opaque;
 155     fpga->reg0 = 0x00;
 156     fpga->reg1 = 0x0F;
 157 }
 158
 159 static void ref405ep_fpga_init (uint32_t base)
 160 {
 161     ref405ep_fpga_t *fpga;
 162     int fpga_memory;
 163
 164     fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
 165     fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
 166                                          ref405ep_fpga_write, fpga);
 167     cpu_register_physical_memory(base, 0x00000100, fpga_memory);
 168     ref405ep_fpga_reset(fpga);
 169     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 170 }
 171
 172 static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size,
 173                            const char *boot_device,
 174                            const char *kernel_filename,
 175                            const char *kernel_cmdline,
 176                            const char *initrd_filename,
 177                            const char *cpu_model)
 178 {
 179     char buf[1024];
 180     ppc4xx_bd_info_t bd;
 181     CPUPPCState *env;
 182     qemu_irq *pic;
 183     ram_addr_t sram_offset, bios_offset, bdloc;
 184     target_phys_addr_t ram_bases[2], ram_sizes[2];
 185     target_ulong sram_size, bios_size;
 186     //int phy_addr = 0;
 187     //static int phy_addr = 1;
 188     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 189     int linux_boot;
 190     int fl_idx, fl_sectors, len;
 191     int ppc_boot_device = boot_device[0];
 192     int index;
 193
 194     /* XXX: fix this */
 195     ram_bases[0] = 0x00000000;
 196     ram_sizes[0] = 0x08000000;
 197     ram_bases[1] = 0x00000000;
 198     ram_sizes[1] = 0x00000000;
 199     ram_size = 128 * 1024 * 1024;
 200 #ifdef DEBUG_BOARD_INIT
 201     printf("%s: register cpu\n", __func__);
 202 #endif
 203     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset,
 204                         kernel_filename == NULL ? 0 : 1);
 205     /* allocate SRAM */
 206 #ifdef DEBUG_BOARD_INIT
 207     printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
 208 #endif
 209     sram_size = 512 * 1024;
 210     cpu_register_physical_memory(0xFFF00000, sram_size,
 211                                  sram_offset | IO_MEM_RAM);
 212     /* allocate and load BIOS */
 213 #ifdef DEBUG_BOARD_INIT
 214     printf("%s: register BIOS\n", __func__);
 215 #endif
 216     bios_offset = sram_offset + sram_size;
 217     fl_idx = 0;
 218 #ifdef USE_FLASH_BIOS
 219     index = drive_get_index(IF_PFLASH, 0, fl_idx);
 220     if (index != -1) {
 221         bios_size = bdrv_getlength(drives_table[index].bdrv);
 222         fl_sectors = (bios_size + 65535) >> 16;
 223 #ifdef DEBUG_BOARD_INIT
 224         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 225                " addr " ADDRX " '%s' %d\n",
 226                fl_idx, bios_size, bios_offset, -bios_size,
 227                bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
 228 #endif
 229         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 230                               drives_table[index].bdrv, 65536, fl_sectors, 1,
 231                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 232         fl_idx++;
 233     } else
 234 #endif
 235     {
 236 #ifdef DEBUG_BOARD_INIT
 237         printf("Load BIOS from file\n");
 238 #endif
 239         if (bios_name == NULL)
 240             bios_name = BIOS_FILENAME;
 241         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 242         bios_size = load_image(buf, phys_ram_base + bios_offset);
 243         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 244             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
 245             exit(1);
 246         }
 247         bios_size = (bios_size + 0xfff) & ~0xfff;
 248         cpu_register_physical_memory((uint32_t)(-bios_size),
 249                                      bios_size, bios_offset | IO_MEM_ROM);
 250     }
 251     bios_offset += bios_size;
 252     /* Register FPGA */
 253 #ifdef DEBUG_BOARD_INIT
 254     printf("%s: register FPGA\n", __func__);
 255 #endif
 256     ref405ep_fpga_init(0xF0300000);
 257     /* Register NVRAM */
 258 #ifdef DEBUG_BOARD_INIT
 259     printf("%s: register NVRAM\n", __func__);
 260 #endif
 261     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 262     /* Load kernel */
 263     linux_boot = (kernel_filename != NULL);
 264     if (linux_boot) {
 265 #ifdef DEBUG_BOARD_INIT
 266         printf("%s: load kernel\n", __func__);
 267 #endif
 268         memset(&bd, 0, sizeof(bd));
 269         bd.bi_memstart = 0x00000000;
 270         bd.bi_memsize = ram_size;
 271         bd.bi_flashstart = -bios_size;
 272         bd.bi_flashsize = -bios_size;
 273         bd.bi_flashoffset = 0;
 274         bd.bi_sramstart = 0xFFF00000;
 275         bd.bi_sramsize = sram_size;
 276         bd.bi_bootflags = 0;
 277         bd.bi_intfreq = 133333333;
 278         bd.bi_busfreq = 33333333;
 279         bd.bi_baudrate = 115200;
 280         bd.bi_s_version[0] = 'Q';
 281         bd.bi_s_version[1] = 'M';
 282         bd.bi_s_version[2] = 'U';
 283         bd.bi_s_version[3] = '\0';
 284         bd.bi_r_version[0] = 'Q';
 285         bd.bi_r_version[1] = 'E';
 286         bd.bi_r_version[2] = 'M';
 287         bd.bi_r_version[3] = 'U';
 288         bd.bi_r_version[4] = '\0';
 289         bd.bi_procfreq = 133333333;
 290         bd.bi_plb_busfreq = 33333333;
 291         bd.bi_pci_busfreq = 33333333;
 292         bd.bi_opbfreq = 33333333;
 293         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 294         env->gpr[3] = bdloc;
 295         kernel_base = KERNEL_LOAD_ADDR;
 296         /* now we can load the kernel */
 297         kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
 298         if (kernel_size < 0) {
 299             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 300                     kernel_filename);
 301             exit(1);
 302         }
 303         printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx
 304                " %02x %02x %02x %02x\n", kernel_size, kernel_base,
 305                *(char *)(phys_ram_base + kernel_base),
 306                *(char *)(phys_ram_base + kernel_base + 1),
 307                *(char *)(phys_ram_base + kernel_base + 2),
 308                *(char *)(phys_ram_base + kernel_base + 3));
 309         /* load initrd */
 310         if (initrd_filename) {
 311             initrd_base = INITRD_LOAD_ADDR;
 312             initrd_size = load_image(initrd_filename,
 313                                      phys_ram_base + initrd_base);
 314             if (initrd_size < 0) {
 315                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 316                         initrd_filename);
 317                 exit(1);
 318             }
 319         } else {
 320             initrd_base = 0;
 321             initrd_size = 0;
 322         }
 323         env->gpr[4] = initrd_base;
 324         env->gpr[5] = initrd_size;
 325         ppc_boot_device = 'm';
 326         if (kernel_cmdline != NULL) {
 327             len = strlen(kernel_cmdline);
 328             bdloc -= ((len + 255) & ~255);
 329             memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);
 330             env->gpr[6] = bdloc;
 331             env->gpr[7] = bdloc + len;
 332         } else {
 333             env->gpr[6] = 0;
 334             env->gpr[7] = 0;
 335         }
 336         env->nip = KERNEL_LOAD_ADDR;
 337     } else {
 338         kernel_base = 0;
 339         kernel_size = 0;
 340         initrd_base = 0;
 341         initrd_size = 0;
 342         bdloc = 0;
 343     }
 344 #ifdef DEBUG_BOARD_INIT
 345     printf("%s: Done\n", __func__);
 346 #endif
 347     printf("bdloc %016lx %s\n",
 348            (unsigned long)bdloc, (char *)(phys_ram_base + bdloc));
 349 }
 350
 351 QEMUMachine ref405ep_machine = {
 352     .name = "ref405ep",
 353     .desc = "ref405ep",
 354     .init = ref405ep_init,
 355     .ram_require = (128 * 1024 * 1024 + 4096 + 512 * 1024 + BIOS_SIZE) | RAMSIZE_FIXED,
 356 };
 357
 358 /*****************************************************************************/
 359 /* AMCC Taihu evaluation board */
 360 /* - PowerPC 405EP processor
 361  * - SDRAM               128 MB at 0x00000000
 362  * - Boot flash          2 MB   at 0xFFE00000
 363  * - Application flash   32 MB  at 0xFC000000
 364  * - 2 serial ports
 365  * - 2 ethernet PHY
 366  * - 1 USB 1.1 device    0x50000000
 367  * - 1 LCD display       0x50100000
 368  * - 1 CPLD              0x50100000
 369  * - 1 I2C EEPROM
 370  * - 1 I2C thermal sensor
 371  * - a set of LEDs
 372  * - bit-bang SPI port using GPIOs
 373  * - 1 EBC interface connector 0 0x50200000
 374  * - 1 cardbus controller + expansion slot.
 375  * - 1 PCI expansion slot.
 376  */
 377 typedef struct taihu_cpld_t taihu_cpld_t;
 378 struct taihu_cpld_t {
 379     uint8_t reg0;
 380     uint8_t reg1;
 381 };
 382
 383 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 384 {
 385     taihu_cpld_t *cpld;
 386     uint32_t ret;
 387
 388     cpld = opaque;
 389     switch (addr) {
 390     case 0x0:
 391         ret = cpld->reg0;
 392         break;
 393     case 0x1:
 394         ret = cpld->reg1;
 395         break;
 396     default:
 397         ret = 0;
 398         break;
 399     }
 400
 401     return ret;
 402 }
 403
 404 static void taihu_cpld_writeb (void *opaque,
 405                                target_phys_addr_t addr, uint32_t value)
 406 {
 407     taihu_cpld_t *cpld;
 408
 409     cpld = opaque;
 410     switch (addr) {
 411     case 0x0:
 412         /* Read only */
 413         break;
 414     case 0x1:
 415         cpld->reg1 = value;
 416         break;
 417     default:
 418         break;
 419     }
 420 }
 421
 422 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 423 {
 424     uint32_t ret;
 425
 426     ret = taihu_cpld_readb(opaque, addr) << 8;
 427     ret |= taihu_cpld_readb(opaque, addr + 1);
 428
 429     return ret;
 430 }
 431
 432 static void taihu_cpld_writew (void *opaque,
 433                                target_phys_addr_t addr, uint32_t value)
 434 {
 435     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 436     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 437 }
 438
 439 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 440 {
 441     uint32_t ret;
 442
 443     ret = taihu_cpld_readb(opaque, addr) << 24;
 444     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 445     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 446     ret |= taihu_cpld_readb(opaque, addr + 3);
 447
 448     return ret;
 449 }
 450
 451 static void taihu_cpld_writel (void *opaque,
 452                                target_phys_addr_t addr, uint32_t value)
 453 {
 454     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 455     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 456     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 457     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 458 }
 459
 460 static CPUReadMemoryFunc *taihu_cpld_read[] = {
 461     &taihu_cpld_readb,
 462     &taihu_cpld_readw,
 463     &taihu_cpld_readl,
 464 };
 465
 466 static CPUWriteMemoryFunc *taihu_cpld_write[] = {
 467     &taihu_cpld_writeb,
 468     &taihu_cpld_writew,
 469     &taihu_cpld_writel,
 470 };
 471
 472 static void taihu_cpld_reset (void *opaque)
 473 {
 474     taihu_cpld_t *cpld;
 475
 476     cpld = opaque;
 477     cpld->reg0 = 0x01;
 478     cpld->reg1 = 0x80;
 479 }
 480
 481 static void taihu_cpld_init (uint32_t base)
 482 {
 483     taihu_cpld_t *cpld;
 484     int cpld_memory;
 485
 486     cpld = qemu_mallocz(sizeof(taihu_cpld_t));
 487     cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
 488                                          taihu_cpld_write, cpld);
 489     cpu_register_physical_memory(base, 0x00000100, cpld_memory);
 490     taihu_cpld_reset(cpld);
 491     qemu_register_reset(&taihu_cpld_reset, cpld);
 492 }
 493
 494 static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size,
 495                              const char *boot_device,
 496                              const char *kernel_filename,
 497                              const char *kernel_cmdline,
 498                              const char *initrd_filename,
 499                              const char *cpu_model)
 500 {
 501     char buf[1024];
 502     CPUPPCState *env;
 503     qemu_irq *pic;
 504     ram_addr_t bios_offset;
 505     target_phys_addr_t ram_bases[2], ram_sizes[2];
 506     target_ulong bios_size;
 507     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 508     int linux_boot;
 509     int fl_idx, fl_sectors;
 510     int ppc_boot_device = boot_device[0];
 511     int index;
 512
 513     /* RAM is soldered to the board so the size cannot be changed */
 514     ram_bases[0] = 0x00000000;
 515     ram_sizes[0] = 0x04000000;
 516     ram_bases[1] = 0x04000000;
 517     ram_sizes[1] = 0x04000000;
 518 #ifdef DEBUG_BOARD_INIT
 519     printf("%s: register cpu\n", __func__);
 520 #endif
 521     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset,
 522                         kernel_filename == NULL ? 0 : 1);
 523     /* allocate and load BIOS */
 524 #ifdef DEBUG_BOARD_INIT
 525     printf("%s: register BIOS\n", __func__);
 526 #endif
 527     fl_idx = 0;
 528 #if defined(USE_FLASH_BIOS)
 529     index = drive_get_index(IF_PFLASH, 0, fl_idx);
 530     if (index != -1) {
 531         bios_size = bdrv_getlength(drives_table[index].bdrv);
 532         /* XXX: should check that size is 2MB */
 533         //        bios_size = 2 * 1024 * 1024;
 534         fl_sectors = (bios_size + 65535) >> 16;
 535 #ifdef DEBUG_BOARD_INIT
 536         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 537                " addr " ADDRX " '%s' %d\n",
 538                fl_idx, bios_size, bios_offset, -bios_size,
 539                bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
 540 #endif
 541         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 542                               drives_table[index].bdrv, 65536, fl_sectors, 1,
 543                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 544         fl_idx++;
 545     } else
 546 #endif
 547     {
 548 #ifdef DEBUG_BOARD_INIT
 549         printf("Load BIOS from file\n");
 550 #endif
 551         if (bios_name == NULL)
 552             bios_name = BIOS_FILENAME;
 553         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 554         bios_size = load_image(buf, phys_ram_base + bios_offset);
 555         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 556             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
 557             exit(1);
 558         }
 559         bios_size = (bios_size + 0xfff) & ~0xfff;
 560         cpu_register_physical_memory((uint32_t)(-bios_size),
 561                                      bios_size, bios_offset | IO_MEM_ROM);
 562     }
 563     bios_offset += bios_size;
 564     /* Register Linux flash */
 565     index = drive_get_index(IF_PFLASH, 0, fl_idx);
 566     if (index != -1) {
 567         bios_size = bdrv_getlength(drives_table[index].bdrv);
 568         /* XXX: should check that size is 32MB */
 569         bios_size = 32 * 1024 * 1024;
 570         fl_sectors = (bios_size + 65535) >> 16;
 571 #ifdef DEBUG_BOARD_INIT
 572         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 573                " addr " ADDRX " '%s'\n",
 574                fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
 575                bdrv_get_device_name(drives_table[index].bdrv));
 576 #endif
 577         pflash_cfi02_register(0xfc000000, bios_offset,
 578                               drives_table[index].bdrv, 65536, fl_sectors, 1,
 579                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 580         fl_idx++;
 581     }
 582     /* Register CLPD & LCD display */
 583 #ifdef DEBUG_BOARD_INIT
 584     printf("%s: register CPLD\n", __func__);
 585 #endif
 586     taihu_cpld_init(0x50100000);
 587     /* Load kernel */
 588     linux_boot = (kernel_filename != NULL);
 589     if (linux_boot) {
 590 #ifdef DEBUG_BOARD_INIT
 591         printf("%s: load kernel\n", __func__);
 592 #endif
 593         kernel_base = KERNEL_LOAD_ADDR;
 594         /* now we can load the kernel */
 595         kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
 596         if (kernel_size < 0) {
 597             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 598                     kernel_filename);
 599             exit(1);
 600         }
 601         /* load initrd */
 602         if (initrd_filename) {
 603             initrd_base = INITRD_LOAD_ADDR;
 604             initrd_size = load_image(initrd_filename,
 605                                      phys_ram_base + initrd_base);
 606             if (initrd_size < 0) {
 607                 fprintf(stderr,
 608                         "qemu: could not load initial ram disk '%s'\n",
 609                         initrd_filename);
 610                 exit(1);
 611             }
 612         } else {
 613             initrd_base = 0;
 614             initrd_size = 0;
 615         }
 616         ppc_boot_device = 'm';
 617     } else {
 618         kernel_base = 0;
 619         kernel_size = 0;
 620         initrd_base = 0;
 621         initrd_size = 0;
 622     }
 623 #ifdef DEBUG_BOARD_INIT
 624     printf("%s: Done\n", __func__);
 625 #endif
 626 }
 627
 628 QEMUMachine taihu_machine = {
 629     "taihu",
 630     "taihu",
 631     taihu_405ep_init,
 632     (128 * 1024 * 1024 + 4096 + BIOS_SIZE + 32 * 1024 * 1024) | RAMSIZE_FIXED,
 633 };