hw/ipf.c

   1 /*
   2  * Itanium Platform Emulator derived from QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Copyright (c) 2007 Intel
   7  * Ported for IA64 Platform Zhang Xiantao <xiantao.zhang@intel.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "hw.h"
  29 #include "pc.h"
  30 #include "fdc.h"
  31 #include "pci.h"
  32 #include "block.h"
  33 #include "sysemu.h"
  34 #include "audio/audio.h"
  35 #include "net.h"
  36 #include "smbus.h"
  37 #include "boards.h"
  38 #include "firmware.h"
  39 #include "ia64intrin.h"
  40 #include <unistd.h>
  41 #include "device-assignment.h"
  42 #include "virtio-blk.h"
  43
  44 #include "qemu-kvm.h"
  45
  46 #define FW_FILENAME "Flash.fd"
  47
  48 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  49 #define ACPI_DATA_SIZE       0x10000
  50
  51 #define MAX_IDE_BUS 2
  52
  53 static fdctrl_t *floppy_controller;
  54 static RTCState *rtc_state;
  55 static PCIDevice *i440fx_state;
  56
  57 void *gfw_start;
  58
  59 static uint32_t ipf_to_legacy_io(target_phys_addr_t addr)
  60 {
  61     return (uint32_t)(((addr&0x3ffffff) >> 12 << 2)|((addr) & 0x3));
  62 }
  63
  64 static void ipf_legacy_io_writeb(void *opaque, target_phys_addr_t addr,
  65                                  uint32_t val) {
  66     uint32_t port = ipf_to_legacy_io(addr);
  67
  68     cpu_outb(0, port, val);
  69 }
  70
  71 static void ipf_legacy_io_writew(void *opaque, target_phys_addr_t addr,
  72                                  uint32_t val) {
  73     uint32_t port = ipf_to_legacy_io(addr);
  74
  75     cpu_outw(0, port, val);
  76 }
  77
  78 static void ipf_legacy_io_writel(void *opaque, target_phys_addr_t addr,
  79                                  uint32_t val) {
  80     uint32_t port = ipf_to_legacy_io(addr);
  81
  82     cpu_outl(0, port, val);
  83 }
  84
  85 static uint32_t ipf_legacy_io_readb(void *opaque, target_phys_addr_t addr)
  86 {
  87     uint32_t port = ipf_to_legacy_io(addr);
  88
  89     return cpu_inb(0, port);
  90 }
  91
  92 static uint32_t ipf_legacy_io_readw(void *opaque, target_phys_addr_t addr)
  93 {
  94     uint32_t port = ipf_to_legacy_io(addr);
  95
  96     return cpu_inw(0, port);
  97 }
  98
  99 static uint32_t ipf_legacy_io_readl(void *opaque, target_phys_addr_t addr)
 100 {
 101     uint32_t port = ipf_to_legacy_io(addr);
 102
 103     return cpu_inl(0, port);
 104 }
 105
 106 static CPUReadMemoryFunc *ipf_legacy_io_read[3] = {
 107     ipf_legacy_io_readb,
 108     ipf_legacy_io_readw,
 109     ipf_legacy_io_readl,
 110 };
 111
 112 static CPUWriteMemoryFunc *ipf_legacy_io_write[3] = {
 113     ipf_legacy_io_writeb,
 114     ipf_legacy_io_writew,
 115     ipf_legacy_io_writel,
 116 };
 117
 118 static void pic_irq_request(void *opaque, int irq, int level)
 119 {
 120     fprintf(stderr,"pic_irq_request called!\n");
 121 }
 122
 123 /* PC cmos mappings */
 124
 125 #define REG_EQUIPMENT_BYTE          0x14
 126
 127 static int cmos_get_fd_drive_type(int fd0)
 128 {
 129     int val;
 130
 131     switch (fd0) {
 132     case 0:
 133         /* 1.44 Mb 3"5 drive */
 134         val = 4;
 135         break;
 136     case 1:
 137         /* 2.88 Mb 3"5 drive */
 138         val = 5;
 139         break;
 140     case 2:
 141         /* 1.2 Mb 5"5 drive */
 142         val = 2;
 143         break;
 144     default:
 145         val = 0;
 146         break;
 147     }
 148     return val;
 149 }
 150
 151 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 152 {
 153     RTCState *s = rtc_state;
 154     int cylinders, heads, sectors;
 155
 156     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 157     rtc_set_memory(s, type_ofs, 47);
 158     rtc_set_memory(s, info_ofs, cylinders);
 159     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 160     rtc_set_memory(s, info_ofs + 2, heads);
 161     rtc_set_memory(s, info_ofs + 3, 0xff);
 162     rtc_set_memory(s, info_ofs + 4, 0xff);
 163     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 164     rtc_set_memory(s, info_ofs + 6, cylinders);
 165     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 166     rtc_set_memory(s, info_ofs + 8, sectors);
 167 }
 168
 169 /* convert boot_device letter to something recognizable by the bios */
 170 static int boot_device2nibble(char boot_device)
 171 {
 172     switch(boot_device) {
 173     case 'a':
 174     case 'b':
 175         return 0x01; /* floppy boot */
 176     case 'c':
 177         return 0x02; /* hard drive boot */
 178     case 'd':
 179         return 0x03; /* CD-ROM boot */
 180     case 'n':
 181         return 0x04; /* Network boot */
 182     }
 183     return 0;
 184 }
 185
 186 /* hd_table must contain 4 block drivers */
 187 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 188                       const char *boot_device, BlockDriverState **hd_table)
 189 {
 190     RTCState *s = rtc_state;
 191     int nbds, bds[3] = { 0, };
 192     int val;
 193     int fd0, fd1, nb;
 194     int i;
 195
 196     /* various important CMOS locations needed by PC/Bochs bios */
 197
 198     /* memory size */
 199     val = 640; /* base memory in K */
 200     rtc_set_memory(s, 0x15, val);
 201     rtc_set_memory(s, 0x16, val >> 8);
 202
 203     val = (ram_size / 1024) - 1024;
 204     if (val > 65535)
 205         val = 65535;
 206     rtc_set_memory(s, 0x17, val);
 207     rtc_set_memory(s, 0x18, val >> 8);
 208     rtc_set_memory(s, 0x30, val);
 209     rtc_set_memory(s, 0x31, val >> 8);
 210
 211     if (above_4g_mem_size) {
 212         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 213         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 214         rtc_set_memory(s, 0x5d, above_4g_mem_size >> 32);
 215     }
 216     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 217
 218     if (ram_size > (16 * 1024 * 1024))
 219         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 220     else
 221         val = 0;
 222     if (val > 65535)
 223         val = 65535;
 224     rtc_set_memory(s, 0x34, val);
 225     rtc_set_memory(s, 0x35, val >> 8);
 226
 227     /* set boot devices, and disable floppy signature check if requested */
 228 #define PC_MAX_BOOT_DEVICES 3
 229     nbds = strlen(boot_device);
 230
 231     if (nbds > PC_MAX_BOOT_DEVICES) {
 232         fprintf(stderr, "Too many boot devices for PC\n");
 233         exit(1);
 234     }
 235
 236     for (i = 0; i < nbds; i++) {
 237         bds[i] = boot_device2nibble(boot_device[i]);
 238         if (bds[i] == 0) {
 239             fprintf(stderr, "Invalid boot device for PC: '%c'\n",
 240                     boot_device[i]);
 241             exit(1);
 242         }
 243     }
 244
 245     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 246     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
 247
 248     /* floppy type */
 249
 250     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 251     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 252
 253     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 254     rtc_set_memory(s, 0x10, val);
 255
 256     val = 0;
 257     nb = 0;
 258     if (fd0 < 3)
 259         nb++;
 260     if (fd1 < 3)
 261         nb++;
 262
 263     switch (nb) {
 264     case 0:
 265         break;
 266     case 1:
 267         val |= 0x01; /* 1 drive, ready for boot */
 268         break;
 269     case 2:
 270         val |= 0x41; /* 2 drives, ready for boot */
 271         break;
 272     }
 273
 274     val |= 0x02; /* FPU is there */
 275     val |= 0x04; /* PS/2 mouse installed */
 276     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 277
 278     /* hard drives */
 279
 280     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 281     if (hd_table[0])
 282         cmos_init_hd(0x19, 0x1b, hd_table[0]);
 283     if (hd_table[1])
 284         cmos_init_hd(0x1a, 0x24, hd_table[1]);
 285
 286     val = 0;
 287     for (i = 0; i < 4; i++) {
 288         if (hd_table[i]) {
 289             int cylinders, heads, sectors, translation;
 290             /* NOTE: bdrv_get_geometry_hint() returns the physical
 291                geometry.  It is always such that: 1 <= sects <= 63, 1
 292                <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 293                geometry can be different if a translation is done. */
 294             translation = bdrv_get_translation_hint(hd_table[i]);
 295             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 296                 bdrv_get_geometry_hint(hd_table[i], &cylinders,
 297                                        &heads, &sectors);
 298                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 299                     /* No translation. */
 300                     translation = 0;
 301                 } else {
 302                     /* LBA translation. */
 303                     translation = 1;
 304                 }
 305             } else {
 306                 translation--;
 307             }
 308             val |= translation << (i * 2);
 309         }
 310     }
 311     rtc_set_memory(s, 0x39, val);
 312 }
 313
 314 static void main_cpu_reset(void *opaque)
 315 {
 316     CPUState *env = opaque;
 317     cpu_reset(env);
 318 }
 319
 320 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 321 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 322 static const int ide_irq[2] = { 14, 15 };
 323
 324 #define NE2000_NB_MAX 6
 325
 326 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340,
 327                                         0x360, 0x280, 0x380 };
 328 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 329
 330 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 331 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 332
 333 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 334 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 335
 336 #ifdef HAS_AUDIO
 337 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 338 {
 339     struct soundhw *c;
 340     int audio_enabled = 0;
 341
 342     for (c = soundhw; !audio_enabled && c->name; ++c) {
 343         audio_enabled = c->enabled;
 344     }
 345
 346     if (audio_enabled) {
 347         AudioState *s;
 348
 349         s = AUD_init ();
 350         if (s) {
 351             for (c = soundhw; c->name; ++c) {
 352                 if (c->enabled) {
 353                     if (c->isa) {
 354                         c->init.init_isa (s, pic);
 355                     } else {
 356                         if (pci_bus) {
 357                             c->init.init_pci (pci_bus, s);
 358                         }
 359                     }
 360                 }
 361             }
 362         }
 363     }
 364 }
 365 #endif
 366
 367 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 368 {
 369     static int nb_ne2k = 0;
 370
 371     if (nb_ne2k == NE2000_NB_MAX)
 372         return;
 373     isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
 374     nb_ne2k++;
 375 }
 376
 377 /* Itanium hardware initialisation */
 378 static void ipf_init1(ram_addr_t ram_size, int vga_ram_size,
 379                       const char *boot_device, DisplayState *ds,
 380                       const char *kernel_filename, const char *kernel_cmdline,
 381                       const char *initrd_filename,
 382                       int pci_enabled, const char *cpu_model)
 383 {
 384     char buf[1024];
 385     int i;
 386     ram_addr_t ram_addr, vga_ram_addr;
 387     ram_addr_t above_4g_mem_size = 0;
 388     PCIBus *pci_bus;
 389     int piix3_devfn = -1;
 390     CPUState *env;
 391     qemu_irq *cpu_irq;
 392     qemu_irq *i8259;
 393     int page_size;
 394     int index;
 395     unsigned long ipf_legacy_io_base, ipf_legacy_io_mem;
 396     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 397     BlockDriverState *fd[MAX_FD];
 398
 399     page_size = getpagesize();
 400     if (page_size != TARGET_PAGE_SIZE) {
 401         fprintf(stderr,"Error! Host page size != qemu target page size,"
 402                 " you may need to change TARGET_PAGE_BITS in qemu!"
 403                 "host page size:0x%x\n", page_size);
 404         exit(-1);
 405     };
 406
 407     if (ram_size >= 0xc0000000 ) {
 408         above_4g_mem_size = ram_size - 0xc0000000;
 409         ram_size = 0xc0000000;
 410     }
 411
 412     /* init CPUs */
 413     if (cpu_model == NULL) {
 414         cpu_model = "IA64";
 415     }
 416
 417     for(i = 0; i < smp_cpus; i++) {
 418         env = cpu_init(cpu_model);
 419         if (!env) {
 420             fprintf(stderr, "Unable to find CPU definition\n");
 421             exit(1);
 422         }
 423         if (i != 0)
 424             env->hflags |= HF_HALTED_MASK;
 425         register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
 426         qemu_register_reset(main_cpu_reset, env);
 427     }
 428
 429     /* allocate RAM */
 430     if (kvm_enabled()) {
 431         ram_addr = qemu_ram_alloc(0xa0000);
 432         cpu_register_physical_memory(0, 0xa0000, ram_addr);
 433
 434         ram_addr = qemu_ram_alloc(0x20000); // Workaround 0xa0000-0xc0000
 435
 436         ram_addr = qemu_ram_alloc(0x40000);
 437         cpu_register_physical_memory(0xc0000, 0x40000, ram_addr);
 438
 439         ram_addr = qemu_ram_alloc(ram_size - 0x100000);
 440         cpu_register_physical_memory(0x100000, ram_size - 0x100000, ram_addr);
 441     } else {
 442         ram_addr = qemu_ram_alloc(ram_size);
 443         cpu_register_physical_memory(0, ram_size, ram_addr);
 444     }
 445     /* allocate VGA RAM */
 446     vga_ram_addr = qemu_ram_alloc(vga_ram_size);
 447
 448     /* above 4giga memory allocation */
 449     if (above_4g_mem_size > 0) {
 450         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 451         cpu_register_physical_memory(0x100000000, above_4g_mem_size, ram_addr);
 452     }
 453
 454     /*Load firware to its proper position.*/
 455     if (kvm_enabled()) {
 456         unsigned long  image_size;
 457         uint8_t *image = NULL;
 458         target_phys_addr_t fw_image_start;
 459         unsigned long nvram_addr = 0;
 460         unsigned long nvram_fd = 0;
 461         unsigned long type = READ_FROM_NVRAM;
 462         unsigned long i = 0;
 463
 464         ram_addr  = qemu_ram_alloc(GFW_SIZE);
 465         gfw_start = qemu_get_ram_ptr(ram_addr);
 466         cpu_register_physical_memory(GFW_START, GFW_SIZE, ram_addr);
 467
 468         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, FW_FILENAME);
 469         image = read_image(buf, &image_size );
 470         if (NULL == image || !image_size) {
 471             fprintf(stderr, "Error when reading Guest Firmware!\n");
 472             fprintf(stderr, "Please check Guest firmware at %s\n", buf);
 473             exit(1);
 474         }
 475
 476         /* Load Guest Firmware to the proper postion. */
 477         fw_image_start = GFW_START + GFW_SIZE - image_size;
 478         cpu_physical_memory_write(fw_image_start, image, image_size);
 479         free(image);
 480
 481
 482         if (nvram) {
 483             nvram_addr = NVRAM_START;
 484             nvram_fd = kvm_ia64_nvram_init(type);
 485             if (nvram_fd != -1) {
 486                 kvm_ia64_copy_from_nvram_to_GFW(nvram_fd, gfw_start);
 487                 close(nvram_fd);
 488             }
 489             i = atexit((void *)kvm_ia64_copy_from_GFW_to_nvram);
 490             if (i != 0)
 491                 fprintf(stderr, "cannot set exit function\n");
 492         }
 493         kvm_ia64_build_hob(ram_size + above_4g_mem_size, smp_cpus,
 494                                         gfw_start, nvram_addr);
 495     }
 496
 497     /*Register legacy io address space, size:64M*/
 498     ipf_legacy_io_base = 0xE0000000;
 499     ipf_legacy_io_mem = cpu_register_io_memory(0, ipf_legacy_io_read,
 500                                                ipf_legacy_io_write, NULL);
 501     cpu_register_physical_memory(ipf_legacy_io_base, 64*1024*1024,
 502                                  ipf_legacy_io_mem);
 503
 504     cpu_irq = qemu_allocate_irqs(pic_irq_request, first_cpu, 1);
 505     i8259 = i8259_init(cpu_irq[0]);
 506
 507     if (pci_enabled) {
 508         pci_bus = i440fx_init(&i440fx_state, i8259);
 509         piix3_devfn = piix3_init(pci_bus, -1);
 510     } else {
 511         pci_bus = NULL;
 512     }
 513
 514     if (cirrus_vga_enabled) {
 515         if (pci_enabled) {
 516             pci_cirrus_vga_init(pci_bus, vga_ram_size);
 517         } else {
 518             isa_cirrus_vga_init(vga_ram_size);
 519         }
 520     } else {
 521         if (pci_enabled) {
 522             pci_vga_init(pci_bus, vga_ram_size, 0, 0);
 523         } else {
 524             isa_vga_init(vga_ram_size);
 525         }
 526     }
 527
 528     rtc_state = rtc_init(0x70, i8259[8], 2000);
 529
 530     if (pci_enabled) {
 531         pic_set_alt_irq_func(isa_pic, NULL, NULL);
 532     }
 533
 534     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 535         if (serial_hds[i]) {
 536             serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
 537                         serial_hds[i]);
 538         }
 539     }
 540
 541     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 542         if (parallel_hds[i]) {
 543             parallel_init(parallel_io[i], i8259[parallel_irq[i]],
 544                           parallel_hds[i]);
 545         }
 546     }
 547
 548     for(i = 0; i < nb_nics; i++) {
 549         NICInfo *nd = &nd_table[i];
 550
 551         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
 552             pc_init_ne2k_isa(nd, i8259);
 553         else
 554             pci_nic_init(pci_bus, nd, -1, "e1000");
 555     }
 556
 557 #undef USE_HYPERCALL  //Disable it now, need to implement later!
 558 #ifdef USE_HYPERCALL
 559     pci_hypercall_init(pci_bus);
 560 #endif
 561
 562     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 563         fprintf(stderr, "qemu: too many IDE bus\n");
 564         exit(1);
 565     }
 566
 567     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 568         index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 569         if (index != -1)
 570             hd[i] = drives_table[index].bdrv;
 571         else
 572             hd[i] = NULL;
 573     }
 574
 575     if (pci_enabled) {
 576         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
 577     } else {
 578         for(i = 0; i < MAX_IDE_BUS; i++) {
 579             isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 580                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
 581         }
 582     }
 583
 584     i8042_init(i8259[1], i8259[12], 0x60);
 585     DMA_init(0);
 586 #ifdef HAS_AUDIO
 587     audio_init(pci_enabled ? pci_bus : NULL, i8259);
 588 #endif
 589
 590     for(i = 0; i < MAX_FD; i++) {
 591         index = drive_get_index(IF_FLOPPY, 0, i);
 592         if (index != -1)
 593             fd[i] = drives_table[index].bdrv;
 594         else
 595             fd[i] = NULL;
 596     }
 597     floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
 598
 599     cmos_init(ram_size, above_4g_mem_size, boot_device, hd);
 600
 601     if (pci_enabled && usb_enabled) {
 602         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
 603     }
 604
 605     if (pci_enabled && acpi_enabled) {
 606         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
 607         i2c_bus *smbus;
 608
 609         /* TODO: Populate SPD eeprom data.  */
 610         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
 611         for (i = 0; i < 8; i++) {
 612             smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
 613         }
 614     }
 615
 616     if (i440fx_state) {
 617         i440fx_init_memory_mappings(i440fx_state);
 618     }
 619
 620     if (pci_enabled) {
 621         int max_bus;
 622         int bus, unit;
 623         void *scsi;
 624
 625         max_bus = drive_get_max_bus(IF_SCSI);
 626
 627         for (bus = 0; bus <= max_bus; bus++) {
 628             scsi = lsi_scsi_init(pci_bus, -1);
 629             for (unit = 0; unit < LSI_MAX_DEVS; unit++) {
 630                 index = drive_get_index(IF_SCSI, bus, unit);
 631                 if (index == -1)
 632                     continue;
 633                 lsi_scsi_attach(scsi, drives_table[index].bdrv, unit);
 634             }
 635         }
 636     }
 637     /* Add virtio block devices */
 638     if (pci_enabled) {
 639         int index;
 640         int unit_id = 0;
 641
 642         while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
 643             virtio_blk_init(pci_bus, drives_table[index].bdrv);
 644             unit_id++;
 645         }
 646     }
 647
 648 #ifdef USE_KVM_DEVICE_ASSIGNMENT
 649     if (kvm_enabled())
 650         add_assigned_devices(pci_bus, assigned_devices, assigned_devices_index);
 651 #endif /* USE_KVM_DEVICE_ASSIGNMENT */
 652
 653 }
 654
 655 static void ipf_init_pci(ram_addr_t ram_size, int vga_ram_size,
 656                          const char *boot_device, DisplayState *ds,
 657                          const char *kernel_filename,
 658                          const char *kernel_cmdline,
 659                          const char *initrd_filename,
 660                          const char *cpu_model)
 661 {
 662     ipf_init1(ram_size, vga_ram_size, boot_device, ds, kernel_filename,
 663               kernel_cmdline, initrd_filename, 1, cpu_model);
 664 }
 665
 666 QEMUMachine ipf_machine = {
 667     .name = "itanium",
 668     .desc = "Itanium Platform",
 669     .init = (QEMUMachineInitFunc *)ipf_init_pci,
 670     .max_cpus = 255,
 671 };
 672
 673 #define IOAPIC_NUM_PINS 48
 674
 675 static int ioapic_irq_count[IOAPIC_NUM_PINS];
 676
 677 static int ioapic_map_irq(int devfn, int irq_num)
 678 {
 679     int irq, dev;
 680     dev = devfn >> 3;
 681     irq = ((((dev << 2) + (dev >> 3) + irq_num) & 31) + 16);
 682     return irq;
 683 }
 684
 685 /*
 686  * Dummy function to provide match for call from hw/apic.c
 687  */
 688 void apic_set_irq_delivered(void) {
 689 }
 690
 691 void ioapic_set_irq(void *opaque, int irq_num, int level)
 692 {
 693     int vector, pic_ret;
 694
 695     PCIDevice *pci_dev = (PCIDevice *)opaque;
 696     vector = ioapic_map_irq(pci_dev->devfn, irq_num);
 697
 698     if (level)
 699         ioapic_irq_count[vector] += 1;
 700     else
 701         ioapic_irq_count[vector] -= 1;
 702
 703     if (kvm_enabled()) {
 704         if (kvm_set_irq(vector, ioapic_irq_count[vector] == 0, &pic_ret))
 705             if (pic_ret != 0)
 706                 apic_set_irq_delivered();
 707             return;
 708     }
 709 }
 710
 711 int ipf_map_irq(PCIDevice *pci_dev, int irq_num)
 712 {
 713         return ioapic_map_irq(pci_dev->devfn, irq_num);
 714 }