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Cleanup kvm cpu loop
[qemu-kvm/fedora.git] / qemu-kvm-x86.c
blob66b2b199b1a2dab0c3fbe24299a0539af6372f46
1 /*
2 * qemu/kvm integration, x86 specific code
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 *
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
8
9 #include "config.h"
10 #include "config-host.h"
11
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
16
17 #include "qemu-kvm.h"
18 #include "libkvm-all.h"
19 #include "libkvm.h"
20 #include <pthread.h>
21 #include <sys/utsname.h>
22 #include <linux/kvm_para.h>
23 #include <sys/ioctl.h>
24
25 #include "kvm.h"
26
27 #define MSR_IA32_TSC 0x10
28
29 static struct kvm_msr_list *kvm_msr_list;
30 extern unsigned int kvm_shadow_memory;
31 static int kvm_has_msr_star;
32 static int kvm_has_vm_hsave_pa;
33
34 static int lm_capable_kernel;
35
36 int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr)
37 {
38 #ifdef KVM_CAP_SET_TSS_ADDR
39 int r;
40
41 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
42 if (r > 0) {
43 r = ioctl(kvm->vm_fd, KVM_SET_TSS_ADDR, addr);
44 if (r == -1) {
45 fprintf(stderr, "kvm_set_tss_addr: %m\n");
46 return -errno;
47 }
48 return 0;
49 }
50 #endif
51 return -ENOSYS;
52 }
53
54 static int kvm_init_tss(kvm_context_t kvm)
55 {
56 #ifdef KVM_CAP_SET_TSS_ADDR
57 int r;
58
59 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
60 if (r > 0) {
61 /*
62 * this address is 3 pages before the bios, and the bios should present
63 * as unavaible memory
64 */
65 r = kvm_set_tss_addr(kvm, 0xfffbd000);
66 if (r < 0) {
67 fprintf(stderr, "kvm_init_tss: unable to set tss addr\n");
68 return r;
69 }
70
71 }
72 #endif
73 return 0;
74 }
75
76 static int kvm_create_pit(kvm_context_t kvm)
77 {
78 #ifdef KVM_CAP_PIT
79 int r;
80
81 kvm->pit_in_kernel = 0;
82 if (!kvm->no_pit_creation) {
83 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_PIT);
84 if (r > 0) {
85 r = ioctl(kvm->vm_fd, KVM_CREATE_PIT);
86 if (r >= 0)
87 kvm->pit_in_kernel = 1;
88 else {
89 fprintf(stderr, "Create kernel PIC irqchip failed\n");
90 return r;
91 }
92 }
93 }
94 #endif
95 return 0;
96 }
97
98 int kvm_arch_create(kvm_context_t kvm, unsigned long phys_mem_bytes,
99 void **vm_mem)
100 {
101 int r = 0;
102
103 r = kvm_init_tss(kvm);
104 if (r < 0)
105 return r;
106
107 r = kvm_create_pit(kvm);
108 if (r < 0)
109 return r;
110
111 r = kvm_init_coalesced_mmio(kvm);
112 if (r < 0)
113 return r;
114
115 return 0;
116 }
117
118 #ifdef KVM_EXIT_TPR_ACCESS
119
120 static int kvm_handle_tpr_access(kvm_vcpu_context_t vcpu)
121 {
122 struct kvm_run *run = vcpu->run;
123 return vcpu->kvm->callbacks->tpr_access(vcpu->kvm->opaque, vcpu,
124 run->tpr_access.rip,
125 run->tpr_access.is_write);
126 }
127
128
129 int kvm_enable_vapic(kvm_vcpu_context_t vcpu, uint64_t vapic)
130 {
131 int r;
132 struct kvm_vapic_addr va = {
133 .vapic_addr = vapic,
134 };
135
136 r = ioctl(vcpu->fd, KVM_SET_VAPIC_ADDR, &va);
137 if (r == -1) {
138 r = -errno;
139 perror("kvm_enable_vapic");
140 return r;
141 }
142 return 0;
143 }
144
145 #endif
146
147 int kvm_arch_run(kvm_vcpu_context_t vcpu)
148 {
149 int r = 0;
150 struct kvm_run *run = vcpu->run;
151
152
153 switch (run->exit_reason) {
154 #ifdef KVM_EXIT_SET_TPR
155 case KVM_EXIT_SET_TPR:
156 break;
157 #endif
158 #ifdef KVM_EXIT_TPR_ACCESS
159 case KVM_EXIT_TPR_ACCESS:
160 r = kvm_handle_tpr_access(vcpu);
161 break;
162 #endif
163 default:
164 r = 1;
165 break;
166 }
167
168 return r;
169 }
170
171 #define MAX_ALIAS_SLOTS 4
172 static struct {
173 uint64_t start;
174 uint64_t len;
175 } kvm_aliases[MAX_ALIAS_SLOTS];
176
177 static int get_alias_slot(uint64_t start)
178 {
179 int i;
180
181 for (i=0; i<MAX_ALIAS_SLOTS; i++)
182 if (kvm_aliases[i].start == start)
183 return i;
184 return -1;
185 }
186 static int get_free_alias_slot(void)
187 {
188 int i;
189
190 for (i=0; i<MAX_ALIAS_SLOTS; i++)
191 if (kvm_aliases[i].len == 0)
192 return i;
193 return -1;
194 }
195
196 static void register_alias(int slot, uint64_t start, uint64_t len)
197 {
198 kvm_aliases[slot].start = start;
199 kvm_aliases[slot].len = len;
200 }
201
202 int kvm_create_memory_alias(kvm_context_t kvm,
203 uint64_t phys_start,
204 uint64_t len,
205 uint64_t target_phys)
206 {
207 struct kvm_memory_alias alias = {
208 .flags = 0,
209 .guest_phys_addr = phys_start,
210 .memory_size = len,
211 .target_phys_addr = target_phys,
212 };
213 int fd = kvm->vm_fd;
214 int r;
215 int slot;
216
217 slot = get_alias_slot(phys_start);
218 if (slot < 0)
219 slot = get_free_alias_slot();
220 if (slot < 0)
221 return -EBUSY;
222 alias.slot = slot;
223
224 r = ioctl(fd, KVM_SET_MEMORY_ALIAS, &alias);
225 if (r == -1)
226 return -errno;
227
228 register_alias(slot, phys_start, len);
229 return 0;
230 }
231
232 int kvm_destroy_memory_alias(kvm_context_t kvm, uint64_t phys_start)
233 {
234 return kvm_create_memory_alias(kvm, phys_start, 0, 0);
235 }
236
237 #ifdef KVM_CAP_IRQCHIP
238
239 int kvm_get_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
240 {
241 int r;
242 if (!kvm_irqchip_in_kernel(vcpu->kvm))
243 return 0;
244 r = ioctl(vcpu->fd, KVM_GET_LAPIC, s);
245 if (r == -1) {
246 r = -errno;
247 perror("kvm_get_lapic");
248 }
249 return r;
250 }
251
252 int kvm_set_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
253 {
254 int r;
255 if (!kvm_irqchip_in_kernel(vcpu->kvm))
256 return 0;
257 r = ioctl(vcpu->fd, KVM_SET_LAPIC, s);
258 if (r == -1) {
259 r = -errno;
260 perror("kvm_set_lapic");
261 }
262 return r;
263 }
264
265 #endif
266
267 #ifdef KVM_CAP_PIT
268
269 int kvm_get_pit(kvm_context_t kvm, struct kvm_pit_state *s)
270 {
271 int r;
272 if (!kvm->pit_in_kernel)
273 return 0;
274 r = ioctl(kvm->vm_fd, KVM_GET_PIT, s);
275 if (r == -1) {
276 r = -errno;
277 perror("kvm_get_pit");
278 }
279 return r;
280 }
281
282 int kvm_set_pit(kvm_context_t kvm, struct kvm_pit_state *s)
283 {
284 int r;
285 if (!kvm->pit_in_kernel)
286 return 0;
287 r = ioctl(kvm->vm_fd, KVM_SET_PIT, s);
288 if (r == -1) {
289 r = -errno;
290 perror("kvm_set_pit");
291 }
292 return r;
293 }
294
295 #endif
296
297 void kvm_show_code(kvm_vcpu_context_t vcpu)
298 {
299 #define SHOW_CODE_LEN 50
300 int fd = vcpu->fd;
301 struct kvm_regs regs;
302 struct kvm_sregs sregs;
303 int r, n;
304 int back_offset;
305 unsigned char code;
306 char code_str[SHOW_CODE_LEN * 3 + 1];
307 unsigned long rip;
308 kvm_context_t kvm = vcpu->kvm;
309
310 r = ioctl(fd, KVM_GET_SREGS, &sregs);
311 if (r == -1) {
312 perror("KVM_GET_SREGS");
313 return;
314 }
315 r = ioctl(fd, KVM_GET_REGS, &regs);
316 if (r == -1) {
317 perror("KVM_GET_REGS");
318 return;
319 }
320 rip = sregs.cs.base + regs.rip;
321 back_offset = regs.rip;
322 if (back_offset > 20)
323 back_offset = 20;
324 *code_str = 0;
325 for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
326 if (n == 0)
327 strcat(code_str, " -->");
328 r = kvm->callbacks->mmio_read(kvm->opaque, rip + n, &code, 1);
329 if (r < 0) {
330 strcat(code_str, " xx");
331 continue;
332 }
333 sprintf(code_str + strlen(code_str), " %02x", code);
334 }
335 fprintf(stderr, "code:%s\n", code_str);
336 }
337
338
339 /*
340 * Returns available msr list. User must free.
341 */
342 struct kvm_msr_list *kvm_get_msr_list(kvm_context_t kvm)
343 {
344 struct kvm_msr_list sizer, *msrs;
345 int r, e;
346
347 sizer.nmsrs = 0;
348 r = ioctl(kvm->fd, KVM_GET_MSR_INDEX_LIST, &sizer);
349 if (r == -1 && errno != E2BIG)
350 return NULL;
351 msrs = malloc(sizeof *msrs + sizer.nmsrs * sizeof *msrs->indices);
352 if (!msrs) {
353 errno = ENOMEM;
354 return NULL;
355 }
356 msrs->nmsrs = sizer.nmsrs;
357 r = ioctl(kvm->fd, KVM_GET_MSR_INDEX_LIST, msrs);
358 if (r == -1) {
359 e = errno;
360 free(msrs);
361 errno = e;
362 return NULL;
363 }
364 return msrs;
365 }
366
367 int kvm_get_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
368 {
369 struct kvm_msrs *kmsrs = malloc(sizeof *kmsrs + n * sizeof *msrs);
370 int r, e;
371
372 if (!kmsrs) {
373 errno = ENOMEM;
374 return -1;
375 }
376 kmsrs->nmsrs = n;
377 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
378 r = ioctl(vcpu->fd, KVM_GET_MSRS, kmsrs);
379 e = errno;
380 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
381 free(kmsrs);
382 errno = e;
383 return r;
384 }
385
386 int kvm_set_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
387 {
388 struct kvm_msrs *kmsrs = malloc(sizeof *kmsrs + n * sizeof *msrs);
389 int r, e;
390
391 if (!kmsrs) {
392 errno = ENOMEM;
393 return -1;
394 }
395 kmsrs->nmsrs = n;
396 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
397 r = ioctl(vcpu->fd, KVM_SET_MSRS, kmsrs);
398 e = errno;
399 free(kmsrs);
400 errno = e;
401 return r;
402 }
403
404 static void print_seg(FILE *file, const char *name, struct kvm_segment *seg)
405 {
406 fprintf(stderr,
407 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
408 " g %d avl %d)\n",
409 name, seg->selector, seg->base, seg->limit, seg->present,
410 seg->dpl, seg->db, seg->s, seg->type, seg->l, seg->g,
411 seg->avl);
412 }
413
414 static void print_dt(FILE *file, const char *name, struct kvm_dtable *dt)
415 {
416 fprintf(stderr, "%s %llx/%x\n", name, dt->base, dt->limit);
417 }
418
419 void kvm_show_regs(kvm_vcpu_context_t vcpu)
420 {
421 int fd = vcpu->fd;
422 struct kvm_regs regs;
423 struct kvm_sregs sregs;
424 int r;
425
426 r = ioctl(fd, KVM_GET_REGS, &regs);
427 if (r == -1) {
428 perror("KVM_GET_REGS");
429 return;
430 }
431 fprintf(stderr,
432 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
433 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
434 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
435 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
436 "rip %016llx rflags %08llx\n",
437 regs.rax, regs.rbx, regs.rcx, regs.rdx,
438 regs.rsi, regs.rdi, regs.rsp, regs.rbp,
439 regs.r8, regs.r9, regs.r10, regs.r11,
440 regs.r12, regs.r13, regs.r14, regs.r15,
441 regs.rip, regs.rflags);
442 r = ioctl(fd, KVM_GET_SREGS, &sregs);
443 if (r == -1) {
444 perror("KVM_GET_SREGS");
445 return;
446 }
447 print_seg(stderr, "cs", &sregs.cs);
448 print_seg(stderr, "ds", &sregs.ds);
449 print_seg(stderr, "es", &sregs.es);
450 print_seg(stderr, "ss", &sregs.ss);
451 print_seg(stderr, "fs", &sregs.fs);
452 print_seg(stderr, "gs", &sregs.gs);
453 print_seg(stderr, "tr", &sregs.tr);
454 print_seg(stderr, "ldt", &sregs.ldt);
455 print_dt(stderr, "gdt", &sregs.gdt);
456 print_dt(stderr, "idt", &sregs.idt);
457 fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
458 " efer %llx\n",
459 sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
460 sregs.efer);
461 }
462
463 uint64_t kvm_get_apic_base(kvm_vcpu_context_t vcpu)
464 {
465 return vcpu->run->apic_base;
466 }
467
468 void kvm_set_cr8(kvm_vcpu_context_t vcpu, uint64_t cr8)
469 {
470 vcpu->run->cr8 = cr8;
471 }
472
473 __u64 kvm_get_cr8(kvm_vcpu_context_t vcpu)
474 {
475 return vcpu->run->cr8;
476 }
477
478 int kvm_setup_cpuid(kvm_vcpu_context_t vcpu, int nent,
479 struct kvm_cpuid_entry *entries)
480 {
481 struct kvm_cpuid *cpuid;
482 int r;
483
484 cpuid = malloc(sizeof(*cpuid) + nent * sizeof(*entries));
485 if (!cpuid)
486 return -ENOMEM;
487
488 cpuid->nent = nent;
489 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
490 r = ioctl(vcpu->fd, KVM_SET_CPUID, cpuid);
491
492 free(cpuid);
493 return r;
494 }
495
496 int kvm_setup_cpuid2(kvm_vcpu_context_t vcpu, int nent,
497 struct kvm_cpuid_entry2 *entries)
498 {
499 struct kvm_cpuid2 *cpuid;
500 int r;
501
502 cpuid = malloc(sizeof(*cpuid) + nent * sizeof(*entries));
503 if (!cpuid)
504 return -ENOMEM;
505
506 cpuid->nent = nent;
507 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
508 r = ioctl(vcpu->fd, KVM_SET_CPUID2, cpuid);
509 if (r == -1) {
510 fprintf(stderr, "kvm_setup_cpuid2: %m\n");
511 return -errno;
512 }
513 free(cpuid);
514 return r;
515 }
516
517 int kvm_set_shadow_pages(kvm_context_t kvm, unsigned int nrshadow_pages)
518 {
519 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
520 int r;
521
522 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION,
523 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
524 if (r > 0) {
525 r = ioctl(kvm->vm_fd, KVM_SET_NR_MMU_PAGES, nrshadow_pages);
526 if (r == -1) {
527 fprintf(stderr, "kvm_set_shadow_pages: %m\n");
528 return -errno;
529 }
530 return 0;
531 }
532 #endif
533 return -1;
534 }
535
536 int kvm_get_shadow_pages(kvm_context_t kvm, unsigned int *nrshadow_pages)
537 {
538 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
539 int r;
540
541 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION,
542 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
543 if (r > 0) {
544 *nrshadow_pages = ioctl(kvm->vm_fd, KVM_GET_NR_MMU_PAGES);
545 return 0;
546 }
547 #endif
548 return -1;
549 }
550
551 #ifdef KVM_CAP_VAPIC
552
553 static int tpr_access_reporting(kvm_vcpu_context_t vcpu, int enabled)
554 {
555 int r;
556 struct kvm_tpr_access_ctl tac = {
557 .enabled = enabled,
558 };
559
560 r = ioctl(vcpu->kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_VAPIC);
561 if (r == -1 || r == 0)
562 return -ENOSYS;
563 r = ioctl(vcpu->fd, KVM_TPR_ACCESS_REPORTING, &tac);
564 if (r == -1) {
565 r = -errno;
566 perror("KVM_TPR_ACCESS_REPORTING");
567 return r;
568 }
569 return 0;
570 }
571
572 int kvm_enable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
573 {
574 return tpr_access_reporting(vcpu, 1);
575 }
576
577 int kvm_disable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
578 {
579 return tpr_access_reporting(vcpu, 0);
580 }
581
582 #endif
583
584 #ifdef KVM_CAP_EXT_CPUID
585
586 static struct kvm_cpuid2 *try_get_cpuid(kvm_context_t kvm, int max)
587 {
588 struct kvm_cpuid2 *cpuid;
589 int r, size;
590
591 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
592 cpuid = (struct kvm_cpuid2 *)malloc(size);
593 cpuid->nent = max;
594 r = ioctl(kvm->fd, KVM_GET_SUPPORTED_CPUID, cpuid);
595 if (r == -1)
596 r = -errno;
597 else if (r == 0 && cpuid->nent >= max)
598 r = -E2BIG;
599 if (r < 0) {
600 if (r == -E2BIG) {
601 free(cpuid);
602 return NULL;
603 } else {
604 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
605 strerror(-r));
606 exit(1);
607 }
608 }
609 return cpuid;
610 }
611
612 #define R_EAX 0
613 #define R_ECX 1
614 #define R_EDX 2
615 #define R_EBX 3
616 #define R_ESP 4
617 #define R_EBP 5
618 #define R_ESI 6
619 #define R_EDI 7
620
621 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
622 {
623 struct kvm_cpuid2 *cpuid;
624 int i, max;
625 uint32_t ret = 0;
626 uint32_t cpuid_1_edx;
627
628 if (!kvm_check_extension(kvm, KVM_CAP_EXT_CPUID)) {
629 return -1U;
630 }
631
632 max = 1;
633 while ((cpuid = try_get_cpuid(kvm, max)) == NULL) {
634 max *= 2;
635 }
636
637 for (i = 0; i < cpuid->nent; ++i) {
638 if (cpuid->entries[i].function == function) {
639 switch (reg) {
640 case R_EAX:
641 ret = cpuid->entries[i].eax;
642 break;
643 case R_EBX:
644 ret = cpuid->entries[i].ebx;
645 break;
646 case R_ECX:
647 ret = cpuid->entries[i].ecx;
648 break;
649 case R_EDX:
650 ret = cpuid->entries[i].edx;
651 if (function == 1) {
652 /* kvm misreports the following features
653 */
654 ret |= 1 << 12; /* MTRR */
655 ret |= 1 << 16; /* PAT */
656 ret |= 1 << 7; /* MCE */
657 ret |= 1 << 14; /* MCA */
658 }
659
660 /* On Intel, kvm returns cpuid according to
661 * the Intel spec, so add missing bits
662 * according to the AMD spec:
663 */
664 if (function == 0x80000001) {
665 cpuid_1_edx = kvm_get_supported_cpuid(kvm, 1, R_EDX);
666 ret |= cpuid_1_edx & 0xdfeff7ff;
667 }
668 break;
669 }
670 }
671 }
672
673 free(cpuid);
674
675 return ret;
676 }
677
678 #else
679
680 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
681 {
682 return -1U;
683 }
684
685 #endif
686 int kvm_qemu_create_memory_alias(uint64_t phys_start,
687 uint64_t len,
688 uint64_t target_phys)
689 {
690 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
691 }
692
693 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
694 {
695 return kvm_destroy_memory_alias(kvm_context, phys_start);
696 }
697
698 int kvm_arch_qemu_create_context(void)
699 {
700 int i;
701 struct utsname utsname;
702
703 uname(&utsname);
704 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
705
706 if (kvm_shadow_memory)
707 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
708
709 kvm_msr_list = kvm_get_msr_list(kvm_context);
710 if (!kvm_msr_list)
711 return -1;
712 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
713 if (kvm_msr_list->indices[i] == MSR_STAR)
714 kvm_has_msr_star = 1;
715 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
716 kvm_has_vm_hsave_pa = 1;
717 }
718
719 return 0;
720 }
721
722 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
723 uint64_t data)
724 {
725 entry->index = index;
726 entry->data = data;
727 }
728
729 /* returns 0 on success, non-0 on failure */
730 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
731 {
732 switch (entry->index) {
733 case MSR_IA32_SYSENTER_CS:
734 env->sysenter_cs = entry->data;
735 break;
736 case MSR_IA32_SYSENTER_ESP:
737 env->sysenter_esp = entry->data;
738 break;
739 case MSR_IA32_SYSENTER_EIP:
740 env->sysenter_eip = entry->data;
741 break;
742 case MSR_STAR:
743 env->star = entry->data;
744 break;
745 #ifdef TARGET_X86_64
746 case MSR_CSTAR:
747 env->cstar = entry->data;
748 break;
749 case MSR_KERNELGSBASE:
750 env->kernelgsbase = entry->data;
751 break;
752 case MSR_FMASK:
753 env->fmask = entry->data;
754 break;
755 case MSR_LSTAR:
756 env->lstar = entry->data;
757 break;
758 #endif
759 case MSR_IA32_TSC:
760 env->tsc = entry->data;
761 break;
762 case MSR_VM_HSAVE_PA:
763 env->vm_hsave = entry->data;
764 break;
765 default:
766 printf("Warning unknown msr index 0x%x\n", entry->index);
767 return 1;
768 }
769 return 0;
770 }
771
772 #ifdef TARGET_X86_64
773 #define MSR_COUNT 9
774 #else
775 #define MSR_COUNT 5
776 #endif
777
778 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
779 {
780 lhs->selector = rhs->selector;
781 lhs->base = rhs->base;
782 lhs->limit = rhs->limit;
783 lhs->type = 3;
784 lhs->present = 1;
785 lhs->dpl = 3;
786 lhs->db = 0;
787 lhs->s = 1;
788 lhs->l = 0;
789 lhs->g = 0;
790 lhs->avl = 0;
791 lhs->unusable = 0;
792 }
793
794 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
795 {
796 unsigned flags = rhs->flags;
797 lhs->selector = rhs->selector;
798 lhs->base = rhs->base;
799 lhs->limit = rhs->limit;
800 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
801 lhs->present = (flags & DESC_P_MASK) != 0;
802 lhs->dpl = rhs->selector & 3;
803 lhs->db = (flags >> DESC_B_SHIFT) & 1;
804 lhs->s = (flags & DESC_S_MASK) != 0;
805 lhs->l = (flags >> DESC_L_SHIFT) & 1;
806 lhs->g = (flags & DESC_G_MASK) != 0;
807 lhs->avl = (flags & DESC_AVL_MASK) != 0;
808 lhs->unusable = 0;
809 }
810
811 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
812 {
813 lhs->selector = rhs->selector;
814 lhs->base = rhs->base;
815 lhs->limit = rhs->limit;
816 lhs->flags =
817 (rhs->type << DESC_TYPE_SHIFT)
818 | (rhs->present * DESC_P_MASK)
819 | (rhs->dpl << DESC_DPL_SHIFT)
820 | (rhs->db << DESC_B_SHIFT)
821 | (rhs->s * DESC_S_MASK)
822 | (rhs->l << DESC_L_SHIFT)
823 | (rhs->g * DESC_G_MASK)
824 | (rhs->avl * DESC_AVL_MASK);
825 }
826
827 void kvm_arch_load_regs(CPUState *env)
828 {
829 struct kvm_regs regs;
830 struct kvm_fpu fpu;
831 struct kvm_sregs sregs;
832 struct kvm_msr_entry msrs[MSR_COUNT];
833 int rc, n, i;
834
835 regs.rax = env->regs[R_EAX];
836 regs.rbx = env->regs[R_EBX];
837 regs.rcx = env->regs[R_ECX];
838 regs.rdx = env->regs[R_EDX];
839 regs.rsi = env->regs[R_ESI];
840 regs.rdi = env->regs[R_EDI];
841 regs.rsp = env->regs[R_ESP];
842 regs.rbp = env->regs[R_EBP];
843 #ifdef TARGET_X86_64
844 regs.r8 = env->regs[8];
845 regs.r9 = env->regs[9];
846 regs.r10 = env->regs[10];
847 regs.r11 = env->regs[11];
848 regs.r12 = env->regs[12];
849 regs.r13 = env->regs[13];
850 regs.r14 = env->regs[14];
851 regs.r15 = env->regs[15];
852 #endif
853
854 regs.rflags = env->eflags;
855 regs.rip = env->eip;
856
857 kvm_set_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
858
859 memset(&fpu, 0, sizeof fpu);
860 fpu.fsw = env->fpus & ~(7 << 11);
861 fpu.fsw |= (env->fpstt & 7) << 11;
862 fpu.fcw = env->fpuc;
863 for (i = 0; i < 8; ++i)
864 fpu.ftwx |= (!env->fptags[i]) << i;
865 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
866 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
867 fpu.mxcsr = env->mxcsr;
868 kvm_set_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
869
870 memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
871
872 if ((env->eflags & VM_MASK)) {
873 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
874 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
875 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
876 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
877 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
878 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
879 } else {
880 set_seg(&sregs.cs, &env->segs[R_CS]);
881 set_seg(&sregs.ds, &env->segs[R_DS]);
882 set_seg(&sregs.es, &env->segs[R_ES]);
883 set_seg(&sregs.fs, &env->segs[R_FS]);
884 set_seg(&sregs.gs, &env->segs[R_GS]);
885 set_seg(&sregs.ss, &env->segs[R_SS]);
886
887 if (env->cr[0] & CR0_PE_MASK) {
888 /* force ss cpl to cs cpl */
889 sregs.ss.selector = (sregs.ss.selector & ~3) |
890 (sregs.cs.selector & 3);
891 sregs.ss.dpl = sregs.ss.selector & 3;
892 }
893 }
894
895 set_seg(&sregs.tr, &env->tr);
896 set_seg(&sregs.ldt, &env->ldt);
897
898 sregs.idt.limit = env->idt.limit;
899 sregs.idt.base = env->idt.base;
900 sregs.gdt.limit = env->gdt.limit;
901 sregs.gdt.base = env->gdt.base;
902
903 sregs.cr0 = env->cr[0];
904 sregs.cr2 = env->cr[2];
905 sregs.cr3 = env->cr[3];
906 sregs.cr4 = env->cr[4];
907
908 sregs.cr8 = cpu_get_apic_tpr(env);
909 sregs.apic_base = cpu_get_apic_base(env);
910
911 sregs.efer = env->efer;
912
913 kvm_set_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
914
915 /* msrs */
916 n = 0;
917 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
918 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
919 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
920 if (kvm_has_msr_star)
921 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
922 if (kvm_has_vm_hsave_pa)
923 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
924 #ifdef TARGET_X86_64
925 if (lm_capable_kernel) {
926 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
927 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
928 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
929 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
930 }
931 #endif
932
933 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
934 if (rc == -1)
935 perror("kvm_set_msrs FAILED");
936 }
937
938 void kvm_load_tsc(CPUState *env)
939 {
940 int rc;
941 struct kvm_msr_entry msr;
942
943 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
944
945 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, &msr, 1);
946 if (rc == -1)
947 perror("kvm_set_tsc FAILED.\n");
948 }
949
950 void kvm_arch_save_mpstate(CPUState *env)
951 {
952 #ifdef KVM_CAP_MP_STATE
953 int r;
954 struct kvm_mp_state mp_state;
955
956 r = kvm_get_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
957 if (r < 0)
958 env->mp_state = -1;
959 else
960 env->mp_state = mp_state.mp_state;
961 #endif
962 }
963
964 void kvm_arch_load_mpstate(CPUState *env)
965 {
966 #ifdef KVM_CAP_MP_STATE
967 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
968
969 /*
970 * -1 indicates that the host did not support GET_MP_STATE ioctl,
971 * so don't touch it.
972 */
973 if (env->mp_state != -1)
974 kvm_set_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
975 #endif
976 }
977
978 void kvm_arch_save_regs(CPUState *env)
979 {
980 struct kvm_regs regs;
981 struct kvm_fpu fpu;
982 struct kvm_sregs sregs;
983 struct kvm_msr_entry msrs[MSR_COUNT];
984 uint32_t hflags;
985 uint32_t i, n, rc;
986
987 kvm_get_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
988
989 env->regs[R_EAX] = regs.rax;
990 env->regs[R_EBX] = regs.rbx;
991 env->regs[R_ECX] = regs.rcx;
992 env->regs[R_EDX] = regs.rdx;
993 env->regs[R_ESI] = regs.rsi;
994 env->regs[R_EDI] = regs.rdi;
995 env->regs[R_ESP] = regs.rsp;
996 env->regs[R_EBP] = regs.rbp;
997 #ifdef TARGET_X86_64
998 env->regs[8] = regs.r8;
999 env->regs[9] = regs.r9;
1000 env->regs[10] = regs.r10;
1001 env->regs[11] = regs.r11;
1002 env->regs[12] = regs.r12;
1003 env->regs[13] = regs.r13;
1004 env->regs[14] = regs.r14;
1005 env->regs[15] = regs.r15;
1006 #endif
1007
1008 env->eflags = regs.rflags;
1009 env->eip = regs.rip;
1010
1011 kvm_get_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
1012 env->fpstt = (fpu.fsw >> 11) & 7;
1013 env->fpus = fpu.fsw;
1014 env->fpuc = fpu.fcw;
1015 for (i = 0; i < 8; ++i)
1016 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1017 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1018 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1019 env->mxcsr = fpu.mxcsr;
1020
1021 kvm_get_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
1022
1023 memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
1024
1025 get_seg(&env->segs[R_CS], &sregs.cs);
1026 get_seg(&env->segs[R_DS], &sregs.ds);
1027 get_seg(&env->segs[R_ES], &sregs.es);
1028 get_seg(&env->segs[R_FS], &sregs.fs);
1029 get_seg(&env->segs[R_GS], &sregs.gs);
1030 get_seg(&env->segs[R_SS], &sregs.ss);
1031
1032 get_seg(&env->tr, &sregs.tr);
1033 get_seg(&env->ldt, &sregs.ldt);
1034
1035 env->idt.limit = sregs.idt.limit;
1036 env->idt.base = sregs.idt.base;
1037 env->gdt.limit = sregs.gdt.limit;
1038 env->gdt.base = sregs.gdt.base;
1039
1040 env->cr[0] = sregs.cr0;
1041 env->cr[2] = sregs.cr2;
1042 env->cr[3] = sregs.cr3;
1043 env->cr[4] = sregs.cr4;
1044
1045 cpu_set_apic_base(env, sregs.apic_base);
1046
1047 env->efer = sregs.efer;
1048 //cpu_set_apic_tpr(env, sregs.cr8);
1049
1050 #define HFLAG_COPY_MASK ~( \
1051 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1052 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1053 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1054 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1055
1056
1057
1058 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1059 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1060 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1061 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1062 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1063 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1064 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1065
1066 if (env->efer & MSR_EFER_LMA) {
1067 hflags |= HF_LMA_MASK;
1068 }
1069
1070 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1071 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1072 } else {
1073 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1074 (DESC_B_SHIFT - HF_CS32_SHIFT);
1075 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1076 (DESC_B_SHIFT - HF_SS32_SHIFT);
1077 if (!(env->cr[0] & CR0_PE_MASK) ||
1078 (env->eflags & VM_MASK) ||
1079 !(hflags & HF_CS32_MASK)) {
1080 hflags |= HF_ADDSEG_MASK;
1081 } else {
1082 hflags |= ((env->segs[R_DS].base |
1083 env->segs[R_ES].base |
1084 env->segs[R_SS].base) != 0) <<
1085 HF_ADDSEG_SHIFT;
1086 }
1087 }
1088 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1089
1090 /* msrs */
1091 n = 0;
1092 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1093 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1094 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1095 if (kvm_has_msr_star)
1096 msrs[n++].index = MSR_STAR;
1097 msrs[n++].index = MSR_IA32_TSC;
1098 if (kvm_has_vm_hsave_pa)
1099 msrs[n++].index = MSR_VM_HSAVE_PA;
1100 #ifdef TARGET_X86_64
1101 if (lm_capable_kernel) {
1102 msrs[n++].index = MSR_CSTAR;
1103 msrs[n++].index = MSR_KERNELGSBASE;
1104 msrs[n++].index = MSR_FMASK;
1105 msrs[n++].index = MSR_LSTAR;
1106 }
1107 #endif
1108 rc = kvm_get_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
1109 if (rc == -1) {
1110 perror("kvm_get_msrs FAILED");
1111 }
1112 else {
1113 n = rc; /* actual number of MSRs */
1114 for (i=0 ; i<n; i++) {
1115 if (get_msr_entry(&msrs[i], env))
1116 return;
1117 }
1118 }
1119 }
1120
1121 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
1122 uint32_t count, CPUState *env)
1123 {
1124 env->regs[R_EAX] = function;
1125 env->regs[R_ECX] = count;
1126 qemu_kvm_cpuid_on_env(env);
1127 e->function = function;
1128 e->flags = 0;
1129 e->index = 0;
1130 e->eax = env->regs[R_EAX];
1131 e->ebx = env->regs[R_EBX];
1132 e->ecx = env->regs[R_ECX];
1133 e->edx = env->regs[R_EDX];
1134 }
1135
1136 struct kvm_para_features {
1137 int cap;
1138 int feature;
1139 } para_features[] = {
1140 #ifdef KVM_CAP_CLOCKSOURCE
1141 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
1142 #endif
1143 #ifdef KVM_CAP_NOP_IO_DELAY
1144 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
1145 #endif
1146 #ifdef KVM_CAP_PV_MMU
1147 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
1148 #endif
1149 #ifdef KVM_CAP_CR3_CACHE
1150 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
1151 #endif
1152 { -1, -1 }
1153 };
1154
1155 static int get_para_features(kvm_context_t kvm_context)
1156 {
1157 int i, features = 0;
1158
1159 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
1160 if (kvm_check_extension(kvm_context, para_features[i].cap))
1161 features |= (1 << para_features[i].feature);
1162 }
1163
1164 return features;
1165 }
1166
1167 static void kvm_trim_features(uint32_t *features, uint32_t supported)
1168 {
1169 int i;
1170 uint32_t mask;
1171
1172 for (i = 0; i < 32; ++i) {
1173 mask = 1U << i;
1174 if ((*features & mask) && !(supported & mask)) {
1175 *features &= ~mask;
1176 }
1177 }
1178 }
1179
1180 int kvm_arch_qemu_init_env(CPUState *cenv)
1181 {
1182 struct kvm_cpuid_entry2 cpuid_ent[100];
1183 #ifdef KVM_CPUID_SIGNATURE
1184 struct kvm_cpuid_entry2 *pv_ent;
1185 uint32_t signature[3];
1186 #endif
1187 int cpuid_nent = 0;
1188 CPUState copy;
1189 uint32_t i, j, limit;
1190
1191 qemu_kvm_load_lapic(cenv);
1192
1193 copy = *cenv;
1194
1195 #ifdef KVM_CPUID_SIGNATURE
1196 /* Paravirtualization CPUIDs */
1197 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1198 pv_ent = &cpuid_ent[cpuid_nent++];
1199 memset(pv_ent, 0, sizeof(*pv_ent));
1200 pv_ent->function = KVM_CPUID_SIGNATURE;
1201 pv_ent->eax = 0;
1202 pv_ent->ebx = signature[0];
1203 pv_ent->ecx = signature[1];
1204 pv_ent->edx = signature[2];
1205
1206 pv_ent = &cpuid_ent[cpuid_nent++];
1207 memset(pv_ent, 0, sizeof(*pv_ent));
1208 pv_ent->function = KVM_CPUID_FEATURES;
1209 pv_ent->eax = get_para_features(kvm_context);
1210 #endif
1211
1212 copy.regs[R_EAX] = 0;
1213 qemu_kvm_cpuid_on_env(&copy);
1214 limit = copy.regs[R_EAX];
1215
1216 for (i = 0; i <= limit; ++i) {
1217 if (i == 4 || i == 0xb || i == 0xd) {
1218 for (j = 0; ; ++j) {
1219 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
1220
1221 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1222 cpuid_ent[cpuid_nent].index = j;
1223
1224 cpuid_nent++;
1225
1226 if (i == 4 && copy.regs[R_EAX] == 0)
1227 break;
1228 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
1229 break;
1230 if (i == 0xd && copy.regs[R_EAX] == 0)
1231 break;
1232 }
1233 } else
1234 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1235 }
1236
1237 copy.regs[R_EAX] = 0x80000000;
1238 qemu_kvm_cpuid_on_env(&copy);
1239 limit = copy.regs[R_EAX];
1240
1241 for (i = 0x80000000; i <= limit; ++i)
1242 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1243
1244 kvm_setup_cpuid2(cenv->kvm_cpu_state.vcpu_ctx, cpuid_nent, cpuid_ent);
1245
1246 kvm_trim_features(&cenv->cpuid_features,
1247 kvm_arch_get_supported_cpuid(cenv, 1, R_EDX));
1248 kvm_trim_features(&cenv->cpuid_ext_features,
1249 kvm_arch_get_supported_cpuid(cenv, 1, R_ECX));
1250 kvm_trim_features(&cenv->cpuid_ext2_features,
1251 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_EDX));
1252 kvm_trim_features(&cenv->cpuid_ext3_features,
1253 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_ECX));
1254
1255 return 0;
1256 }
1257
1258 int kvm_arch_halt(void *opaque, kvm_vcpu_context_t vcpu)
1259 {
1260 CPUState *env = cpu_single_env;
1261
1262 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1263 (env->eflags & IF_MASK)) &&
1264 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1265 env->halted = 1;
1266 }
1267 return 1;
1268 }
1269
1270 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
1271 {
1272 if (!kvm_irqchip_in_kernel(kvm_context))
1273 kvm_set_cr8(env->kvm_cpu_state.vcpu_ctx, cpu_get_apic_tpr(env));
1274 }
1275
1276 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
1277 {
1278 cpu_single_env = env;
1279
1280 env->eflags = kvm_get_interrupt_flag(env->kvm_cpu_state.vcpu_ctx)
1281 ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
1282
1283 cpu_set_apic_tpr(env, kvm_get_cr8(env->kvm_cpu_state.vcpu_ctx));
1284 cpu_set_apic_base(env, kvm_get_apic_base(env->kvm_cpu_state.vcpu_ctx));
1285 }
1286
1287 int kvm_arch_has_work(CPUState *env)
1288 {
1289 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1290 (env->eflags & IF_MASK)) ||
1291 (env->interrupt_request & CPU_INTERRUPT_NMI))
1292 return 1;
1293 return 0;
1294 }
1295
1296 int kvm_arch_try_push_interrupts(void *opaque)
1297 {
1298 CPUState *env = cpu_single_env;
1299 int r, irq;
1300
1301 if (kvm_is_ready_for_interrupt_injection(env->kvm_cpu_state.vcpu_ctx) &&
1302 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1303 (env->eflags & IF_MASK)) {
1304 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1305 irq = cpu_get_pic_interrupt(env);
1306 if (irq >= 0) {
1307 r = kvm_inject_irq(env->kvm_cpu_state.vcpu_ctx, irq);
1308 if (r < 0)
1309 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
1310 }
1311 }
1312
1313 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
1314 }
1315
1316 #ifdef KVM_CAP_USER_NMI
1317 void kvm_arch_push_nmi(void *opaque)
1318 {
1319 CPUState *env = cpu_single_env;
1320 int r;
1321
1322 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
1323 return;
1324
1325 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1326 r = kvm_inject_nmi(env->kvm_cpu_state.vcpu_ctx);
1327 if (r < 0)
1328 printf("cpu %d fail inject NMI\n", env->cpu_index);
1329 }
1330 #endif /* KVM_CAP_USER_NMI */
1331
1332 void kvm_arch_update_regs_for_sipi(CPUState *env)
1333 {
1334 SegmentCache cs = env->segs[R_CS];
1335
1336 kvm_arch_save_regs(env);
1337 env->segs[R_CS] = cs;
1338 env->eip = 0;
1339 kvm_arch_load_regs(env);
1340 }
1341
1342 int handle_tpr_access(void *opaque, kvm_vcpu_context_t vcpu,
1343 uint64_t rip, int is_write)
1344 {
1345 kvm_tpr_access_report(cpu_single_env, rip, is_write);
1346 return 0;
1347 }
1348
1349 void kvm_arch_cpu_reset(CPUState *env)
1350 {
1351 kvm_arch_load_regs(env);
1352 if (env->cpu_index != 0) {
1353 if (kvm_irqchip_in_kernel(kvm_context)) {
1354 #ifdef KVM_CAP_MP_STATE
1355 kvm_reset_mpstate(env->kvm_cpu_state.vcpu_ctx);
1356 #endif
1357 } else {
1358 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1359 env->halted = 1;
1360 }
1361 }
1362 }
1363
1364 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1365 {
1366 uint8_t int3 = 0xcc;
1367
1368 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1369 cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
1370 return -EINVAL;
1371 return 0;
1372 }
1373
1374 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1375 {
1376 uint8_t int3;
1377
1378 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1379 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1380 return -EINVAL;
1381 return 0;
1382 }
1383
1384 #ifdef KVM_CAP_SET_GUEST_DEBUG
1385 static struct {
1386 target_ulong addr;
1387 int len;
1388 int type;
1389 } hw_breakpoint[4];
1390
1391 static int nb_hw_breakpoint;
1392
1393 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1394 {
1395 int n;
1396
1397 for (n = 0; n < nb_hw_breakpoint; n++)
1398 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1399 (hw_breakpoint[n].len == len || len == -1))
1400 return n;
1401 return -1;
1402 }
1403
1404 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1405 target_ulong len, int type)
1406 {
1407 switch (type) {
1408 case GDB_BREAKPOINT_HW:
1409 len = 1;
1410 break;
1411 case GDB_WATCHPOINT_WRITE:
1412 case GDB_WATCHPOINT_ACCESS:
1413 switch (len) {
1414 case 1:
1415 break;
1416 case 2:
1417 case 4:
1418 case 8:
1419 if (addr & (len - 1))
1420 return -EINVAL;
1421 break;
1422 default:
1423 return -EINVAL;
1424 }
1425 break;
1426 default:
1427 return -ENOSYS;
1428 }
1429
1430 if (nb_hw_breakpoint == 4)
1431 return -ENOBUFS;
1432
1433 if (find_hw_breakpoint(addr, len, type) >= 0)
1434 return -EEXIST;
1435
1436 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1437 hw_breakpoint[nb_hw_breakpoint].len = len;
1438 hw_breakpoint[nb_hw_breakpoint].type = type;
1439 nb_hw_breakpoint++;
1440
1441 return 0;
1442 }
1443
1444 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1445 target_ulong len, int type)
1446 {
1447 int n;
1448
1449 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1450 if (n < 0)
1451 return -ENOENT;
1452
1453 nb_hw_breakpoint--;
1454 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1455
1456 return 0;
1457 }
1458
1459 void kvm_arch_remove_all_hw_breakpoints(void)
1460 {
1461 nb_hw_breakpoint = 0;
1462 }
1463
1464 static CPUWatchpoint hw_watchpoint;
1465
1466 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1467 {
1468 int handle = 0;
1469 int n;
1470
1471 if (arch_info->exception == 1) {
1472 if (arch_info->dr6 & (1 << 14)) {
1473 if (cpu_single_env->singlestep_enabled)
1474 handle = 1;
1475 } else {
1476 for (n = 0; n < 4; n++)
1477 if (arch_info->dr6 & (1 << n))
1478 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1479 case 0x0:
1480 handle = 1;
1481 break;
1482 case 0x1:
1483 handle = 1;
1484 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1485 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1486 hw_watchpoint.flags = BP_MEM_WRITE;
1487 break;
1488 case 0x3:
1489 handle = 1;
1490 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1491 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1492 hw_watchpoint.flags = BP_MEM_ACCESS;
1493 break;
1494 }
1495 }
1496 } else if (kvm_find_sw_breakpoint(arch_info->pc))
1497 handle = 1;
1498
1499 if (!handle)
1500 kvm_update_guest_debug(cpu_single_env,
1501 (arch_info->exception == 1) ?
1502 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1503
1504 return handle;
1505 }
1506
1507 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1508 {
1509 const uint8_t type_code[] = {
1510 [GDB_BREAKPOINT_HW] = 0x0,
1511 [GDB_WATCHPOINT_WRITE] = 0x1,
1512 [GDB_WATCHPOINT_ACCESS] = 0x3
1513 };
1514 const uint8_t len_code[] = {
1515 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1516 };
1517 int n;
1518
1519 if (!TAILQ_EMPTY(&kvm_sw_breakpoints))
1520 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1521
1522 if (nb_hw_breakpoint > 0) {
1523 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1524 dbg->arch.debugreg[7] = 0x0600;
1525 for (n = 0; n < nb_hw_breakpoint; n++) {
1526 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1527 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1528 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1529 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1530 }
1531 }
1532 }
1533 #endif
1534
1535 void kvm_arch_do_ioperm(void *_data)
1536 {
1537 struct ioperm_data *data = _data;
1538 ioperm(data->start_port, data->num, data->turn_on);
1539 }
1540
1541 /*
1542 * Setup x86 specific IRQ routing
1543 */
1544 int kvm_arch_init_irq_routing(void)
1545 {
1546 int i, r;
1547
1548 if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
1549 kvm_clear_gsi_routes(kvm_context);
1550 for (i = 0; i < 8; ++i) {
1551 if (i == 2)
1552 continue;
1553 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
1554 if (r < 0)
1555 return r;
1556 }
1557 for (i = 8; i < 16; ++i) {
1558 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
1559 if (r < 0)
1560 return r;
1561 }
1562 for (i = 0; i < 24; ++i) {
1563 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
1564 if (r < 0)
1565 return r;
1566 }
1567 kvm_commit_irq_routes(kvm_context);
1568 }
1569 return 0;
1570 }
1571
1572 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
1573 int reg)
1574 {
1575 return kvm_get_supported_cpuid(kvm_context, function, reg);
1576 }
Patches shipped by Fedora