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Cirrus: remove extraneous assignment (if !ok limit is not used)
[qemu-kvm/fedora.git] / hw / cirrus_vga.c
blobf18c70749f2f157fe1ad4ceb4058edec9556ad65
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "vl.h"
30 #include "vga_int.h"
31 #ifndef _WIN32
32 #include <sys/mman.h>
33 #endif
34
35 /*
36 * TODO:
37 * - destination write mask support not complete (bits 5..7)
38 * - optimize linear mappings
39 * - optimize bitblt functions
40 */
41
42 //#define DEBUG_CIRRUS
43 //#define DEBUG_BITBLT
44
45 /***************************************
46 *
47 * definitions
48 *
49 ***************************************/
50
51 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
52
53 // ID
54 #define CIRRUS_ID_CLGD5422 (0x23<<2)
55 #define CIRRUS_ID_CLGD5426 (0x24<<2)
56 #define CIRRUS_ID_CLGD5424 (0x25<<2)
57 #define CIRRUS_ID_CLGD5428 (0x26<<2)
58 #define CIRRUS_ID_CLGD5430 (0x28<<2)
59 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
60 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
61 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
62
63 // sequencer 0x07
64 #define CIRRUS_SR7_BPP_VGA 0x00
65 #define CIRRUS_SR7_BPP_SVGA 0x01
66 #define CIRRUS_SR7_BPP_MASK 0x0e
67 #define CIRRUS_SR7_BPP_8 0x00
68 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69 #define CIRRUS_SR7_BPP_24 0x04
70 #define CIRRUS_SR7_BPP_16 0x06
71 #define CIRRUS_SR7_BPP_32 0x08
72 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
73
74 // sequencer 0x0f
75 #define CIRRUS_MEMSIZE_512k 0x08
76 #define CIRRUS_MEMSIZE_1M 0x10
77 #define CIRRUS_MEMSIZE_2M 0x18
78 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
79
80 // sequencer 0x12
81 #define CIRRUS_CURSOR_SHOW 0x01
82 #define CIRRUS_CURSOR_HIDDENPEL 0x02
83 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
84
85 // sequencer 0x17
86 #define CIRRUS_BUSTYPE_VLBFAST 0x10
87 #define CIRRUS_BUSTYPE_PCI 0x20
88 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
89 #define CIRRUS_BUSTYPE_ISA 0x38
90 #define CIRRUS_MMIO_ENABLE 0x04
91 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
93
94 // control 0x0b
95 #define CIRRUS_BANKING_DUAL 0x01
96 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
97
98 // control 0x30
99 #define CIRRUS_BLTMODE_BACKWARDS 0x01
100 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
105 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
110
111 // control 0x31
112 #define CIRRUS_BLT_BUSY 0x01
113 #define CIRRUS_BLT_START 0x02
114 #define CIRRUS_BLT_RESET 0x04
115 #define CIRRUS_BLT_FIFOUSED 0x10
116 #define CIRRUS_BLT_AUTOSTART 0x80
117
118 // control 0x32
119 #define CIRRUS_ROP_0 0x00
120 #define CIRRUS_ROP_SRC_AND_DST 0x05
121 #define CIRRUS_ROP_NOP 0x06
122 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123 #define CIRRUS_ROP_NOTDST 0x0b
124 #define CIRRUS_ROP_SRC 0x0d
125 #define CIRRUS_ROP_1 0x0e
126 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127 #define CIRRUS_ROP_SRC_XOR_DST 0x59
128 #define CIRRUS_ROP_SRC_OR_DST 0x6d
129 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132 #define CIRRUS_ROP_NOTSRC 0xd0
133 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
135
136 #define CIRRUS_ROP_NOP_INDEX 2
137 #define CIRRUS_ROP_SRC_INDEX 5
138
139 // control 0x33
140 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
141 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
142 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
143
144 // memory-mapped IO
145 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
155 #define CIRRUS_MMIO_BLTROP 0x1a // byte
156 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
174
175 // PCI 0x00: vendor, 0x02: device
176 #define PCI_VENDOR_CIRRUS 0x1013
177 #define PCI_DEVICE_CLGD5462 0x00d0
178 #define PCI_DEVICE_CLGD5465 0x00d6
179
180 // PCI 0x04: command(word), 0x06(word): status
181 #define PCI_COMMAND_IOACCESS 0x0001
182 #define PCI_COMMAND_MEMACCESS 0x0002
183 #define PCI_COMMAND_BUSMASTER 0x0004
184 #define PCI_COMMAND_SPECIALCYCLE 0x0008
185 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
186 #define PCI_COMMAND_PALETTESNOOPING 0x0020
187 #define PCI_COMMAND_PARITYDETECTION 0x0040
188 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
189 #define PCI_COMMAND_SERR 0x0100
190 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
191 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
192 #define PCI_CLASS_BASE_DISPLAY 0x03
193 // PCI 0x08, 0x00ff0000
194 #define PCI_CLASS_SUB_VGA 0x00
195 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
196 #define PCI_CLASS_HEADERTYPE_00h 0x00
197 // 0x10-0x3f (headertype 00h)
198 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
199 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
200 #define PCI_MAP_MEM 0x0
201 #define PCI_MAP_IO 0x1
202 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
203 #define PCI_MAP_IO_ADDR_MASK (~0x3)
204 #define PCI_MAP_MEMFLAGS_32BIT 0x0
205 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
206 #define PCI_MAP_MEMFLAGS_64BIT 0x4
207 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
208 // PCI 0x28: cardbus CIS pointer
209 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
210 // PCI 0x30: expansion ROM base address
211 #define PCI_ROMBIOS_ENABLED 0x1
212 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
213 // PCI 0x38: reserved
214 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
215
216 #define CIRRUS_PNPMMIO_SIZE 0x1000
217
218
219 /* I/O and memory hook */
220 #define CIRRUS_HOOK_NOT_HANDLED 0
221 #define CIRRUS_HOOK_HANDLED 1
222
223 struct CirrusVGAState;
224 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
225 uint8_t * dst, const uint8_t * src,
226 int dstpitch, int srcpitch,
227 int bltwidth, int bltheight);
228 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
229 uint8_t *dst, int dst_pitch, int width, int height);
230
231 typedef struct CirrusVGAState {
232 VGA_STATE_COMMON
233
234 int cirrus_linear_io_addr;
235 int cirrus_linear_bitblt_io_addr;
236 int cirrus_mmio_io_addr;
237 #ifdef USE_KVM
238 unsigned long cirrus_lfb_addr;
239 unsigned long cirrus_lfb_end;
240 int aliases_enabled;
241 uint32_t aliased_bank_base[2];
242 uint32_t aliased_bank_limit[2];
243 #endif
244 uint32_t cirrus_addr_mask;
245 uint32_t linear_mmio_mask;
246 uint8_t cirrus_shadow_gr0;
247 uint8_t cirrus_shadow_gr1;
248 uint8_t cirrus_hidden_dac_lockindex;
249 uint8_t cirrus_hidden_dac_data;
250 uint32_t cirrus_bank_base[2];
251 uint32_t cirrus_bank_limit[2];
252 uint8_t cirrus_hidden_palette[48];
253 uint32_t hw_cursor_x;
254 uint32_t hw_cursor_y;
255 int cirrus_blt_pixelwidth;
256 int cirrus_blt_width;
257 int cirrus_blt_height;
258 int cirrus_blt_dstpitch;
259 int cirrus_blt_srcpitch;
260 uint32_t cirrus_blt_fgcol;
261 uint32_t cirrus_blt_bgcol;
262 uint32_t cirrus_blt_dstaddr;
263 uint32_t cirrus_blt_srcaddr;
264 uint8_t cirrus_blt_mode;
265 uint8_t cirrus_blt_modeext;
266 cirrus_bitblt_rop_t cirrus_rop;
267 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
268 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
269 uint8_t *cirrus_srcptr;
270 uint8_t *cirrus_srcptr_end;
271 uint32_t cirrus_srccounter;
272 /* hwcursor display state */
273 int last_hw_cursor_size;
274 int last_hw_cursor_x;
275 int last_hw_cursor_y;
276 int last_hw_cursor_y_start;
277 int last_hw_cursor_y_end;
278 int real_vram_size; /* XXX: suppress that */
279 CPUWriteMemoryFunc **cirrus_linear_write;
280 #ifdef USE_KVM
281 unsigned long map_addr;
282 unsigned long map_end;
283 #endif
284 } CirrusVGAState;
285
286 typedef struct PCICirrusVGAState {
287 PCIDevice dev;
288 CirrusVGAState cirrus_vga;
289 } PCICirrusVGAState;
290
291 static uint8_t rop_to_index[256];
292
293 /***************************************
294 *
295 * prototypes.
296 *
297 ***************************************/
298
299
300 static void cirrus_bitblt_reset(CirrusVGAState *s);
301 static void cirrus_update_memory_access(CirrusVGAState *s);
302
303 /***************************************
304 *
305 * raster operations
306 *
307 ***************************************/
308
309 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
310 uint8_t *dst,const uint8_t *src,
311 int dstpitch,int srcpitch,
312 int bltwidth,int bltheight)
313 {
314 }
315
316 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
317 uint8_t *dst,
318 int dstpitch, int bltwidth,int bltheight)
319 {
320 }
321
322 #define ROP_NAME 0
323 #define ROP_OP(d, s) d = 0
324 #include "cirrus_vga_rop.h"
325
326 #define ROP_NAME src_and_dst
327 #define ROP_OP(d, s) d = (s) & (d)
328 #include "cirrus_vga_rop.h"
329
330 #define ROP_NAME src_and_notdst
331 #define ROP_OP(d, s) d = (s) & (~(d))
332 #include "cirrus_vga_rop.h"
333
334 #define ROP_NAME notdst
335 #define ROP_OP(d, s) d = ~(d)
336 #include "cirrus_vga_rop.h"
337
338 #define ROP_NAME src
339 #define ROP_OP(d, s) d = s
340 #include "cirrus_vga_rop.h"
341
342 #define ROP_NAME 1
343 #define ROP_OP(d, s) d = ~0
344 #include "cirrus_vga_rop.h"
345
346 #define ROP_NAME notsrc_and_dst
347 #define ROP_OP(d, s) d = (~(s)) & (d)
348 #include "cirrus_vga_rop.h"
349
350 #define ROP_NAME src_xor_dst
351 #define ROP_OP(d, s) d = (s) ^ (d)
352 #include "cirrus_vga_rop.h"
353
354 #define ROP_NAME src_or_dst
355 #define ROP_OP(d, s) d = (s) | (d)
356 #include "cirrus_vga_rop.h"
357
358 #define ROP_NAME notsrc_or_notdst
359 #define ROP_OP(d, s) d = (~(s)) | (~(d))
360 #include "cirrus_vga_rop.h"
361
362 #define ROP_NAME src_notxor_dst
363 #define ROP_OP(d, s) d = ~((s) ^ (d))
364 #include "cirrus_vga_rop.h"
365
366 #define ROP_NAME src_or_notdst
367 #define ROP_OP(d, s) d = (s) | (~(d))
368 #include "cirrus_vga_rop.h"
369
370 #define ROP_NAME notsrc
371 #define ROP_OP(d, s) d = (~(s))
372 #include "cirrus_vga_rop.h"
373
374 #define ROP_NAME notsrc_or_dst
375 #define ROP_OP(d, s) d = (~(s)) | (d)
376 #include "cirrus_vga_rop.h"
377
378 #define ROP_NAME notsrc_and_notdst
379 #define ROP_OP(d, s) d = (~(s)) & (~(d))
380 #include "cirrus_vga_rop.h"
381
382 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
383 cirrus_bitblt_rop_fwd_0,
384 cirrus_bitblt_rop_fwd_src_and_dst,
385 cirrus_bitblt_rop_nop,
386 cirrus_bitblt_rop_fwd_src_and_notdst,
387 cirrus_bitblt_rop_fwd_notdst,
388 cirrus_bitblt_rop_fwd_src,
389 cirrus_bitblt_rop_fwd_1,
390 cirrus_bitblt_rop_fwd_notsrc_and_dst,
391 cirrus_bitblt_rop_fwd_src_xor_dst,
392 cirrus_bitblt_rop_fwd_src_or_dst,
393 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
394 cirrus_bitblt_rop_fwd_src_notxor_dst,
395 cirrus_bitblt_rop_fwd_src_or_notdst,
396 cirrus_bitblt_rop_fwd_notsrc,
397 cirrus_bitblt_rop_fwd_notsrc_or_dst,
398 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
399 };
400
401 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
402 cirrus_bitblt_rop_bkwd_0,
403 cirrus_bitblt_rop_bkwd_src_and_dst,
404 cirrus_bitblt_rop_nop,
405 cirrus_bitblt_rop_bkwd_src_and_notdst,
406 cirrus_bitblt_rop_bkwd_notdst,
407 cirrus_bitblt_rop_bkwd_src,
408 cirrus_bitblt_rop_bkwd_1,
409 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
410 cirrus_bitblt_rop_bkwd_src_xor_dst,
411 cirrus_bitblt_rop_bkwd_src_or_dst,
412 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
413 cirrus_bitblt_rop_bkwd_src_notxor_dst,
414 cirrus_bitblt_rop_bkwd_src_or_notdst,
415 cirrus_bitblt_rop_bkwd_notsrc,
416 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
417 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
418 };
419
420 #define ROP2(name) {\
421 name ## _8,\
422 name ## _16,\
423 name ## _24,\
424 name ## _32,\
425 }
426
427 #define ROP_NOP2(func) {\
428 func,\
429 func,\
430 func,\
431 func,\
432 }
433
434 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
435 ROP2(cirrus_patternfill_0),
436 ROP2(cirrus_patternfill_src_and_dst),
437 ROP_NOP2(cirrus_bitblt_rop_nop),
438 ROP2(cirrus_patternfill_src_and_notdst),
439 ROP2(cirrus_patternfill_notdst),
440 ROP2(cirrus_patternfill_src),
441 ROP2(cirrus_patternfill_1),
442 ROP2(cirrus_patternfill_notsrc_and_dst),
443 ROP2(cirrus_patternfill_src_xor_dst),
444 ROP2(cirrus_patternfill_src_or_dst),
445 ROP2(cirrus_patternfill_notsrc_or_notdst),
446 ROP2(cirrus_patternfill_src_notxor_dst),
447 ROP2(cirrus_patternfill_src_or_notdst),
448 ROP2(cirrus_patternfill_notsrc),
449 ROP2(cirrus_patternfill_notsrc_or_dst),
450 ROP2(cirrus_patternfill_notsrc_and_notdst),
451 };
452
453 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
454 ROP2(cirrus_colorexpand_transp_0),
455 ROP2(cirrus_colorexpand_transp_src_and_dst),
456 ROP_NOP2(cirrus_bitblt_rop_nop),
457 ROP2(cirrus_colorexpand_transp_src_and_notdst),
458 ROP2(cirrus_colorexpand_transp_notdst),
459 ROP2(cirrus_colorexpand_transp_src),
460 ROP2(cirrus_colorexpand_transp_1),
461 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
462 ROP2(cirrus_colorexpand_transp_src_xor_dst),
463 ROP2(cirrus_colorexpand_transp_src_or_dst),
464 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
465 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
466 ROP2(cirrus_colorexpand_transp_src_or_notdst),
467 ROP2(cirrus_colorexpand_transp_notsrc),
468 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
469 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
470 };
471
472 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
473 ROP2(cirrus_colorexpand_0),
474 ROP2(cirrus_colorexpand_src_and_dst),
475 ROP_NOP2(cirrus_bitblt_rop_nop),
476 ROP2(cirrus_colorexpand_src_and_notdst),
477 ROP2(cirrus_colorexpand_notdst),
478 ROP2(cirrus_colorexpand_src),
479 ROP2(cirrus_colorexpand_1),
480 ROP2(cirrus_colorexpand_notsrc_and_dst),
481 ROP2(cirrus_colorexpand_src_xor_dst),
482 ROP2(cirrus_colorexpand_src_or_dst),
483 ROP2(cirrus_colorexpand_notsrc_or_notdst),
484 ROP2(cirrus_colorexpand_src_notxor_dst),
485 ROP2(cirrus_colorexpand_src_or_notdst),
486 ROP2(cirrus_colorexpand_notsrc),
487 ROP2(cirrus_colorexpand_notsrc_or_dst),
488 ROP2(cirrus_colorexpand_notsrc_and_notdst),
489 };
490
491 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
492 ROP2(cirrus_colorexpand_pattern_transp_0),
493 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
494 ROP_NOP2(cirrus_bitblt_rop_nop),
495 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
496 ROP2(cirrus_colorexpand_pattern_transp_notdst),
497 ROP2(cirrus_colorexpand_pattern_transp_src),
498 ROP2(cirrus_colorexpand_pattern_transp_1),
499 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
500 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
501 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
502 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
503 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
504 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
505 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
506 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
507 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
508 };
509
510 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
511 ROP2(cirrus_colorexpand_pattern_0),
512 ROP2(cirrus_colorexpand_pattern_src_and_dst),
513 ROP_NOP2(cirrus_bitblt_rop_nop),
514 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
515 ROP2(cirrus_colorexpand_pattern_notdst),
516 ROP2(cirrus_colorexpand_pattern_src),
517 ROP2(cirrus_colorexpand_pattern_1),
518 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
519 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
520 ROP2(cirrus_colorexpand_pattern_src_or_dst),
521 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
522 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
523 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
524 ROP2(cirrus_colorexpand_pattern_notsrc),
525 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
526 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
527 };
528
529 static const cirrus_fill_t cirrus_fill[16][4] = {
530 ROP2(cirrus_fill_0),
531 ROP2(cirrus_fill_src_and_dst),
532 ROP_NOP2(cirrus_bitblt_fill_nop),
533 ROP2(cirrus_fill_src_and_notdst),
534 ROP2(cirrus_fill_notdst),
535 ROP2(cirrus_fill_src),
536 ROP2(cirrus_fill_1),
537 ROP2(cirrus_fill_notsrc_and_dst),
538 ROP2(cirrus_fill_src_xor_dst),
539 ROP2(cirrus_fill_src_or_dst),
540 ROP2(cirrus_fill_notsrc_or_notdst),
541 ROP2(cirrus_fill_src_notxor_dst),
542 ROP2(cirrus_fill_src_or_notdst),
543 ROP2(cirrus_fill_notsrc),
544 ROP2(cirrus_fill_notsrc_or_dst),
545 ROP2(cirrus_fill_notsrc_and_notdst),
546 };
547
548 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
549 {
550 unsigned int color;
551 switch (s->cirrus_blt_pixelwidth) {
552 case 1:
553 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
554 break;
555 case 2:
556 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
557 s->cirrus_blt_fgcol = le16_to_cpu(color);
558 break;
559 case 3:
560 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
561 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
562 break;
563 default:
564 case 4:
565 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
566 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
567 s->cirrus_blt_fgcol = le32_to_cpu(color);
568 break;
569 }
570 }
571
572 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
573 {
574 unsigned int color;
575 switch (s->cirrus_blt_pixelwidth) {
576 case 1:
577 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
578 break;
579 case 2:
580 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
581 s->cirrus_blt_bgcol = le16_to_cpu(color);
582 break;
583 case 3:
584 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
585 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
586 break;
587 default:
588 case 4:
589 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
590 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
591 s->cirrus_blt_bgcol = le32_to_cpu(color);
592 break;
593 }
594 }
595
596 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
597 int off_pitch, int bytesperline,
598 int lines)
599 {
600 int y;
601 int off_cur;
602 int off_cur_end;
603
604 for (y = 0; y < lines; y++) {
605 off_cur = off_begin;
606 off_cur_end = off_cur + bytesperline;
607 off_cur &= TARGET_PAGE_MASK;
608 while (off_cur < off_cur_end) {
609 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
610 off_cur += TARGET_PAGE_SIZE;
611 }
612 off_begin += off_pitch;
613 }
614 }
615
616 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
617 const uint8_t * src)
618 {
619 uint8_t *dst;
620
621 dst = s->vram_ptr + s->cirrus_blt_dstaddr;
622 (*s->cirrus_rop) (s, dst, src,
623 s->cirrus_blt_dstpitch, 0,
624 s->cirrus_blt_width, s->cirrus_blt_height);
625 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
626 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
627 s->cirrus_blt_height);
628 return 1;
629 }
630
631 /* fill */
632
633 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
634 {
635 cirrus_fill_t rop_func;
636
637 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
638 rop_func(s, s->vram_ptr + s->cirrus_blt_dstaddr,
639 s->cirrus_blt_dstpitch,
640 s->cirrus_blt_width, s->cirrus_blt_height);
641 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
642 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
643 s->cirrus_blt_height);
644 cirrus_bitblt_reset(s);
645 return 1;
646 }
647
648 /***************************************
649 *
650 * bitblt (video-to-video)
651 *
652 ***************************************/
653
654 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
655 {
656 return cirrus_bitblt_common_patterncopy(s,
657 s->vram_ptr +
658 (s->cirrus_blt_srcaddr & ~7));
659 }
660
661 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
662 {
663 int sx, sy;
664 int dx, dy;
665 int width, height;
666 int depth;
667 int notify = 0;
668
669 depth = s->get_bpp((VGAState *)s) / 8;
670 s->get_resolution((VGAState *)s, &width, &height);
671
672 /* extra x, y */
673 sx = (src % (width * depth)) / depth;
674 sy = (src / (width * depth));
675 dx = (dst % (width *depth)) / depth;
676 dy = (dst / (width * depth));
677
678 /* normalize width */
679 w /= depth;
680
681 /* if we're doing a backward copy, we have to adjust
682 our x/y to be the upper left corner (instead of the lower
683 right corner) */
684 if (s->cirrus_blt_dstpitch < 0) {
685 sx -= (s->cirrus_blt_width / depth) - 1;
686 dx -= (s->cirrus_blt_width / depth) - 1;
687 sy -= s->cirrus_blt_height - 1;
688 dy -= s->cirrus_blt_height - 1;
689 }
690
691 /* are we in the visible portion of memory? */
692 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
693 (sx + w) <= width && (sy + h) <= height &&
694 (dx + w) <= width && (dy + h) <= height) {
695 notify = 1;
696 }
697
698 /* make to sure only copy if it's a plain copy ROP */
699 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
700 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
701 notify = 0;
702
703 /* we have to flush all pending changes so that the copy
704 is generated at the appropriate moment in time */
705 if (notify)
706 vga_hw_update();
707
708 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
709 s->vram_ptr + s->cirrus_blt_srcaddr,
710 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
711 s->cirrus_blt_width, s->cirrus_blt_height);
712
713 if (notify)
714 s->ds->dpy_copy(s->ds,
715 sx, sy, dx, dy,
716 s->cirrus_blt_width / depth,
717 s->cirrus_blt_height);
718
719 /* we don't have to notify the display that this portion has
720 changed since dpy_copy implies this */
721
722 if (!notify)
723 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
724 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
725 s->cirrus_blt_height);
726 }
727
728 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
729 {
730 if (s->ds->dpy_copy) {
731 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
732 s->cirrus_blt_srcaddr - s->start_addr,
733 s->cirrus_blt_width, s->cirrus_blt_height);
734 } else {
735 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
736 s->vram_ptr + s->cirrus_blt_srcaddr,
737 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
738 s->cirrus_blt_width, s->cirrus_blt_height);
739
740 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
741 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
742 s->cirrus_blt_height);
743 }
744
745 return 1;
746 }
747
748 /***************************************
749 *
750 * bitblt (cpu-to-video)
751 *
752 ***************************************/
753
754 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
755 {
756 int copy_count;
757 uint8_t *end_ptr;
758
759 if (s->cirrus_srccounter > 0) {
760 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
761 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
762 the_end:
763 s->cirrus_srccounter = 0;
764 cirrus_bitblt_reset(s);
765 } else {
766 /* at least one scan line */
767 do {
768 (*s->cirrus_rop)(s, s->vram_ptr + s->cirrus_blt_dstaddr,
769 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
770 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
771 s->cirrus_blt_width, 1);
772 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
773 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
774 if (s->cirrus_srccounter <= 0)
775 goto the_end;
776 /* more bytes than needed can be transfered because of
777 word alignment, so we keep them for the next line */
778 /* XXX: keep alignment to speed up transfer */
779 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
780 copy_count = s->cirrus_srcptr_end - end_ptr;
781 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
782 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
783 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
784 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
785 }
786 }
787 }
788
789 /***************************************
790 *
791 * bitblt wrapper
792 *
793 ***************************************/
794
795 static void cirrus_bitblt_reset(CirrusVGAState * s)
796 {
797 s->gr[0x31] &=
798 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
799 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
800 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
801 s->cirrus_srccounter = 0;
802 cirrus_update_memory_access(s);
803 }
804
805 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
806 {
807 int w;
808
809 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
810 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
811 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
812
813 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
814 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
815 s->cirrus_blt_srcpitch = 8;
816 } else {
817 /* XXX: check for 24 bpp */
818 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
819 }
820 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
821 } else {
822 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
823 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
824 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
825 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
826 else
827 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
828 } else {
829 /* always align input size to 32 bits */
830 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
831 }
832 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
833 }
834 s->cirrus_srcptr = s->cirrus_bltbuf;
835 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
836 cirrus_update_memory_access(s);
837 return 1;
838 }
839
840 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
841 {
842 /* XXX */
843 #ifdef DEBUG_BITBLT
844 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
845 #endif
846 return 0;
847 }
848
849 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
850 {
851 int ret;
852
853 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
854 ret = cirrus_bitblt_videotovideo_patterncopy(s);
855 } else {
856 ret = cirrus_bitblt_videotovideo_copy(s);
857 }
858 if (ret)
859 cirrus_bitblt_reset(s);
860 return ret;
861 }
862
863 static void cirrus_bitblt_start(CirrusVGAState * s)
864 {
865 uint8_t blt_rop;
866
867 s->gr[0x31] |= CIRRUS_BLT_BUSY;
868
869 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
870 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
871 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
872 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
873 s->cirrus_blt_dstaddr =
874 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
875 s->cirrus_blt_srcaddr =
876 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
877 s->cirrus_blt_mode = s->gr[0x30];
878 s->cirrus_blt_modeext = s->gr[0x33];
879 blt_rop = s->gr[0x32];
880
881 #ifdef DEBUG_BITBLT
882 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
883 blt_rop,
884 s->cirrus_blt_mode,
885 s->cirrus_blt_modeext,
886 s->cirrus_blt_width,
887 s->cirrus_blt_height,
888 s->cirrus_blt_dstpitch,
889 s->cirrus_blt_srcpitch,
890 s->cirrus_blt_dstaddr,
891 s->cirrus_blt_srcaddr,
892 s->gr[0x2f]);
893 #endif
894
895 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
896 case CIRRUS_BLTMODE_PIXELWIDTH8:
897 s->cirrus_blt_pixelwidth = 1;
898 break;
899 case CIRRUS_BLTMODE_PIXELWIDTH16:
900 s->cirrus_blt_pixelwidth = 2;
901 break;
902 case CIRRUS_BLTMODE_PIXELWIDTH24:
903 s->cirrus_blt_pixelwidth = 3;
904 break;
905 case CIRRUS_BLTMODE_PIXELWIDTH32:
906 s->cirrus_blt_pixelwidth = 4;
907 break;
908 default:
909 #ifdef DEBUG_BITBLT
910 printf("cirrus: bitblt - pixel width is unknown\n");
911 #endif
912 goto bitblt_ignore;
913 }
914 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
915
916 if ((s->
917 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
918 CIRRUS_BLTMODE_MEMSYSDEST))
919 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
920 #ifdef DEBUG_BITBLT
921 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
922 #endif
923 goto bitblt_ignore;
924 }
925
926 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
927 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
928 CIRRUS_BLTMODE_TRANSPARENTCOMP |
929 CIRRUS_BLTMODE_PATTERNCOPY |
930 CIRRUS_BLTMODE_COLOREXPAND)) ==
931 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
932 cirrus_bitblt_fgcol(s);
933 cirrus_bitblt_solidfill(s, blt_rop);
934 } else {
935 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
936 CIRRUS_BLTMODE_PATTERNCOPY)) ==
937 CIRRUS_BLTMODE_COLOREXPAND) {
938
939 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
940 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
941 cirrus_bitblt_bgcol(s);
942 else
943 cirrus_bitblt_fgcol(s);
944 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
945 } else {
946 cirrus_bitblt_fgcol(s);
947 cirrus_bitblt_bgcol(s);
948 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
949 }
950 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
951 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
952 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
953 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
954 cirrus_bitblt_bgcol(s);
955 else
956 cirrus_bitblt_fgcol(s);
957 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
958 } else {
959 cirrus_bitblt_fgcol(s);
960 cirrus_bitblt_bgcol(s);
961 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
962 }
963 } else {
964 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
965 }
966 } else {
967 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
968 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
969 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
970 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
971 } else {
972 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
973 }
974 }
975
976 // setup bitblt engine.
977 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
978 if (!cirrus_bitblt_cputovideo(s))
979 goto bitblt_ignore;
980 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
981 if (!cirrus_bitblt_videotocpu(s))
982 goto bitblt_ignore;
983 } else {
984 if (!cirrus_bitblt_videotovideo(s))
985 goto bitblt_ignore;
986 }
987 }
988 return;
989 bitblt_ignore:;
990 cirrus_bitblt_reset(s);
991 }
992
993 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
994 {
995 unsigned old_value;
996
997 old_value = s->gr[0x31];
998 s->gr[0x31] = reg_value;
999
1000 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1001 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1002 cirrus_bitblt_reset(s);
1003 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1004 ((reg_value & CIRRUS_BLT_START) != 0)) {
1005 cirrus_bitblt_start(s);
1006 }
1007 }
1008
1009
1010 /***************************************
1011 *
1012 * basic parameters
1013 *
1014 ***************************************/
1015
1016 static void cirrus_get_offsets(VGAState *s1,
1017 uint32_t *pline_offset,
1018 uint32_t *pstart_addr,
1019 uint32_t *pline_compare)
1020 {
1021 CirrusVGAState * s = (CirrusVGAState *)s1;
1022 uint32_t start_addr, line_offset, line_compare;
1023
1024 line_offset = s->cr[0x13]
1025 | ((s->cr[0x1b] & 0x10) << 4);
1026 line_offset <<= 3;
1027 *pline_offset = line_offset;
1028
1029 start_addr = (s->cr[0x0c] << 8)
1030 | s->cr[0x0d]
1031 | ((s->cr[0x1b] & 0x01) << 16)
1032 | ((s->cr[0x1b] & 0x0c) << 15)
1033 | ((s->cr[0x1d] & 0x80) << 12);
1034 *pstart_addr = start_addr;
1035
1036 line_compare = s->cr[0x18] |
1037 ((s->cr[0x07] & 0x10) << 4) |
1038 ((s->cr[0x09] & 0x40) << 3);
1039 *pline_compare = line_compare;
1040 }
1041
1042 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1043 {
1044 uint32_t ret = 16;
1045
1046 switch (s->cirrus_hidden_dac_data & 0xf) {
1047 case 0:
1048 ret = 15;
1049 break; /* Sierra HiColor */
1050 case 1:
1051 ret = 16;
1052 break; /* XGA HiColor */
1053 default:
1054 #ifdef DEBUG_CIRRUS
1055 printf("cirrus: invalid DAC value %x in 16bpp\n",
1056 (s->cirrus_hidden_dac_data & 0xf));
1057 #endif
1058 ret = 15; /* XXX */
1059 break;
1060 }
1061 return ret;
1062 }
1063
1064 static int cirrus_get_bpp(VGAState *s1)
1065 {
1066 CirrusVGAState * s = (CirrusVGAState *)s1;
1067 uint32_t ret = 8;
1068
1069 if ((s->sr[0x07] & 0x01) != 0) {
1070 /* Cirrus SVGA */
1071 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1072 case CIRRUS_SR7_BPP_8:
1073 ret = 8;
1074 break;
1075 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1076 ret = cirrus_get_bpp16_depth(s);
1077 break;
1078 case CIRRUS_SR7_BPP_24:
1079 ret = 24;
1080 break;
1081 case CIRRUS_SR7_BPP_16:
1082 ret = cirrus_get_bpp16_depth(s);
1083 break;
1084 case CIRRUS_SR7_BPP_32:
1085 ret = 32;
1086 break;
1087 default:
1088 #ifdef DEBUG_CIRRUS
1089 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1090 #endif
1091 ret = 8;
1092 break;
1093 }
1094 } else {
1095 /* VGA */
1096 ret = 0;
1097 }
1098
1099 return ret;
1100 }
1101
1102 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1103 {
1104 int width, height;
1105
1106 width = (s->cr[0x01] + 1) * 8;
1107 height = s->cr[0x12] |
1108 ((s->cr[0x07] & 0x02) << 7) |
1109 ((s->cr[0x07] & 0x40) << 3);
1110 height = (height + 1);
1111 /* interlace support */
1112 if (s->cr[0x1a] & 0x01)
1113 height = height * 2;
1114 *pwidth = width;
1115 *pheight = height;
1116 }
1117
1118 /***************************************
1119 *
1120 * bank memory
1121 *
1122 ***************************************/
1123
1124 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1125 {
1126 unsigned offset;
1127 unsigned limit;
1128
1129 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1130 offset = s->gr[0x09 + bank_index];
1131 else /* single bank */
1132 offset = s->gr[0x09];
1133
1134 if ((s->gr[0x0b] & 0x20) != 0)
1135 offset <<= 14;
1136 else
1137 offset <<= 12;
1138
1139 if (s->real_vram_size <= offset)
1140 limit = 0;
1141 else
1142 limit = s->real_vram_size - offset;
1143
1144 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1145 if (limit > 0x8000) {
1146 offset += 0x8000;
1147 limit -= 0x8000;
1148 } else {
1149 limit = 0;
1150 }
1151 }
1152
1153 if (limit > 0) {
1154 s->cirrus_bank_base[bank_index] = offset;
1155 s->cirrus_bank_limit[bank_index] = limit;
1156 } else {
1157 s->cirrus_bank_base[bank_index] = 0;
1158 s->cirrus_bank_limit[bank_index] = 0;
1159 }
1160 }
1161
1162 /***************************************
1163 *
1164 * I/O access between 0x3c4-0x3c5
1165 *
1166 ***************************************/
1167
1168 static int
1169 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1170 {
1171 switch (reg_index) {
1172 case 0x00: // Standard VGA
1173 case 0x01: // Standard VGA
1174 case 0x02: // Standard VGA
1175 case 0x03: // Standard VGA
1176 case 0x04: // Standard VGA
1177 return CIRRUS_HOOK_NOT_HANDLED;
1178 case 0x06: // Unlock Cirrus extensions
1179 *reg_value = s->sr[reg_index];
1180 break;
1181 case 0x10:
1182 case 0x30:
1183 case 0x50:
1184 case 0x70: // Graphics Cursor X
1185 case 0x90:
1186 case 0xb0:
1187 case 0xd0:
1188 case 0xf0: // Graphics Cursor X
1189 *reg_value = s->sr[0x10];
1190 break;
1191 case 0x11:
1192 case 0x31:
1193 case 0x51:
1194 case 0x71: // Graphics Cursor Y
1195 case 0x91:
1196 case 0xb1:
1197 case 0xd1:
1198 case 0xf1: // Graphics Cursor Y
1199 *reg_value = s->sr[0x11];
1200 break;
1201 case 0x05: // ???
1202 case 0x07: // Extended Sequencer Mode
1203 case 0x08: // EEPROM Control
1204 case 0x09: // Scratch Register 0
1205 case 0x0a: // Scratch Register 1
1206 case 0x0b: // VCLK 0
1207 case 0x0c: // VCLK 1
1208 case 0x0d: // VCLK 2
1209 case 0x0e: // VCLK 3
1210 case 0x0f: // DRAM Control
1211 case 0x12: // Graphics Cursor Attribute
1212 case 0x13: // Graphics Cursor Pattern Address
1213 case 0x14: // Scratch Register 2
1214 case 0x15: // Scratch Register 3
1215 case 0x16: // Performance Tuning Register
1216 case 0x17: // Configuration Readback and Extended Control
1217 case 0x18: // Signature Generator Control
1218 case 0x19: // Signal Generator Result
1219 case 0x1a: // Signal Generator Result
1220 case 0x1b: // VCLK 0 Denominator & Post
1221 case 0x1c: // VCLK 1 Denominator & Post
1222 case 0x1d: // VCLK 2 Denominator & Post
1223 case 0x1e: // VCLK 3 Denominator & Post
1224 case 0x1f: // BIOS Write Enable and MCLK select
1225 #ifdef DEBUG_CIRRUS
1226 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1227 #endif
1228 *reg_value = s->sr[reg_index];
1229 break;
1230 default:
1231 #ifdef DEBUG_CIRRUS
1232 printf("cirrus: inport sr_index %02x\n", reg_index);
1233 #endif
1234 *reg_value = 0xff;
1235 break;
1236 }
1237
1238 return CIRRUS_HOOK_HANDLED;
1239 }
1240
1241 static int
1242 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1243 {
1244 switch (reg_index) {
1245 case 0x00: // Standard VGA
1246 case 0x01: // Standard VGA
1247 case 0x02: // Standard VGA
1248 case 0x03: // Standard VGA
1249 case 0x04: // Standard VGA
1250 return CIRRUS_HOOK_NOT_HANDLED;
1251 case 0x06: // Unlock Cirrus extensions
1252 reg_value &= 0x17;
1253 if (reg_value == 0x12) {
1254 s->sr[reg_index] = 0x12;
1255 } else {
1256 s->sr[reg_index] = 0x0f;
1257 }
1258 break;
1259 case 0x10:
1260 case 0x30:
1261 case 0x50:
1262 case 0x70: // Graphics Cursor X
1263 case 0x90:
1264 case 0xb0:
1265 case 0xd0:
1266 case 0xf0: // Graphics Cursor X
1267 s->sr[0x10] = reg_value;
1268 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1269 break;
1270 case 0x11:
1271 case 0x31:
1272 case 0x51:
1273 case 0x71: // Graphics Cursor Y
1274 case 0x91:
1275 case 0xb1:
1276 case 0xd1:
1277 case 0xf1: // Graphics Cursor Y
1278 s->sr[0x11] = reg_value;
1279 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1280 break;
1281 case 0x07: // Extended Sequencer Mode
1282 case 0x08: // EEPROM Control
1283 case 0x09: // Scratch Register 0
1284 case 0x0a: // Scratch Register 1
1285 case 0x0b: // VCLK 0
1286 case 0x0c: // VCLK 1
1287 case 0x0d: // VCLK 2
1288 case 0x0e: // VCLK 3
1289 case 0x0f: // DRAM Control
1290 case 0x12: // Graphics Cursor Attribute
1291 case 0x13: // Graphics Cursor Pattern Address
1292 case 0x14: // Scratch Register 2
1293 case 0x15: // Scratch Register 3
1294 case 0x16: // Performance Tuning Register
1295 case 0x18: // Signature Generator Control
1296 case 0x19: // Signature Generator Result
1297 case 0x1a: // Signature Generator Result
1298 case 0x1b: // VCLK 0 Denominator & Post
1299 case 0x1c: // VCLK 1 Denominator & Post
1300 case 0x1d: // VCLK 2 Denominator & Post
1301 case 0x1e: // VCLK 3 Denominator & Post
1302 case 0x1f: // BIOS Write Enable and MCLK select
1303 s->sr[reg_index] = reg_value;
1304 #ifdef DEBUG_CIRRUS
1305 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1306 reg_index, reg_value);
1307 #endif
1308 if (reg_index == 0x07)
1309 cirrus_update_memory_access(s);
1310 break;
1311 case 0x17: // Configuration Readback and Extended Control
1312 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1313 cirrus_update_memory_access(s);
1314 break;
1315 default:
1316 #ifdef DEBUG_CIRRUS
1317 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1318 reg_value);
1319 #endif
1320 break;
1321 }
1322
1323 return CIRRUS_HOOK_HANDLED;
1324 }
1325
1326 /***************************************
1327 *
1328 * I/O access at 0x3c6
1329 *
1330 ***************************************/
1331
1332 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1333 {
1334 *reg_value = 0xff;
1335 if (++s->cirrus_hidden_dac_lockindex == 5) {
1336 *reg_value = s->cirrus_hidden_dac_data;
1337 s->cirrus_hidden_dac_lockindex = 0;
1338 }
1339 }
1340
1341 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1342 {
1343 if (s->cirrus_hidden_dac_lockindex == 4) {
1344 s->cirrus_hidden_dac_data = reg_value;
1345 #if defined(DEBUG_CIRRUS)
1346 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1347 #endif
1348 }
1349 s->cirrus_hidden_dac_lockindex = 0;
1350 }
1351
1352 /***************************************
1353 *
1354 * I/O access at 0x3c9
1355 *
1356 ***************************************/
1357
1358 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1359 {
1360 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1361 return CIRRUS_HOOK_NOT_HANDLED;
1362 *reg_value =
1363 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1364 s->dac_sub_index];
1365 if (++s->dac_sub_index == 3) {
1366 s->dac_sub_index = 0;
1367 s->dac_read_index++;
1368 }
1369 return CIRRUS_HOOK_HANDLED;
1370 }
1371
1372 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1373 {
1374 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1375 return CIRRUS_HOOK_NOT_HANDLED;
1376 s->dac_cache[s->dac_sub_index] = reg_value;
1377 if (++s->dac_sub_index == 3) {
1378 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1379 s->dac_cache, 3);
1380 /* XXX update cursor */
1381 s->dac_sub_index = 0;
1382 s->dac_write_index++;
1383 }
1384 return CIRRUS_HOOK_HANDLED;
1385 }
1386
1387 /***************************************
1388 *
1389 * I/O access between 0x3ce-0x3cf
1390 *
1391 ***************************************/
1392
1393 static int
1394 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1395 {
1396 switch (reg_index) {
1397 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1398 *reg_value = s->cirrus_shadow_gr0;
1399 return CIRRUS_HOOK_HANDLED;
1400 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1401 *reg_value = s->cirrus_shadow_gr1;
1402 return CIRRUS_HOOK_HANDLED;
1403 case 0x02: // Standard VGA
1404 case 0x03: // Standard VGA
1405 case 0x04: // Standard VGA
1406 case 0x06: // Standard VGA
1407 case 0x07: // Standard VGA
1408 case 0x08: // Standard VGA
1409 return CIRRUS_HOOK_NOT_HANDLED;
1410 case 0x05: // Standard VGA, Cirrus extended mode
1411 default:
1412 break;
1413 }
1414
1415 if (reg_index < 0x3a) {
1416 *reg_value = s->gr[reg_index];
1417 } else {
1418 #ifdef DEBUG_CIRRUS
1419 printf("cirrus: inport gr_index %02x\n", reg_index);
1420 #endif
1421 *reg_value = 0xff;
1422 }
1423
1424 return CIRRUS_HOOK_HANDLED;
1425 }
1426
1427 static int
1428 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1429 {
1430 #if defined(DEBUG_BITBLT) && 0
1431 printf("gr%02x: %02x\n", reg_index, reg_value);
1432 #endif
1433 switch (reg_index) {
1434 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1435 s->cirrus_shadow_gr0 = reg_value;
1436 return CIRRUS_HOOK_NOT_HANDLED;
1437 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1438 s->cirrus_shadow_gr1 = reg_value;
1439 return CIRRUS_HOOK_NOT_HANDLED;
1440 case 0x02: // Standard VGA
1441 case 0x03: // Standard VGA
1442 case 0x04: // Standard VGA
1443 case 0x06: // Standard VGA
1444 case 0x07: // Standard VGA
1445 case 0x08: // Standard VGA
1446 return CIRRUS_HOOK_NOT_HANDLED;
1447 case 0x05: // Standard VGA, Cirrus extended mode
1448 s->gr[reg_index] = reg_value & 0x7f;
1449 cirrus_update_memory_access(s);
1450 break;
1451 case 0x09: // bank offset #0
1452 case 0x0A: // bank offset #1
1453 s->gr[reg_index] = reg_value;
1454 cirrus_update_bank_ptr(s, 0);
1455 cirrus_update_bank_ptr(s, 1);
1456 cirrus_update_memory_access(s);
1457 break;
1458 case 0x0B:
1459 s->gr[reg_index] = reg_value;
1460 cirrus_update_bank_ptr(s, 0);
1461 cirrus_update_bank_ptr(s, 1);
1462 cirrus_update_memory_access(s);
1463 break;
1464 case 0x10: // BGCOLOR 0x0000ff00
1465 case 0x11: // FGCOLOR 0x0000ff00
1466 case 0x12: // BGCOLOR 0x00ff0000
1467 case 0x13: // FGCOLOR 0x00ff0000
1468 case 0x14: // BGCOLOR 0xff000000
1469 case 0x15: // FGCOLOR 0xff000000
1470 case 0x20: // BLT WIDTH 0x0000ff
1471 case 0x22: // BLT HEIGHT 0x0000ff
1472 case 0x24: // BLT DEST PITCH 0x0000ff
1473 case 0x26: // BLT SRC PITCH 0x0000ff
1474 case 0x28: // BLT DEST ADDR 0x0000ff
1475 case 0x29: // BLT DEST ADDR 0x00ff00
1476 case 0x2c: // BLT SRC ADDR 0x0000ff
1477 case 0x2d: // BLT SRC ADDR 0x00ff00
1478 case 0x2f: // BLT WRITEMASK
1479 case 0x30: // BLT MODE
1480 case 0x32: // RASTER OP
1481 case 0x33: // BLT MODEEXT
1482 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1483 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1484 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1485 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1486 s->gr[reg_index] = reg_value;
1487 break;
1488 case 0x21: // BLT WIDTH 0x001f00
1489 case 0x23: // BLT HEIGHT 0x001f00
1490 case 0x25: // BLT DEST PITCH 0x001f00
1491 case 0x27: // BLT SRC PITCH 0x001f00
1492 s->gr[reg_index] = reg_value & 0x1f;
1493 break;
1494 case 0x2a: // BLT DEST ADDR 0x3f0000
1495 s->gr[reg_index] = reg_value & 0x3f;
1496 /* if auto start mode, starts bit blt now */
1497 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1498 cirrus_bitblt_start(s);
1499 }
1500 break;
1501 case 0x2e: // BLT SRC ADDR 0x3f0000
1502 s->gr[reg_index] = reg_value & 0x3f;
1503 break;
1504 case 0x31: // BLT STATUS/START
1505 cirrus_write_bitblt(s, reg_value);
1506 break;
1507 default:
1508 #ifdef DEBUG_CIRRUS
1509 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1510 reg_value);
1511 #endif
1512 break;
1513 }
1514
1515 return CIRRUS_HOOK_HANDLED;
1516 }
1517
1518 /***************************************
1519 *
1520 * I/O access between 0x3d4-0x3d5
1521 *
1522 ***************************************/
1523
1524 static int
1525 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1526 {
1527 switch (reg_index) {
1528 case 0x00: // Standard VGA
1529 case 0x01: // Standard VGA
1530 case 0x02: // Standard VGA
1531 case 0x03: // Standard VGA
1532 case 0x04: // Standard VGA
1533 case 0x05: // Standard VGA
1534 case 0x06: // Standard VGA
1535 case 0x07: // Standard VGA
1536 case 0x08: // Standard VGA
1537 case 0x09: // Standard VGA
1538 case 0x0a: // Standard VGA
1539 case 0x0b: // Standard VGA
1540 case 0x0c: // Standard VGA
1541 case 0x0d: // Standard VGA
1542 case 0x0e: // Standard VGA
1543 case 0x0f: // Standard VGA
1544 case 0x10: // Standard VGA
1545 case 0x11: // Standard VGA
1546 case 0x12: // Standard VGA
1547 case 0x13: // Standard VGA
1548 case 0x14: // Standard VGA
1549 case 0x15: // Standard VGA
1550 case 0x16: // Standard VGA
1551 case 0x17: // Standard VGA
1552 case 0x18: // Standard VGA
1553 return CIRRUS_HOOK_NOT_HANDLED;
1554 case 0x19: // Interlace End
1555 case 0x1a: // Miscellaneous Control
1556 case 0x1b: // Extended Display Control
1557 case 0x1c: // Sync Adjust and Genlock
1558 case 0x1d: // Overlay Extended Control
1559 case 0x22: // Graphics Data Latches Readback (R)
1560 case 0x24: // Attribute Controller Toggle Readback (R)
1561 case 0x25: // Part Status
1562 case 0x27: // Part ID (R)
1563 *reg_value = s->cr[reg_index];
1564 break;
1565 case 0x26: // Attribute Controller Index Readback (R)
1566 *reg_value = s->ar_index & 0x3f;
1567 break;
1568 default:
1569 #ifdef DEBUG_CIRRUS
1570 printf("cirrus: inport cr_index %02x\n", reg_index);
1571 *reg_value = 0xff;
1572 #endif
1573 break;
1574 }
1575
1576 return CIRRUS_HOOK_HANDLED;
1577 }
1578
1579 static int
1580 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1581 {
1582 switch (reg_index) {
1583 case 0x00: // Standard VGA
1584 case 0x01: // Standard VGA
1585 case 0x02: // Standard VGA
1586 case 0x03: // Standard VGA
1587 case 0x04: // Standard VGA
1588 case 0x05: // Standard VGA
1589 case 0x06: // Standard VGA
1590 case 0x07: // Standard VGA
1591 case 0x08: // Standard VGA
1592 case 0x09: // Standard VGA
1593 case 0x0a: // Standard VGA
1594 case 0x0b: // Standard VGA
1595 case 0x0c: // Standard VGA
1596 case 0x0d: // Standard VGA
1597 case 0x0e: // Standard VGA
1598 case 0x0f: // Standard VGA
1599 case 0x10: // Standard VGA
1600 case 0x11: // Standard VGA
1601 case 0x12: // Standard VGA
1602 case 0x13: // Standard VGA
1603 case 0x14: // Standard VGA
1604 case 0x15: // Standard VGA
1605 case 0x16: // Standard VGA
1606 case 0x17: // Standard VGA
1607 case 0x18: // Standard VGA
1608 return CIRRUS_HOOK_NOT_HANDLED;
1609 case 0x19: // Interlace End
1610 case 0x1a: // Miscellaneous Control
1611 case 0x1b: // Extended Display Control
1612 case 0x1c: // Sync Adjust and Genlock
1613 case 0x1d: // Overlay Extended Control
1614 s->cr[reg_index] = reg_value;
1615 #ifdef DEBUG_CIRRUS
1616 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1617 reg_index, reg_value);
1618 #endif
1619 break;
1620 case 0x22: // Graphics Data Latches Readback (R)
1621 case 0x24: // Attribute Controller Toggle Readback (R)
1622 case 0x26: // Attribute Controller Index Readback (R)
1623 case 0x27: // Part ID (R)
1624 break;
1625 case 0x25: // Part Status
1626 default:
1627 #ifdef DEBUG_CIRRUS
1628 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1629 reg_value);
1630 #endif
1631 break;
1632 }
1633
1634 return CIRRUS_HOOK_HANDLED;
1635 }
1636
1637 /***************************************
1638 *
1639 * memory-mapped I/O (bitblt)
1640 *
1641 ***************************************/
1642
1643 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1644 {
1645 int value = 0xff;
1646
1647 switch (address) {
1648 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1649 cirrus_hook_read_gr(s, 0x00, &value);
1650 break;
1651 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1652 cirrus_hook_read_gr(s, 0x10, &value);
1653 break;
1654 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1655 cirrus_hook_read_gr(s, 0x12, &value);
1656 break;
1657 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1658 cirrus_hook_read_gr(s, 0x14, &value);
1659 break;
1660 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1661 cirrus_hook_read_gr(s, 0x01, &value);
1662 break;
1663 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1664 cirrus_hook_read_gr(s, 0x11, &value);
1665 break;
1666 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1667 cirrus_hook_read_gr(s, 0x13, &value);
1668 break;
1669 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1670 cirrus_hook_read_gr(s, 0x15, &value);
1671 break;
1672 case (CIRRUS_MMIO_BLTWIDTH + 0):
1673 cirrus_hook_read_gr(s, 0x20, &value);
1674 break;
1675 case (CIRRUS_MMIO_BLTWIDTH + 1):
1676 cirrus_hook_read_gr(s, 0x21, &value);
1677 break;
1678 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1679 cirrus_hook_read_gr(s, 0x22, &value);
1680 break;
1681 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1682 cirrus_hook_read_gr(s, 0x23, &value);
1683 break;
1684 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1685 cirrus_hook_read_gr(s, 0x24, &value);
1686 break;
1687 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1688 cirrus_hook_read_gr(s, 0x25, &value);
1689 break;
1690 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1691 cirrus_hook_read_gr(s, 0x26, &value);
1692 break;
1693 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1694 cirrus_hook_read_gr(s, 0x27, &value);
1695 break;
1696 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1697 cirrus_hook_read_gr(s, 0x28, &value);
1698 break;
1699 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1700 cirrus_hook_read_gr(s, 0x29, &value);
1701 break;
1702 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1703 cirrus_hook_read_gr(s, 0x2a, &value);
1704 break;
1705 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1706 cirrus_hook_read_gr(s, 0x2c, &value);
1707 break;
1708 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1709 cirrus_hook_read_gr(s, 0x2d, &value);
1710 break;
1711 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1712 cirrus_hook_read_gr(s, 0x2e, &value);
1713 break;
1714 case CIRRUS_MMIO_BLTWRITEMASK:
1715 cirrus_hook_read_gr(s, 0x2f, &value);
1716 break;
1717 case CIRRUS_MMIO_BLTMODE:
1718 cirrus_hook_read_gr(s, 0x30, &value);
1719 break;
1720 case CIRRUS_MMIO_BLTROP:
1721 cirrus_hook_read_gr(s, 0x32, &value);
1722 break;
1723 case CIRRUS_MMIO_BLTMODEEXT:
1724 cirrus_hook_read_gr(s, 0x33, &value);
1725 break;
1726 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1727 cirrus_hook_read_gr(s, 0x34, &value);
1728 break;
1729 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1730 cirrus_hook_read_gr(s, 0x35, &value);
1731 break;
1732 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1733 cirrus_hook_read_gr(s, 0x38, &value);
1734 break;
1735 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1736 cirrus_hook_read_gr(s, 0x39, &value);
1737 break;
1738 case CIRRUS_MMIO_BLTSTATUS:
1739 cirrus_hook_read_gr(s, 0x31, &value);
1740 break;
1741 default:
1742 #ifdef DEBUG_CIRRUS
1743 printf("cirrus: mmio read - address 0x%04x\n", address);
1744 #endif
1745 break;
1746 }
1747
1748 return (uint8_t) value;
1749 }
1750
1751 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1752 uint8_t value)
1753 {
1754 switch (address) {
1755 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1756 cirrus_hook_write_gr(s, 0x00, value);
1757 break;
1758 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1759 cirrus_hook_write_gr(s, 0x10, value);
1760 break;
1761 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1762 cirrus_hook_write_gr(s, 0x12, value);
1763 break;
1764 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1765 cirrus_hook_write_gr(s, 0x14, value);
1766 break;
1767 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1768 cirrus_hook_write_gr(s, 0x01, value);
1769 break;
1770 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1771 cirrus_hook_write_gr(s, 0x11, value);
1772 break;
1773 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1774 cirrus_hook_write_gr(s, 0x13, value);
1775 break;
1776 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1777 cirrus_hook_write_gr(s, 0x15, value);
1778 break;
1779 case (CIRRUS_MMIO_BLTWIDTH + 0):
1780 cirrus_hook_write_gr(s, 0x20, value);
1781 break;
1782 case (CIRRUS_MMIO_BLTWIDTH + 1):
1783 cirrus_hook_write_gr(s, 0x21, value);
1784 break;
1785 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1786 cirrus_hook_write_gr(s, 0x22, value);
1787 break;
1788 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1789 cirrus_hook_write_gr(s, 0x23, value);
1790 break;
1791 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1792 cirrus_hook_write_gr(s, 0x24, value);
1793 break;
1794 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1795 cirrus_hook_write_gr(s, 0x25, value);
1796 break;
1797 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1798 cirrus_hook_write_gr(s, 0x26, value);
1799 break;
1800 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1801 cirrus_hook_write_gr(s, 0x27, value);
1802 break;
1803 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1804 cirrus_hook_write_gr(s, 0x28, value);
1805 break;
1806 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1807 cirrus_hook_write_gr(s, 0x29, value);
1808 break;
1809 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1810 cirrus_hook_write_gr(s, 0x2a, value);
1811 break;
1812 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1813 /* ignored */
1814 break;
1815 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1816 cirrus_hook_write_gr(s, 0x2c, value);
1817 break;
1818 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1819 cirrus_hook_write_gr(s, 0x2d, value);
1820 break;
1821 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1822 cirrus_hook_write_gr(s, 0x2e, value);
1823 break;
1824 case CIRRUS_MMIO_BLTWRITEMASK:
1825 cirrus_hook_write_gr(s, 0x2f, value);
1826 break;
1827 case CIRRUS_MMIO_BLTMODE:
1828 cirrus_hook_write_gr(s, 0x30, value);
1829 break;
1830 case CIRRUS_MMIO_BLTROP:
1831 cirrus_hook_write_gr(s, 0x32, value);
1832 break;
1833 case CIRRUS_MMIO_BLTMODEEXT:
1834 cirrus_hook_write_gr(s, 0x33, value);
1835 break;
1836 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1837 cirrus_hook_write_gr(s, 0x34, value);
1838 break;
1839 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1840 cirrus_hook_write_gr(s, 0x35, value);
1841 break;
1842 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1843 cirrus_hook_write_gr(s, 0x38, value);
1844 break;
1845 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1846 cirrus_hook_write_gr(s, 0x39, value);
1847 break;
1848 case CIRRUS_MMIO_BLTSTATUS:
1849 cirrus_hook_write_gr(s, 0x31, value);
1850 break;
1851 default:
1852 #ifdef DEBUG_CIRRUS
1853 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1854 address, value);
1855 #endif
1856 break;
1857 }
1858 }
1859
1860 /***************************************
1861 *
1862 * write mode 4/5
1863 *
1864 * assume TARGET_PAGE_SIZE >= 16
1865 *
1866 ***************************************/
1867
1868 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1869 unsigned mode,
1870 unsigned offset,
1871 uint32_t mem_value)
1872 {
1873 int x;
1874 unsigned val = mem_value;
1875 uint8_t *dst;
1876
1877 dst = s->vram_ptr + offset;
1878 for (x = 0; x < 8; x++) {
1879 if (val & 0x80) {
1880 *dst = s->cirrus_shadow_gr1;
1881 } else if (mode == 5) {
1882 *dst = s->cirrus_shadow_gr0;
1883 }
1884 val <<= 1;
1885 dst++;
1886 }
1887 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1888 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1889 }
1890
1891 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1892 unsigned mode,
1893 unsigned offset,
1894 uint32_t mem_value)
1895 {
1896 int x;
1897 unsigned val = mem_value;
1898 uint8_t *dst;
1899
1900 dst = s->vram_ptr + offset;
1901 for (x = 0; x < 8; x++) {
1902 if (val & 0x80) {
1903 *dst = s->cirrus_shadow_gr1;
1904 *(dst + 1) = s->gr[0x11];
1905 } else if (mode == 5) {
1906 *dst = s->cirrus_shadow_gr0;
1907 *(dst + 1) = s->gr[0x10];
1908 }
1909 val <<= 1;
1910 dst += 2;
1911 }
1912 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1913 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1914 }
1915
1916 /***************************************
1917 *
1918 * memory access between 0xa0000-0xbffff
1919 *
1920 ***************************************/
1921
1922 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1923 {
1924 CirrusVGAState *s = opaque;
1925 unsigned bank_index;
1926 unsigned bank_offset;
1927 uint32_t val;
1928
1929 if ((s->sr[0x07] & 0x01) == 0) {
1930 return vga_mem_readb(s, addr);
1931 }
1932
1933 addr &= 0x1ffff;
1934
1935 if (addr < 0x10000) {
1936 /* XXX handle bitblt */
1937 /* video memory */
1938 bank_index = addr >> 15;
1939 bank_offset = addr & 0x7fff;
1940 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1941 bank_offset += s->cirrus_bank_base[bank_index];
1942 if ((s->gr[0x0B] & 0x14) == 0x14) {
1943 bank_offset <<= 4;
1944 } else if (s->gr[0x0B] & 0x02) {
1945 bank_offset <<= 3;
1946 }
1947 bank_offset &= s->cirrus_addr_mask;
1948 val = *(s->vram_ptr + bank_offset);
1949 } else
1950 val = 0xff;
1951 } else if (addr >= 0x18000 && addr < 0x18100) {
1952 /* memory-mapped I/O */
1953 val = 0xff;
1954 if ((s->sr[0x17] & 0x44) == 0x04) {
1955 val = cirrus_mmio_blt_read(s, addr & 0xff);
1956 }
1957 } else {
1958 val = 0xff;
1959 #ifdef DEBUG_CIRRUS
1960 printf("cirrus: mem_readb %06x\n", addr);
1961 #endif
1962 }
1963 return val;
1964 }
1965
1966 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
1967 {
1968 uint32_t v;
1969 #ifdef TARGET_WORDS_BIGENDIAN
1970 v = cirrus_vga_mem_readb(opaque, addr) << 8;
1971 v |= cirrus_vga_mem_readb(opaque, addr + 1);
1972 #else
1973 v = cirrus_vga_mem_readb(opaque, addr);
1974 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
1975 #endif
1976 return v;
1977 }
1978
1979 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
1980 {
1981 uint32_t v;
1982 #ifdef TARGET_WORDS_BIGENDIAN
1983 v = cirrus_vga_mem_readb(opaque, addr) << 24;
1984 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
1985 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
1986 v |= cirrus_vga_mem_readb(opaque, addr + 3);
1987 #else
1988 v = cirrus_vga_mem_readb(opaque, addr);
1989 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
1990 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
1991 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
1992 #endif
1993 return v;
1994 }
1995
1996 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
1997 uint32_t mem_value)
1998 {
1999 CirrusVGAState *s = opaque;
2000 unsigned bank_index;
2001 unsigned bank_offset;
2002 unsigned mode;
2003
2004 if ((s->sr[0x07] & 0x01) == 0) {
2005 vga_mem_writeb(s, addr, mem_value);
2006 return;
2007 }
2008
2009 addr &= 0x1ffff;
2010
2011 if (addr < 0x10000) {
2012 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2013 /* bitblt */
2014 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2015 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2016 cirrus_bitblt_cputovideo_next(s);
2017 }
2018 } else {
2019 /* video memory */
2020 bank_index = addr >> 15;
2021 bank_offset = addr & 0x7fff;
2022 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2023 bank_offset += s->cirrus_bank_base[bank_index];
2024 if ((s->gr[0x0B] & 0x14) == 0x14) {
2025 bank_offset <<= 4;
2026 } else if (s->gr[0x0B] & 0x02) {
2027 bank_offset <<= 3;
2028 }
2029 bank_offset &= s->cirrus_addr_mask;
2030 mode = s->gr[0x05] & 0x7;
2031 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2032 *(s->vram_ptr + bank_offset) = mem_value;
2033 cpu_physical_memory_set_dirty(s->vram_offset +
2034 bank_offset);
2035 } else {
2036 if ((s->gr[0x0B] & 0x14) != 0x14) {
2037 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2038 bank_offset,
2039 mem_value);
2040 } else {
2041 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2042 bank_offset,
2043 mem_value);
2044 }
2045 }
2046 }
2047 }
2048 } else if (addr >= 0x18000 && addr < 0x18100) {
2049 /* memory-mapped I/O */
2050 if ((s->sr[0x17] & 0x44) == 0x04) {
2051 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2052 }
2053 } else {
2054 #ifdef DEBUG_CIRRUS
2055 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2056 #endif
2057 }
2058 }
2059
2060 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2061 {
2062 #ifdef TARGET_WORDS_BIGENDIAN
2063 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2064 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2065 #else
2066 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2067 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2068 #endif
2069 }
2070
2071 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2072 {
2073 #ifdef TARGET_WORDS_BIGENDIAN
2074 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2075 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2076 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2077 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2078 #else
2079 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2080 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2081 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2082 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2083 #endif
2084 }
2085
2086 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2087 cirrus_vga_mem_readb,
2088 cirrus_vga_mem_readw,
2089 cirrus_vga_mem_readl,
2090 };
2091
2092 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2093 cirrus_vga_mem_writeb,
2094 cirrus_vga_mem_writew,
2095 cirrus_vga_mem_writel,
2096 };
2097
2098 /***************************************
2099 *
2100 * hardware cursor
2101 *
2102 ***************************************/
2103
2104 static inline void invalidate_cursor1(CirrusVGAState *s)
2105 {
2106 if (s->last_hw_cursor_size) {
2107 vga_invalidate_scanlines((VGAState *)s,
2108 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2109 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2110 }
2111 }
2112
2113 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2114 {
2115 const uint8_t *src;
2116 uint32_t content;
2117 int y, y_min, y_max;
2118
2119 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2120 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2121 src += (s->sr[0x13] & 0x3c) * 256;
2122 y_min = 64;
2123 y_max = -1;
2124 for(y = 0; y < 64; y++) {
2125 content = ((uint32_t *)src)[0] |
2126 ((uint32_t *)src)[1] |
2127 ((uint32_t *)src)[2] |
2128 ((uint32_t *)src)[3];
2129 if (content) {
2130 if (y < y_min)
2131 y_min = y;
2132 if (y > y_max)
2133 y_max = y;
2134 }
2135 src += 16;
2136 }
2137 } else {
2138 src += (s->sr[0x13] & 0x3f) * 256;
2139 y_min = 32;
2140 y_max = -1;
2141 for(y = 0; y < 32; y++) {
2142 content = ((uint32_t *)src)[0] |
2143 ((uint32_t *)(src + 128))[0];
2144 if (content) {
2145 if (y < y_min)
2146 y_min = y;
2147 if (y > y_max)
2148 y_max = y;
2149 }
2150 src += 4;
2151 }
2152 }
2153 if (y_min > y_max) {
2154 s->last_hw_cursor_y_start = 0;
2155 s->last_hw_cursor_y_end = 0;
2156 } else {
2157 s->last_hw_cursor_y_start = y_min;
2158 s->last_hw_cursor_y_end = y_max + 1;
2159 }
2160 }
2161
2162 /* NOTE: we do not currently handle the cursor bitmap change, so we
2163 update the cursor only if it moves. */
2164 static void cirrus_cursor_invalidate(VGAState *s1)
2165 {
2166 CirrusVGAState *s = (CirrusVGAState *)s1;
2167 int size;
2168
2169 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2170 size = 0;
2171 } else {
2172 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2173 size = 64;
2174 else
2175 size = 32;
2176 }
2177 /* invalidate last cursor and new cursor if any change */
2178 if (s->last_hw_cursor_size != size ||
2179 s->last_hw_cursor_x != s->hw_cursor_x ||
2180 s->last_hw_cursor_y != s->hw_cursor_y) {
2181
2182 invalidate_cursor1(s);
2183
2184 s->last_hw_cursor_size = size;
2185 s->last_hw_cursor_x = s->hw_cursor_x;
2186 s->last_hw_cursor_y = s->hw_cursor_y;
2187 /* compute the real cursor min and max y */
2188 cirrus_cursor_compute_yrange(s);
2189 invalidate_cursor1(s);
2190 }
2191 }
2192
2193 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2194 {
2195 CirrusVGAState *s = (CirrusVGAState *)s1;
2196 int w, h, bpp, x1, x2, poffset;
2197 unsigned int color0, color1;
2198 const uint8_t *palette, *src;
2199 uint32_t content;
2200
2201 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2202 return;
2203 /* fast test to see if the cursor intersects with the scan line */
2204 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2205 h = 64;
2206 } else {
2207 h = 32;
2208 }
2209 if (scr_y < s->hw_cursor_y ||
2210 scr_y >= (s->hw_cursor_y + h))
2211 return;
2212
2213 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2214 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2215 src += (s->sr[0x13] & 0x3c) * 256;
2216 src += (scr_y - s->hw_cursor_y) * 16;
2217 poffset = 8;
2218 content = ((uint32_t *)src)[0] |
2219 ((uint32_t *)src)[1] |
2220 ((uint32_t *)src)[2] |
2221 ((uint32_t *)src)[3];
2222 } else {
2223 src += (s->sr[0x13] & 0x3f) * 256;
2224 src += (scr_y - s->hw_cursor_y) * 4;
2225 poffset = 128;
2226 content = ((uint32_t *)src)[0] |
2227 ((uint32_t *)(src + 128))[0];
2228 }
2229 /* if nothing to draw, no need to continue */
2230 if (!content)
2231 return;
2232 w = h;
2233
2234 x1 = s->hw_cursor_x;
2235 if (x1 >= s->last_scr_width)
2236 return;
2237 x2 = s->hw_cursor_x + w;
2238 if (x2 > s->last_scr_width)
2239 x2 = s->last_scr_width;
2240 w = x2 - x1;
2241 palette = s->cirrus_hidden_palette;
2242 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2243 c6_to_8(palette[0x0 * 3 + 1]),
2244 c6_to_8(palette[0x0 * 3 + 2]));
2245 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2246 c6_to_8(palette[0xf * 3 + 1]),
2247 c6_to_8(palette[0xf * 3 + 2]));
2248 bpp = ((s->ds->depth + 7) >> 3);
2249 d1 += x1 * bpp;
2250 switch(s->ds->depth) {
2251 default:
2252 break;
2253 case 8:
2254 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2255 break;
2256 case 15:
2257 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2258 break;
2259 case 16:
2260 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2261 break;
2262 case 32:
2263 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2264 break;
2265 }
2266 }
2267
2268 /***************************************
2269 *
2270 * LFB memory access
2271 *
2272 ***************************************/
2273
2274 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2275 {
2276 CirrusVGAState *s = (CirrusVGAState *) opaque;
2277 uint32_t ret;
2278
2279 addr &= s->cirrus_addr_mask;
2280
2281 if (((s->sr[0x17] & 0x44) == 0x44) &&
2282 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2283 /* memory-mapped I/O */
2284 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2285 } else if (0) {
2286 /* XXX handle bitblt */
2287 ret = 0xff;
2288 } else {
2289 /* video memory */
2290 if ((s->gr[0x0B] & 0x14) == 0x14) {
2291 addr <<= 4;
2292 } else if (s->gr[0x0B] & 0x02) {
2293 addr <<= 3;
2294 }
2295 addr &= s->cirrus_addr_mask;
2296 ret = *(s->vram_ptr + addr);
2297 }
2298
2299 return ret;
2300 }
2301
2302 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2303 {
2304 uint32_t v;
2305 #ifdef TARGET_WORDS_BIGENDIAN
2306 v = cirrus_linear_readb(opaque, addr) << 8;
2307 v |= cirrus_linear_readb(opaque, addr + 1);
2308 #else
2309 v = cirrus_linear_readb(opaque, addr);
2310 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2311 #endif
2312 return v;
2313 }
2314
2315 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2316 {
2317 uint32_t v;
2318 #ifdef TARGET_WORDS_BIGENDIAN
2319 v = cirrus_linear_readb(opaque, addr) << 24;
2320 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2321 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2322 v |= cirrus_linear_readb(opaque, addr + 3);
2323 #else
2324 v = cirrus_linear_readb(opaque, addr);
2325 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2326 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2327 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2328 #endif
2329 return v;
2330 }
2331
2332 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2333 uint32_t val)
2334 {
2335 CirrusVGAState *s = (CirrusVGAState *) opaque;
2336 unsigned mode;
2337
2338 addr &= s->cirrus_addr_mask;
2339
2340 if (((s->sr[0x17] & 0x44) == 0x44) &&
2341 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2342 /* memory-mapped I/O */
2343 cirrus_mmio_blt_write(s, addr & 0xff, val);
2344 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2345 /* bitblt */
2346 *s->cirrus_srcptr++ = (uint8_t) val;
2347 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2348 cirrus_bitblt_cputovideo_next(s);
2349 }
2350 } else {
2351 /* video memory */
2352 if ((s->gr[0x0B] & 0x14) == 0x14) {
2353 addr <<= 4;
2354 } else if (s->gr[0x0B] & 0x02) {
2355 addr <<= 3;
2356 }
2357 addr &= s->cirrus_addr_mask;
2358
2359 mode = s->gr[0x05] & 0x7;
2360 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2361 *(s->vram_ptr + addr) = (uint8_t) val;
2362 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2363 } else {
2364 if ((s->gr[0x0B] & 0x14) != 0x14) {
2365 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2366 } else {
2367 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2368 }
2369 }
2370 }
2371 }
2372
2373 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2374 uint32_t val)
2375 {
2376 #ifdef TARGET_WORDS_BIGENDIAN
2377 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2378 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2379 #else
2380 cirrus_linear_writeb(opaque, addr, val & 0xff);
2381 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2382 #endif
2383 }
2384
2385 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2386 uint32_t val)
2387 {
2388 #ifdef TARGET_WORDS_BIGENDIAN
2389 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2390 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2391 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2392 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2393 #else
2394 cirrus_linear_writeb(opaque, addr, val & 0xff);
2395 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2396 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2397 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2398 #endif
2399 }
2400
2401
2402 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2403 cirrus_linear_readb,
2404 cirrus_linear_readw,
2405 cirrus_linear_readl,
2406 };
2407
2408 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2409 cirrus_linear_writeb,
2410 cirrus_linear_writew,
2411 cirrus_linear_writel,
2412 };
2413
2414 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2415 uint32_t val)
2416 {
2417 CirrusVGAState *s = (CirrusVGAState *) opaque;
2418
2419 addr &= s->cirrus_addr_mask;
2420 *(s->vram_ptr + addr) = val;
2421 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2422 }
2423
2424 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2425 uint32_t val)
2426 {
2427 CirrusVGAState *s = (CirrusVGAState *) opaque;
2428
2429 addr &= s->cirrus_addr_mask;
2430 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2431 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2432 }
2433
2434 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2435 uint32_t val)
2436 {
2437 CirrusVGAState *s = (CirrusVGAState *) opaque;
2438
2439 addr &= s->cirrus_addr_mask;
2440 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2441 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2442 }
2443
2444 /***************************************
2445 *
2446 * system to screen memory access
2447 *
2448 ***************************************/
2449
2450
2451 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2452 {
2453 uint32_t ret;
2454
2455 /* XXX handle bitblt */
2456 ret = 0xff;
2457 return ret;
2458 }
2459
2460 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2461 {
2462 uint32_t v;
2463 #ifdef TARGET_WORDS_BIGENDIAN
2464 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2465 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2466 #else
2467 v = cirrus_linear_bitblt_readb(opaque, addr);
2468 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2469 #endif
2470 return v;
2471 }
2472
2473 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2474 {
2475 uint32_t v;
2476 #ifdef TARGET_WORDS_BIGENDIAN
2477 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2478 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2479 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2480 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2481 #else
2482 v = cirrus_linear_bitblt_readb(opaque, addr);
2483 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2484 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2485 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2486 #endif
2487 return v;
2488 }
2489
2490 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2491 uint32_t val)
2492 {
2493 CirrusVGAState *s = (CirrusVGAState *) opaque;
2494
2495 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2496 /* bitblt */
2497 *s->cirrus_srcptr++ = (uint8_t) val;
2498 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2499 cirrus_bitblt_cputovideo_next(s);
2500 }
2501 }
2502 }
2503
2504 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2505 uint32_t val)
2506 {
2507 #ifdef TARGET_WORDS_BIGENDIAN
2508 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2509 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2510 #else
2511 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2512 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2513 #endif
2514 }
2515
2516 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2517 uint32_t val)
2518 {
2519 #ifdef TARGET_WORDS_BIGENDIAN
2520 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2521 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2522 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2523 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2524 #else
2525 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2526 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2527 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2528 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2529 #endif
2530 }
2531
2532
2533 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2534 cirrus_linear_bitblt_readb,
2535 cirrus_linear_bitblt_readw,
2536 cirrus_linear_bitblt_readl,
2537 };
2538
2539 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2540 cirrus_linear_bitblt_writeb,
2541 cirrus_linear_bitblt_writew,
2542 cirrus_linear_bitblt_writel,
2543 };
2544
2545 #ifdef USE_KVM
2546
2547 #include "qemu-kvm.h"
2548
2549 extern kvm_context_t kvm_context;
2550
2551 void *set_vram_mapping(unsigned long begin, unsigned long end)
2552 {
2553 void *vram_pointer = NULL;
2554
2555 /* align begin and end address */
2556 begin = begin & TARGET_PAGE_MASK;
2557 end = begin + VGA_RAM_SIZE;
2558 end = (end + TARGET_PAGE_SIZE -1 ) & TARGET_PAGE_MASK;
2559
2560 vram_pointer = kvm_create_phys_mem(kvm_context, begin, end - begin, 1,
2561 1, 1);
2562
2563 if (vram_pointer == NULL) {
2564 printf("set_vram_mapping: cannot allocate memory: %m\n");
2565 return NULL;
2566 }
2567
2568 memset(vram_pointer, 0, end - begin);
2569
2570 return vram_pointer;
2571 }
2572
2573 int unset_vram_mapping(unsigned long begin, unsigned long end)
2574 {
2575 /* align begin and end address */
2576 end = begin + VGA_RAM_SIZE;
2577 begin = begin & TARGET_PAGE_MASK;
2578 end = (end + TARGET_PAGE_SIZE -1 ) & TARGET_PAGE_MASK;
2579
2580 kvm_destroy_phys_mem(kvm_context, begin, end - begin);
2581
2582 return 0;
2583 }
2584
2585 static void kvm_update_vga_alias(CirrusVGAState *s, int ok, int bank)
2586 {
2587 unsigned limit, base;
2588
2589 if (!ok && !s->aliases_enabled)
2590 return;
2591 limit = s->cirrus_bank_limit[bank];
2592 if (limit > 0x8000)
2593 limit = 0x8000;
2594 base = s->cirrus_lfb_addr + s->cirrus_bank_base[bank];
2595 if (ok) {
2596 if (!s->aliases_enabled
2597 || base != s->aliased_bank_base[bank]
2598 || limit != s->aliased_bank_limit[bank]) {
2599 kvm_create_memory_alias(kvm_context, bank,
2600 0xa0000 + bank * 0x8000,
2601 limit, base);
2602 s->aliased_bank_base[bank] = base;
2603 s->aliased_bank_limit[bank] = limit;
2604 }
2605 } else {
2606 kvm_destroy_memory_alias(kvm_context, bank);
2607 }
2608 }
2609
2610 static void kvm_update_vga_aliases(CirrusVGAState *s, int ok)
2611 {
2612 if (kvm_allowed) {
2613 kvm_update_vga_alias(s, ok, 0);
2614 kvm_update_vga_alias(s, ok, 1);
2615 }
2616 s->aliases_enabled = ok;
2617 }
2618
2619 #endif
2620
2621 /* Compute the memory access functions */
2622 static void cirrus_update_memory_access(CirrusVGAState *s)
2623 {
2624 unsigned mode;
2625 #ifdef USE_KVM
2626 int want_vga_alias = 0;
2627 #endif
2628
2629 if ((s->sr[0x17] & 0x44) == 0x44) {
2630 goto generic_io;
2631 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2632 goto generic_io;
2633 } else {
2634 if ((s->gr[0x0B] & 0x14) == 0x14) {
2635 goto generic_io;
2636 } else if (s->gr[0x0B] & 0x02) {
2637 goto generic_io;
2638 }
2639
2640 mode = s->gr[0x05] & 0x7;
2641 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2642 #ifdef USE_KVM
2643 if (kvm_allowed && s->cirrus_lfb_addr && s->cirrus_lfb_end &&
2644 !s->map_addr) {
2645 void *vram_pointer, *old_vram;
2646
2647 vram_pointer = set_vram_mapping(s->cirrus_lfb_addr,
2648 s->cirrus_lfb_end);
2649 if (!vram_pointer)
2650 fprintf(stderr, "NULL vram_pointer\n");
2651 else {
2652 old_vram = vga_update_vram((VGAState *)s, vram_pointer,
2653 VGA_RAM_SIZE);
2654 qemu_free(old_vram);
2655 }
2656 s->map_addr = s->cirrus_lfb_addr;
2657 s->map_end = s->cirrus_lfb_end;
2658 }
2659 if (kvm_allowed
2660 && !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2661 && !((s->sr[0x07] & 0x01) == 0)
2662 && !((s->gr[0x0B] & 0x14) == 0x14)
2663 && !(s->gr[0x0B] & 0x02))
2664 want_vga_alias = 1;
2665 #endif
2666 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2667 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2668 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2669 } else {
2670 generic_io:
2671 #ifdef USE_KVM
2672 if (kvm_allowed && s->cirrus_lfb_addr && s->cirrus_lfb_end &&
2673 s->map_addr) {
2674 int error;
2675 void *old_vram = NULL;
2676
2677 error = unset_vram_mapping(s->cirrus_lfb_addr,
2678 s->cirrus_lfb_end);
2679 if (!error)
2680 old_vram = vga_update_vram((VGAState *)s, NULL,
2681 VGA_RAM_SIZE);
2682 if (old_vram)
2683 munmap(old_vram, s->map_end - s->map_addr);
2684 s->map_addr = s->map_end = 0;
2685 }
2686 #endif
2687 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2688 s->cirrus_linear_write[1] = cirrus_linear_writew;
2689 s->cirrus_linear_write[2] = cirrus_linear_writel;
2690 }
2691 }
2692 #ifdef USE_KVM
2693 kvm_update_vga_aliases(s, want_vga_alias);
2694 #endif
2695 }
2696
2697
2698 /* I/O ports */
2699
2700 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2701 {
2702 CirrusVGAState *s = opaque;
2703 int val, index;
2704
2705 /* check port range access depending on color/monochrome mode */
2706 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2707 || (addr >= 0x3d0 && addr <= 0x3df
2708 && !(s->msr & MSR_COLOR_EMULATION))) {
2709 val = 0xff;
2710 } else {
2711 switch (addr) {
2712 case 0x3c0:
2713 if (s->ar_flip_flop == 0) {
2714 val = s->ar_index;
2715 } else {
2716 val = 0;
2717 }
2718 break;
2719 case 0x3c1:
2720 index = s->ar_index & 0x1f;
2721 if (index < 21)
2722 val = s->ar[index];
2723 else
2724 val = 0;
2725 break;
2726 case 0x3c2:
2727 val = s->st00;
2728 break;
2729 case 0x3c4:
2730 val = s->sr_index;
2731 break;
2732 case 0x3c5:
2733 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2734 break;
2735 val = s->sr[s->sr_index];
2736 #ifdef DEBUG_VGA_REG
2737 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2738 #endif
2739 break;
2740 case 0x3c6:
2741 cirrus_read_hidden_dac(s, &val);
2742 break;
2743 case 0x3c7:
2744 val = s->dac_state;
2745 break;
2746 case 0x3c8:
2747 val = s->dac_write_index;
2748 s->cirrus_hidden_dac_lockindex = 0;
2749 break;
2750 case 0x3c9:
2751 if (cirrus_hook_read_palette(s, &val))
2752 break;
2753 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2754 if (++s->dac_sub_index == 3) {
2755 s->dac_sub_index = 0;
2756 s->dac_read_index++;
2757 }
2758 break;
2759 case 0x3ca:
2760 val = s->fcr;
2761 break;
2762 case 0x3cc:
2763 val = s->msr;
2764 break;
2765 case 0x3ce:
2766 val = s->gr_index;
2767 break;
2768 case 0x3cf:
2769 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2770 break;
2771 val = s->gr[s->gr_index];
2772 #ifdef DEBUG_VGA_REG
2773 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2774 #endif
2775 break;
2776 case 0x3b4:
2777 case 0x3d4:
2778 val = s->cr_index;
2779 break;
2780 case 0x3b5:
2781 case 0x3d5:
2782 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2783 break;
2784 val = s->cr[s->cr_index];
2785 #ifdef DEBUG_VGA_REG
2786 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2787 #endif
2788 break;
2789 case 0x3ba:
2790 case 0x3da:
2791 /* just toggle to fool polling */
2792 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
2793 val = s->st01;
2794 s->ar_flip_flop = 0;
2795 break;
2796 default:
2797 val = 0x00;
2798 break;
2799 }
2800 }
2801 #if defined(DEBUG_VGA)
2802 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2803 #endif
2804 return val;
2805 }
2806
2807 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2808 {
2809 CirrusVGAState *s = opaque;
2810 int index;
2811
2812 /* check port range access depending on color/monochrome mode */
2813 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2814 || (addr >= 0x3d0 && addr <= 0x3df
2815 && !(s->msr & MSR_COLOR_EMULATION)))
2816 return;
2817
2818 #ifdef DEBUG_VGA
2819 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2820 #endif
2821
2822 switch (addr) {
2823 case 0x3c0:
2824 if (s->ar_flip_flop == 0) {
2825 val &= 0x3f;
2826 s->ar_index = val;
2827 } else {
2828 index = s->ar_index & 0x1f;
2829 switch (index) {
2830 case 0x00 ... 0x0f:
2831 s->ar[index] = val & 0x3f;
2832 break;
2833 case 0x10:
2834 s->ar[index] = val & ~0x10;
2835 break;
2836 case 0x11:
2837 s->ar[index] = val;
2838 break;
2839 case 0x12:
2840 s->ar[index] = val & ~0xc0;
2841 break;
2842 case 0x13:
2843 s->ar[index] = val & ~0xf0;
2844 break;
2845 case 0x14:
2846 s->ar[index] = val & ~0xf0;
2847 break;
2848 default:
2849 break;
2850 }
2851 }
2852 s->ar_flip_flop ^= 1;
2853 break;
2854 case 0x3c2:
2855 s->msr = val & ~0x10;
2856 break;
2857 case 0x3c4:
2858 s->sr_index = val;
2859 break;
2860 case 0x3c5:
2861 if (cirrus_hook_write_sr(s, s->sr_index, val))
2862 break;
2863 #ifdef DEBUG_VGA_REG
2864 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2865 #endif
2866 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2867 break;
2868 case 0x3c6:
2869 cirrus_write_hidden_dac(s, val);
2870 break;
2871 case 0x3c7:
2872 s->dac_read_index = val;
2873 s->dac_sub_index = 0;
2874 s->dac_state = 3;
2875 break;
2876 case 0x3c8:
2877 s->dac_write_index = val;
2878 s->dac_sub_index = 0;
2879 s->dac_state = 0;
2880 break;
2881 case 0x3c9:
2882 if (cirrus_hook_write_palette(s, val))
2883 break;
2884 s->dac_cache[s->dac_sub_index] = val;
2885 if (++s->dac_sub_index == 3) {
2886 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2887 s->dac_sub_index = 0;
2888 s->dac_write_index++;
2889 }
2890 break;
2891 case 0x3ce:
2892 s->gr_index = val;
2893 break;
2894 case 0x3cf:
2895 if (cirrus_hook_write_gr(s, s->gr_index, val))
2896 break;
2897 #ifdef DEBUG_VGA_REG
2898 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2899 #endif
2900 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2901 break;
2902 case 0x3b4:
2903 case 0x3d4:
2904 s->cr_index = val;
2905 break;
2906 case 0x3b5:
2907 case 0x3d5:
2908 if (cirrus_hook_write_cr(s, s->cr_index, val))
2909 break;
2910 #ifdef DEBUG_VGA_REG
2911 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2912 #endif
2913 /* handle CR0-7 protection */
2914 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2915 /* can always write bit 4 of CR7 */
2916 if (s->cr_index == 7)
2917 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2918 return;
2919 }
2920 switch (s->cr_index) {
2921 case 0x01: /* horizontal display end */
2922 case 0x07:
2923 case 0x09:
2924 case 0x0c:
2925 case 0x0d:
2926 case 0x12: /* veritcal display end */
2927 s->cr[s->cr_index] = val;
2928 break;
2929
2930 default:
2931 s->cr[s->cr_index] = val;
2932 break;
2933 }
2934 break;
2935 case 0x3ba:
2936 case 0x3da:
2937 s->fcr = val & 0x10;
2938 break;
2939 }
2940 }
2941
2942 /***************************************
2943 *
2944 * memory-mapped I/O access
2945 *
2946 ***************************************/
2947
2948 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2949 {
2950 CirrusVGAState *s = (CirrusVGAState *) opaque;
2951
2952 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2953
2954 if (addr >= 0x100) {
2955 return cirrus_mmio_blt_read(s, addr - 0x100);
2956 } else {
2957 return vga_ioport_read(s, addr + 0x3c0);
2958 }
2959 }
2960
2961 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2962 {
2963 uint32_t v;
2964 #ifdef TARGET_WORDS_BIGENDIAN
2965 v = cirrus_mmio_readb(opaque, addr) << 8;
2966 v |= cirrus_mmio_readb(opaque, addr + 1);
2967 #else
2968 v = cirrus_mmio_readb(opaque, addr);
2969 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2970 #endif
2971 return v;
2972 }
2973
2974 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2975 {
2976 uint32_t v;
2977 #ifdef TARGET_WORDS_BIGENDIAN
2978 v = cirrus_mmio_readb(opaque, addr) << 24;
2979 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2980 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2981 v |= cirrus_mmio_readb(opaque, addr + 3);
2982 #else
2983 v = cirrus_mmio_readb(opaque, addr);
2984 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2985 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2986 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2987 #endif
2988 return v;
2989 }
2990
2991 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2992 uint32_t val)
2993 {
2994 CirrusVGAState *s = (CirrusVGAState *) opaque;
2995
2996 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2997
2998 if (addr >= 0x100) {
2999 cirrus_mmio_blt_write(s, addr - 0x100, val);
3000 } else {
3001 vga_ioport_write(s, addr + 0x3c0, val);
3002 }
3003 }
3004
3005 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3006 uint32_t val)
3007 {
3008 #ifdef TARGET_WORDS_BIGENDIAN
3009 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3010 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3011 #else
3012 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3013 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3014 #endif
3015 }
3016
3017 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3018 uint32_t val)
3019 {
3020 #ifdef TARGET_WORDS_BIGENDIAN
3021 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3022 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3023 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3024 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3025 #else
3026 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3027 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3028 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3029 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3030 #endif
3031 }
3032
3033
3034 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3035 cirrus_mmio_readb,
3036 cirrus_mmio_readw,
3037 cirrus_mmio_readl,
3038 };
3039
3040 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3041 cirrus_mmio_writeb,
3042 cirrus_mmio_writew,
3043 cirrus_mmio_writel,
3044 };
3045
3046 /* load/save state */
3047
3048 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3049 {
3050 CirrusVGAState *s = opaque;
3051
3052 if (s->pci_dev)
3053 pci_device_save(s->pci_dev, f);
3054
3055 qemu_put_be32s(f, &s->latch);
3056 qemu_put_8s(f, &s->sr_index);
3057 qemu_put_buffer(f, s->sr, 256);
3058 qemu_put_8s(f, &s->gr_index);
3059 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3060 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3061 qemu_put_buffer(f, s->gr + 2, 254);
3062 qemu_put_8s(f, &s->ar_index);
3063 qemu_put_buffer(f, s->ar, 21);
3064 qemu_put_be32s(f, &s->ar_flip_flop);
3065 qemu_put_8s(f, &s->cr_index);
3066 qemu_put_buffer(f, s->cr, 256);
3067 qemu_put_8s(f, &s->msr);
3068 qemu_put_8s(f, &s->fcr);
3069 qemu_put_8s(f, &s->st00);
3070 qemu_put_8s(f, &s->st01);
3071
3072 qemu_put_8s(f, &s->dac_state);
3073 qemu_put_8s(f, &s->dac_sub_index);
3074 qemu_put_8s(f, &s->dac_read_index);
3075 qemu_put_8s(f, &s->dac_write_index);
3076 qemu_put_buffer(f, s->dac_cache, 3);
3077 qemu_put_buffer(f, s->palette, 768);
3078
3079 qemu_put_be32s(f, &s->bank_offset);
3080
3081 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3082 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3083
3084 qemu_put_be32s(f, &s->hw_cursor_x);
3085 qemu_put_be32s(f, &s->hw_cursor_y);
3086 /* XXX: we do not save the bitblt state - we assume we do not save
3087 the state when the blitter is active */
3088
3089 #ifdef USE_KVM
3090 if (kvm_allowed) { /* XXX: KVM images ought to be loadable in QEMU */
3091 qemu_put_be32s(f, &s->real_vram_size);
3092 qemu_put_buffer(f, s->vram_ptr, s->real_vram_size);
3093 }
3094 #endif
3095 }
3096
3097 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3098 {
3099 CirrusVGAState *s = opaque;
3100 int ret;
3101
3102 if (version_id > 2)
3103 return -EINVAL;
3104
3105 if (s->pci_dev && version_id >= 2) {
3106 ret = pci_device_load(s->pci_dev, f);
3107 if (ret < 0)
3108 return ret;
3109 }
3110
3111 qemu_get_be32s(f, &s->latch);
3112 qemu_get_8s(f, &s->sr_index);
3113 qemu_get_buffer(f, s->sr, 256);
3114 qemu_get_8s(f, &s->gr_index);
3115 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3116 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3117 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3118 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3119 qemu_get_buffer(f, s->gr + 2, 254);
3120 qemu_get_8s(f, &s->ar_index);
3121 qemu_get_buffer(f, s->ar, 21);
3122 qemu_get_be32s(f, &s->ar_flip_flop);
3123 qemu_get_8s(f, &s->cr_index);
3124 qemu_get_buffer(f, s->cr, 256);
3125 qemu_get_8s(f, &s->msr);
3126 qemu_get_8s(f, &s->fcr);
3127 qemu_get_8s(f, &s->st00);
3128 qemu_get_8s(f, &s->st01);
3129
3130 qemu_get_8s(f, &s->dac_state);
3131 qemu_get_8s(f, &s->dac_sub_index);
3132 qemu_get_8s(f, &s->dac_read_index);
3133 qemu_get_8s(f, &s->dac_write_index);
3134 qemu_get_buffer(f, s->dac_cache, 3);
3135 qemu_get_buffer(f, s->palette, 768);
3136
3137 qemu_get_be32s(f, &s->bank_offset);
3138
3139 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3140 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3141
3142 qemu_get_be32s(f, &s->hw_cursor_x);
3143 qemu_get_be32s(f, &s->hw_cursor_y);
3144
3145 #ifdef USE_KVM
3146 if (kvm_allowed) {
3147 int real_vram_size;
3148 qemu_get_be32s(f, &real_vram_size);
3149 if (real_vram_size != s->real_vram_size) {
3150 if (real_vram_size > s->real_vram_size)
3151 real_vram_size = s->real_vram_size;
3152 printf("%s: REAL_VRAM_SIZE MISMATCH !!!!!! SAVED=%d CURRENT=%d",
3153 __FUNCTION__, real_vram_size, s->real_vram_size);
3154 }
3155 qemu_get_buffer(f, s->vram_ptr, real_vram_size);
3156 cirrus_update_memory_access(s);
3157 }
3158 #endif
3159
3160
3161 /* force refresh */
3162 s->graphic_mode = -1;
3163 cirrus_update_bank_ptr(s, 0);
3164 cirrus_update_bank_ptr(s, 1);
3165 return 0;
3166 }
3167
3168 /***************************************
3169 *
3170 * initialize
3171 *
3172 ***************************************/
3173
3174 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3175 {
3176 int vga_io_memory, i;
3177 static int inited;
3178
3179 if (!inited) {
3180 inited = 1;
3181 for(i = 0;i < 256; i++)
3182 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3183 rop_to_index[CIRRUS_ROP_0] = 0;
3184 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3185 rop_to_index[CIRRUS_ROP_NOP] = 2;
3186 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3187 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3188 rop_to_index[CIRRUS_ROP_SRC] = 5;
3189 rop_to_index[CIRRUS_ROP_1] = 6;
3190 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3191 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3192 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3193 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3194 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3195 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3196 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3197 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3198 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3199 }
3200
3201 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3202
3203 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3204 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3205 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3206 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3207
3208 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3209
3210 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3211 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3212 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3213 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3214
3215 vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3216 cirrus_vga_mem_write, s);
3217 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3218 vga_io_memory);
3219
3220 s->sr[0x06] = 0x0f;
3221 if (device_id == CIRRUS_ID_CLGD5446) {
3222 /* 4MB 64 bit memory config, always PCI */
3223 s->sr[0x1F] = 0x2d; // MemClock
3224 s->gr[0x18] = 0x0f; // fastest memory configuration
3225 #if 1
3226 s->sr[0x0f] = 0x98;
3227 s->sr[0x17] = 0x20;
3228 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3229 s->real_vram_size = 4096 * 1024;
3230 #else
3231 s->sr[0x0f] = 0x18;
3232 s->sr[0x17] = 0x20;
3233 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3234 s->real_vram_size = 2048 * 1024;
3235 #endif
3236 } else {
3237 s->sr[0x1F] = 0x22; // MemClock
3238 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3239 if (is_pci)
3240 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3241 else
3242 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3243 s->real_vram_size = 2048 * 1024;
3244 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3245 }
3246 s->cr[0x27] = device_id;
3247
3248 /* Win2K seems to assume that the pattern buffer is at 0xff
3249 initially ! */
3250 memset(s->vram_ptr, 0xff, s->real_vram_size);
3251
3252 s->cirrus_hidden_dac_lockindex = 5;
3253 s->cirrus_hidden_dac_data = 0;
3254
3255 /* I/O handler for LFB */
3256 s->cirrus_linear_io_addr =
3257 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3258 s);
3259 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3260
3261 /* I/O handler for LFB */
3262 s->cirrus_linear_bitblt_io_addr =
3263 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3264 s);
3265
3266 /* I/O handler for memory-mapped I/O */
3267 s->cirrus_mmio_io_addr =
3268 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3269
3270 /* XXX: s->vram_size must be a power of two */
3271 s->cirrus_addr_mask = s->real_vram_size - 1;
3272 s->linear_mmio_mask = s->real_vram_size - 256;
3273
3274 s->get_bpp = cirrus_get_bpp;
3275 s->get_offsets = cirrus_get_offsets;
3276 s->get_resolution = cirrus_get_resolution;
3277 s->cursor_invalidate = cirrus_cursor_invalidate;
3278 s->cursor_draw_line = cirrus_cursor_draw_line;
3279
3280 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3281 }
3282
3283 /***************************************
3284 *
3285 * ISA bus support
3286 *
3287 ***************************************/
3288
3289 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3290 unsigned long vga_ram_offset, int vga_ram_size)
3291 {
3292 CirrusVGAState *s;
3293
3294 s = qemu_mallocz(sizeof(CirrusVGAState));
3295
3296 vga_common_init((VGAState *)s,
3297 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3298 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3299 /* XXX ISA-LFB support */
3300 }
3301
3302 /***************************************
3303 *
3304 * PCI bus support
3305 *
3306 ***************************************/
3307
3308 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3309 uint32_t addr, uint32_t size, int type)
3310 {
3311 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3312
3313 /* XXX: add byte swapping apertures */
3314 cpu_register_physical_memory(addr, s->vram_size,
3315 s->cirrus_linear_io_addr);
3316 #ifdef USE_KVM
3317 if (kvm_allowed) {
3318 s->cirrus_lfb_addr = addr;
3319 s->cirrus_lfb_end = addr + VGA_RAM_SIZE;
3320
3321 if (s->map_addr && (s->cirrus_lfb_addr != s->map_addr) &&
3322 (s->cirrus_lfb_end != s->map_end))
3323 printf("cirrus vga map change while on lfb mode\n");
3324 }
3325 #endif
3326
3327 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3328 s->cirrus_linear_bitblt_io_addr);
3329 }
3330
3331 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3332 uint32_t addr, uint32_t size, int type)
3333 {
3334 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3335
3336 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3337 s->cirrus_mmio_io_addr);
3338 }
3339
3340 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3341 unsigned long vga_ram_offset, int vga_ram_size)
3342 {
3343 PCICirrusVGAState *d;
3344 uint8_t *pci_conf;
3345 CirrusVGAState *s;
3346 int device_id;
3347
3348 device_id = CIRRUS_ID_CLGD5446;
3349
3350 /* setup PCI configuration registers */
3351 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3352 sizeof(PCICirrusVGAState),
3353 -1, NULL, NULL);
3354 pci_conf = d->dev.config;
3355 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3356 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3357 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3358 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3359 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3360 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3361 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3362 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3363
3364 /* setup VGA */
3365 s = &d->cirrus_vga;
3366 vga_common_init((VGAState *)s,
3367 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3368 cirrus_init_common(s, device_id, 1);
3369 s->pci_dev = (PCIDevice *)d;
3370
3371 /* setup memory space */
3372 /* memory #0 LFB */
3373 /* memory #1 memory-mapped I/O */
3374 /* XXX: s->vram_size must be a power of two */
3375 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3376 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3377 if (device_id == CIRRUS_ID_CLGD5446) {
3378 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3379 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3380 }
3381 /* XXX: ROM BIOS */
3382 }
Patches shipped by Fedora