hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24
  25 #include "qemu-kvm.h"
  26
  27 //#define DEBUG_APIC
  28 //#define DEBUG_IOAPIC
  29
  30 /* APIC Local Vector Table */
  31 #define APIC_LVT_TIMER   0
  32 #define APIC_LVT_THERMAL 1
  33 #define APIC_LVT_PERFORM 2
  34 #define APIC_LVT_LINT0   3
  35 #define APIC_LVT_LINT1   4
  36 #define APIC_LVT_ERROR   5
  37 #define APIC_LVT_NB      6
  38
  39 /* APIC delivery modes */
  40 #define APIC_DM_FIXED   0
  41 #define APIC_DM_LOWPRI  1
  42 #define APIC_DM_SMI     2
  43 #define APIC_DM_NMI     4
  44 #define APIC_DM_INIT    5
  45 #define APIC_DM_SIPI    6
  46 #define APIC_DM_EXTINT  7
  47
  48 /* APIC destination mode */
  49 #define APIC_DESTMODE_FLAT      0xf
  50 #define APIC_DESTMODE_CLUSTER   1
  51
  52 #define APIC_TRIGGER_EDGE  0
  53 #define APIC_TRIGGER_LEVEL 1
  54
  55 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  56 #define APIC_LVT_MASKED                 (1<<16)
  57 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  58 #define APIC_LVT_REMOTE_IRR             (1<<14)
  59 #define APIC_INPUT_POLARITY             (1<<13)
  60 #define APIC_SEND_PENDING               (1<<12)
  61
  62 /* FIXME: it's now hard coded to be equal with KVM_IOAPIC_NUM_PINS */
  63 #define IOAPIC_NUM_PINS                 0x18
  64 #define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
  65
  66 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  67
  68 #define APIC_SV_ENABLE (1 << 8)
  69
  70 #define MAX_APICS 255
  71 #define MAX_APIC_WORDS 8
  72
  73 typedef struct APICState {
  74     CPUState *cpu_env;
  75     uint32_t apicbase;
  76     uint8_t id;
  77     uint8_t arb_id;
  78     uint8_t tpr;
  79     uint32_t spurious_vec;
  80     uint8_t log_dest;
  81     uint8_t dest_mode;
  82     uint32_t isr[8];  /* in service register */
  83     uint32_t tmr[8];  /* trigger mode register */
  84     uint32_t irr[8]; /* interrupt request register */
  85     uint32_t lvt[APIC_LVT_NB];
  86     uint32_t esr; /* error register */
  87     uint32_t icr[2];
  88
  89     uint32_t divide_conf;
  90     int count_shift;
  91     uint32_t initial_count;
  92     int64_t initial_count_load_time, next_time;
  93     QEMUTimer *timer;
  94 } APICState;
  95
  96 struct IOAPICState {
  97     uint8_t id;
  98     uint8_t ioregsel;
  99     uint64_t base_address;
 100
 101     uint32_t irr;
 102     uint64_t ioredtbl[IOAPIC_NUM_PINS];
 103 };
 104
 105 static int apic_io_memory;
 106 static APICState *local_apics[MAX_APICS + 1];
 107 static int last_apic_id = 0;
 108
 109 static void apic_init_ipi(APICState *s);
 110 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 111 static void apic_update_irq(APICState *s);
 112
 113 /* Find first bit starting from msb */
 114 static int fls_bit(uint32_t value)
 115 {
 116     return 31 - clz32(value);
 117 }
 118
 119 /* Find first bit starting from lsb */
 120 static int ffs_bit(uint32_t value)
 121 {
 122     return ctz32(value);
 123 }
 124
 125 static inline void set_bit(uint32_t *tab, int index)
 126 {
 127     int i, mask;
 128     i = index >> 5;
 129     mask = 1 << (index & 0x1f);
 130     tab[i] |= mask;
 131 }
 132
 133 static inline void reset_bit(uint32_t *tab, int index)
 134 {
 135     int i, mask;
 136     i = index >> 5;
 137     mask = 1 << (index & 0x1f);
 138     tab[i] &= ~mask;
 139 }
 140
 141 static void apic_local_deliver(CPUState *env, int vector)
 142 {
 143     APICState *s = env->apic_state;
 144     uint32_t lvt = s->lvt[vector];
 145     int trigger_mode;
 146
 147     if (lvt & APIC_LVT_MASKED)
 148         return;
 149
 150     switch ((lvt >> 8) & 7) {
 151     case APIC_DM_SMI:
 152         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 153         break;
 154
 155     case APIC_DM_NMI:
 156         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 157         break;
 158
 159     case APIC_DM_EXTINT:
 160         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 161         break;
 162
 163     case APIC_DM_FIXED:
 164         trigger_mode = APIC_TRIGGER_EDGE;
 165         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 166             (lvt & APIC_LVT_LEVEL_TRIGGER))
 167             trigger_mode = APIC_TRIGGER_LEVEL;
 168         apic_set_irq(s, lvt & 0xff, trigger_mode);
 169     }
 170 }
 171
 172 void apic_deliver_pic_intr(CPUState *env, int level)
 173 {
 174     if (level)
 175         apic_local_deliver(env, APIC_LVT_LINT0);
 176     else {
 177         APICState *s = env->apic_state;
 178         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 179
 180         switch ((lvt >> 8) & 7) {
 181         case APIC_DM_FIXED:
 182             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 183                 break;
 184             reset_bit(s->irr, lvt & 0xff);
 185             /* fall through */
 186         case APIC_DM_EXTINT:
 187             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 188             break;
 189         }
 190     }
 191 }
 192
 193 #define foreach_apic(apic, deliver_bitmask, code) \
 194 {\
 195     int __i, __j, __mask;\
 196     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 197         __mask = deliver_bitmask[__i];\
 198         if (__mask) {\
 199             for(__j = 0; __j < 32; __j++) {\
 200                 if (__mask & (1 << __j)) {\
 201                     apic = local_apics[__i * 32 + __j];\
 202                     if (apic) {\
 203                         code;\
 204                     }\
 205                 }\
 206             }\
 207         }\
 208     }\
 209 }
 210
 211 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 212                              uint8_t delivery_mode,
 213                              uint8_t vector_num, uint8_t polarity,
 214                              uint8_t trigger_mode)
 215 {
 216     APICState *apic_iter;
 217
 218     switch (delivery_mode) {
 219         case APIC_DM_LOWPRI:
 220             /* XXX: search for focus processor, arbitration */
 221             {
 222                 int i, d;
 223                 d = -1;
 224                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 225                     if (deliver_bitmask[i]) {
 226                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 227                         break;
 228                     }
 229                 }
 230                 if (d >= 0) {
 231                     apic_iter = local_apics[d];
 232                     if (apic_iter) {
 233                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 234                     }
 235                 }
 236             }
 237             return;
 238
 239         case APIC_DM_FIXED:
 240             break;
 241
 242         case APIC_DM_SMI:
 243             foreach_apic(apic_iter, deliver_bitmask,
 244                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 245             return;
 246
 247         case APIC_DM_NMI:
 248             foreach_apic(apic_iter, deliver_bitmask,
 249                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 250             return;
 251
 252         case APIC_DM_INIT:
 253             /* normal INIT IPI sent to processors */
 254             foreach_apic(apic_iter, deliver_bitmask,
 255                          apic_init_ipi(apic_iter) );
 256             return;
 257
 258         case APIC_DM_EXTINT:
 259             /* handled in I/O APIC code */
 260             break;
 261
 262         default:
 263             return;
 264     }
 265
 266     foreach_apic(apic_iter, deliver_bitmask,
 267                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 268 }
 269
 270 void cpu_set_apic_base(CPUState *env, uint64_t val)
 271 {
 272     APICState *s = env->apic_state;
 273 #ifdef DEBUG_APIC
 274     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 275 #endif
 276     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel())
 277         s->apicbase = val;
 278     else
 279         s->apicbase = (val & 0xfffff000) |
 280             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 281     /* if disabled, cannot be enabled again */
 282     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 283         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 284         env->cpuid_features &= ~CPUID_APIC;
 285         s->spurious_vec &= ~APIC_SV_ENABLE;
 286     }
 287 }
 288
 289 uint64_t cpu_get_apic_base(CPUState *env)
 290 {
 291     APICState *s = env->apic_state;
 292 #ifdef DEBUG_APIC
 293     printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
 294 #endif
 295     return s->apicbase;
 296 }
 297
 298 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 299 {
 300     APICState *s = env->apic_state;
 301     s->tpr = (val & 0x0f) << 4;
 302     apic_update_irq(s);
 303 }
 304
 305 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 306 {
 307     APICState *s = env->apic_state;
 308     return s->tpr >> 4;
 309 }
 310
 311 /* return -1 if no bit is set */
 312 static int get_highest_priority_int(uint32_t *tab)
 313 {
 314     int i;
 315     for(i = 7; i >= 0; i--) {
 316         if (tab[i] != 0) {
 317             return i * 32 + fls_bit(tab[i]);
 318         }
 319     }
 320     return -1;
 321 }
 322
 323 static int apic_get_ppr(APICState *s)
 324 {
 325     int tpr, isrv, ppr;
 326
 327     tpr = (s->tpr >> 4);
 328     isrv = get_highest_priority_int(s->isr);
 329     if (isrv < 0)
 330         isrv = 0;
 331     isrv >>= 4;
 332     if (tpr >= isrv)
 333         ppr = s->tpr;
 334     else
 335         ppr = isrv << 4;
 336     return ppr;
 337 }
 338
 339 static int apic_get_arb_pri(APICState *s)
 340 {
 341     /* XXX: arbitration */
 342     return 0;
 343 }
 344
 345 /* signal the CPU if an irq is pending */
 346 static void apic_update_irq(APICState *s)
 347 {
 348     int irrv, ppr;
 349     if (!(s->spurious_vec & APIC_SV_ENABLE))
 350         return;
 351     irrv = get_highest_priority_int(s->irr);
 352     if (irrv < 0)
 353         return;
 354     ppr = apic_get_ppr(s);
 355     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 356         return;
 357     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 358 }
 359
 360 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 361 {
 362     set_bit(s->irr, vector_num);
 363     if (trigger_mode)
 364         set_bit(s->tmr, vector_num);
 365     else
 366         reset_bit(s->tmr, vector_num);
 367     apic_update_irq(s);
 368 }
 369
 370 static void apic_eoi(APICState *s)
 371 {
 372     int isrv;
 373     isrv = get_highest_priority_int(s->isr);
 374     if (isrv < 0)
 375         return;
 376     reset_bit(s->isr, isrv);
 377     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 378             set the remote IRR bit for level triggered interrupts. */
 379     apic_update_irq(s);
 380 }
 381
 382 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 383                                       uint8_t dest, uint8_t dest_mode)
 384 {
 385     APICState *apic_iter;
 386     int i;
 387
 388     if (dest_mode == 0) {
 389         if (dest == 0xff) {
 390             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 391         } else {
 392             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 393             set_bit(deliver_bitmask, dest);
 394         }
 395     } else {
 396         /* XXX: cluster mode */
 397         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 398         for(i = 0; i < MAX_APICS; i++) {
 399             apic_iter = local_apics[i];
 400             if (apic_iter) {
 401                 if (apic_iter->dest_mode == 0xf) {
 402                     if (dest & apic_iter->log_dest)
 403                         set_bit(deliver_bitmask, i);
 404                 } else if (apic_iter->dest_mode == 0x0) {
 405                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 406                         (dest & apic_iter->log_dest & 0x0f)) {
 407                         set_bit(deliver_bitmask, i);
 408                     }
 409                 }
 410             }
 411         }
 412     }
 413 }
 414
 415
 416 static void apic_init_ipi(APICState *s)
 417 {
 418     int i;
 419
 420     s->tpr = 0;
 421     s->spurious_vec = 0xff;
 422     s->log_dest = 0;
 423     s->dest_mode = 0xf;
 424     memset(s->isr, 0, sizeof(s->isr));
 425     memset(s->tmr, 0, sizeof(s->tmr));
 426     memset(s->irr, 0, sizeof(s->irr));
 427     for(i = 0; i < APIC_LVT_NB; i++)
 428         s->lvt[i] = 1 << 16; /* mask LVT */
 429     s->esr = 0;
 430     memset(s->icr, 0, sizeof(s->icr));
 431     s->divide_conf = 0;
 432     s->count_shift = 0;
 433     s->initial_count = 0;
 434     s->initial_count_load_time = 0;
 435     s->next_time = 0;
 436
 437     cpu_reset(s->cpu_env);
 438
 439     if (!(s->apicbase & MSR_IA32_APICBASE_BSP) && !qemu_kvm_irqchip_in_kernel())
 440         s->cpu_env->halted = 1;
 441
 442     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 443         if (s->cpu_env)
 444             kvm_apic_init(s->cpu_env);
 445 }
 446
 447 /* send a SIPI message to the CPU to start it */
 448 static void apic_startup(APICState *s, int vector_num)
 449 {
 450     CPUState *env = s->cpu_env;
 451     if (!env->halted)
 452         return;
 453     env->eip = 0;
 454     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
 455                            0xffff, 0);
 456     env->halted = 0;
 457     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 458         kvm_update_after_sipi(env);
 459 }
 460
 461 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 462                          uint8_t delivery_mode, uint8_t vector_num,
 463                          uint8_t polarity, uint8_t trigger_mode)
 464 {
 465     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 466     int dest_shorthand = (s->icr[0] >> 18) & 3;
 467     APICState *apic_iter;
 468
 469     switch (dest_shorthand) {
 470     case 0:
 471         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 472         break;
 473     case 1:
 474         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 475         set_bit(deliver_bitmask, s->id);
 476         break;
 477     case 2:
 478         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 479         break;
 480     case 3:
 481         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 482         reset_bit(deliver_bitmask, s->id);
 483         break;
 484     }
 485
 486     switch (delivery_mode) {
 487         case APIC_DM_INIT:
 488             {
 489                 int trig_mode = (s->icr[0] >> 15) & 1;
 490                 int level = (s->icr[0] >> 14) & 1;
 491                 if (level == 0 && trig_mode == 1) {
 492                     foreach_apic(apic_iter, deliver_bitmask,
 493                                  apic_iter->arb_id = apic_iter->id );
 494                     return;
 495                 }
 496             }
 497             break;
 498
 499         case APIC_DM_SIPI:
 500             foreach_apic(apic_iter, deliver_bitmask,
 501                          apic_startup(apic_iter, vector_num) );
 502             return;
 503     }
 504
 505     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 506                      trigger_mode);
 507 }
 508
 509 int apic_get_interrupt(CPUState *env)
 510 {
 511     APICState *s = env->apic_state;
 512     int intno;
 513
 514     /* if the APIC is installed or enabled, we let the 8259 handle the
 515        IRQs */
 516     if (!s)
 517         return -1;
 518     if (!(s->spurious_vec & APIC_SV_ENABLE))
 519         return -1;
 520
 521     /* XXX: spurious IRQ handling */
 522     intno = get_highest_priority_int(s->irr);
 523     if (intno < 0)
 524         return -1;
 525     if (s->tpr && intno <= s->tpr)
 526         return s->spurious_vec & 0xff;
 527     reset_bit(s->irr, intno);
 528     set_bit(s->isr, intno);
 529     apic_update_irq(s);
 530     return intno;
 531 }
 532
 533 int apic_accept_pic_intr(CPUState *env)
 534 {
 535     APICState *s = env->apic_state;
 536     uint32_t lvt0;
 537
 538     if (!s)
 539         return -1;
 540
 541     lvt0 = s->lvt[APIC_LVT_LINT0];
 542
 543     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 544         (lvt0 & APIC_LVT_MASKED) == 0)
 545         return 1;
 546
 547     return 0;
 548 }
 549
 550 static uint32_t apic_get_current_count(APICState *s)
 551 {
 552     int64_t d;
 553     uint32_t val;
 554     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 555         s->count_shift;
 556     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 557         /* periodic */
 558         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 559     } else {
 560         if (d >= s->initial_count)
 561             val = 0;
 562         else
 563             val = s->initial_count - d;
 564     }
 565     return val;
 566 }
 567
 568 static void apic_timer_update(APICState *s, int64_t current_time)
 569 {
 570     int64_t next_time, d;
 571
 572     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 573         d = (current_time - s->initial_count_load_time) >>
 574             s->count_shift;
 575         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 576             if (!s->initial_count)
 577                 goto no_timer;
 578             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 579         } else {
 580             if (d >= s->initial_count)
 581                 goto no_timer;
 582             d = (uint64_t)s->initial_count + 1;
 583         }
 584         next_time = s->initial_count_load_time + (d << s->count_shift);
 585         qemu_mod_timer(s->timer, next_time);
 586         s->next_time = next_time;
 587     } else {
 588     no_timer:
 589         qemu_del_timer(s->timer);
 590     }
 591 }
 592
 593 static void apic_timer(void *opaque)
 594 {
 595     APICState *s = opaque;
 596
 597     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 598     apic_timer_update(s, s->next_time);
 599 }
 600
 601 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 602 {
 603     return 0;
 604 }
 605
 606 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 607 {
 608     return 0;
 609 }
 610
 611 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 612 {
 613 }
 614
 615 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 616 {
 617 }
 618
 619 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 620 {
 621     CPUState *env;
 622     APICState *s;
 623     uint32_t val;
 624     int index;
 625
 626     env = cpu_single_env;
 627     if (!env)
 628         return 0;
 629     s = env->apic_state;
 630
 631     index = (addr >> 4) & 0xff;
 632     switch(index) {
 633     case 0x02: /* id */
 634         val = s->id << 24;
 635         break;
 636     case 0x03: /* version */
 637         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 638         break;
 639     case 0x08:
 640         val = s->tpr;
 641         break;
 642     case 0x09:
 643         val = apic_get_arb_pri(s);
 644         break;
 645     case 0x0a:
 646         /* ppr */
 647         val = apic_get_ppr(s);
 648         break;
 649     case 0x0b:
 650         val = 0;
 651         break;
 652     case 0x0d:
 653         val = s->log_dest << 24;
 654         break;
 655     case 0x0e:
 656         val = s->dest_mode << 28;
 657         break;
 658     case 0x0f:
 659         val = s->spurious_vec;
 660         break;
 661     case 0x10 ... 0x17:
 662         val = s->isr[index & 7];
 663         break;
 664     case 0x18 ... 0x1f:
 665         val = s->tmr[index & 7];
 666         break;
 667     case 0x20 ... 0x27:
 668         val = s->irr[index & 7];
 669         break;
 670     case 0x28:
 671         val = s->esr;
 672         break;
 673     case 0x30:
 674     case 0x31:
 675         val = s->icr[index & 1];
 676         break;
 677     case 0x32 ... 0x37:
 678         val = s->lvt[index - 0x32];
 679         break;
 680     case 0x38:
 681         val = s->initial_count;
 682         break;
 683     case 0x39:
 684         val = apic_get_current_count(s);
 685         break;
 686     case 0x3e:
 687         val = s->divide_conf;
 688         break;
 689     default:
 690         s->esr |= ESR_ILLEGAL_ADDRESS;
 691         val = 0;
 692         break;
 693     }
 694 #ifdef DEBUG_APIC
 695     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 696 #endif
 697     return val;
 698 }
 699
 700 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 701 {
 702     CPUState *env;
 703     APICState *s;
 704     int index;
 705
 706     env = cpu_single_env;
 707     if (!env)
 708         return;
 709     s = env->apic_state;
 710
 711 #ifdef DEBUG_APIC
 712     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 713 #endif
 714
 715     index = (addr >> 4) & 0xff;
 716     switch(index) {
 717     case 0x02:
 718         s->id = (val >> 24);
 719         break;
 720     case 0x03:
 721         break;
 722     case 0x08:
 723         s->tpr = val;
 724         apic_update_irq(s);
 725         break;
 726     case 0x09:
 727     case 0x0a:
 728         break;
 729     case 0x0b: /* EOI */
 730         apic_eoi(s);
 731         break;
 732     case 0x0d:
 733         s->log_dest = val >> 24;
 734         break;
 735     case 0x0e:
 736         s->dest_mode = val >> 28;
 737         break;
 738     case 0x0f:
 739         s->spurious_vec = val & 0x1ff;
 740         apic_update_irq(s);
 741         break;
 742     case 0x10 ... 0x17:
 743     case 0x18 ... 0x1f:
 744     case 0x20 ... 0x27:
 745     case 0x28:
 746         break;
 747     case 0x30:
 748         s->icr[0] = val;
 749         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 750                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 751                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 752         break;
 753     case 0x31:
 754         s->icr[1] = val;
 755         break;
 756     case 0x32 ... 0x37:
 757         {
 758             int n = index - 0x32;
 759             s->lvt[n] = val;
 760             if (n == APIC_LVT_TIMER)
 761                 apic_timer_update(s, qemu_get_clock(vm_clock));
 762         }
 763         break;
 764     case 0x38:
 765         s->initial_count = val;
 766         s->initial_count_load_time = qemu_get_clock(vm_clock);
 767         apic_timer_update(s, s->initial_count_load_time);
 768         break;
 769     case 0x39:
 770         break;
 771     case 0x3e:
 772         {
 773             int v;
 774             s->divide_conf = val & 0xb;
 775             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 776             s->count_shift = (v + 1) & 7;
 777         }
 778         break;
 779     default:
 780         s->esr |= ESR_ILLEGAL_ADDRESS;
 781         break;
 782     }
 783 }
 784
 785 #ifdef KVM_CAP_IRQCHIP
 786
 787 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 788 {
 789     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 790 }
 791
 792 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 793                                  int reg_id, uint32_t val)
 794 {
 795     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 796 }
 797
 798 static void kvm_kernel_lapic_save_to_user(APICState *s)
 799 {
 800     struct kvm_lapic_state apic;
 801     struct kvm_lapic_state *kapic = &apic;
 802     int i, v;
 803
 804     kvm_get_lapic(kvm_context, s->cpu_env->cpu_index, kapic);
 805
 806     s->id = kapic_reg(kapic, 0x2);
 807     s->tpr = kapic_reg(kapic, 0x8);
 808     s->arb_id = kapic_reg(kapic, 0x9);
 809     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 810     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 811     s->spurious_vec = kapic_reg(kapic, 0xf);
 812     for (i = 0; i < 8; i++) {
 813         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 814         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 815         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 816     }
 817     s->esr = kapic_reg(kapic, 0x28);
 818     s->icr[0] = kapic_reg(kapic, 0x30);
 819     s->icr[1] = kapic_reg(kapic, 0x31);
 820     for (i = 0; i < APIC_LVT_NB; i++)
 821         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 822     s->initial_count = kapic_reg(kapic, 0x38);
 823     s->divide_conf = kapic_reg(kapic, 0x3e);
 824
 825     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 826     s->count_shift = (v + 1) & 7;
 827
 828     s->initial_count_load_time = qemu_get_clock(vm_clock);
 829     apic_timer_update(s, s->initial_count_load_time);
 830 }
 831
 832 static void kvm_kernel_lapic_load_from_user(APICState *s)
 833 {
 834     struct kvm_lapic_state apic;
 835     struct kvm_lapic_state *klapic = &apic;
 836     int i;
 837
 838     memset(klapic, 0, sizeof apic);
 839     kapic_set_reg(klapic, 0x2, s->id);
 840     kapic_set_reg(klapic, 0x8, s->tpr);
 841     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 842     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 843     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 844     for (i = 0; i < 8; i++) {
 845         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 846         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 847         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 848     }
 849     kapic_set_reg(klapic, 0x28, s->esr);
 850     kapic_set_reg(klapic, 0x30, s->icr[0]);
 851     kapic_set_reg(klapic, 0x31, s->icr[1]);
 852     for (i = 0; i < APIC_LVT_NB; i++)
 853         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 854     kapic_set_reg(klapic, 0x38, s->initial_count);
 855     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 856
 857     kvm_set_lapic(kvm_context, s->cpu_env->cpu_index, klapic);
 858 }
 859
 860 #endif
 861
 862 static void apic_save(QEMUFile *f, void *opaque)
 863 {
 864     APICState *s = opaque;
 865     int i;
 866
 867 #ifdef KVM_CAP_IRQCHIP
 868     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 869         kvm_kernel_lapic_save_to_user(s);
 870     }
 871 #endif
 872
 873     qemu_put_be32s(f, &s->apicbase);
 874     qemu_put_8s(f, &s->id);
 875     qemu_put_8s(f, &s->arb_id);
 876     qemu_put_8s(f, &s->tpr);
 877     qemu_put_be32s(f, &s->spurious_vec);
 878     qemu_put_8s(f, &s->log_dest);
 879     qemu_put_8s(f, &s->dest_mode);
 880     for (i = 0; i < 8; i++) {
 881         qemu_put_be32s(f, &s->isr[i]);
 882         qemu_put_be32s(f, &s->tmr[i]);
 883         qemu_put_be32s(f, &s->irr[i]);
 884     }
 885     for (i = 0; i < APIC_LVT_NB; i++) {
 886         qemu_put_be32s(f, &s->lvt[i]);
 887     }
 888     qemu_put_be32s(f, &s->esr);
 889     qemu_put_be32s(f, &s->icr[0]);
 890     qemu_put_be32s(f, &s->icr[1]);
 891     qemu_put_be32s(f, &s->divide_conf);
 892     qemu_put_be32(f, s->count_shift);
 893     qemu_put_be32s(f, &s->initial_count);
 894     qemu_put_be64(f, s->initial_count_load_time);
 895     qemu_put_be64(f, s->next_time);
 896
 897     qemu_put_timer(f, s->timer);
 898 }
 899
 900 static int apic_load(QEMUFile *f, void *opaque, int version_id)
 901 {
 902     APICState *s = opaque;
 903     int i;
 904
 905     if (version_id > 2)
 906         return -EINVAL;
 907
 908     /* XXX: what if the base changes? (registered memory regions) */
 909     qemu_get_be32s(f, &s->apicbase);
 910     qemu_get_8s(f, &s->id);
 911     qemu_get_8s(f, &s->arb_id);
 912     qemu_get_8s(f, &s->tpr);
 913     qemu_get_be32s(f, &s->spurious_vec);
 914     qemu_get_8s(f, &s->log_dest);
 915     qemu_get_8s(f, &s->dest_mode);
 916     for (i = 0; i < 8; i++) {
 917         qemu_get_be32s(f, &s->isr[i]);
 918         qemu_get_be32s(f, &s->tmr[i]);
 919         qemu_get_be32s(f, &s->irr[i]);
 920     }
 921     for (i = 0; i < APIC_LVT_NB; i++) {
 922         qemu_get_be32s(f, &s->lvt[i]);
 923     }
 924     qemu_get_be32s(f, &s->esr);
 925     qemu_get_be32s(f, &s->icr[0]);
 926     qemu_get_be32s(f, &s->icr[1]);
 927     qemu_get_be32s(f, &s->divide_conf);
 928     s->count_shift=qemu_get_be32(f);
 929     qemu_get_be32s(f, &s->initial_count);
 930     s->initial_count_load_time=qemu_get_be64(f);
 931     s->next_time=qemu_get_be64(f);
 932
 933     if (version_id >= 2)
 934         qemu_get_timer(f, s->timer);
 935
 936 #ifdef KVM_CAP_IRQCHIP
 937     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 938         kvm_kernel_lapic_load_from_user(s);
 939     }
 940 #endif
 941
 942     return 0;
 943 }
 944
 945 static void apic_reset(void *opaque)
 946 {
 947     APICState *s = opaque;
 948
 949     s->apicbase = 0xfee00000 |
 950         (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
 951
 952     apic_init_ipi(s);
 953
 954     if (s->id == 0) {
 955         /*
 956          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 957          * time typically by BIOS, so PIC interrupt can be delivered to the
 958          * processor when local APIC is enabled.
 959          */
 960         s->lvt[APIC_LVT_LINT0] = 0x700;
 961     }
 962 #ifdef KVM_CAP_IRQCHIP
 963     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 964         kvm_kernel_lapic_load_from_user(s);
 965     }
 966 #endif
 967 }
 968
 969 static CPUReadMemoryFunc *apic_mem_read[3] = {
 970     apic_mem_readb,
 971     apic_mem_readw,
 972     apic_mem_readl,
 973 };
 974
 975 static CPUWriteMemoryFunc *apic_mem_write[3] = {
 976     apic_mem_writeb,
 977     apic_mem_writew,
 978     apic_mem_writel,
 979 };
 980
 981 int apic_init(CPUState *env)
 982 {
 983     APICState *s;
 984
 985     if (last_apic_id >= MAX_APICS)
 986         return -1;
 987     s = qemu_mallocz(sizeof(APICState));
 988     if (!s)
 989         return -1;
 990     env->apic_state = s;
 991     s->id = last_apic_id++;
 992     env->cpuid_apic_id = s->id;
 993     s->cpu_env = env;
 994
 995     apic_reset(s);
 996
 997     /* XXX: mapping more APICs at the same memory location */
 998     if (apic_io_memory == 0) {
 999         /* NOTE: the APIC is directly connected to the CPU - it is not
1000            on the global memory bus. */
1001         apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1002                                                 apic_mem_write, NULL);
1003         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1004                                      apic_io_memory);
1005     }
1006     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1007
1008     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
1009     qemu_register_reset(apic_reset, s);
1010
1011     local_apics[s->id] = s;
1012     return 0;
1013 }
1014
1015 static void ioapic_service(IOAPICState *s)
1016 {
1017     uint8_t i;
1018     uint8_t trig_mode;
1019     uint8_t vector;
1020     uint8_t delivery_mode;
1021     uint32_t mask;
1022     uint64_t entry;
1023     uint8_t dest;
1024     uint8_t dest_mode;
1025     uint8_t polarity;
1026     uint32_t deliver_bitmask[MAX_APIC_WORDS];
1027
1028     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1029         mask = 1 << i;
1030         if (s->irr & mask) {
1031             entry = s->ioredtbl[i];
1032             if (!(entry & APIC_LVT_MASKED)) {
1033                 trig_mode = ((entry >> 15) & 1);
1034                 dest = entry >> 56;
1035                 dest_mode = (entry >> 11) & 1;
1036                 delivery_mode = (entry >> 8) & 7;
1037                 polarity = (entry >> 13) & 1;
1038                 if (trig_mode == APIC_TRIGGER_EDGE)
1039                     s->irr &= ~mask;
1040                 if (delivery_mode == APIC_DM_EXTINT)
1041                     vector = pic_read_irq(isa_pic);
1042                 else
1043                     vector = entry & 0xff;
1044
1045                 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
1046                 apic_bus_deliver(deliver_bitmask, delivery_mode,
1047                                  vector, polarity, trig_mode);
1048             }
1049         }
1050     }
1051 }
1052
1053 void ioapic_set_irq(void *opaque, int vector, int level)
1054 {
1055     IOAPICState *s = opaque;
1056
1057     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1058         uint32_t mask = 1 << vector;
1059         uint64_t entry = s->ioredtbl[vector];
1060
1061         if ((entry >> 15) & 1) {
1062             /* level triggered */
1063             if (level) {
1064                 s->irr |= mask;
1065                 ioapic_service(s);
1066             } else {
1067                 s->irr &= ~mask;
1068             }
1069         } else {
1070             /* edge triggered */
1071             if (level) {
1072                 s->irr |= mask;
1073                 ioapic_service(s);
1074             }
1075         }
1076     }
1077 }
1078
1079 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1080 {
1081     IOAPICState *s = opaque;
1082     int index;
1083     uint32_t val = 0;
1084
1085     addr &= 0xff;
1086     if (addr == 0x00) {
1087         val = s->ioregsel;
1088     } else if (addr == 0x10) {
1089         switch (s->ioregsel) {
1090             case 0x00:
1091                 val = s->id << 24;
1092                 break;
1093             case 0x01:
1094                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1095                 break;
1096             case 0x02:
1097                 val = 0;
1098                 break;
1099             default:
1100                 index = (s->ioregsel - 0x10) >> 1;
1101                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1102                     if (s->ioregsel & 1)
1103                         val = s->ioredtbl[index] >> 32;
1104                     else
1105                         val = s->ioredtbl[index] & 0xffffffff;
1106                 }
1107         }
1108 #ifdef DEBUG_IOAPIC
1109         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
1110 #endif
1111     }
1112     return val;
1113 }
1114
1115 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1116 {
1117     IOAPICState *s = opaque;
1118     int index;
1119
1120     addr &= 0xff;
1121     if (addr == 0x00)  {
1122         s->ioregsel = val;
1123         return;
1124     } else if (addr == 0x10) {
1125 #ifdef DEBUG_IOAPIC
1126         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
1127 #endif
1128         switch (s->ioregsel) {
1129             case 0x00:
1130                 s->id = (val >> 24) & 0xff;
1131                 return;
1132             case 0x01:
1133             case 0x02:
1134                 return;
1135             default:
1136                 index = (s->ioregsel - 0x10) >> 1;
1137                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1138                     if (s->ioregsel & 1) {
1139                         s->ioredtbl[index] &= 0xffffffff;
1140                         s->ioredtbl[index] |= (uint64_t)val << 32;
1141                     } else {
1142                         s->ioredtbl[index] &= ~0xffffffffULL;
1143                         s->ioredtbl[index] |= val;
1144                     }
1145                     ioapic_service(s);
1146                 }
1147         }
1148     }
1149 }
1150
1151 static void kvm_kernel_ioapic_save_to_user(IOAPICState *s)
1152 {
1153 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
1154     struct kvm_irqchip chip;
1155     struct kvm_ioapic_state *kioapic;
1156     int i;
1157
1158     chip.chip_id = KVM_IRQCHIP_IOAPIC;
1159     kvm_get_irqchip(kvm_context, &chip);
1160     kioapic = &chip.chip.ioapic;
1161
1162     s->id = kioapic->id;
1163     s->ioregsel = kioapic->ioregsel;
1164     s->base_address = kioapic->base_address;
1165     s->irr = kioapic->irr;
1166     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1167         s->ioredtbl[i] = kioapic->redirtbl[i].bits;
1168     }
1169 #endif
1170 }
1171
1172 static void kvm_kernel_ioapic_load_from_user(IOAPICState *s)
1173 {
1174 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
1175     struct kvm_irqchip chip;
1176     struct kvm_ioapic_state *kioapic;
1177     int i;
1178
1179     chip.chip_id = KVM_IRQCHIP_IOAPIC;
1180     kioapic = &chip.chip.ioapic;
1181
1182     kioapic->id = s->id;
1183     kioapic->ioregsel = s->ioregsel;
1184     kioapic->base_address = s->base_address;
1185     kioapic->irr = s->irr;
1186     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1187         kioapic->redirtbl[i].bits = s->ioredtbl[i];
1188     }
1189
1190     kvm_set_irqchip(kvm_context, &chip);
1191 #endif
1192 }
1193
1194 static void ioapic_save(QEMUFile *f, void *opaque)
1195 {
1196     IOAPICState *s = opaque;
1197     int i;
1198
1199     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1200         kvm_kernel_ioapic_save_to_user(s);
1201     }
1202
1203     qemu_put_8s(f, &s->id);
1204     qemu_put_8s(f, &s->ioregsel);
1205     qemu_put_be64s(f, &s->base_address);
1206     qemu_put_be32s(f, &s->irr);
1207     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1208         qemu_put_be64s(f, &s->ioredtbl[i]);
1209     }
1210 }
1211
1212 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1213 {
1214     IOAPICState *s = opaque;
1215     int i;
1216
1217     if (version_id < 1 || version_id > 2)
1218         return -EINVAL;
1219
1220     qemu_get_8s(f, &s->id);
1221     qemu_get_8s(f, &s->ioregsel);
1222     if (version_id == 2) {
1223       /* for version 2, we get this data off of the wire */
1224       qemu_get_be64s(f, &s->base_address);
1225       qemu_get_be32s(f, &s->irr);
1226     }
1227     else {
1228       /* in case we are doing version 1, we just set these to sane values */
1229       s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
1230       s->irr = 0;
1231     }
1232     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1233         qemu_get_be64s(f, &s->ioredtbl[i]);
1234     }
1235
1236     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1237         kvm_kernel_ioapic_load_from_user(s);
1238     }
1239
1240     return 0;
1241 }
1242
1243 static void ioapic_reset(void *opaque)
1244 {
1245     IOAPICState *s = opaque;
1246     int i;
1247
1248     memset(s, 0, sizeof(*s));
1249     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
1250     for(i = 0; i < IOAPIC_NUM_PINS; i++)
1251         s->ioredtbl[i] = 1 << 16; /* mask LVT */
1252 #ifdef KVM_CAP_IRQCHIP
1253     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1254         kvm_kernel_ioapic_load_from_user(s);
1255     }
1256 #endif
1257 }
1258
1259 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1260     ioapic_mem_readl,
1261     ioapic_mem_readl,
1262     ioapic_mem_readl,
1263 };
1264
1265 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1266     ioapic_mem_writel,
1267     ioapic_mem_writel,
1268     ioapic_mem_writel,
1269 };
1270
1271 IOAPICState *ioapic_init(void)
1272 {
1273     IOAPICState *s;
1274     int io_memory;
1275
1276     s = qemu_mallocz(sizeof(IOAPICState));
1277     if (!s)
1278         return NULL;
1279     ioapic_reset(s);
1280     s->id = last_apic_id++;
1281
1282     io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1283                                        ioapic_mem_write, s);
1284     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1285
1286     register_savevm("ioapic", 0, 2, ioapic_save, ioapic_load, s);
1287     qemu_register_reset(ioapic_reset, s);
1288
1289     return s;
1290 }