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Remove env->ready_for_interrupt_injection
[qemu-kvm/fedora.git] / target-sparc / translate.c
blobeb0ab3343fbeb20229a833a5c2e9611c10102332
1 /*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include <stdarg.h>
23 #include <stdlib.h>
24 #include <stdio.h>
25 #include <string.h>
26 #include <inttypes.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "disas.h"
31 #include "helper.h"
32 #include "tcg-op.h"
33
34 #define DEBUG_DISAS
35
36 #define DYNAMIC_PC 1 /* dynamic pc value */
37 #define JUMP_PC 2 /* dynamic pc value which takes only two values
38 according to jump_pc[T2] */
39
40 /* global register indexes */
41 static TCGv cpu_env, cpu_T[2], cpu_regwptr;
42 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
43 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
44 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
45 #ifdef TARGET_SPARC64
46 static TCGv cpu_xcc;
47 #endif
48 /* local register indexes (only used inside old micro ops) */
49 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
50
51 typedef struct DisasContext {
52 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
53 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
54 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
55 int is_br;
56 int mem_idx;
57 int fpu_enabled;
58 struct TranslationBlock *tb;
59 uint32_t features;
60 } DisasContext;
61
62 // This function uses non-native bit order
63 #define GET_FIELD(X, FROM, TO) \
64 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
65
66 // This function uses the order in the manuals, i.e. bit 0 is 2^0
67 #define GET_FIELD_SP(X, FROM, TO) \
68 GET_FIELD(X, 31 - (TO), 31 - (FROM))
69
70 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
71 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
72
73 #ifdef TARGET_SPARC64
74 #define FFPREG(r) (r)
75 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
76 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
77 #else
78 #define FFPREG(r) (r)
79 #define DFPREG(r) (r & 0x1e)
80 #define QFPREG(r) (r & 0x1c)
81 #endif
82
83 static int sign_extend(int x, int len)
84 {
85 len = 32 - len;
86 return (x << len) >> len;
87 }
88
89 #define IS_IMM (insn & (1<<13))
90
91 /* floating point registers moves */
92 static void gen_op_load_fpr_FT0(unsigned int src)
93 {
94 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
95 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
96 }
97
98 static void gen_op_load_fpr_FT1(unsigned int src)
99 {
100 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
101 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
102 }
103
104 static void gen_op_store_FT0_fpr(unsigned int dst)
105 {
106 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
107 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
108 }
109
110 static void gen_op_load_fpr_DT0(unsigned int src)
111 {
112 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
113 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
114 offsetof(CPU_DoubleU, l.upper));
115 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
116 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
117 offsetof(CPU_DoubleU, l.lower));
118 }
119
120 static void gen_op_load_fpr_DT1(unsigned int src)
121 {
122 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
123 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
124 offsetof(CPU_DoubleU, l.upper));
125 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
126 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
127 offsetof(CPU_DoubleU, l.lower));
128 }
129
130 static void gen_op_store_DT0_fpr(unsigned int dst)
131 {
132 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
133 offsetof(CPU_DoubleU, l.upper));
134 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
135 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
136 offsetof(CPU_DoubleU, l.lower));
137 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
138 }
139
140 static void gen_op_load_fpr_QT0(unsigned int src)
141 {
142 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
143 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
144 offsetof(CPU_QuadU, l.upmost));
145 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
146 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
147 offsetof(CPU_QuadU, l.upper));
148 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
149 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
150 offsetof(CPU_QuadU, l.lower));
151 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
152 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
153 offsetof(CPU_QuadU, l.lowest));
154 }
155
156 static void gen_op_load_fpr_QT1(unsigned int src)
157 {
158 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
159 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
160 offsetof(CPU_QuadU, l.upmost));
161 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
162 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
163 offsetof(CPU_QuadU, l.upper));
164 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
165 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
166 offsetof(CPU_QuadU, l.lower));
167 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
168 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
169 offsetof(CPU_QuadU, l.lowest));
170 }
171
172 static void gen_op_store_QT0_fpr(unsigned int dst)
173 {
174 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
175 offsetof(CPU_QuadU, l.upmost));
176 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
177 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
178 offsetof(CPU_QuadU, l.upper));
179 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
180 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
181 offsetof(CPU_QuadU, l.lower));
182 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
183 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
184 offsetof(CPU_QuadU, l.lowest));
185 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
186 }
187
188 /* moves */
189 #ifdef CONFIG_USER_ONLY
190 #define supervisor(dc) 0
191 #ifdef TARGET_SPARC64
192 #define hypervisor(dc) 0
193 #endif
194 #else
195 #define supervisor(dc) (dc->mem_idx >= 1)
196 #ifdef TARGET_SPARC64
197 #define hypervisor(dc) (dc->mem_idx == 2)
198 #else
199 #endif
200 #endif
201
202 #ifdef TARGET_ABI32
203 #define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
204 #else
205 #define ABI32_MASK(addr)
206 #endif
207
208 static inline void gen_movl_reg_TN(int reg, TCGv tn)
209 {
210 if (reg == 0)
211 tcg_gen_movi_tl(tn, 0);
212 else if (reg < 8)
213 tcg_gen_mov_tl(tn, cpu_gregs[reg]);
214 else {
215 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
216 }
217 }
218
219 static inline void gen_movl_TN_reg(int reg, TCGv tn)
220 {
221 if (reg == 0)
222 return;
223 else if (reg < 8)
224 tcg_gen_mov_tl(cpu_gregs[reg], tn);
225 else {
226 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
227 }
228 }
229
230 static inline void gen_goto_tb(DisasContext *s, int tb_num,
231 target_ulong pc, target_ulong npc)
232 {
233 TranslationBlock *tb;
234
235 tb = s->tb;
236 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
237 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
238 /* jump to same page: we can use a direct jump */
239 tcg_gen_goto_tb(tb_num);
240 tcg_gen_movi_tl(cpu_pc, pc);
241 tcg_gen_movi_tl(cpu_npc, npc);
242 tcg_gen_exit_tb((long)tb + tb_num);
243 } else {
244 /* jump to another page: currently not optimized */
245 tcg_gen_movi_tl(cpu_pc, pc);
246 tcg_gen_movi_tl(cpu_npc, npc);
247 tcg_gen_exit_tb(0);
248 }
249 }
250
251 // XXX suboptimal
252 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
253 {
254 tcg_gen_extu_i32_tl(reg, src);
255 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
256 tcg_gen_andi_tl(reg, reg, 0x1);
257 }
258
259 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
260 {
261 tcg_gen_extu_i32_tl(reg, src);
262 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
263 tcg_gen_andi_tl(reg, reg, 0x1);
264 }
265
266 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
267 {
268 tcg_gen_extu_i32_tl(reg, src);
269 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
270 tcg_gen_andi_tl(reg, reg, 0x1);
271 }
272
273 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
274 {
275 tcg_gen_extu_i32_tl(reg, src);
276 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
277 tcg_gen_andi_tl(reg, reg, 0x1);
278 }
279
280 static inline void gen_cc_clear_icc(void)
281 {
282 tcg_gen_movi_i32(cpu_psr, 0);
283 }
284
285 #ifdef TARGET_SPARC64
286 static inline void gen_cc_clear_xcc(void)
287 {
288 tcg_gen_movi_i32(cpu_xcc, 0);
289 }
290 #endif
291
292 /* old op:
293 if (!T0)
294 env->psr |= PSR_ZERO;
295 if ((int32_t) T0 < 0)
296 env->psr |= PSR_NEG;
297 */
298 static inline void gen_cc_NZ_icc(TCGv dst)
299 {
300 TCGv r_temp;
301 int l1, l2;
302
303 l1 = gen_new_label();
304 l2 = gen_new_label();
305 r_temp = tcg_temp_new(TCG_TYPE_TL);
306 tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
307 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
308 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
309 gen_set_label(l1);
310 tcg_gen_ext_i32_tl(r_temp, dst);
311 tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
312 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
313 gen_set_label(l2);
314 tcg_temp_free(r_temp);
315 }
316
317 #ifdef TARGET_SPARC64
318 static inline void gen_cc_NZ_xcc(TCGv dst)
319 {
320 int l1, l2;
321
322 l1 = gen_new_label();
323 l2 = gen_new_label();
324 tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
325 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
326 gen_set_label(l1);
327 tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
328 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
329 gen_set_label(l2);
330 }
331 #endif
332
333 /* old op:
334 if (T0 < src1)
335 env->psr |= PSR_CARRY;
336 */
337 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
338 {
339 TCGv r_temp;
340 int l1;
341
342 l1 = gen_new_label();
343 r_temp = tcg_temp_new(TCG_TYPE_TL);
344 tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
345 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
346 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
347 gen_set_label(l1);
348 tcg_temp_free(r_temp);
349 }
350
351 #ifdef TARGET_SPARC64
352 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
353 {
354 int l1;
355
356 l1 = gen_new_label();
357 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
358 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
359 gen_set_label(l1);
360 }
361 #endif
362
363 /* old op:
364 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
365 env->psr |= PSR_OVF;
366 */
367 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
368 {
369 TCGv r_temp;
370
371 r_temp = tcg_temp_new(TCG_TYPE_TL);
372 tcg_gen_xor_tl(r_temp, src1, src2);
373 tcg_gen_xori_tl(r_temp, r_temp, -1);
374 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
375 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
376 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
377 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
378 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
379 tcg_temp_free(r_temp);
380 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
381 }
382
383 #ifdef TARGET_SPARC64
384 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
385 {
386 TCGv r_temp;
387
388 r_temp = tcg_temp_new(TCG_TYPE_TL);
389 tcg_gen_xor_tl(r_temp, src1, src2);
390 tcg_gen_xori_tl(r_temp, r_temp, -1);
391 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
392 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
393 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
394 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
395 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
396 tcg_temp_free(r_temp);
397 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
398 }
399 #endif
400
401 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
402 {
403 TCGv r_temp, r_const;
404 int l1;
405
406 l1 = gen_new_label();
407
408 r_temp = tcg_temp_new(TCG_TYPE_TL);
409 tcg_gen_xor_tl(r_temp, src1, src2);
410 tcg_gen_xori_tl(r_temp, r_temp, -1);
411 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
412 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
413 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
414 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
415 r_const = tcg_const_i32(TT_TOVF);
416 tcg_gen_helper_0_1(raise_exception, r_const);
417 tcg_temp_free(r_const);
418 gen_set_label(l1);
419 tcg_temp_free(r_temp);
420 }
421
422 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
423 {
424 int l1;
425
426 l1 = gen_new_label();
427 tcg_gen_or_tl(cpu_tmp0, src1, src2);
428 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
429 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
430 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
431 gen_set_label(l1);
432 }
433
434 static inline void gen_tag_tv(TCGv src1, TCGv src2)
435 {
436 int l1;
437 TCGv r_const;
438
439 l1 = gen_new_label();
440 tcg_gen_or_tl(cpu_tmp0, src1, src2);
441 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
442 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
443 r_const = tcg_const_i32(TT_TOVF);
444 tcg_gen_helper_0_1(raise_exception, r_const);
445 tcg_temp_free(r_const);
446 gen_set_label(l1);
447 }
448
449 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
450 {
451 tcg_gen_mov_tl(cpu_cc_src, src1);
452 tcg_gen_mov_tl(cpu_cc_src2, src2);
453 tcg_gen_add_tl(dst, src1, src2);
454 tcg_gen_mov_tl(cpu_cc_dst, dst);
455 gen_cc_clear_icc();
456 gen_cc_NZ_icc(cpu_cc_dst);
457 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
458 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
459 #ifdef TARGET_SPARC64
460 gen_cc_clear_xcc();
461 gen_cc_NZ_xcc(cpu_cc_dst);
462 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
463 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
464 #endif
465 }
466
467 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
468 {
469 tcg_gen_mov_tl(cpu_cc_src, src1);
470 tcg_gen_mov_tl(cpu_cc_src2, src2);
471 gen_mov_reg_C(cpu_tmp0, cpu_psr);
472 tcg_gen_add_tl(dst, src1, cpu_tmp0);
473 gen_cc_clear_icc();
474 gen_cc_C_add_icc(dst, cpu_cc_src);
475 #ifdef TARGET_SPARC64
476 gen_cc_clear_xcc();
477 gen_cc_C_add_xcc(dst, cpu_cc_src);
478 #endif
479 tcg_gen_add_tl(dst, dst, cpu_cc_src2);
480 tcg_gen_mov_tl(cpu_cc_dst, dst);
481 gen_cc_NZ_icc(cpu_cc_dst);
482 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
483 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
484 #ifdef TARGET_SPARC64
485 gen_cc_NZ_xcc(cpu_cc_dst);
486 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
487 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
488 #endif
489 }
490
491 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
492 {
493 tcg_gen_mov_tl(cpu_cc_src, src1);
494 tcg_gen_mov_tl(cpu_cc_src2, src2);
495 tcg_gen_add_tl(dst, src1, src2);
496 tcg_gen_mov_tl(cpu_cc_dst, dst);
497 gen_cc_clear_icc();
498 gen_cc_NZ_icc(cpu_cc_dst);
499 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
500 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
501 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
502 #ifdef TARGET_SPARC64
503 gen_cc_clear_xcc();
504 gen_cc_NZ_xcc(cpu_cc_dst);
505 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
506 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
507 #endif
508 }
509
510 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
511 {
512 tcg_gen_mov_tl(cpu_cc_src, src1);
513 tcg_gen_mov_tl(cpu_cc_src2, src2);
514 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
515 tcg_gen_add_tl(dst, src1, src2);
516 tcg_gen_mov_tl(cpu_cc_dst, dst);
517 gen_add_tv(dst, cpu_cc_src, cpu_cc_src2);
518 gen_cc_clear_icc();
519 gen_cc_NZ_icc(cpu_cc_dst);
520 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
521 #ifdef TARGET_SPARC64
522 gen_cc_clear_xcc();
523 gen_cc_NZ_xcc(cpu_cc_dst);
524 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
525 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
526 #endif
527 }
528
529 /* old op:
530 if (src1 < T1)
531 env->psr |= PSR_CARRY;
532 */
533 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
534 {
535 TCGv r_temp1, r_temp2;
536 int l1;
537
538 l1 = gen_new_label();
539 r_temp1 = tcg_temp_new(TCG_TYPE_TL);
540 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
541 tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
542 tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
543 tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
544 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
545 gen_set_label(l1);
546 tcg_temp_free(r_temp1);
547 tcg_temp_free(r_temp2);
548 }
549
550 #ifdef TARGET_SPARC64
551 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
552 {
553 int l1;
554
555 l1 = gen_new_label();
556 tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
557 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
558 gen_set_label(l1);
559 }
560 #endif
561
562 /* old op:
563 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
564 env->psr |= PSR_OVF;
565 */
566 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
567 {
568 TCGv r_temp;
569
570 r_temp = tcg_temp_new(TCG_TYPE_TL);
571 tcg_gen_xor_tl(r_temp, src1, src2);
572 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
573 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
574 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
575 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
576 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
577 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
578 tcg_temp_free(r_temp);
579 }
580
581 #ifdef TARGET_SPARC64
582 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
583 {
584 TCGv r_temp;
585
586 r_temp = tcg_temp_new(TCG_TYPE_TL);
587 tcg_gen_xor_tl(r_temp, src1, src2);
588 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
589 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
590 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
591 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
592 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
593 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
594 tcg_temp_free(r_temp);
595 }
596 #endif
597
598 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
599 {
600 TCGv r_temp, r_const;
601 int l1;
602
603 l1 = gen_new_label();
604
605 r_temp = tcg_temp_new(TCG_TYPE_TL);
606 tcg_gen_xor_tl(r_temp, src1, src2);
607 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
608 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
609 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
610 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
611 r_const = tcg_const_i32(TT_TOVF);
612 tcg_gen_helper_0_1(raise_exception, r_const);
613 tcg_temp_free(r_const);
614 gen_set_label(l1);
615 tcg_temp_free(r_temp);
616 }
617
618 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
619 {
620 tcg_gen_mov_tl(cpu_cc_src, src1);
621 tcg_gen_mov_tl(cpu_cc_src2, src2);
622 tcg_gen_sub_tl(dst, src1, src2);
623 tcg_gen_mov_tl(cpu_cc_dst, dst);
624 gen_cc_clear_icc();
625 gen_cc_NZ_icc(cpu_cc_dst);
626 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
627 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
628 #ifdef TARGET_SPARC64
629 gen_cc_clear_xcc();
630 gen_cc_NZ_xcc(cpu_cc_dst);
631 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
632 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
633 #endif
634 }
635
636 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
637 {
638 tcg_gen_mov_tl(cpu_cc_src, src1);
639 tcg_gen_mov_tl(cpu_cc_src2, src2);
640 gen_mov_reg_C(cpu_tmp0, cpu_psr);
641 tcg_gen_sub_tl(dst, src1, cpu_tmp0);
642 gen_cc_clear_icc();
643 gen_cc_C_sub_icc(dst, cpu_cc_src);
644 #ifdef TARGET_SPARC64
645 gen_cc_clear_xcc();
646 gen_cc_C_sub_xcc(dst, cpu_cc_src);
647 #endif
648 tcg_gen_sub_tl(dst, dst, cpu_cc_src2);
649 tcg_gen_mov_tl(cpu_cc_dst, dst);
650 gen_cc_NZ_icc(cpu_cc_dst);
651 gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
652 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
653 #ifdef TARGET_SPARC64
654 gen_cc_NZ_xcc(cpu_cc_dst);
655 gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
656 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
657 #endif
658 }
659
660 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
661 {
662 tcg_gen_mov_tl(cpu_cc_src, src1);
663 tcg_gen_mov_tl(cpu_cc_src2, src2);
664 tcg_gen_sub_tl(dst, src1, src2);
665 tcg_gen_mov_tl(cpu_cc_dst, dst);
666 gen_cc_clear_icc();
667 gen_cc_NZ_icc(cpu_cc_dst);
668 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
669 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
670 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
671 #ifdef TARGET_SPARC64
672 gen_cc_clear_xcc();
673 gen_cc_NZ_xcc(cpu_cc_dst);
674 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
675 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
676 #endif
677 }
678
679 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
680 {
681 tcg_gen_mov_tl(cpu_cc_src, src1);
682 tcg_gen_mov_tl(cpu_cc_src2, src2);
683 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
684 tcg_gen_sub_tl(dst, src1, src2);
685 tcg_gen_mov_tl(cpu_cc_dst, dst);
686 gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2);
687 gen_cc_clear_icc();
688 gen_cc_NZ_icc(cpu_cc_dst);
689 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
690 #ifdef TARGET_SPARC64
691 gen_cc_clear_xcc();
692 gen_cc_NZ_xcc(cpu_cc_dst);
693 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
694 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
695 #endif
696 }
697
698 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
699 {
700 TCGv r_temp, r_temp2;
701 int l1;
702
703 l1 = gen_new_label();
704 r_temp = tcg_temp_new(TCG_TYPE_TL);
705 r_temp2 = tcg_temp_new(TCG_TYPE_I32);
706
707 /* old op:
708 if (!(env->y & 1))
709 T1 = 0;
710 */
711 tcg_gen_mov_tl(cpu_cc_src, src1);
712 tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
713 tcg_gen_trunc_tl_i32(r_temp2, r_temp);
714 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
715 tcg_gen_mov_tl(cpu_cc_src2, src2);
716 tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
717 tcg_gen_movi_tl(cpu_cc_src2, 0);
718 gen_set_label(l1);
719
720 // b2 = T0 & 1;
721 // env->y = (b2 << 31) | (env->y >> 1);
722 tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
723 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
724 tcg_gen_shli_i32(r_temp2, r_temp2, 31);
725 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
726 tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
727 tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
728 tcg_temp_free(r_temp2);
729 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
730
731 // b1 = N ^ V;
732 gen_mov_reg_N(cpu_tmp0, cpu_psr);
733 gen_mov_reg_V(r_temp, cpu_psr);
734 tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
735 tcg_temp_free(r_temp);
736
737 // T0 = (b1 << 31) | (T0 >> 1);
738 // src1 = T0;
739 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
740 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
741 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
742
743 /* do addition and update flags */
744 tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
745 tcg_gen_mov_tl(cpu_cc_dst, dst);
746
747 gen_cc_clear_icc();
748 gen_cc_NZ_icc(cpu_cc_dst);
749 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
750 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
751 }
752
753 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
754 {
755 TCGv r_temp, r_temp2;
756
757 r_temp = tcg_temp_new(TCG_TYPE_I64);
758 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
759
760 tcg_gen_extu_tl_i64(r_temp, src2);
761 tcg_gen_extu_tl_i64(r_temp2, src1);
762 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
763
764 tcg_gen_shri_i64(r_temp, r_temp2, 32);
765 tcg_gen_trunc_i64_i32(r_temp, r_temp);
766 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
767 tcg_temp_free(r_temp);
768 #ifdef TARGET_SPARC64
769 tcg_gen_mov_i64(dst, r_temp2);
770 #else
771 tcg_gen_trunc_i64_tl(dst, r_temp2);
772 #endif
773 tcg_temp_free(r_temp2);
774 }
775
776 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
777 {
778 TCGv r_temp, r_temp2;
779
780 r_temp = tcg_temp_new(TCG_TYPE_I64);
781 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
782
783 tcg_gen_ext_tl_i64(r_temp, src2);
784 tcg_gen_ext_tl_i64(r_temp2, src1);
785 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
786
787 tcg_gen_shri_i64(r_temp, r_temp2, 32);
788 tcg_gen_trunc_i64_i32(r_temp, r_temp);
789 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
790 tcg_temp_free(r_temp);
791 #ifdef TARGET_SPARC64
792 tcg_gen_mov_i64(dst, r_temp2);
793 #else
794 tcg_gen_trunc_i64_tl(dst, r_temp2);
795 #endif
796 tcg_temp_free(r_temp2);
797 }
798
799 #ifdef TARGET_SPARC64
800 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
801 {
802 TCGv r_const;
803 int l1;
804
805 l1 = gen_new_label();
806 tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
807 r_const = tcg_const_i32(TT_DIV_ZERO);
808 tcg_gen_helper_0_1(raise_exception, r_const);
809 tcg_temp_free(r_const);
810 gen_set_label(l1);
811 }
812
813 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
814 {
815 int l1, l2;
816
817 l1 = gen_new_label();
818 l2 = gen_new_label();
819 tcg_gen_mov_tl(cpu_cc_src, src1);
820 tcg_gen_mov_tl(cpu_cc_src2, src2);
821 gen_trap_ifdivzero_tl(src2);
822 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
823 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
824 tcg_gen_movi_i64(dst, INT64_MIN);
825 tcg_gen_br(l2);
826 gen_set_label(l1);
827 tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
828 gen_set_label(l2);
829 }
830 #endif
831
832 static inline void gen_op_div_cc(TCGv dst)
833 {
834 int l1;
835
836 tcg_gen_mov_tl(cpu_cc_dst, dst);
837 gen_cc_clear_icc();
838 gen_cc_NZ_icc(cpu_cc_dst);
839 l1 = gen_new_label();
840 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
841 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
842 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
843 gen_set_label(l1);
844 }
845
846 static inline void gen_op_logic_cc(TCGv dst)
847 {
848 tcg_gen_mov_tl(cpu_cc_dst, dst);
849
850 gen_cc_clear_icc();
851 gen_cc_NZ_icc(cpu_cc_dst);
852 #ifdef TARGET_SPARC64
853 gen_cc_clear_xcc();
854 gen_cc_NZ_xcc(cpu_cc_dst);
855 #endif
856 }
857
858 // 1
859 static inline void gen_op_eval_ba(TCGv dst)
860 {
861 tcg_gen_movi_tl(dst, 1);
862 }
863
864 // Z
865 static inline void gen_op_eval_be(TCGv dst, TCGv src)
866 {
867 gen_mov_reg_Z(dst, src);
868 }
869
870 // Z | (N ^ V)
871 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
872 {
873 gen_mov_reg_N(cpu_tmp0, src);
874 gen_mov_reg_V(dst, src);
875 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
876 gen_mov_reg_Z(cpu_tmp0, src);
877 tcg_gen_or_tl(dst, dst, cpu_tmp0);
878 }
879
880 // N ^ V
881 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
882 {
883 gen_mov_reg_V(cpu_tmp0, src);
884 gen_mov_reg_N(dst, src);
885 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
886 }
887
888 // C | Z
889 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
890 {
891 gen_mov_reg_Z(cpu_tmp0, src);
892 gen_mov_reg_C(dst, src);
893 tcg_gen_or_tl(dst, dst, cpu_tmp0);
894 }
895
896 // C
897 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
898 {
899 gen_mov_reg_C(dst, src);
900 }
901
902 // V
903 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
904 {
905 gen_mov_reg_V(dst, src);
906 }
907
908 // 0
909 static inline void gen_op_eval_bn(TCGv dst)
910 {
911 tcg_gen_movi_tl(dst, 0);
912 }
913
914 // N
915 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
916 {
917 gen_mov_reg_N(dst, src);
918 }
919
920 // !Z
921 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
922 {
923 gen_mov_reg_Z(dst, src);
924 tcg_gen_xori_tl(dst, dst, 0x1);
925 }
926
927 // !(Z | (N ^ V))
928 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
929 {
930 gen_mov_reg_N(cpu_tmp0, src);
931 gen_mov_reg_V(dst, src);
932 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
933 gen_mov_reg_Z(cpu_tmp0, src);
934 tcg_gen_or_tl(dst, dst, cpu_tmp0);
935 tcg_gen_xori_tl(dst, dst, 0x1);
936 }
937
938 // !(N ^ V)
939 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
940 {
941 gen_mov_reg_V(cpu_tmp0, src);
942 gen_mov_reg_N(dst, src);
943 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
944 tcg_gen_xori_tl(dst, dst, 0x1);
945 }
946
947 // !(C | Z)
948 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
949 {
950 gen_mov_reg_Z(cpu_tmp0, src);
951 gen_mov_reg_C(dst, src);
952 tcg_gen_or_tl(dst, dst, cpu_tmp0);
953 tcg_gen_xori_tl(dst, dst, 0x1);
954 }
955
956 // !C
957 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
958 {
959 gen_mov_reg_C(dst, src);
960 tcg_gen_xori_tl(dst, dst, 0x1);
961 }
962
963 // !N
964 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
965 {
966 gen_mov_reg_N(dst, src);
967 tcg_gen_xori_tl(dst, dst, 0x1);
968 }
969
970 // !V
971 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
972 {
973 gen_mov_reg_V(dst, src);
974 tcg_gen_xori_tl(dst, dst, 0x1);
975 }
976
977 /*
978 FPSR bit field FCC1 | FCC0:
979 0 =
980 1 <
981 2 >
982 3 unordered
983 */
984 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
985 unsigned int fcc_offset)
986 {
987 tcg_gen_extu_i32_tl(reg, src);
988 tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
989 tcg_gen_andi_tl(reg, reg, 0x1);
990 }
991
992 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
993 unsigned int fcc_offset)
994 {
995 tcg_gen_extu_i32_tl(reg, src);
996 tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
997 tcg_gen_andi_tl(reg, reg, 0x1);
998 }
999
1000 // !0: FCC0 | FCC1
1001 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1002 unsigned int fcc_offset)
1003 {
1004 gen_mov_reg_FCC0(dst, src, fcc_offset);
1005 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1006 tcg_gen_or_tl(dst, dst, cpu_tmp0);
1007 }
1008
1009 // 1 or 2: FCC0 ^ FCC1
1010 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1011 unsigned int fcc_offset)
1012 {
1013 gen_mov_reg_FCC0(dst, src, fcc_offset);
1014 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1015 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1016 }
1017
1018 // 1 or 3: FCC0
1019 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1020 unsigned int fcc_offset)
1021 {
1022 gen_mov_reg_FCC0(dst, src, fcc_offset);
1023 }
1024
1025 // 1: FCC0 & !FCC1
1026 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1027 unsigned int fcc_offset)
1028 {
1029 gen_mov_reg_FCC0(dst, src, fcc_offset);
1030 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1031 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1032 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1033 }
1034
1035 // 2 or 3: FCC1
1036 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1037 unsigned int fcc_offset)
1038 {
1039 gen_mov_reg_FCC1(dst, src, fcc_offset);
1040 }
1041
1042 // 2: !FCC0 & FCC1
1043 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1044 unsigned int fcc_offset)
1045 {
1046 gen_mov_reg_FCC0(dst, src, fcc_offset);
1047 tcg_gen_xori_tl(dst, dst, 0x1);
1048 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1049 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1050 }
1051
1052 // 3: FCC0 & FCC1
1053 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1054 unsigned int fcc_offset)
1055 {
1056 gen_mov_reg_FCC0(dst, src, fcc_offset);
1057 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1058 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1059 }
1060
1061 // 0: !(FCC0 | FCC1)
1062 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1063 unsigned int fcc_offset)
1064 {
1065 gen_mov_reg_FCC0(dst, src, fcc_offset);
1066 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1067 tcg_gen_or_tl(dst, dst, cpu_tmp0);
1068 tcg_gen_xori_tl(dst, dst, 0x1);
1069 }
1070
1071 // 0 or 3: !(FCC0 ^ FCC1)
1072 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1073 unsigned int fcc_offset)
1074 {
1075 gen_mov_reg_FCC0(dst, src, fcc_offset);
1076 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1077 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1078 tcg_gen_xori_tl(dst, dst, 0x1);
1079 }
1080
1081 // 0 or 2: !FCC0
1082 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1083 unsigned int fcc_offset)
1084 {
1085 gen_mov_reg_FCC0(dst, src, fcc_offset);
1086 tcg_gen_xori_tl(dst, dst, 0x1);
1087 }
1088
1089 // !1: !(FCC0 & !FCC1)
1090 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1091 unsigned int fcc_offset)
1092 {
1093 gen_mov_reg_FCC0(dst, src, fcc_offset);
1094 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1095 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1096 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1097 tcg_gen_xori_tl(dst, dst, 0x1);
1098 }
1099
1100 // 0 or 1: !FCC1
1101 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1102 unsigned int fcc_offset)
1103 {
1104 gen_mov_reg_FCC1(dst, src, fcc_offset);
1105 tcg_gen_xori_tl(dst, dst, 0x1);
1106 }
1107
1108 // !2: !(!FCC0 & FCC1)
1109 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1110 unsigned int fcc_offset)
1111 {
1112 gen_mov_reg_FCC0(dst, src, fcc_offset);
1113 tcg_gen_xori_tl(dst, dst, 0x1);
1114 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1115 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1116 tcg_gen_xori_tl(dst, dst, 0x1);
1117 }
1118
1119 // !3: !(FCC0 & FCC1)
1120 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1121 unsigned int fcc_offset)
1122 {
1123 gen_mov_reg_FCC0(dst, src, fcc_offset);
1124 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1125 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1126 tcg_gen_xori_tl(dst, dst, 0x1);
1127 }
1128
1129 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1130 target_ulong pc2, TCGv r_cond)
1131 {
1132 int l1;
1133
1134 l1 = gen_new_label();
1135
1136 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1137
1138 gen_goto_tb(dc, 0, pc1, pc1 + 4);
1139
1140 gen_set_label(l1);
1141 gen_goto_tb(dc, 1, pc2, pc2 + 4);
1142 }
1143
1144 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1145 target_ulong pc2, TCGv r_cond)
1146 {
1147 int l1;
1148
1149 l1 = gen_new_label();
1150
1151 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1152
1153 gen_goto_tb(dc, 0, pc2, pc1);
1154
1155 gen_set_label(l1);
1156 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1157 }
1158
1159 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1160 TCGv r_cond)
1161 {
1162 int l1, l2;
1163
1164 l1 = gen_new_label();
1165 l2 = gen_new_label();
1166
1167 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1168
1169 tcg_gen_movi_tl(cpu_npc, npc1);
1170 tcg_gen_br(l2);
1171
1172 gen_set_label(l1);
1173 tcg_gen_movi_tl(cpu_npc, npc2);
1174 gen_set_label(l2);
1175 }
1176
1177 /* call this function before using the condition register as it may
1178 have been set for a jump */
1179 static inline void flush_cond(DisasContext *dc, TCGv cond)
1180 {
1181 if (dc->npc == JUMP_PC) {
1182 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1183 dc->npc = DYNAMIC_PC;
1184 }
1185 }
1186
1187 static inline void save_npc(DisasContext *dc, TCGv cond)
1188 {
1189 if (dc->npc == JUMP_PC) {
1190 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1191 dc->npc = DYNAMIC_PC;
1192 } else if (dc->npc != DYNAMIC_PC) {
1193 tcg_gen_movi_tl(cpu_npc, dc->npc);
1194 }
1195 }
1196
1197 static inline void save_state(DisasContext *dc, TCGv cond)
1198 {
1199 tcg_gen_movi_tl(cpu_pc, dc->pc);
1200 save_npc(dc, cond);
1201 }
1202
1203 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1204 {
1205 if (dc->npc == JUMP_PC) {
1206 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1207 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1208 dc->pc = DYNAMIC_PC;
1209 } else if (dc->npc == DYNAMIC_PC) {
1210 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1211 dc->pc = DYNAMIC_PC;
1212 } else {
1213 dc->pc = dc->npc;
1214 }
1215 }
1216
1217 static inline void gen_op_next_insn(void)
1218 {
1219 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1220 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1221 }
1222
1223 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1224 {
1225 TCGv r_src;
1226
1227 #ifdef TARGET_SPARC64
1228 if (cc)
1229 r_src = cpu_xcc;
1230 else
1231 r_src = cpu_psr;
1232 #else
1233 r_src = cpu_psr;
1234 #endif
1235 switch (cond) {
1236 case 0x0:
1237 gen_op_eval_bn(r_dst);
1238 break;
1239 case 0x1:
1240 gen_op_eval_be(r_dst, r_src);
1241 break;
1242 case 0x2:
1243 gen_op_eval_ble(r_dst, r_src);
1244 break;
1245 case 0x3:
1246 gen_op_eval_bl(r_dst, r_src);
1247 break;
1248 case 0x4:
1249 gen_op_eval_bleu(r_dst, r_src);
1250 break;
1251 case 0x5:
1252 gen_op_eval_bcs(r_dst, r_src);
1253 break;
1254 case 0x6:
1255 gen_op_eval_bneg(r_dst, r_src);
1256 break;
1257 case 0x7:
1258 gen_op_eval_bvs(r_dst, r_src);
1259 break;
1260 case 0x8:
1261 gen_op_eval_ba(r_dst);
1262 break;
1263 case 0x9:
1264 gen_op_eval_bne(r_dst, r_src);
1265 break;
1266 case 0xa:
1267 gen_op_eval_bg(r_dst, r_src);
1268 break;
1269 case 0xb:
1270 gen_op_eval_bge(r_dst, r_src);
1271 break;
1272 case 0xc:
1273 gen_op_eval_bgu(r_dst, r_src);
1274 break;
1275 case 0xd:
1276 gen_op_eval_bcc(r_dst, r_src);
1277 break;
1278 case 0xe:
1279 gen_op_eval_bpos(r_dst, r_src);
1280 break;
1281 case 0xf:
1282 gen_op_eval_bvc(r_dst, r_src);
1283 break;
1284 }
1285 }
1286
1287 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1288 {
1289 unsigned int offset;
1290
1291 switch (cc) {
1292 default:
1293 case 0x0:
1294 offset = 0;
1295 break;
1296 case 0x1:
1297 offset = 32 - 10;
1298 break;
1299 case 0x2:
1300 offset = 34 - 10;
1301 break;
1302 case 0x3:
1303 offset = 36 - 10;
1304 break;
1305 }
1306
1307 switch (cond) {
1308 case 0x0:
1309 gen_op_eval_bn(r_dst);
1310 break;
1311 case 0x1:
1312 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1313 break;
1314 case 0x2:
1315 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1316 break;
1317 case 0x3:
1318 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1319 break;
1320 case 0x4:
1321 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1322 break;
1323 case 0x5:
1324 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1325 break;
1326 case 0x6:
1327 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1328 break;
1329 case 0x7:
1330 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1331 break;
1332 case 0x8:
1333 gen_op_eval_ba(r_dst);
1334 break;
1335 case 0x9:
1336 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1337 break;
1338 case 0xa:
1339 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1340 break;
1341 case 0xb:
1342 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1343 break;
1344 case 0xc:
1345 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1346 break;
1347 case 0xd:
1348 gen_op_eval_fble(r_dst, cpu_fsr, offset);
1349 break;
1350 case 0xe:
1351 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1352 break;
1353 case 0xf:
1354 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1355 break;
1356 }
1357 }
1358
1359 #ifdef TARGET_SPARC64
1360 // Inverted logic
1361 static const int gen_tcg_cond_reg[8] = {
1362 -1,
1363 TCG_COND_NE,
1364 TCG_COND_GT,
1365 TCG_COND_GE,
1366 -1,
1367 TCG_COND_EQ,
1368 TCG_COND_LE,
1369 TCG_COND_LT,
1370 };
1371
1372 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1373 {
1374 int l1;
1375
1376 l1 = gen_new_label();
1377 tcg_gen_movi_tl(r_dst, 0);
1378 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1379 tcg_gen_movi_tl(r_dst, 1);
1380 gen_set_label(l1);
1381 }
1382 #endif
1383
1384 /* XXX: potentially incorrect if dynamic npc */
1385 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1386 TCGv r_cond)
1387 {
1388 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1389 target_ulong target = dc->pc + offset;
1390
1391 if (cond == 0x0) {
1392 /* unconditional not taken */
1393 if (a) {
1394 dc->pc = dc->npc + 4;
1395 dc->npc = dc->pc + 4;
1396 } else {
1397 dc->pc = dc->npc;
1398 dc->npc = dc->pc + 4;
1399 }
1400 } else if (cond == 0x8) {
1401 /* unconditional taken */
1402 if (a) {
1403 dc->pc = target;
1404 dc->npc = dc->pc + 4;
1405 } else {
1406 dc->pc = dc->npc;
1407 dc->npc = target;
1408 }
1409 } else {
1410 flush_cond(dc, r_cond);
1411 gen_cond(r_cond, cc, cond);
1412 if (a) {
1413 gen_branch_a(dc, target, dc->npc, r_cond);
1414 dc->is_br = 1;
1415 } else {
1416 dc->pc = dc->npc;
1417 dc->jump_pc[0] = target;
1418 dc->jump_pc[1] = dc->npc + 4;
1419 dc->npc = JUMP_PC;
1420 }
1421 }
1422 }
1423
1424 /* XXX: potentially incorrect if dynamic npc */
1425 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1426 TCGv r_cond)
1427 {
1428 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1429 target_ulong target = dc->pc + offset;
1430
1431 if (cond == 0x0) {
1432 /* unconditional not taken */
1433 if (a) {
1434 dc->pc = dc->npc + 4;
1435 dc->npc = dc->pc + 4;
1436 } else {
1437 dc->pc = dc->npc;
1438 dc->npc = dc->pc + 4;
1439 }
1440 } else if (cond == 0x8) {
1441 /* unconditional taken */
1442 if (a) {
1443 dc->pc = target;
1444 dc->npc = dc->pc + 4;
1445 } else {
1446 dc->pc = dc->npc;
1447 dc->npc = target;
1448 }
1449 } else {
1450 flush_cond(dc, r_cond);
1451 gen_fcond(r_cond, cc, cond);
1452 if (a) {
1453 gen_branch_a(dc, target, dc->npc, r_cond);
1454 dc->is_br = 1;
1455 } else {
1456 dc->pc = dc->npc;
1457 dc->jump_pc[0] = target;
1458 dc->jump_pc[1] = dc->npc + 4;
1459 dc->npc = JUMP_PC;
1460 }
1461 }
1462 }
1463
1464 #ifdef TARGET_SPARC64
1465 /* XXX: potentially incorrect if dynamic npc */
1466 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1467 TCGv r_cond, TCGv r_reg)
1468 {
1469 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1470 target_ulong target = dc->pc + offset;
1471
1472 flush_cond(dc, r_cond);
1473 gen_cond_reg(r_cond, cond, r_reg);
1474 if (a) {
1475 gen_branch_a(dc, target, dc->npc, r_cond);
1476 dc->is_br = 1;
1477 } else {
1478 dc->pc = dc->npc;
1479 dc->jump_pc[0] = target;
1480 dc->jump_pc[1] = dc->npc + 4;
1481 dc->npc = JUMP_PC;
1482 }
1483 }
1484
1485 static GenOpFunc * const gen_fcmps[4] = {
1486 helper_fcmps,
1487 helper_fcmps_fcc1,
1488 helper_fcmps_fcc2,
1489 helper_fcmps_fcc3,
1490 };
1491
1492 static GenOpFunc * const gen_fcmpd[4] = {
1493 helper_fcmpd,
1494 helper_fcmpd_fcc1,
1495 helper_fcmpd_fcc2,
1496 helper_fcmpd_fcc3,
1497 };
1498
1499 static GenOpFunc * const gen_fcmpq[4] = {
1500 helper_fcmpq,
1501 helper_fcmpq_fcc1,
1502 helper_fcmpq_fcc2,
1503 helper_fcmpq_fcc3,
1504 };
1505
1506 static GenOpFunc * const gen_fcmpes[4] = {
1507 helper_fcmpes,
1508 helper_fcmpes_fcc1,
1509 helper_fcmpes_fcc2,
1510 helper_fcmpes_fcc3,
1511 };
1512
1513 static GenOpFunc * const gen_fcmped[4] = {
1514 helper_fcmped,
1515 helper_fcmped_fcc1,
1516 helper_fcmped_fcc2,
1517 helper_fcmped_fcc3,
1518 };
1519
1520 static GenOpFunc * const gen_fcmpeq[4] = {
1521 helper_fcmpeq,
1522 helper_fcmpeq_fcc1,
1523 helper_fcmpeq_fcc2,
1524 helper_fcmpeq_fcc3,
1525 };
1526
1527 static inline void gen_op_fcmps(int fccno)
1528 {
1529 tcg_gen_helper_0_0(gen_fcmps[fccno]);
1530 }
1531
1532 static inline void gen_op_fcmpd(int fccno)
1533 {
1534 tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1535 }
1536
1537 static inline void gen_op_fcmpq(int fccno)
1538 {
1539 tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1540 }
1541
1542 static inline void gen_op_fcmpes(int fccno)
1543 {
1544 tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1545 }
1546
1547 static inline void gen_op_fcmped(int fccno)
1548 {
1549 tcg_gen_helper_0_0(gen_fcmped[fccno]);
1550 }
1551
1552 static inline void gen_op_fcmpeq(int fccno)
1553 {
1554 tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1555 }
1556
1557 #else
1558
1559 static inline void gen_op_fcmps(int fccno)
1560 {
1561 tcg_gen_helper_0_0(helper_fcmps);
1562 }
1563
1564 static inline void gen_op_fcmpd(int fccno)
1565 {
1566 tcg_gen_helper_0_0(helper_fcmpd);
1567 }
1568
1569 static inline void gen_op_fcmpq(int fccno)
1570 {
1571 tcg_gen_helper_0_0(helper_fcmpq);
1572 }
1573
1574 static inline void gen_op_fcmpes(int fccno)
1575 {
1576 tcg_gen_helper_0_0(helper_fcmpes);
1577 }
1578
1579 static inline void gen_op_fcmped(int fccno)
1580 {
1581 tcg_gen_helper_0_0(helper_fcmped);
1582 }
1583
1584 static inline void gen_op_fcmpeq(int fccno)
1585 {
1586 tcg_gen_helper_0_0(helper_fcmpeq);
1587 }
1588 #endif
1589
1590 static inline void gen_op_fpexception_im(int fsr_flags)
1591 {
1592 TCGv r_const;
1593
1594 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1595 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1596 r_const = tcg_const_i32(TT_FP_EXCP);
1597 tcg_gen_helper_0_1(raise_exception, r_const);
1598 tcg_temp_free(r_const);
1599 }
1600
1601 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1602 {
1603 #if !defined(CONFIG_USER_ONLY)
1604 if (!dc->fpu_enabled) {
1605 TCGv r_const;
1606
1607 save_state(dc, r_cond);
1608 r_const = tcg_const_i32(TT_NFPU_INSN);
1609 tcg_gen_helper_0_1(raise_exception, r_const);
1610 tcg_temp_free(r_const);
1611 dc->is_br = 1;
1612 return 1;
1613 }
1614 #endif
1615 return 0;
1616 }
1617
1618 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1619 {
1620 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1621 }
1622
1623 static inline void gen_clear_float_exceptions(void)
1624 {
1625 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1626 }
1627
1628 /* asi moves */
1629 #ifdef TARGET_SPARC64
1630 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1631 {
1632 int asi, offset;
1633 TCGv r_asi;
1634
1635 if (IS_IMM) {
1636 r_asi = tcg_temp_new(TCG_TYPE_I32);
1637 offset = GET_FIELD(insn, 25, 31);
1638 tcg_gen_addi_tl(r_addr, r_addr, offset);
1639 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1640 } else {
1641 asi = GET_FIELD(insn, 19, 26);
1642 r_asi = tcg_const_i32(asi);
1643 }
1644 return r_asi;
1645 }
1646
1647 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1648 int sign)
1649 {
1650 TCGv r_asi, r_size, r_sign;
1651
1652 r_asi = gen_get_asi(insn, addr);
1653 r_size = tcg_const_i32(size);
1654 r_sign = tcg_const_i32(sign);
1655 tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1656 tcg_temp_free(r_sign);
1657 tcg_temp_free(r_size);
1658 tcg_temp_free(r_asi);
1659 }
1660
1661 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1662 {
1663 TCGv r_asi, r_size;
1664
1665 r_asi = gen_get_asi(insn, addr);
1666 r_size = tcg_const_i32(size);
1667 tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1668 tcg_temp_free(r_size);
1669 tcg_temp_free(r_asi);
1670 }
1671
1672 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1673 {
1674 TCGv r_asi, r_size, r_rd;
1675
1676 r_asi = gen_get_asi(insn, addr);
1677 r_size = tcg_const_i32(size);
1678 r_rd = tcg_const_i32(rd);
1679 tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1680 tcg_temp_free(r_rd);
1681 tcg_temp_free(r_size);
1682 tcg_temp_free(r_asi);
1683 }
1684
1685 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1686 {
1687 TCGv r_asi, r_size, r_rd;
1688
1689 r_asi = gen_get_asi(insn, addr);
1690 r_size = tcg_const_i32(size);
1691 r_rd = tcg_const_i32(rd);
1692 tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1693 tcg_temp_free(r_rd);
1694 tcg_temp_free(r_size);
1695 tcg_temp_free(r_asi);
1696 }
1697
1698 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1699 {
1700 TCGv r_asi, r_size, r_sign;
1701
1702 r_asi = gen_get_asi(insn, addr);
1703 r_size = tcg_const_i32(4);
1704 r_sign = tcg_const_i32(0);
1705 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1706 tcg_temp_free(r_sign);
1707 tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1708 tcg_temp_free(r_size);
1709 tcg_temp_free(r_asi);
1710 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1711 }
1712
1713 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1714 {
1715 TCGv r_asi, r_size, r_sign;
1716
1717 r_asi = gen_get_asi(insn, addr);
1718 r_size = tcg_const_i32(8);
1719 r_sign = tcg_const_i32(0);
1720 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1721 tcg_temp_free(r_sign);
1722 tcg_temp_free(r_size);
1723 tcg_temp_free(r_asi);
1724 tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1725 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1726 tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1727 }
1728
1729 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1730 {
1731 TCGv r_temp, r_asi, r_size;
1732
1733 r_temp = tcg_temp_new(TCG_TYPE_TL);
1734 gen_movl_reg_TN(rd + 1, r_temp);
1735 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1736 r_temp);
1737 tcg_temp_free(r_temp);
1738 r_asi = gen_get_asi(insn, addr);
1739 r_size = tcg_const_i32(8);
1740 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1741 tcg_temp_free(r_size);
1742 tcg_temp_free(r_asi);
1743 }
1744
1745 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1746 int rd)
1747 {
1748 TCGv r_val1, r_asi;
1749
1750 r_val1 = tcg_temp_new(TCG_TYPE_TL);
1751 gen_movl_reg_TN(rd, r_val1);
1752 r_asi = gen_get_asi(insn, addr);
1753 tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1754 tcg_temp_free(r_asi);
1755 tcg_temp_free(r_val1);
1756 }
1757
1758 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1759 int rd)
1760 {
1761 TCGv r_asi;
1762
1763 gen_movl_reg_TN(rd, cpu_tmp64);
1764 r_asi = gen_get_asi(insn, addr);
1765 tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1766 tcg_temp_free(r_asi);
1767 }
1768
1769 #elif !defined(CONFIG_USER_ONLY)
1770
1771 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1772 int sign)
1773 {
1774 TCGv r_asi, r_size, r_sign;
1775
1776 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1777 r_size = tcg_const_i32(size);
1778 r_sign = tcg_const_i32(sign);
1779 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1780 tcg_temp_free(r_sign);
1781 tcg_temp_free(r_size);
1782 tcg_temp_free(r_asi);
1783 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1784 }
1785
1786 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1787 {
1788 TCGv r_asi, r_size;
1789
1790 tcg_gen_extu_tl_i64(cpu_tmp64, src);
1791 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1792 r_size = tcg_const_i32(size);
1793 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1794 tcg_temp_free(r_size);
1795 tcg_temp_free(r_asi);
1796 }
1797
1798 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1799 {
1800 TCGv r_asi, r_size, r_sign;
1801
1802 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1803 r_size = tcg_const_i32(4);
1804 r_sign = tcg_const_i32(0);
1805 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1806 tcg_temp_free(r_sign);
1807 tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1808 tcg_temp_free(r_size);
1809 tcg_temp_free(r_asi);
1810 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1811 }
1812
1813 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1814 {
1815 TCGv r_asi, r_size, r_sign;
1816
1817 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1818 r_size = tcg_const_i32(8);
1819 r_sign = tcg_const_i32(0);
1820 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1821 tcg_temp_free(r_sign);
1822 tcg_temp_free(r_size);
1823 tcg_temp_free(r_asi);
1824 tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1825 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1826 tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1827 }
1828
1829 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1830 {
1831 TCGv r_temp, r_asi, r_size;
1832
1833 r_temp = tcg_temp_new(TCG_TYPE_TL);
1834 gen_movl_reg_TN(rd + 1, r_temp);
1835 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1836 tcg_temp_free(r_temp);
1837 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1838 r_size = tcg_const_i32(8);
1839 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1840 tcg_temp_free(r_size);
1841 tcg_temp_free(r_asi);
1842 }
1843 #endif
1844
1845 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1846 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1847 {
1848 TCGv r_val, r_asi, r_size;
1849
1850 gen_ld_asi(dst, addr, insn, 1, 0);
1851
1852 r_val = tcg_const_i64(0xffULL);
1853 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1854 r_size = tcg_const_i32(1);
1855 tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1856 tcg_temp_free(r_size);
1857 tcg_temp_free(r_asi);
1858 tcg_temp_free(r_val);
1859 }
1860 #endif
1861
1862 static inline TCGv get_src1(unsigned int insn, TCGv def)
1863 {
1864 TCGv r_rs1 = def;
1865 unsigned int rs1;
1866
1867 rs1 = GET_FIELD(insn, 13, 17);
1868 if (rs1 == 0)
1869 //r_rs1 = tcg_const_tl(0);
1870 tcg_gen_movi_tl(def, 0);
1871 else if (rs1 < 8)
1872 //r_rs1 = cpu_gregs[rs1];
1873 tcg_gen_mov_tl(def, cpu_gregs[rs1]);
1874 else
1875 tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1876 return r_rs1;
1877 }
1878
1879 static inline TCGv get_src2(unsigned int insn, TCGv def)
1880 {
1881 TCGv r_rs2 = def;
1882 unsigned int rs2;
1883
1884 if (IS_IMM) { /* immediate */
1885 rs2 = GET_FIELDs(insn, 19, 31);
1886 r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1887 } else { /* register */
1888 rs2 = GET_FIELD(insn, 27, 31);
1889 if (rs2 == 0)
1890 r_rs2 = tcg_const_tl(0); // XXX how to free?
1891 else if (rs2 < 8)
1892 r_rs2 = cpu_gregs[rs2];
1893 else
1894 tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1895 }
1896 return r_rs2;
1897 }
1898
1899 #define CHECK_IU_FEATURE(dc, FEATURE) \
1900 if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
1901 goto illegal_insn;
1902 #define CHECK_FPU_FEATURE(dc, FEATURE) \
1903 if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
1904 goto nfpu_insn;
1905
1906 /* before an instruction, dc->pc must be static */
1907 static void disas_sparc_insn(DisasContext * dc)
1908 {
1909 unsigned int insn, opc, rs1, rs2, rd;
1910
1911 if (unlikely(loglevel & CPU_LOG_TB_OP))
1912 tcg_gen_debug_insn_start(dc->pc);
1913 insn = ldl_code(dc->pc);
1914 opc = GET_FIELD(insn, 0, 1);
1915
1916 rd = GET_FIELD(insn, 2, 6);
1917
1918 cpu_dst = cpu_T[0];
1919 cpu_src1 = cpu_T[0]; // const
1920 cpu_src2 = cpu_T[1]; // const
1921
1922 // loads and stores
1923 cpu_addr = cpu_T[0];
1924 cpu_val = cpu_T[1];
1925
1926 switch (opc) {
1927 case 0: /* branches/sethi */
1928 {
1929 unsigned int xop = GET_FIELD(insn, 7, 9);
1930 int32_t target;
1931 switch (xop) {
1932 #ifdef TARGET_SPARC64
1933 case 0x1: /* V9 BPcc */
1934 {
1935 int cc;
1936
1937 target = GET_FIELD_SP(insn, 0, 18);
1938 target = sign_extend(target, 18);
1939 target <<= 2;
1940 cc = GET_FIELD_SP(insn, 20, 21);
1941 if (cc == 0)
1942 do_branch(dc, target, insn, 0, cpu_cond);
1943 else if (cc == 2)
1944 do_branch(dc, target, insn, 1, cpu_cond);
1945 else
1946 goto illegal_insn;
1947 goto jmp_insn;
1948 }
1949 case 0x3: /* V9 BPr */
1950 {
1951 target = GET_FIELD_SP(insn, 0, 13) |
1952 (GET_FIELD_SP(insn, 20, 21) << 14);
1953 target = sign_extend(target, 16);
1954 target <<= 2;
1955 cpu_src1 = get_src1(insn, cpu_src1);
1956 do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1957 goto jmp_insn;
1958 }
1959 case 0x5: /* V9 FBPcc */
1960 {
1961 int cc = GET_FIELD_SP(insn, 20, 21);
1962 if (gen_trap_ifnofpu(dc, cpu_cond))
1963 goto jmp_insn;
1964 target = GET_FIELD_SP(insn, 0, 18);
1965 target = sign_extend(target, 19);
1966 target <<= 2;
1967 do_fbranch(dc, target, insn, cc, cpu_cond);
1968 goto jmp_insn;
1969 }
1970 #else
1971 case 0x7: /* CBN+x */
1972 {
1973 goto ncp_insn;
1974 }
1975 #endif
1976 case 0x2: /* BN+x */
1977 {
1978 target = GET_FIELD(insn, 10, 31);
1979 target = sign_extend(target, 22);
1980 target <<= 2;
1981 do_branch(dc, target, insn, 0, cpu_cond);
1982 goto jmp_insn;
1983 }
1984 case 0x6: /* FBN+x */
1985 {
1986 if (gen_trap_ifnofpu(dc, cpu_cond))
1987 goto jmp_insn;
1988 target = GET_FIELD(insn, 10, 31);
1989 target = sign_extend(target, 22);
1990 target <<= 2;
1991 do_fbranch(dc, target, insn, 0, cpu_cond);
1992 goto jmp_insn;
1993 }
1994 case 0x4: /* SETHI */
1995 if (rd) { // nop
1996 uint32_t value = GET_FIELD(insn, 10, 31);
1997 TCGv r_const;
1998
1999 r_const = tcg_const_tl(value << 10);
2000 gen_movl_TN_reg(rd, r_const);
2001 tcg_temp_free(r_const);
2002 }
2003 break;
2004 case 0x0: /* UNIMPL */
2005 default:
2006 goto illegal_insn;
2007 }
2008 break;
2009 }
2010 break;
2011 case 1:
2012 /*CALL*/ {
2013 target_long target = GET_FIELDs(insn, 2, 31) << 2;
2014 TCGv r_const;
2015
2016 r_const = tcg_const_tl(dc->pc);
2017 gen_movl_TN_reg(15, r_const);
2018 tcg_temp_free(r_const);
2019 target += dc->pc;
2020 gen_mov_pc_npc(dc, cpu_cond);
2021 dc->npc = target;
2022 }
2023 goto jmp_insn;
2024 case 2: /* FPU & Logical Operations */
2025 {
2026 unsigned int xop = GET_FIELD(insn, 7, 12);
2027 if (xop == 0x3a) { /* generate trap */
2028 int cond;
2029
2030 cpu_src1 = get_src1(insn, cpu_src1);
2031 if (IS_IMM) {
2032 rs2 = GET_FIELD(insn, 25, 31);
2033 tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2034 } else {
2035 rs2 = GET_FIELD(insn, 27, 31);
2036 if (rs2 != 0) {
2037 gen_movl_reg_TN(rs2, cpu_src2);
2038 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2039 } else
2040 tcg_gen_mov_tl(cpu_dst, cpu_src1);
2041 }
2042 cond = GET_FIELD(insn, 3, 6);
2043 if (cond == 0x8) {
2044 save_state(dc, cpu_cond);
2045 tcg_gen_helper_0_1(helper_trap, cpu_dst);
2046 } else if (cond != 0) {
2047 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2048 #ifdef TARGET_SPARC64
2049 /* V9 icc/xcc */
2050 int cc = GET_FIELD_SP(insn, 11, 12);
2051
2052 save_state(dc, cpu_cond);
2053 if (cc == 0)
2054 gen_cond(r_cond, 0, cond);
2055 else if (cc == 2)
2056 gen_cond(r_cond, 1, cond);
2057 else
2058 goto illegal_insn;
2059 #else
2060 save_state(dc, cpu_cond);
2061 gen_cond(r_cond, 0, cond);
2062 #endif
2063 tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2064 tcg_temp_free(r_cond);
2065 }
2066 gen_op_next_insn();
2067 tcg_gen_exit_tb(0);
2068 dc->is_br = 1;
2069 goto jmp_insn;
2070 } else if (xop == 0x28) {
2071 rs1 = GET_FIELD(insn, 13, 17);
2072 switch(rs1) {
2073 case 0: /* rdy */
2074 #ifndef TARGET_SPARC64
2075 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2076 manual, rdy on the microSPARC
2077 II */
2078 case 0x0f: /* stbar in the SPARCv8 manual,
2079 rdy on the microSPARC II */
2080 case 0x10 ... 0x1f: /* implementation-dependent in the
2081 SPARCv8 manual, rdy on the
2082 microSPARC II */
2083 #endif
2084 tcg_gen_ld_tl(cpu_dst, cpu_env,
2085 offsetof(CPUSPARCState, y));
2086 gen_movl_TN_reg(rd, cpu_dst);
2087 break;
2088 #ifdef TARGET_SPARC64
2089 case 0x2: /* V9 rdccr */
2090 tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2091 gen_movl_TN_reg(rd, cpu_dst);
2092 break;
2093 case 0x3: /* V9 rdasi */
2094 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2095 offsetof(CPUSPARCState, asi));
2096 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2097 gen_movl_TN_reg(rd, cpu_dst);
2098 break;
2099 case 0x4: /* V9 rdtick */
2100 {
2101 TCGv r_tickptr;
2102
2103 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2104 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2105 offsetof(CPUState, tick));
2106 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2107 r_tickptr);
2108 tcg_temp_free(r_tickptr);
2109 gen_movl_TN_reg(rd, cpu_dst);
2110 }
2111 break;
2112 case 0x5: /* V9 rdpc */
2113 {
2114 TCGv r_const;
2115
2116 r_const = tcg_const_tl(dc->pc);
2117 gen_movl_TN_reg(rd, r_const);
2118 tcg_temp_free(r_const);
2119 }
2120 break;
2121 case 0x6: /* V9 rdfprs */
2122 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2123 offsetof(CPUSPARCState, fprs));
2124 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2125 gen_movl_TN_reg(rd, cpu_dst);
2126 break;
2127 case 0xf: /* V9 membar */
2128 break; /* no effect */
2129 case 0x13: /* Graphics Status */
2130 if (gen_trap_ifnofpu(dc, cpu_cond))
2131 goto jmp_insn;
2132 tcg_gen_ld_tl(cpu_dst, cpu_env,
2133 offsetof(CPUSPARCState, gsr));
2134 gen_movl_TN_reg(rd, cpu_dst);
2135 break;
2136 case 0x17: /* Tick compare */
2137 tcg_gen_ld_tl(cpu_dst, cpu_env,
2138 offsetof(CPUSPARCState, tick_cmpr));
2139 gen_movl_TN_reg(rd, cpu_dst);
2140 break;
2141 case 0x18: /* System tick */
2142 {
2143 TCGv r_tickptr;
2144
2145 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2146 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2147 offsetof(CPUState, stick));
2148 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2149 r_tickptr);
2150 tcg_temp_free(r_tickptr);
2151 gen_movl_TN_reg(rd, cpu_dst);
2152 }
2153 break;
2154 case 0x19: /* System tick compare */
2155 tcg_gen_ld_tl(cpu_dst, cpu_env,
2156 offsetof(CPUSPARCState, stick_cmpr));
2157 gen_movl_TN_reg(rd, cpu_dst);
2158 break;
2159 case 0x10: /* Performance Control */
2160 case 0x11: /* Performance Instrumentation Counter */
2161 case 0x12: /* Dispatch Control */
2162 case 0x14: /* Softint set, WO */
2163 case 0x15: /* Softint clear, WO */
2164 case 0x16: /* Softint write */
2165 #endif
2166 default:
2167 goto illegal_insn;
2168 }
2169 #if !defined(CONFIG_USER_ONLY)
2170 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2171 #ifndef TARGET_SPARC64
2172 if (!supervisor(dc))
2173 goto priv_insn;
2174 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2175 #else
2176 if (!hypervisor(dc))
2177 goto priv_insn;
2178 rs1 = GET_FIELD(insn, 13, 17);
2179 switch (rs1) {
2180 case 0: // hpstate
2181 // gen_op_rdhpstate();
2182 break;
2183 case 1: // htstate
2184 // gen_op_rdhtstate();
2185 break;
2186 case 3: // hintp
2187 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2188 offsetof(CPUSPARCState, hintp));
2189 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2190 break;
2191 case 5: // htba
2192 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2193 offsetof(CPUSPARCState, htba));
2194 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2195 break;
2196 case 6: // hver
2197 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2198 offsetof(CPUSPARCState, hver));
2199 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2200 break;
2201 case 31: // hstick_cmpr
2202 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2203 tcg_gen_st_i32(cpu_tmp32, cpu_env,
2204 offsetof(CPUSPARCState, hstick_cmpr));
2205 break;
2206 default:
2207 goto illegal_insn;
2208 }
2209 #endif
2210 gen_movl_TN_reg(rd, cpu_dst);
2211 break;
2212 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2213 if (!supervisor(dc))
2214 goto priv_insn;
2215 #ifdef TARGET_SPARC64
2216 rs1 = GET_FIELD(insn, 13, 17);
2217 switch (rs1) {
2218 case 0: // tpc
2219 {
2220 TCGv r_tsptr;
2221
2222 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2223 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2224 offsetof(CPUState, tsptr));
2225 tcg_gen_ld_tl(cpu_dst, r_tsptr,
2226 offsetof(trap_state, tpc));
2227 tcg_temp_free(r_tsptr);
2228 }
2229 break;
2230 case 1: // tnpc
2231 {
2232 TCGv r_tsptr;
2233
2234 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2235 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2236 offsetof(CPUState, tsptr));
2237 tcg_gen_ld_tl(cpu_dst, r_tsptr,
2238 offsetof(trap_state, tnpc));
2239 tcg_temp_free(r_tsptr);
2240 }
2241 break;
2242 case 2: // tstate
2243 {
2244 TCGv r_tsptr;
2245
2246 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2247 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2248 offsetof(CPUState, tsptr));
2249 tcg_gen_ld_tl(cpu_dst, r_tsptr,
2250 offsetof(trap_state, tstate));
2251 tcg_temp_free(r_tsptr);
2252 }
2253 break;
2254 case 3: // tt
2255 {
2256 TCGv r_tsptr;
2257
2258 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2259 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2260 offsetof(CPUState, tsptr));
2261 tcg_gen_ld_i32(cpu_dst, r_tsptr,
2262 offsetof(trap_state, tt));
2263 tcg_temp_free(r_tsptr);
2264 }
2265 break;
2266 case 4: // tick
2267 {
2268 TCGv r_tickptr;
2269
2270 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2271 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2272 offsetof(CPUState, tick));
2273 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2274 r_tickptr);
2275 gen_movl_TN_reg(rd, cpu_dst);
2276 tcg_temp_free(r_tickptr);
2277 }
2278 break;
2279 case 5: // tba
2280 tcg_gen_ld_tl(cpu_dst, cpu_env,
2281 offsetof(CPUSPARCState, tbr));
2282 break;
2283 case 6: // pstate
2284 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2285 offsetof(CPUSPARCState, pstate));
2286 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2287 break;
2288 case 7: // tl
2289 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2290 offsetof(CPUSPARCState, tl));
2291 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2292 break;
2293 case 8: // pil
2294 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2295 offsetof(CPUSPARCState, psrpil));
2296 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2297 break;
2298 case 9: // cwp
2299 tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
2300 break;
2301 case 10: // cansave
2302 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2303 offsetof(CPUSPARCState, cansave));
2304 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2305 break;
2306 case 11: // canrestore
2307 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2308 offsetof(CPUSPARCState, canrestore));
2309 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2310 break;
2311 case 12: // cleanwin
2312 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2313 offsetof(CPUSPARCState, cleanwin));
2314 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2315 break;
2316 case 13: // otherwin
2317 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2318 offsetof(CPUSPARCState, otherwin));
2319 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2320 break;
2321 case 14: // wstate
2322 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2323 offsetof(CPUSPARCState, wstate));
2324 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2325 break;
2326 case 16: // UA2005 gl
2327 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2328 offsetof(CPUSPARCState, gl));
2329 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2330 break;
2331 case 26: // UA2005 strand status
2332 if (!hypervisor(dc))
2333 goto priv_insn;
2334 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2335 offsetof(CPUSPARCState, ssr));
2336 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2337 break;
2338 case 31: // ver
2339 tcg_gen_ld_tl(cpu_dst, cpu_env,
2340 offsetof(CPUSPARCState, version));
2341 break;
2342 case 15: // fq
2343 default:
2344 goto illegal_insn;
2345 }
2346 #else
2347 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2348 offsetof(CPUSPARCState, wim));
2349 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2350 #endif
2351 gen_movl_TN_reg(rd, cpu_dst);
2352 break;
2353 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2354 #ifdef TARGET_SPARC64
2355 tcg_gen_helper_0_0(helper_flushw);
2356 #else
2357 if (!supervisor(dc))
2358 goto priv_insn;
2359 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2360 gen_movl_TN_reg(rd, cpu_dst);
2361 #endif
2362 break;
2363 #endif
2364 } else if (xop == 0x34) { /* FPU Operations */
2365 if (gen_trap_ifnofpu(dc, cpu_cond))
2366 goto jmp_insn;
2367 gen_op_clear_ieee_excp_and_FTT();
2368 rs1 = GET_FIELD(insn, 13, 17);
2369 rs2 = GET_FIELD(insn, 27, 31);
2370 xop = GET_FIELD(insn, 18, 26);
2371 switch (xop) {
2372 case 0x1: /* fmovs */
2373 gen_op_load_fpr_FT0(rs2);
2374 gen_op_store_FT0_fpr(rd);
2375 break;
2376 case 0x5: /* fnegs */
2377 gen_op_load_fpr_FT1(rs2);
2378 tcg_gen_helper_0_0(helper_fnegs);
2379 gen_op_store_FT0_fpr(rd);
2380 break;
2381 case 0x9: /* fabss */
2382 gen_op_load_fpr_FT1(rs2);
2383 tcg_gen_helper_0_0(helper_fabss);
2384 gen_op_store_FT0_fpr(rd);
2385 break;
2386 case 0x29: /* fsqrts */
2387 CHECK_FPU_FEATURE(dc, FSQRT);
2388 gen_op_load_fpr_FT1(rs2);
2389 gen_clear_float_exceptions();
2390 tcg_gen_helper_0_0(helper_fsqrts);
2391 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2392 gen_op_store_FT0_fpr(rd);
2393 break;
2394 case 0x2a: /* fsqrtd */
2395 CHECK_FPU_FEATURE(dc, FSQRT);
2396 gen_op_load_fpr_DT1(DFPREG(rs2));
2397 gen_clear_float_exceptions();
2398 tcg_gen_helper_0_0(helper_fsqrtd);
2399 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2400 gen_op_store_DT0_fpr(DFPREG(rd));
2401 break;
2402 case 0x2b: /* fsqrtq */
2403 CHECK_FPU_FEATURE(dc, FLOAT128);
2404 gen_op_load_fpr_QT1(QFPREG(rs2));
2405 gen_clear_float_exceptions();
2406 tcg_gen_helper_0_0(helper_fsqrtq);
2407 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2408 gen_op_store_QT0_fpr(QFPREG(rd));
2409 break;
2410 case 0x41:
2411 gen_op_load_fpr_FT0(rs1);
2412 gen_op_load_fpr_FT1(rs2);
2413 gen_clear_float_exceptions();
2414 tcg_gen_helper_0_0(helper_fadds);
2415 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2416 gen_op_store_FT0_fpr(rd);
2417 break;
2418 case 0x42:
2419 gen_op_load_fpr_DT0(DFPREG(rs1));
2420 gen_op_load_fpr_DT1(DFPREG(rs2));
2421 gen_clear_float_exceptions();
2422 tcg_gen_helper_0_0(helper_faddd);
2423 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2424 gen_op_store_DT0_fpr(DFPREG(rd));
2425 break;
2426 case 0x43: /* faddq */
2427 CHECK_FPU_FEATURE(dc, FLOAT128);
2428 gen_op_load_fpr_QT0(QFPREG(rs1));
2429 gen_op_load_fpr_QT1(QFPREG(rs2));
2430 gen_clear_float_exceptions();
2431 tcg_gen_helper_0_0(helper_faddq);
2432 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2433 gen_op_store_QT0_fpr(QFPREG(rd));
2434 break;
2435 case 0x45:
2436 gen_op_load_fpr_FT0(rs1);
2437 gen_op_load_fpr_FT1(rs2);
2438 gen_clear_float_exceptions();
2439 tcg_gen_helper_0_0(helper_fsubs);
2440 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2441 gen_op_store_FT0_fpr(rd);
2442 break;
2443 case 0x46:
2444 gen_op_load_fpr_DT0(DFPREG(rs1));
2445 gen_op_load_fpr_DT1(DFPREG(rs2));
2446 gen_clear_float_exceptions();
2447 tcg_gen_helper_0_0(helper_fsubd);
2448 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2449 gen_op_store_DT0_fpr(DFPREG(rd));
2450 break;
2451 case 0x47: /* fsubq */
2452 CHECK_FPU_FEATURE(dc, FLOAT128);
2453 gen_op_load_fpr_QT0(QFPREG(rs1));
2454 gen_op_load_fpr_QT1(QFPREG(rs2));
2455 gen_clear_float_exceptions();
2456 tcg_gen_helper_0_0(helper_fsubq);
2457 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2458 gen_op_store_QT0_fpr(QFPREG(rd));
2459 break;
2460 case 0x49: /* fmuls */
2461 CHECK_FPU_FEATURE(dc, FMUL);
2462 gen_op_load_fpr_FT0(rs1);
2463 gen_op_load_fpr_FT1(rs2);
2464 gen_clear_float_exceptions();
2465 tcg_gen_helper_0_0(helper_fmuls);
2466 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2467 gen_op_store_FT0_fpr(rd);
2468 break;
2469 case 0x4a: /* fmuld */
2470 CHECK_FPU_FEATURE(dc, FMUL);
2471 gen_op_load_fpr_DT0(DFPREG(rs1));
2472 gen_op_load_fpr_DT1(DFPREG(rs2));
2473 gen_clear_float_exceptions();
2474 tcg_gen_helper_0_0(helper_fmuld);
2475 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2476 gen_op_store_DT0_fpr(DFPREG(rd));
2477 break;
2478 case 0x4b: /* fmulq */
2479 CHECK_FPU_FEATURE(dc, FLOAT128);
2480 CHECK_FPU_FEATURE(dc, FMUL);
2481 gen_op_load_fpr_QT0(QFPREG(rs1));
2482 gen_op_load_fpr_QT1(QFPREG(rs2));
2483 gen_clear_float_exceptions();
2484 tcg_gen_helper_0_0(helper_fmulq);
2485 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2486 gen_op_store_QT0_fpr(QFPREG(rd));
2487 break;
2488 case 0x4d:
2489 gen_op_load_fpr_FT0(rs1);
2490 gen_op_load_fpr_FT1(rs2);
2491 gen_clear_float_exceptions();
2492 tcg_gen_helper_0_0(helper_fdivs);
2493 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2494 gen_op_store_FT0_fpr(rd);
2495 break;
2496 case 0x4e:
2497 gen_op_load_fpr_DT0(DFPREG(rs1));
2498 gen_op_load_fpr_DT1(DFPREG(rs2));
2499 gen_clear_float_exceptions();
2500 tcg_gen_helper_0_0(helper_fdivd);
2501 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2502 gen_op_store_DT0_fpr(DFPREG(rd));
2503 break;
2504 case 0x4f: /* fdivq */
2505 CHECK_FPU_FEATURE(dc, FLOAT128);
2506 gen_op_load_fpr_QT0(QFPREG(rs1));
2507 gen_op_load_fpr_QT1(QFPREG(rs2));
2508 gen_clear_float_exceptions();
2509 tcg_gen_helper_0_0(helper_fdivq);
2510 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2511 gen_op_store_QT0_fpr(QFPREG(rd));
2512 break;
2513 case 0x69:
2514 CHECK_FPU_FEATURE(dc, FSMULD);
2515 gen_op_load_fpr_FT0(rs1);
2516 gen_op_load_fpr_FT1(rs2);
2517 gen_clear_float_exceptions();
2518 tcg_gen_helper_0_0(helper_fsmuld);
2519 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2520 gen_op_store_DT0_fpr(DFPREG(rd));
2521 break;
2522 case 0x6e: /* fdmulq */
2523 CHECK_FPU_FEATURE(dc, FLOAT128);
2524 gen_op_load_fpr_DT0(DFPREG(rs1));
2525 gen_op_load_fpr_DT1(DFPREG(rs2));
2526 gen_clear_float_exceptions();
2527 tcg_gen_helper_0_0(helper_fdmulq);
2528 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2529 gen_op_store_QT0_fpr(QFPREG(rd));
2530 break;
2531 case 0xc4:
2532 gen_op_load_fpr_FT1(rs2);
2533 gen_clear_float_exceptions();
2534 tcg_gen_helper_0_0(helper_fitos);
2535 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2536 gen_op_store_FT0_fpr(rd);
2537 break;
2538 case 0xc6:
2539 gen_op_load_fpr_DT1(DFPREG(rs2));
2540 gen_clear_float_exceptions();
2541 tcg_gen_helper_0_0(helper_fdtos);
2542 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2543 gen_op_store_FT0_fpr(rd);
2544 break;
2545 case 0xc7: /* fqtos */
2546 CHECK_FPU_FEATURE(dc, FLOAT128);
2547 gen_op_load_fpr_QT1(QFPREG(rs2));
2548 gen_clear_float_exceptions();
2549 tcg_gen_helper_0_0(helper_fqtos);
2550 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2551 gen_op_store_FT0_fpr(rd);
2552 break;
2553 case 0xc8:
2554 gen_op_load_fpr_FT1(rs2);
2555 tcg_gen_helper_0_0(helper_fitod);
2556 gen_op_store_DT0_fpr(DFPREG(rd));
2557 break;
2558 case 0xc9:
2559 gen_op_load_fpr_FT1(rs2);
2560 tcg_gen_helper_0_0(helper_fstod);
2561 gen_op_store_DT0_fpr(DFPREG(rd));
2562 break;
2563 case 0xcb: /* fqtod */
2564 CHECK_FPU_FEATURE(dc, FLOAT128);
2565 gen_op_load_fpr_QT1(QFPREG(rs2));
2566 gen_clear_float_exceptions();
2567 tcg_gen_helper_0_0(helper_fqtod);
2568 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2569 gen_op_store_DT0_fpr(DFPREG(rd));
2570 break;
2571 case 0xcc: /* fitoq */
2572 CHECK_FPU_FEATURE(dc, FLOAT128);
2573 gen_op_load_fpr_FT1(rs2);
2574 tcg_gen_helper_0_0(helper_fitoq);
2575 gen_op_store_QT0_fpr(QFPREG(rd));
2576 break;
2577 case 0xcd: /* fstoq */
2578 CHECK_FPU_FEATURE(dc, FLOAT128);
2579 gen_op_load_fpr_FT1(rs2);
2580 tcg_gen_helper_0_0(helper_fstoq);
2581 gen_op_store_QT0_fpr(QFPREG(rd));
2582 break;
2583 case 0xce: /* fdtoq */
2584 CHECK_FPU_FEATURE(dc, FLOAT128);
2585 gen_op_load_fpr_DT1(DFPREG(rs2));
2586 tcg_gen_helper_0_0(helper_fdtoq);
2587 gen_op_store_QT0_fpr(QFPREG(rd));
2588 break;
2589 case 0xd1:
2590 gen_op_load_fpr_FT1(rs2);
2591 gen_clear_float_exceptions();
2592 tcg_gen_helper_0_0(helper_fstoi);
2593 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2594 gen_op_store_FT0_fpr(rd);
2595 break;
2596 case 0xd2:
2597 gen_op_load_fpr_DT1(DFPREG(rs2));
2598 gen_clear_float_exceptions();
2599 tcg_gen_helper_0_0(helper_fdtoi);
2600 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2601 gen_op_store_FT0_fpr(rd);
2602 break;
2603 case 0xd3: /* fqtoi */
2604 CHECK_FPU_FEATURE(dc, FLOAT128);
2605 gen_op_load_fpr_QT1(QFPREG(rs2));
2606 gen_clear_float_exceptions();
2607 tcg_gen_helper_0_0(helper_fqtoi);
2608 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2609 gen_op_store_FT0_fpr(rd);
2610 break;
2611 #ifdef TARGET_SPARC64
2612 case 0x2: /* V9 fmovd */
2613 gen_op_load_fpr_DT0(DFPREG(rs2));
2614 gen_op_store_DT0_fpr(DFPREG(rd));
2615 break;
2616 case 0x3: /* V9 fmovq */
2617 CHECK_FPU_FEATURE(dc, FLOAT128);
2618 gen_op_load_fpr_QT0(QFPREG(rs2));
2619 gen_op_store_QT0_fpr(QFPREG(rd));
2620 break;
2621 case 0x6: /* V9 fnegd */
2622 gen_op_load_fpr_DT1(DFPREG(rs2));
2623 tcg_gen_helper_0_0(helper_fnegd);
2624 gen_op_store_DT0_fpr(DFPREG(rd));
2625 break;
2626 case 0x7: /* V9 fnegq */
2627 CHECK_FPU_FEATURE(dc, FLOAT128);
2628 gen_op_load_fpr_QT1(QFPREG(rs2));
2629 tcg_gen_helper_0_0(helper_fnegq);
2630 gen_op_store_QT0_fpr(QFPREG(rd));
2631 break;
2632 case 0xa: /* V9 fabsd */
2633 gen_op_load_fpr_DT1(DFPREG(rs2));
2634 tcg_gen_helper_0_0(helper_fabsd);
2635 gen_op_store_DT0_fpr(DFPREG(rd));
2636 break;
2637 case 0xb: /* V9 fabsq */
2638 CHECK_FPU_FEATURE(dc, FLOAT128);
2639 gen_op_load_fpr_QT1(QFPREG(rs2));
2640 tcg_gen_helper_0_0(helper_fabsq);
2641 gen_op_store_QT0_fpr(QFPREG(rd));
2642 break;
2643 case 0x81: /* V9 fstox */
2644 gen_op_load_fpr_FT1(rs2);
2645 gen_clear_float_exceptions();
2646 tcg_gen_helper_0_0(helper_fstox);
2647 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2648 gen_op_store_DT0_fpr(DFPREG(rd));
2649 break;
2650 case 0x82: /* V9 fdtox */
2651 gen_op_load_fpr_DT1(DFPREG(rs2));
2652 gen_clear_float_exceptions();
2653 tcg_gen_helper_0_0(helper_fdtox);
2654 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2655 gen_op_store_DT0_fpr(DFPREG(rd));
2656 break;
2657 case 0x83: /* V9 fqtox */
2658 CHECK_FPU_FEATURE(dc, FLOAT128);
2659 gen_op_load_fpr_QT1(QFPREG(rs2));
2660 gen_clear_float_exceptions();
2661 tcg_gen_helper_0_0(helper_fqtox);
2662 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2663 gen_op_store_DT0_fpr(DFPREG(rd));
2664 break;
2665 case 0x84: /* V9 fxtos */
2666 gen_op_load_fpr_DT1(DFPREG(rs2));
2667 gen_clear_float_exceptions();
2668 tcg_gen_helper_0_0(helper_fxtos);
2669 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2670 gen_op_store_FT0_fpr(rd);
2671 break;
2672 case 0x88: /* V9 fxtod */
2673 gen_op_load_fpr_DT1(DFPREG(rs2));
2674 gen_clear_float_exceptions();
2675 tcg_gen_helper_0_0(helper_fxtod);
2676 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2677 gen_op_store_DT0_fpr(DFPREG(rd));
2678 break;
2679 case 0x8c: /* V9 fxtoq */
2680 CHECK_FPU_FEATURE(dc, FLOAT128);
2681 gen_op_load_fpr_DT1(DFPREG(rs2));
2682 gen_clear_float_exceptions();
2683 tcg_gen_helper_0_0(helper_fxtoq);
2684 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2685 gen_op_store_QT0_fpr(QFPREG(rd));
2686 break;
2687 #endif
2688 default:
2689 goto illegal_insn;
2690 }
2691 } else if (xop == 0x35) { /* FPU Operations */
2692 #ifdef TARGET_SPARC64
2693 int cond;
2694 #endif
2695 if (gen_trap_ifnofpu(dc, cpu_cond))
2696 goto jmp_insn;
2697 gen_op_clear_ieee_excp_and_FTT();
2698 rs1 = GET_FIELD(insn, 13, 17);
2699 rs2 = GET_FIELD(insn, 27, 31);
2700 xop = GET_FIELD(insn, 18, 26);
2701 #ifdef TARGET_SPARC64
2702 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2703 int l1;
2704
2705 l1 = gen_new_label();
2706 cond = GET_FIELD_SP(insn, 14, 17);
2707 cpu_src1 = get_src1(insn, cpu_src1);
2708 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2709 0, l1);
2710 gen_op_load_fpr_FT0(rs2);
2711 gen_op_store_FT0_fpr(rd);
2712 gen_set_label(l1);
2713 break;
2714 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2715 int l1;
2716
2717 l1 = gen_new_label();
2718 cond = GET_FIELD_SP(insn, 14, 17);
2719 cpu_src1 = get_src1(insn, cpu_src1);
2720 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2721 0, l1);
2722 gen_op_load_fpr_DT0(DFPREG(rs2));
2723 gen_op_store_DT0_fpr(DFPREG(rd));
2724 gen_set_label(l1);
2725 break;
2726 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2727 int l1;
2728
2729 CHECK_FPU_FEATURE(dc, FLOAT128);
2730 l1 = gen_new_label();
2731 cond = GET_FIELD_SP(insn, 14, 17);
2732 cpu_src1 = get_src1(insn, cpu_src1);
2733 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2734 0, l1);
2735 gen_op_load_fpr_QT0(QFPREG(rs2));
2736 gen_op_store_QT0_fpr(QFPREG(rd));
2737 gen_set_label(l1);
2738 break;
2739 }
2740 #endif
2741 switch (xop) {
2742 #ifdef TARGET_SPARC64
2743 #define FMOVCC(size_FDQ, fcc) \
2744 { \
2745 TCGv r_cond; \
2746 int l1; \
2747 \
2748 l1 = gen_new_label(); \
2749 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2750 cond = GET_FIELD_SP(insn, 14, 17); \
2751 gen_fcond(r_cond, fcc, cond); \
2752 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2753 0, l1); \
2754 glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2755 (glue(size_FDQ, FPREG(rs2))); \
2756 glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2757 (glue(size_FDQ, FPREG(rd))); \
2758 gen_set_label(l1); \
2759 tcg_temp_free(r_cond); \
2760 }
2761 case 0x001: /* V9 fmovscc %fcc0 */
2762 FMOVCC(F, 0);
2763 break;
2764 case 0x002: /* V9 fmovdcc %fcc0 */
2765 FMOVCC(D, 0);
2766 break;
2767 case 0x003: /* V9 fmovqcc %fcc0 */
2768 CHECK_FPU_FEATURE(dc, FLOAT128);
2769 FMOVCC(Q, 0);
2770 break;
2771 case 0x041: /* V9 fmovscc %fcc1 */
2772 FMOVCC(F, 1);
2773 break;
2774 case 0x042: /* V9 fmovdcc %fcc1 */
2775 FMOVCC(D, 1);
2776 break;
2777 case 0x043: /* V9 fmovqcc %fcc1 */
2778 CHECK_FPU_FEATURE(dc, FLOAT128);
2779 FMOVCC(Q, 1);
2780 break;
2781 case 0x081: /* V9 fmovscc %fcc2 */
2782 FMOVCC(F, 2);
2783 break;
2784 case 0x082: /* V9 fmovdcc %fcc2 */
2785 FMOVCC(D, 2);
2786 break;
2787 case 0x083: /* V9 fmovqcc %fcc2 */
2788 CHECK_FPU_FEATURE(dc, FLOAT128);
2789 FMOVCC(Q, 2);
2790 break;
2791 case 0x0c1: /* V9 fmovscc %fcc3 */
2792 FMOVCC(F, 3);
2793 break;
2794 case 0x0c2: /* V9 fmovdcc %fcc3 */
2795 FMOVCC(D, 3);
2796 break;
2797 case 0x0c3: /* V9 fmovqcc %fcc3 */
2798 CHECK_FPU_FEATURE(dc, FLOAT128);
2799 FMOVCC(Q, 3);
2800 break;
2801 #undef FMOVCC
2802 #define FMOVCC(size_FDQ, icc) \
2803 { \
2804 TCGv r_cond; \
2805 int l1; \
2806 \
2807 l1 = gen_new_label(); \
2808 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2809 cond = GET_FIELD_SP(insn, 14, 17); \
2810 gen_cond(r_cond, icc, cond); \
2811 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2812 0, l1); \
2813 glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2814 (glue(size_FDQ, FPREG(rs2))); \
2815 glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2816 (glue(size_FDQ, FPREG(rd))); \
2817 gen_set_label(l1); \
2818 tcg_temp_free(r_cond); \
2819 }
2820
2821 case 0x101: /* V9 fmovscc %icc */
2822 FMOVCC(F, 0);
2823 break;
2824 case 0x102: /* V9 fmovdcc %icc */
2825 FMOVCC(D, 0);
2826 case 0x103: /* V9 fmovqcc %icc */
2827 CHECK_FPU_FEATURE(dc, FLOAT128);
2828 FMOVCC(Q, 0);
2829 break;
2830 case 0x181: /* V9 fmovscc %xcc */
2831 FMOVCC(F, 1);
2832 break;
2833 case 0x182: /* V9 fmovdcc %xcc */
2834 FMOVCC(D, 1);
2835 break;
2836 case 0x183: /* V9 fmovqcc %xcc */
2837 CHECK_FPU_FEATURE(dc, FLOAT128);
2838 FMOVCC(Q, 1);
2839 break;
2840 #undef FMOVCC
2841 #endif
2842 case 0x51: /* fcmps, V9 %fcc */
2843 gen_op_load_fpr_FT0(rs1);
2844 gen_op_load_fpr_FT1(rs2);
2845 gen_op_fcmps(rd & 3);
2846 break;
2847 case 0x52: /* fcmpd, V9 %fcc */
2848 gen_op_load_fpr_DT0(DFPREG(rs1));
2849 gen_op_load_fpr_DT1(DFPREG(rs2));
2850 gen_op_fcmpd(rd & 3);
2851 break;
2852 case 0x53: /* fcmpq, V9 %fcc */
2853 CHECK_FPU_FEATURE(dc, FLOAT128);
2854 gen_op_load_fpr_QT0(QFPREG(rs1));
2855 gen_op_load_fpr_QT1(QFPREG(rs2));
2856 gen_op_fcmpq(rd & 3);
2857 break;
2858 case 0x55: /* fcmpes, V9 %fcc */
2859 gen_op_load_fpr_FT0(rs1);
2860 gen_op_load_fpr_FT1(rs2);
2861 gen_op_fcmpes(rd & 3);
2862 break;
2863 case 0x56: /* fcmped, V9 %fcc */
2864 gen_op_load_fpr_DT0(DFPREG(rs1));
2865 gen_op_load_fpr_DT1(DFPREG(rs2));
2866 gen_op_fcmped(rd & 3);
2867 break;
2868 case 0x57: /* fcmpeq, V9 %fcc */
2869 CHECK_FPU_FEATURE(dc, FLOAT128);
2870 gen_op_load_fpr_QT0(QFPREG(rs1));
2871 gen_op_load_fpr_QT1(QFPREG(rs2));
2872 gen_op_fcmpeq(rd & 3);
2873 break;
2874 default:
2875 goto illegal_insn;
2876 }
2877 } else if (xop == 0x2) {
2878 // clr/mov shortcut
2879
2880 rs1 = GET_FIELD(insn, 13, 17);
2881 if (rs1 == 0) {
2882 // or %g0, x, y -> mov T0, x; mov y, T0
2883 if (IS_IMM) { /* immediate */
2884 TCGv r_const;
2885
2886 rs2 = GET_FIELDs(insn, 19, 31);
2887 r_const = tcg_const_tl((int)rs2);
2888 gen_movl_TN_reg(rd, r_const);
2889 tcg_temp_free(r_const);
2890 } else { /* register */
2891 rs2 = GET_FIELD(insn, 27, 31);
2892 gen_movl_reg_TN(rs2, cpu_dst);
2893 gen_movl_TN_reg(rd, cpu_dst);
2894 }
2895 } else {
2896 cpu_src1 = get_src1(insn, cpu_src1);
2897 if (IS_IMM) { /* immediate */
2898 rs2 = GET_FIELDs(insn, 19, 31);
2899 tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2900 gen_movl_TN_reg(rd, cpu_dst);
2901 } else { /* register */
2902 // or x, %g0, y -> mov T1, x; mov y, T1
2903 rs2 = GET_FIELD(insn, 27, 31);
2904 if (rs2 != 0) {
2905 gen_movl_reg_TN(rs2, cpu_src2);
2906 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2907 gen_movl_TN_reg(rd, cpu_dst);
2908 } else
2909 gen_movl_TN_reg(rd, cpu_src1);
2910 }
2911 }
2912 #ifdef TARGET_SPARC64
2913 } else if (xop == 0x25) { /* sll, V9 sllx */
2914 cpu_src1 = get_src1(insn, cpu_src1);
2915 if (IS_IMM) { /* immediate */
2916 rs2 = GET_FIELDs(insn, 20, 31);
2917 if (insn & (1 << 12)) {
2918 tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2919 } else {
2920 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2921 tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2922 }
2923 } else { /* register */
2924 rs2 = GET_FIELD(insn, 27, 31);
2925 gen_movl_reg_TN(rs2, cpu_src2);
2926 if (insn & (1 << 12)) {
2927 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2928 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2929 } else {
2930 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2931 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2932 tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2933 }
2934 }
2935 gen_movl_TN_reg(rd, cpu_dst);
2936 } else if (xop == 0x26) { /* srl, V9 srlx */
2937 cpu_src1 = get_src1(insn, cpu_src1);
2938 if (IS_IMM) { /* immediate */
2939 rs2 = GET_FIELDs(insn, 20, 31);
2940 if (insn & (1 << 12)) {
2941 tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2942 } else {
2943 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2944 tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2945 }
2946 } else { /* register */
2947 rs2 = GET_FIELD(insn, 27, 31);
2948 gen_movl_reg_TN(rs2, cpu_src2);
2949 if (insn & (1 << 12)) {
2950 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2951 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2952 } else {
2953 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2954 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2955 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2956 }
2957 }
2958 gen_movl_TN_reg(rd, cpu_dst);
2959 } else if (xop == 0x27) { /* sra, V9 srax */
2960 cpu_src1 = get_src1(insn, cpu_src1);
2961 if (IS_IMM) { /* immediate */
2962 rs2 = GET_FIELDs(insn, 20, 31);
2963 if (insn & (1 << 12)) {
2964 tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2965 } else {
2966 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2967 tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2968 tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2969 }
2970 } else { /* register */
2971 rs2 = GET_FIELD(insn, 27, 31);
2972 gen_movl_reg_TN(rs2, cpu_src2);
2973 if (insn & (1 << 12)) {
2974 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2975 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2976 } else {
2977 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2978 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2979 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2980 }
2981 }
2982 gen_movl_TN_reg(rd, cpu_dst);
2983 #endif
2984 } else if (xop < 0x36) {
2985 cpu_src1 = get_src1(insn, cpu_src1);
2986 cpu_src2 = get_src2(insn, cpu_src2);
2987 if (xop < 0x20) {
2988 switch (xop & ~0x10) {
2989 case 0x0:
2990 if (xop & 0x10)
2991 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2992 else
2993 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2994 break;
2995 case 0x1:
2996 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2997 if (xop & 0x10)
2998 gen_op_logic_cc(cpu_dst);
2999 break;
3000 case 0x2:
3001 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3002 if (xop & 0x10)
3003 gen_op_logic_cc(cpu_dst);
3004 break;
3005 case 0x3:
3006 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3007 if (xop & 0x10)
3008 gen_op_logic_cc(cpu_dst);
3009 break;
3010 case 0x4:
3011 if (xop & 0x10)
3012 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3013 else
3014 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3015 break;
3016 case 0x5:
3017 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3018 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3019 if (xop & 0x10)
3020 gen_op_logic_cc(cpu_dst);
3021 break;
3022 case 0x6:
3023 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3024 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3025 if (xop & 0x10)
3026 gen_op_logic_cc(cpu_dst);
3027 break;
3028 case 0x7:
3029 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3030 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3031 if (xop & 0x10)
3032 gen_op_logic_cc(cpu_dst);
3033 break;
3034 case 0x8:
3035 if (xop & 0x10)
3036 gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3037 else {
3038 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3039 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3040 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3041 }
3042 break;
3043 #ifdef TARGET_SPARC64
3044 case 0x9: /* V9 mulx */
3045 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3046 break;
3047 #endif
3048 case 0xa:
3049 CHECK_IU_FEATURE(dc, MUL);
3050 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3051 if (xop & 0x10)
3052 gen_op_logic_cc(cpu_dst);
3053 break;
3054 case 0xb:
3055 CHECK_IU_FEATURE(dc, MUL);
3056 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3057 if (xop & 0x10)
3058 gen_op_logic_cc(cpu_dst);
3059 break;
3060 case 0xc:
3061 if (xop & 0x10)
3062 gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3063 else {
3064 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3065 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3066 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3067 }
3068 break;
3069 #ifdef TARGET_SPARC64
3070 case 0xd: /* V9 udivx */
3071 gen_trap_ifdivzero_tl(cpu_src2);
3072 tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
3073 break;
3074 #endif
3075 case 0xe:
3076 CHECK_IU_FEATURE(dc, DIV);
3077 tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3078 cpu_src2);
3079 if (xop & 0x10)
3080 gen_op_div_cc(cpu_dst);
3081 break;
3082 case 0xf:
3083 CHECK_IU_FEATURE(dc, DIV);
3084 tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3085 cpu_src2);
3086 if (xop & 0x10)
3087 gen_op_div_cc(cpu_dst);
3088 break;
3089 default:
3090 goto illegal_insn;
3091 }
3092 gen_movl_TN_reg(rd, cpu_dst);
3093 } else {
3094 switch (xop) {
3095 case 0x20: /* taddcc */
3096 gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3097 gen_movl_TN_reg(rd, cpu_dst);
3098 break;
3099 case 0x21: /* tsubcc */
3100 gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3101 gen_movl_TN_reg(rd, cpu_dst);
3102 break;
3103 case 0x22: /* taddcctv */
3104 save_state(dc, cpu_cond);
3105 gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3106 gen_movl_TN_reg(rd, cpu_dst);
3107 break;
3108 case 0x23: /* tsubcctv */
3109 save_state(dc, cpu_cond);
3110 gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3111 gen_movl_TN_reg(rd, cpu_dst);
3112 break;
3113 case 0x24: /* mulscc */
3114 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3115 gen_movl_TN_reg(rd, cpu_dst);
3116 break;
3117 #ifndef TARGET_SPARC64
3118 case 0x25: /* sll */
3119 if (IS_IMM) { /* immediate */
3120 rs2 = GET_FIELDs(insn, 20, 31);
3121 tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3122 } else { /* register */
3123 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3124 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3125 }
3126 gen_movl_TN_reg(rd, cpu_dst);
3127 break;
3128 case 0x26: /* srl */
3129 if (IS_IMM) { /* immediate */
3130 rs2 = GET_FIELDs(insn, 20, 31);
3131 tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3132 } else { /* register */
3133 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3134 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3135 }
3136 gen_movl_TN_reg(rd, cpu_dst);
3137 break;
3138 case 0x27: /* sra */
3139 if (IS_IMM) { /* immediate */
3140 rs2 = GET_FIELDs(insn, 20, 31);
3141 tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3142 } else { /* register */
3143 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3144 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3145 }
3146 gen_movl_TN_reg(rd, cpu_dst);
3147 break;
3148 #endif
3149 case 0x30:
3150 {
3151 switch(rd) {
3152 case 0: /* wry */
3153 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3154 tcg_gen_st_tl(cpu_dst, cpu_env,
3155 offsetof(CPUSPARCState, y));
3156 break;
3157 #ifndef TARGET_SPARC64
3158 case 0x01 ... 0x0f: /* undefined in the
3159 SPARCv8 manual, nop
3160 on the microSPARC
3161 II */
3162 case 0x10 ... 0x1f: /* implementation-dependent
3163 in the SPARCv8
3164 manual, nop on the
3165 microSPARC II */
3166 break;
3167 #else
3168 case 0x2: /* V9 wrccr */
3169 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3170 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3171 break;
3172 case 0x3: /* V9 wrasi */
3173 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3174 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3175 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3176 offsetof(CPUSPARCState, asi));
3177 break;
3178 case 0x6: /* V9 wrfprs */
3179 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3180 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3181 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3182 offsetof(CPUSPARCState, fprs));
3183 save_state(dc, cpu_cond);
3184 gen_op_next_insn();
3185 tcg_gen_exit_tb(0);
3186 dc->is_br = 1;
3187 break;
3188 case 0xf: /* V9 sir, nop if user */
3189 #if !defined(CONFIG_USER_ONLY)
3190 if (supervisor(dc))
3191 ; // XXX
3192 #endif
3193 break;
3194 case 0x13: /* Graphics Status */
3195 if (gen_trap_ifnofpu(dc, cpu_cond))
3196 goto jmp_insn;
3197 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3198 tcg_gen_st_tl(cpu_dst, cpu_env,
3199 offsetof(CPUSPARCState, gsr));
3200 break;
3201 case 0x17: /* Tick compare */
3202 #if !defined(CONFIG_USER_ONLY)
3203 if (!supervisor(dc))
3204 goto illegal_insn;
3205 #endif
3206 {
3207 TCGv r_tickptr;
3208
3209 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3210 cpu_src2);
3211 tcg_gen_st_tl(cpu_dst, cpu_env,
3212 offsetof(CPUSPARCState,
3213 tick_cmpr));
3214 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3215 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3216 offsetof(CPUState, tick));
3217 tcg_gen_helper_0_2(helper_tick_set_limit,
3218 r_tickptr, cpu_dst);
3219 tcg_temp_free(r_tickptr);
3220 }
3221 break;
3222 case 0x18: /* System tick */
3223 #if !defined(CONFIG_USER_ONLY)
3224 if (!supervisor(dc))
3225 goto illegal_insn;
3226 #endif
3227 {
3228 TCGv r_tickptr;
3229
3230 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3231 cpu_src2);
3232 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3233 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3234 offsetof(CPUState, stick));
3235 tcg_gen_helper_0_2(helper_tick_set_count,
3236 r_tickptr, cpu_dst);
3237 tcg_temp_free(r_tickptr);
3238 }
3239 break;
3240 case 0x19: /* System tick compare */
3241 #if !defined(CONFIG_USER_ONLY)
3242 if (!supervisor(dc))
3243 goto illegal_insn;
3244 #endif
3245 {
3246 TCGv r_tickptr;
3247
3248 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3249 cpu_src2);
3250 tcg_gen_st_tl(cpu_dst, cpu_env,
3251 offsetof(CPUSPARCState,
3252 stick_cmpr));
3253 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3254 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3255 offsetof(CPUState, stick));
3256 tcg_gen_helper_0_2(helper_tick_set_limit,
3257 r_tickptr, cpu_dst);
3258 tcg_temp_free(r_tickptr);
3259 }
3260 break;
3261
3262 case 0x10: /* Performance Control */
3263 case 0x11: /* Performance Instrumentation
3264 Counter */
3265 case 0x12: /* Dispatch Control */
3266 case 0x14: /* Softint set */
3267 case 0x15: /* Softint clear */
3268 case 0x16: /* Softint write */
3269 #endif
3270 default:
3271 goto illegal_insn;
3272 }
3273 }
3274 break;
3275 #if !defined(CONFIG_USER_ONLY)
3276 case 0x31: /* wrpsr, V9 saved, restored */
3277 {
3278 if (!supervisor(dc))
3279 goto priv_insn;
3280 #ifdef TARGET_SPARC64
3281 switch (rd) {
3282 case 0:
3283 tcg_gen_helper_0_0(helper_saved);
3284 break;
3285 case 1:
3286 tcg_gen_helper_0_0(helper_restored);
3287 break;
3288 case 2: /* UA2005 allclean */
3289 case 3: /* UA2005 otherw */
3290 case 4: /* UA2005 normalw */
3291 case 5: /* UA2005 invalw */
3292 // XXX
3293 default:
3294 goto illegal_insn;
3295 }
3296 #else
3297 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3298 tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3299 save_state(dc, cpu_cond);
3300 gen_op_next_insn();
3301 tcg_gen_exit_tb(0);
3302 dc->is_br = 1;
3303 #endif
3304 }
3305 break;
3306 case 0x32: /* wrwim, V9 wrpr */
3307 {
3308 if (!supervisor(dc))
3309 goto priv_insn;
3310 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3311 #ifdef TARGET_SPARC64
3312 switch (rd) {
3313 case 0: // tpc
3314 {
3315 TCGv r_tsptr;
3316
3317 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3318 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3319 offsetof(CPUState, tsptr));
3320 tcg_gen_st_tl(cpu_dst, r_tsptr,
3321 offsetof(trap_state, tpc));
3322 tcg_temp_free(r_tsptr);
3323 }
3324 break;
3325 case 1: // tnpc
3326 {
3327 TCGv r_tsptr;
3328
3329 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3330 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3331 offsetof(CPUState, tsptr));
3332 tcg_gen_st_tl(cpu_dst, r_tsptr,
3333 offsetof(trap_state, tnpc));
3334 tcg_temp_free(r_tsptr);
3335 }
3336 break;
3337 case 2: // tstate
3338 {
3339 TCGv r_tsptr;
3340
3341 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3342 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3343 offsetof(CPUState, tsptr));
3344 tcg_gen_st_tl(cpu_dst, r_tsptr,
3345 offsetof(trap_state,
3346 tstate));
3347 tcg_temp_free(r_tsptr);
3348 }
3349 break;
3350 case 3: // tt
3351 {
3352 TCGv r_tsptr;
3353
3354 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3355 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3356 offsetof(CPUState, tsptr));
3357 tcg_gen_st_i32(cpu_dst, r_tsptr,
3358 offsetof(trap_state, tt));
3359 tcg_temp_free(r_tsptr);
3360 }
3361 break;
3362 case 4: // tick
3363 {
3364 TCGv r_tickptr;
3365
3366 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3367 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3368 offsetof(CPUState, tick));
3369 tcg_gen_helper_0_2(helper_tick_set_count,
3370 r_tickptr, cpu_dst);
3371 tcg_temp_free(r_tickptr);
3372 }
3373 break;
3374 case 5: // tba
3375 tcg_gen_st_tl(cpu_dst, cpu_env,
3376 offsetof(CPUSPARCState, tbr));
3377 break;
3378 case 6: // pstate
3379 save_state(dc, cpu_cond);
3380 tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
3381 gen_op_next_insn();
3382 tcg_gen_exit_tb(0);
3383 dc->is_br = 1;
3384 break;
3385 case 7: // tl
3386 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3387 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3388 offsetof(CPUSPARCState, tl));
3389 break;
3390 case 8: // pil
3391 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3392 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3393 offsetof(CPUSPARCState,
3394 psrpil));
3395 break;
3396 case 9: // cwp
3397 tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
3398 break;
3399 case 10: // cansave
3400 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3401 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3402 offsetof(CPUSPARCState,
3403 cansave));
3404 break;
3405 case 11: // canrestore
3406 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3407 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3408 offsetof(CPUSPARCState,
3409 canrestore));
3410 break;
3411 case 12: // cleanwin
3412 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3413 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3414 offsetof(CPUSPARCState,
3415 cleanwin));
3416 break;
3417 case 13: // otherwin
3418 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3419 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3420 offsetof(CPUSPARCState,
3421 otherwin));
3422 break;
3423 case 14: // wstate
3424 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3425 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3426 offsetof(CPUSPARCState,
3427 wstate));
3428 break;
3429 case 16: // UA2005 gl
3430 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3431 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3432 offsetof(CPUSPARCState, gl));
3433 break;
3434 case 26: // UA2005 strand status
3435 if (!hypervisor(dc))
3436 goto priv_insn;
3437 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3438 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3439 offsetof(CPUSPARCState, ssr));
3440 break;
3441 default:
3442 goto illegal_insn;
3443 }
3444 #else
3445 tcg_gen_andi_tl(cpu_dst, cpu_dst,
3446 ((1 << NWINDOWS) - 1));
3447 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3448 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3449 offsetof(CPUSPARCState, wim));
3450 #endif
3451 }
3452 break;
3453 case 0x33: /* wrtbr, UA2005 wrhpr */
3454 {
3455 #ifndef TARGET_SPARC64
3456 if (!supervisor(dc))
3457 goto priv_insn;
3458 tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3459 tcg_gen_st_tl(cpu_dst, cpu_env,
3460 offsetof(CPUSPARCState, tbr));
3461 #else
3462 if (!hypervisor(dc))
3463 goto priv_insn;
3464 tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3465 switch (rd) {
3466 case 0: // hpstate
3467 // XXX gen_op_wrhpstate();
3468 save_state(dc, cpu_cond);
3469 gen_op_next_insn();
3470 tcg_gen_exit_tb(0);
3471 dc->is_br = 1;
3472 break;
3473 case 1: // htstate
3474 // XXX gen_op_wrhtstate();
3475 break;
3476 case 3: // hintp
3477 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3478 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3479 offsetof(CPUSPARCState, hintp));
3480 break;
3481 case 5: // htba
3482 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3483 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3484 offsetof(CPUSPARCState, htba));
3485 break;
3486 case 31: // hstick_cmpr
3487 {
3488 TCGv r_tickptr;
3489
3490 tcg_gen_st_tl(cpu_dst, cpu_env,
3491 offsetof(CPUSPARCState,
3492 hstick_cmpr));
3493 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3494 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3495 offsetof(CPUState, hstick));
3496 tcg_gen_helper_0_2(helper_tick_set_limit,
3497 r_tickptr, cpu_dst);
3498 tcg_temp_free(r_tickptr);
3499 }
3500 break;
3501 case 6: // hver readonly
3502 default:
3503 goto illegal_insn;
3504 }
3505 #endif
3506 }
3507 break;
3508 #endif
3509 #ifdef TARGET_SPARC64
3510 case 0x2c: /* V9 movcc */
3511 {
3512 int cc = GET_FIELD_SP(insn, 11, 12);
3513 int cond = GET_FIELD_SP(insn, 14, 17);
3514 TCGv r_cond;
3515 int l1;
3516
3517 r_cond = tcg_temp_new(TCG_TYPE_TL);
3518 if (insn & (1 << 18)) {
3519 if (cc == 0)
3520 gen_cond(r_cond, 0, cond);
3521 else if (cc == 2)
3522 gen_cond(r_cond, 1, cond);
3523 else
3524 goto illegal_insn;
3525 } else {
3526 gen_fcond(r_cond, cc, cond);
3527 }
3528
3529 l1 = gen_new_label();
3530
3531 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3532 if (IS_IMM) { /* immediate */
3533 TCGv r_const;
3534
3535 rs2 = GET_FIELD_SPs(insn, 0, 10);
3536 r_const = tcg_const_tl((int)rs2);
3537 gen_movl_TN_reg(rd, r_const);
3538 tcg_temp_free(r_const);
3539 } else {
3540 rs2 = GET_FIELD_SP(insn, 0, 4);
3541 gen_movl_reg_TN(rs2, cpu_tmp0);
3542 gen_movl_TN_reg(rd, cpu_tmp0);
3543 }
3544 gen_set_label(l1);
3545 tcg_temp_free(r_cond);
3546 break;
3547 }
3548 case 0x2d: /* V9 sdivx */
3549 gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3550 gen_movl_TN_reg(rd, cpu_dst);
3551 break;
3552 case 0x2e: /* V9 popc */
3553 {
3554 cpu_src2 = get_src2(insn, cpu_src2);
3555 tcg_gen_helper_1_1(helper_popc, cpu_dst,
3556 cpu_src2);
3557 gen_movl_TN_reg(rd, cpu_dst);
3558 }
3559 case 0x2f: /* V9 movr */
3560 {
3561 int cond = GET_FIELD_SP(insn, 10, 12);
3562 int l1;
3563
3564 cpu_src1 = get_src1(insn, cpu_src1);
3565
3566 l1 = gen_new_label();
3567
3568 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3569 cpu_src1, 0, l1);
3570 if (IS_IMM) { /* immediate */
3571 TCGv r_const;
3572
3573 rs2 = GET_FIELD_SPs(insn, 0, 9);
3574 r_const = tcg_const_tl((int)rs2);
3575 gen_movl_TN_reg(rd, r_const);
3576 tcg_temp_free(r_const);
3577 } else {
3578 rs2 = GET_FIELD_SP(insn, 0, 4);
3579 gen_movl_reg_TN(rs2, cpu_tmp0);
3580 gen_movl_TN_reg(rd, cpu_tmp0);
3581 }
3582 gen_set_label(l1);
3583 break;
3584 }
3585 #endif
3586 default:
3587 goto illegal_insn;
3588 }
3589 }
3590 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3591 #ifdef TARGET_SPARC64
3592 int opf = GET_FIELD_SP(insn, 5, 13);
3593 rs1 = GET_FIELD(insn, 13, 17);
3594 rs2 = GET_FIELD(insn, 27, 31);
3595 if (gen_trap_ifnofpu(dc, cpu_cond))
3596 goto jmp_insn;
3597
3598 switch (opf) {
3599 case 0x000: /* VIS I edge8cc */
3600 case 0x001: /* VIS II edge8n */
3601 case 0x002: /* VIS I edge8lcc */
3602 case 0x003: /* VIS II edge8ln */
3603 case 0x004: /* VIS I edge16cc */
3604 case 0x005: /* VIS II edge16n */
3605 case 0x006: /* VIS I edge16lcc */
3606 case 0x007: /* VIS II edge16ln */
3607 case 0x008: /* VIS I edge32cc */
3608 case 0x009: /* VIS II edge32n */
3609 case 0x00a: /* VIS I edge32lcc */
3610 case 0x00b: /* VIS II edge32ln */
3611 // XXX
3612 goto illegal_insn;
3613 case 0x010: /* VIS I array8 */
3614 CHECK_FPU_FEATURE(dc, VIS1);
3615 cpu_src1 = get_src1(insn, cpu_src1);
3616 gen_movl_reg_TN(rs2, cpu_src2);
3617 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3618 cpu_src2);
3619 gen_movl_TN_reg(rd, cpu_dst);
3620 break;
3621 case 0x012: /* VIS I array16 */
3622 CHECK_FPU_FEATURE(dc, VIS1);
3623 cpu_src1 = get_src1(insn, cpu_src1);
3624 gen_movl_reg_TN(rs2, cpu_src2);
3625 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3626 cpu_src2);
3627 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3628 gen_movl_TN_reg(rd, cpu_dst);
3629 break;
3630 case 0x014: /* VIS I array32 */
3631 CHECK_FPU_FEATURE(dc, VIS1);
3632 cpu_src1 = get_src1(insn, cpu_src1);
3633 gen_movl_reg_TN(rs2, cpu_src2);
3634 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3635 cpu_src2);
3636 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3637 gen_movl_TN_reg(rd, cpu_dst);
3638 break;
3639 case 0x018: /* VIS I alignaddr */
3640 CHECK_FPU_FEATURE(dc, VIS1);
3641 cpu_src1 = get_src1(insn, cpu_src1);
3642 gen_movl_reg_TN(rs2, cpu_src2);
3643 tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3644 cpu_src2);
3645 gen_movl_TN_reg(rd, cpu_dst);
3646 break;
3647 case 0x019: /* VIS II bmask */
3648 case 0x01a: /* VIS I alignaddrl */
3649 // XXX
3650 goto illegal_insn;
3651 case 0x020: /* VIS I fcmple16 */
3652 CHECK_FPU_FEATURE(dc, VIS1);
3653 gen_op_load_fpr_DT0(DFPREG(rs1));
3654 gen_op_load_fpr_DT1(DFPREG(rs2));
3655 tcg_gen_helper_0_0(helper_fcmple16);
3656 gen_op_store_DT0_fpr(DFPREG(rd));
3657 break;
3658 case 0x022: /* VIS I fcmpne16 */
3659 CHECK_FPU_FEATURE(dc, VIS1);
3660 gen_op_load_fpr_DT0(DFPREG(rs1));
3661 gen_op_load_fpr_DT1(DFPREG(rs2));
3662 tcg_gen_helper_0_0(helper_fcmpne16);
3663 gen_op_store_DT0_fpr(DFPREG(rd));
3664 break;
3665 case 0x024: /* VIS I fcmple32 */
3666 CHECK_FPU_FEATURE(dc, VIS1);
3667 gen_op_load_fpr_DT0(DFPREG(rs1));
3668 gen_op_load_fpr_DT1(DFPREG(rs2));
3669 tcg_gen_helper_0_0(helper_fcmple32);
3670 gen_op_store_DT0_fpr(DFPREG(rd));
3671 break;
3672 case 0x026: /* VIS I fcmpne32 */
3673 CHECK_FPU_FEATURE(dc, VIS1);
3674 gen_op_load_fpr_DT0(DFPREG(rs1));
3675 gen_op_load_fpr_DT1(DFPREG(rs2));
3676 tcg_gen_helper_0_0(helper_fcmpne32);
3677 gen_op_store_DT0_fpr(DFPREG(rd));
3678 break;
3679 case 0x028: /* VIS I fcmpgt16 */
3680 CHECK_FPU_FEATURE(dc, VIS1);
3681 gen_op_load_fpr_DT0(DFPREG(rs1));
3682 gen_op_load_fpr_DT1(DFPREG(rs2));
3683 tcg_gen_helper_0_0(helper_fcmpgt16);
3684 gen_op_store_DT0_fpr(DFPREG(rd));
3685 break;
3686 case 0x02a: /* VIS I fcmpeq16 */
3687 CHECK_FPU_FEATURE(dc, VIS1);
3688 gen_op_load_fpr_DT0(DFPREG(rs1));
3689 gen_op_load_fpr_DT1(DFPREG(rs2));
3690 tcg_gen_helper_0_0(helper_fcmpeq16);
3691 gen_op_store_DT0_fpr(DFPREG(rd));
3692 break;
3693 case 0x02c: /* VIS I fcmpgt32 */
3694 CHECK_FPU_FEATURE(dc, VIS1);
3695 gen_op_load_fpr_DT0(DFPREG(rs1));
3696 gen_op_load_fpr_DT1(DFPREG(rs2));
3697 tcg_gen_helper_0_0(helper_fcmpgt32);
3698 gen_op_store_DT0_fpr(DFPREG(rd));
3699 break;
3700 case 0x02e: /* VIS I fcmpeq32 */
3701 CHECK_FPU_FEATURE(dc, VIS1);
3702 gen_op_load_fpr_DT0(DFPREG(rs1));
3703 gen_op_load_fpr_DT1(DFPREG(rs2));
3704 tcg_gen_helper_0_0(helper_fcmpeq32);
3705 gen_op_store_DT0_fpr(DFPREG(rd));
3706 break;
3707 case 0x031: /* VIS I fmul8x16 */
3708 CHECK_FPU_FEATURE(dc, VIS1);
3709 gen_op_load_fpr_DT0(DFPREG(rs1));
3710 gen_op_load_fpr_DT1(DFPREG(rs2));
3711 tcg_gen_helper_0_0(helper_fmul8x16);
3712 gen_op_store_DT0_fpr(DFPREG(rd));
3713 break;
3714 case 0x033: /* VIS I fmul8x16au */
3715 CHECK_FPU_FEATURE(dc, VIS1);
3716 gen_op_load_fpr_DT0(DFPREG(rs1));
3717 gen_op_load_fpr_DT1(DFPREG(rs2));
3718 tcg_gen_helper_0_0(helper_fmul8x16au);
3719 gen_op_store_DT0_fpr(DFPREG(rd));
3720 break;
3721 case 0x035: /* VIS I fmul8x16al */
3722 CHECK_FPU_FEATURE(dc, VIS1);
3723 gen_op_load_fpr_DT0(DFPREG(rs1));
3724 gen_op_load_fpr_DT1(DFPREG(rs2));
3725 tcg_gen_helper_0_0(helper_fmul8x16al);
3726 gen_op_store_DT0_fpr(DFPREG(rd));
3727 break;
3728 case 0x036: /* VIS I fmul8sux16 */
3729 CHECK_FPU_FEATURE(dc, VIS1);
3730 gen_op_load_fpr_DT0(DFPREG(rs1));
3731 gen_op_load_fpr_DT1(DFPREG(rs2));
3732 tcg_gen_helper_0_0(helper_fmul8sux16);
3733 gen_op_store_DT0_fpr(DFPREG(rd));
3734 break;
3735 case 0x037: /* VIS I fmul8ulx16 */
3736 CHECK_FPU_FEATURE(dc, VIS1);
3737 gen_op_load_fpr_DT0(DFPREG(rs1));
3738 gen_op_load_fpr_DT1(DFPREG(rs2));
3739 tcg_gen_helper_0_0(helper_fmul8ulx16);
3740 gen_op_store_DT0_fpr(DFPREG(rd));
3741 break;
3742 case 0x038: /* VIS I fmuld8sux16 */
3743 CHECK_FPU_FEATURE(dc, VIS1);
3744 gen_op_load_fpr_DT0(DFPREG(rs1));
3745 gen_op_load_fpr_DT1(DFPREG(rs2));
3746 tcg_gen_helper_0_0(helper_fmuld8sux16);
3747 gen_op_store_DT0_fpr(DFPREG(rd));
3748 break;
3749 case 0x039: /* VIS I fmuld8ulx16 */
3750 CHECK_FPU_FEATURE(dc, VIS1);
3751 gen_op_load_fpr_DT0(DFPREG(rs1));
3752 gen_op_load_fpr_DT1(DFPREG(rs2));
3753 tcg_gen_helper_0_0(helper_fmuld8ulx16);
3754 gen_op_store_DT0_fpr(DFPREG(rd));
3755 break;
3756 case 0x03a: /* VIS I fpack32 */
3757 case 0x03b: /* VIS I fpack16 */
3758 case 0x03d: /* VIS I fpackfix */
3759 case 0x03e: /* VIS I pdist */
3760 // XXX
3761 goto illegal_insn;
3762 case 0x048: /* VIS I faligndata */
3763 CHECK_FPU_FEATURE(dc, VIS1);
3764 gen_op_load_fpr_DT0(DFPREG(rs1));
3765 gen_op_load_fpr_DT1(DFPREG(rs2));
3766 tcg_gen_helper_0_0(helper_faligndata);
3767 gen_op_store_DT0_fpr(DFPREG(rd));
3768 break;
3769 case 0x04b: /* VIS I fpmerge */
3770 CHECK_FPU_FEATURE(dc, VIS1);
3771 gen_op_load_fpr_DT0(DFPREG(rs1));
3772 gen_op_load_fpr_DT1(DFPREG(rs2));
3773 tcg_gen_helper_0_0(helper_fpmerge);
3774 gen_op_store_DT0_fpr(DFPREG(rd));
3775 break;
3776 case 0x04c: /* VIS II bshuffle */
3777 // XXX
3778 goto illegal_insn;
3779 case 0x04d: /* VIS I fexpand */
3780 CHECK_FPU_FEATURE(dc, VIS1);
3781 gen_op_load_fpr_DT0(DFPREG(rs1));
3782 gen_op_load_fpr_DT1(DFPREG(rs2));
3783 tcg_gen_helper_0_0(helper_fexpand);
3784 gen_op_store_DT0_fpr(DFPREG(rd));
3785 break;
3786 case 0x050: /* VIS I fpadd16 */
3787 CHECK_FPU_FEATURE(dc, VIS1);
3788 gen_op_load_fpr_DT0(DFPREG(rs1));
3789 gen_op_load_fpr_DT1(DFPREG(rs2));
3790 tcg_gen_helper_0_0(helper_fpadd16);
3791 gen_op_store_DT0_fpr(DFPREG(rd));
3792 break;
3793 case 0x051: /* VIS I fpadd16s */
3794 CHECK_FPU_FEATURE(dc, VIS1);
3795 gen_op_load_fpr_FT0(rs1);
3796 gen_op_load_fpr_FT1(rs2);
3797 tcg_gen_helper_0_0(helper_fpadd16s);
3798 gen_op_store_FT0_fpr(rd);
3799 break;
3800 case 0x052: /* VIS I fpadd32 */
3801 CHECK_FPU_FEATURE(dc, VIS1);
3802 gen_op_load_fpr_DT0(DFPREG(rs1));
3803 gen_op_load_fpr_DT1(DFPREG(rs2));
3804 tcg_gen_helper_0_0(helper_fpadd32);
3805 gen_op_store_DT0_fpr(DFPREG(rd));
3806 break;
3807 case 0x053: /* VIS I fpadd32s */
3808 CHECK_FPU_FEATURE(dc, VIS1);
3809 gen_op_load_fpr_FT0(rs1);
3810 gen_op_load_fpr_FT1(rs2);
3811 tcg_gen_helper_0_0(helper_fpadd32s);
3812 gen_op_store_FT0_fpr(rd);
3813 break;
3814 case 0x054: /* VIS I fpsub16 */
3815 CHECK_FPU_FEATURE(dc, VIS1);
3816 gen_op_load_fpr_DT0(DFPREG(rs1));
3817 gen_op_load_fpr_DT1(DFPREG(rs2));
3818 tcg_gen_helper_0_0(helper_fpsub16);
3819 gen_op_store_DT0_fpr(DFPREG(rd));
3820 break;
3821 case 0x055: /* VIS I fpsub16s */
3822 CHECK_FPU_FEATURE(dc, VIS1);
3823 gen_op_load_fpr_FT0(rs1);
3824 gen_op_load_fpr_FT1(rs2);
3825 tcg_gen_helper_0_0(helper_fpsub16s);
3826 gen_op_store_FT0_fpr(rd);
3827 break;
3828 case 0x056: /* VIS I fpsub32 */
3829 CHECK_FPU_FEATURE(dc, VIS1);
3830 gen_op_load_fpr_DT0(DFPREG(rs1));
3831 gen_op_load_fpr_DT1(DFPREG(rs2));
3832 tcg_gen_helper_0_0(helper_fpadd32);
3833 gen_op_store_DT0_fpr(DFPREG(rd));
3834 break;
3835 case 0x057: /* VIS I fpsub32s */
3836 CHECK_FPU_FEATURE(dc, VIS1);
3837 gen_op_load_fpr_FT0(rs1);
3838 gen_op_load_fpr_FT1(rs2);
3839 tcg_gen_helper_0_0(helper_fpsub32s);
3840 gen_op_store_FT0_fpr(rd);
3841 break;
3842 case 0x060: /* VIS I fzero */
3843 CHECK_FPU_FEATURE(dc, VIS1);
3844 tcg_gen_helper_0_0(helper_movl_DT0_0);
3845 gen_op_store_DT0_fpr(DFPREG(rd));
3846 break;
3847 case 0x061: /* VIS I fzeros */
3848 CHECK_FPU_FEATURE(dc, VIS1);
3849 tcg_gen_helper_0_0(helper_movl_FT0_0);
3850 gen_op_store_FT0_fpr(rd);
3851 break;
3852 case 0x062: /* VIS I fnor */
3853 CHECK_FPU_FEATURE(dc, VIS1);
3854 gen_op_load_fpr_DT0(DFPREG(rs1));
3855 gen_op_load_fpr_DT1(DFPREG(rs2));
3856 tcg_gen_helper_0_0(helper_fnor);
3857 gen_op_store_DT0_fpr(DFPREG(rd));
3858 break;
3859 case 0x063: /* VIS I fnors */
3860 CHECK_FPU_FEATURE(dc, VIS1);
3861 gen_op_load_fpr_FT0(rs1);
3862 gen_op_load_fpr_FT1(rs2);
3863 tcg_gen_helper_0_0(helper_fnors);
3864 gen_op_store_FT0_fpr(rd);
3865 break;
3866 case 0x064: /* VIS I fandnot2 */
3867 CHECK_FPU_FEATURE(dc, VIS1);
3868 gen_op_load_fpr_DT1(DFPREG(rs1));
3869 gen_op_load_fpr_DT0(DFPREG(rs2));
3870 tcg_gen_helper_0_0(helper_fandnot);
3871 gen_op_store_DT0_fpr(DFPREG(rd));
3872 break;
3873 case 0x065: /* VIS I fandnot2s */
3874 CHECK_FPU_FEATURE(dc, VIS1);
3875 gen_op_load_fpr_FT1(rs1);
3876 gen_op_load_fpr_FT0(rs2);
3877 tcg_gen_helper_0_0(helper_fandnots);
3878 gen_op_store_FT0_fpr(rd);
3879 break;
3880 case 0x066: /* VIS I fnot2 */
3881 CHECK_FPU_FEATURE(dc, VIS1);
3882 gen_op_load_fpr_DT1(DFPREG(rs2));
3883 tcg_gen_helper_0_0(helper_fnot);
3884 gen_op_store_DT0_fpr(DFPREG(rd));
3885 break;
3886 case 0x067: /* VIS I fnot2s */
3887 CHECK_FPU_FEATURE(dc, VIS1);
3888 gen_op_load_fpr_FT1(rs2);
3889 tcg_gen_helper_0_0(helper_fnot);
3890 gen_op_store_FT0_fpr(rd);
3891 break;
3892 case 0x068: /* VIS I fandnot1 */
3893 CHECK_FPU_FEATURE(dc, VIS1);
3894 gen_op_load_fpr_DT0(DFPREG(rs1));
3895 gen_op_load_fpr_DT1(DFPREG(rs2));
3896 tcg_gen_helper_0_0(helper_fandnot);
3897 gen_op_store_DT0_fpr(DFPREG(rd));
3898 break;
3899 case 0x069: /* VIS I fandnot1s */
3900 CHECK_FPU_FEATURE(dc, VIS1);
3901 gen_op_load_fpr_FT0(rs1);
3902 gen_op_load_fpr_FT1(rs2);
3903 tcg_gen_helper_0_0(helper_fandnots);
3904 gen_op_store_FT0_fpr(rd);
3905 break;
3906 case 0x06a: /* VIS I fnot1 */
3907 CHECK_FPU_FEATURE(dc, VIS1);
3908 gen_op_load_fpr_DT1(DFPREG(rs1));
3909 tcg_gen_helper_0_0(helper_fnot);
3910 gen_op_store_DT0_fpr(DFPREG(rd));
3911 break;
3912 case 0x06b: /* VIS I fnot1s */
3913 CHECK_FPU_FEATURE(dc, VIS1);
3914 gen_op_load_fpr_FT1(rs1);
3915 tcg_gen_helper_0_0(helper_fnot);
3916 gen_op_store_FT0_fpr(rd);
3917 break;
3918 case 0x06c: /* VIS I fxor */
3919 CHECK_FPU_FEATURE(dc, VIS1);
3920 gen_op_load_fpr_DT0(DFPREG(rs1));
3921 gen_op_load_fpr_DT1(DFPREG(rs2));
3922 tcg_gen_helper_0_0(helper_fxor);
3923 gen_op_store_DT0_fpr(DFPREG(rd));
3924 break;
3925 case 0x06d: /* VIS I fxors */
3926 CHECK_FPU_FEATURE(dc, VIS1);
3927 gen_op_load_fpr_FT0(rs1);
3928 gen_op_load_fpr_FT1(rs2);
3929 tcg_gen_helper_0_0(helper_fxors);
3930 gen_op_store_FT0_fpr(rd);
3931 break;
3932 case 0x06e: /* VIS I fnand */
3933 CHECK_FPU_FEATURE(dc, VIS1);
3934 gen_op_load_fpr_DT0(DFPREG(rs1));
3935 gen_op_load_fpr_DT1(DFPREG(rs2));
3936 tcg_gen_helper_0_0(helper_fnand);
3937 gen_op_store_DT0_fpr(DFPREG(rd));
3938 break;
3939 case 0x06f: /* VIS I fnands */
3940 CHECK_FPU_FEATURE(dc, VIS1);
3941 gen_op_load_fpr_FT0(rs1);
3942 gen_op_load_fpr_FT1(rs2);
3943 tcg_gen_helper_0_0(helper_fnands);
3944 gen_op_store_FT0_fpr(rd);
3945 break;
3946 case 0x070: /* VIS I fand */
3947 CHECK_FPU_FEATURE(dc, VIS1);
3948 gen_op_load_fpr_DT0(DFPREG(rs1));
3949 gen_op_load_fpr_DT1(DFPREG(rs2));
3950 tcg_gen_helper_0_0(helper_fand);
3951 gen_op_store_DT0_fpr(DFPREG(rd));
3952 break;
3953 case 0x071: /* VIS I fands */
3954 CHECK_FPU_FEATURE(dc, VIS1);
3955 gen_op_load_fpr_FT0(rs1);
3956 gen_op_load_fpr_FT1(rs2);
3957 tcg_gen_helper_0_0(helper_fands);
3958 gen_op_store_FT0_fpr(rd);
3959 break;
3960 case 0x072: /* VIS I fxnor */
3961 CHECK_FPU_FEATURE(dc, VIS1);
3962 gen_op_load_fpr_DT0(DFPREG(rs1));
3963 gen_op_load_fpr_DT1(DFPREG(rs2));
3964 tcg_gen_helper_0_0(helper_fxnor);
3965 gen_op_store_DT0_fpr(DFPREG(rd));
3966 break;
3967 case 0x073: /* VIS I fxnors */
3968 CHECK_FPU_FEATURE(dc, VIS1);
3969 gen_op_load_fpr_FT0(rs1);
3970 gen_op_load_fpr_FT1(rs2);
3971 tcg_gen_helper_0_0(helper_fxnors);
3972 gen_op_store_FT0_fpr(rd);
3973 break;
3974 case 0x074: /* VIS I fsrc1 */
3975 CHECK_FPU_FEATURE(dc, VIS1);
3976 gen_op_load_fpr_DT0(DFPREG(rs1));
3977 gen_op_store_DT0_fpr(DFPREG(rd));
3978 break;
3979 case 0x075: /* VIS I fsrc1s */
3980 CHECK_FPU_FEATURE(dc, VIS1);
3981 gen_op_load_fpr_FT0(rs1);
3982 gen_op_store_FT0_fpr(rd);
3983 break;
3984 case 0x076: /* VIS I fornot2 */
3985 CHECK_FPU_FEATURE(dc, VIS1);
3986 gen_op_load_fpr_DT1(DFPREG(rs1));
3987 gen_op_load_fpr_DT0(DFPREG(rs2));
3988 tcg_gen_helper_0_0(helper_fornot);
3989 gen_op_store_DT0_fpr(DFPREG(rd));
3990 break;
3991 case 0x077: /* VIS I fornot2s */
3992 CHECK_FPU_FEATURE(dc, VIS1);
3993 gen_op_load_fpr_FT1(rs1);
3994 gen_op_load_fpr_FT0(rs2);
3995 tcg_gen_helper_0_0(helper_fornots);
3996 gen_op_store_FT0_fpr(rd);
3997 break;
3998 case 0x078: /* VIS I fsrc2 */
3999 CHECK_FPU_FEATURE(dc, VIS1);
4000 gen_op_load_fpr_DT0(DFPREG(rs2));
4001 gen_op_store_DT0_fpr(DFPREG(rd));
4002 break;
4003 case 0x079: /* VIS I fsrc2s */
4004 CHECK_FPU_FEATURE(dc, VIS1);
4005 gen_op_load_fpr_FT0(rs2);
4006 gen_op_store_FT0_fpr(rd);
4007 break;
4008 case 0x07a: /* VIS I fornot1 */
4009 CHECK_FPU_FEATURE(dc, VIS1);
4010 gen_op_load_fpr_DT0(DFPREG(rs1));
4011 gen_op_load_fpr_DT1(DFPREG(rs2));
4012 tcg_gen_helper_0_0(helper_fornot);
4013 gen_op_store_DT0_fpr(DFPREG(rd));
4014 break;
4015 case 0x07b: /* VIS I fornot1s */
4016 CHECK_FPU_FEATURE(dc, VIS1);
4017 gen_op_load_fpr_FT0(rs1);
4018 gen_op_load_fpr_FT1(rs2);
4019 tcg_gen_helper_0_0(helper_fornots);
4020 gen_op_store_FT0_fpr(rd);
4021 break;
4022 case 0x07c: /* VIS I for */
4023 CHECK_FPU_FEATURE(dc, VIS1);
4024 gen_op_load_fpr_DT0(DFPREG(rs1));
4025 gen_op_load_fpr_DT1(DFPREG(rs2));
4026 tcg_gen_helper_0_0(helper_for);
4027 gen_op_store_DT0_fpr(DFPREG(rd));
4028 break;
4029 case 0x07d: /* VIS I fors */
4030 CHECK_FPU_FEATURE(dc, VIS1);
4031 gen_op_load_fpr_FT0(rs1);
4032 gen_op_load_fpr_FT1(rs2);
4033 tcg_gen_helper_0_0(helper_fors);
4034 gen_op_store_FT0_fpr(rd);
4035 break;
4036 case 0x07e: /* VIS I fone */
4037 CHECK_FPU_FEATURE(dc, VIS1);
4038 tcg_gen_helper_0_0(helper_movl_DT0_1);
4039 gen_op_store_DT0_fpr(DFPREG(rd));
4040 break;
4041 case 0x07f: /* VIS I fones */
4042 CHECK_FPU_FEATURE(dc, VIS1);
4043 tcg_gen_helper_0_0(helper_movl_FT0_1);
4044 gen_op_store_FT0_fpr(rd);
4045 break;
4046 case 0x080: /* VIS I shutdown */
4047 case 0x081: /* VIS II siam */
4048 // XXX
4049 goto illegal_insn;
4050 default:
4051 goto illegal_insn;
4052 }
4053 #else
4054 goto ncp_insn;
4055 #endif
4056 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4057 #ifdef TARGET_SPARC64
4058 goto illegal_insn;
4059 #else
4060 goto ncp_insn;
4061 #endif
4062 #ifdef TARGET_SPARC64
4063 } else if (xop == 0x39) { /* V9 return */
4064 TCGv r_const;
4065
4066 save_state(dc, cpu_cond);
4067 cpu_src1 = get_src1(insn, cpu_src1);
4068 if (IS_IMM) { /* immediate */
4069 rs2 = GET_FIELDs(insn, 19, 31);
4070 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4071 } else { /* register */
4072 rs2 = GET_FIELD(insn, 27, 31);
4073 if (rs2) {
4074 gen_movl_reg_TN(rs2, cpu_src2);
4075 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4076 } else
4077 tcg_gen_mov_tl(cpu_dst, cpu_src1);
4078 }
4079 tcg_gen_helper_0_0(helper_restore);
4080 gen_mov_pc_npc(dc, cpu_cond);
4081 r_const = tcg_const_i32(3);
4082 tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4083 tcg_temp_free(r_const);
4084 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4085 dc->npc = DYNAMIC_PC;
4086 goto jmp_insn;
4087 #endif
4088 } else {
4089 cpu_src1 = get_src1(insn, cpu_src1);
4090 if (IS_IMM) { /* immediate */
4091 rs2 = GET_FIELDs(insn, 19, 31);
4092 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4093 } else { /* register */
4094 rs2 = GET_FIELD(insn, 27, 31);
4095 if (rs2) {
4096 gen_movl_reg_TN(rs2, cpu_src2);
4097 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4098 } else
4099 tcg_gen_mov_tl(cpu_dst, cpu_src1);
4100 }
4101 switch (xop) {
4102 case 0x38: /* jmpl */
4103 {
4104 TCGv r_const;
4105
4106 r_const = tcg_const_tl(dc->pc);
4107 gen_movl_TN_reg(rd, r_const);
4108 tcg_temp_free(r_const);
4109 gen_mov_pc_npc(dc, cpu_cond);
4110 r_const = tcg_const_i32(3);
4111 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4112 r_const);
4113 tcg_temp_free(r_const);
4114 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4115 dc->npc = DYNAMIC_PC;
4116 }
4117 goto jmp_insn;
4118 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4119 case 0x39: /* rett, V9 return */
4120 {
4121 TCGv r_const;
4122
4123 if (!supervisor(dc))
4124 goto priv_insn;
4125 gen_mov_pc_npc(dc, cpu_cond);
4126 r_const = tcg_const_i32(3);
4127 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4128 r_const);
4129 tcg_temp_free(r_const);
4130 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4131 dc->npc = DYNAMIC_PC;
4132 tcg_gen_helper_0_0(helper_rett);
4133 }
4134 goto jmp_insn;
4135 #endif
4136 case 0x3b: /* flush */
4137 if (!((dc)->features & CPU_FEATURE_FLUSH))
4138 goto unimp_flush;
4139 tcg_gen_helper_0_1(helper_flush, cpu_dst);
4140 break;
4141 case 0x3c: /* save */
4142 save_state(dc, cpu_cond);
4143 tcg_gen_helper_0_0(helper_save);
4144 gen_movl_TN_reg(rd, cpu_dst);
4145 break;
4146 case 0x3d: /* restore */
4147 save_state(dc, cpu_cond);
4148 tcg_gen_helper_0_0(helper_restore);
4149 gen_movl_TN_reg(rd, cpu_dst);
4150 break;
4151 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4152 case 0x3e: /* V9 done/retry */
4153 {
4154 switch (rd) {
4155 case 0:
4156 if (!supervisor(dc))
4157 goto priv_insn;
4158 dc->npc = DYNAMIC_PC;
4159 dc->pc = DYNAMIC_PC;
4160 tcg_gen_helper_0_0(helper_done);
4161 goto jmp_insn;
4162 case 1:
4163 if (!supervisor(dc))
4164 goto priv_insn;
4165 dc->npc = DYNAMIC_PC;
4166 dc->pc = DYNAMIC_PC;
4167 tcg_gen_helper_0_0(helper_retry);
4168 goto jmp_insn;
4169 default:
4170 goto illegal_insn;
4171 }
4172 }
4173 break;
4174 #endif
4175 default:
4176 goto illegal_insn;
4177 }
4178 }
4179 break;
4180 }
4181 break;
4182 case 3: /* load/store instructions */
4183 {
4184 unsigned int xop = GET_FIELD(insn, 7, 12);
4185
4186 cpu_src1 = get_src1(insn, cpu_src1);
4187 if (xop == 0x3c || xop == 0x3e)
4188 {
4189 rs2 = GET_FIELD(insn, 27, 31);
4190 gen_movl_reg_TN(rs2, cpu_src2);
4191 }
4192 else if (IS_IMM) { /* immediate */
4193 rs2 = GET_FIELDs(insn, 19, 31);
4194 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4195 } else { /* register */
4196 rs2 = GET_FIELD(insn, 27, 31);
4197 if (rs2 != 0) {
4198 gen_movl_reg_TN(rs2, cpu_src2);
4199 tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4200 } else
4201 tcg_gen_mov_tl(cpu_addr, cpu_src1);
4202 }
4203 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4204 (xop > 0x17 && xop <= 0x1d ) ||
4205 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4206 switch (xop) {
4207 case 0x0: /* load unsigned word */
4208 ABI32_MASK(cpu_addr);
4209 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4210 break;
4211 case 0x1: /* load unsigned byte */
4212 ABI32_MASK(cpu_addr);
4213 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4214 break;
4215 case 0x2: /* load unsigned halfword */
4216 ABI32_MASK(cpu_addr);
4217 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4218 break;
4219 case 0x3: /* load double word */
4220 if (rd & 1)
4221 goto illegal_insn;
4222 else {
4223 TCGv r_const;
4224
4225 save_state(dc, cpu_cond);
4226 r_const = tcg_const_i32(7);
4227 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4228 r_const); // XXX remove
4229 tcg_temp_free(r_const);
4230 ABI32_MASK(cpu_addr);
4231 tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4232 tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4233 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4234 gen_movl_TN_reg(rd + 1, cpu_tmp0);
4235 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4236 tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4237 tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4238 }
4239 break;
4240 case 0x9: /* load signed byte */
4241 ABI32_MASK(cpu_addr);
4242 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4243 break;
4244 case 0xa: /* load signed halfword */
4245 ABI32_MASK(cpu_addr);
4246 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4247 break;
4248 case 0xd: /* ldstub -- XXX: should be atomically */
4249 {
4250 TCGv r_const;
4251
4252 ABI32_MASK(cpu_addr);
4253 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4254 r_const = tcg_const_tl(0xff);
4255 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4256 tcg_temp_free(r_const);
4257 }
4258 break;
4259 case 0x0f: /* swap register with memory. Also
4260 atomically */
4261 CHECK_IU_FEATURE(dc, SWAP);
4262 gen_movl_reg_TN(rd, cpu_val);
4263 ABI32_MASK(cpu_addr);
4264 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4265 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4266 tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4267 break;
4268 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4269 case 0x10: /* load word alternate */
4270 #ifndef TARGET_SPARC64
4271 if (IS_IMM)
4272 goto illegal_insn;
4273 if (!supervisor(dc))
4274 goto priv_insn;
4275 #endif
4276 save_state(dc, cpu_cond);
4277 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4278 break;
4279 case 0x11: /* load unsigned byte alternate */
4280 #ifndef TARGET_SPARC64
4281 if (IS_IMM)
4282 goto illegal_insn;
4283 if (!supervisor(dc))
4284 goto priv_insn;
4285 #endif
4286 save_state(dc, cpu_cond);
4287 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4288 break;
4289 case 0x12: /* load unsigned halfword alternate */
4290 #ifndef TARGET_SPARC64
4291 if (IS_IMM)
4292 goto illegal_insn;
4293 if (!supervisor(dc))
4294 goto priv_insn;
4295 #endif
4296 save_state(dc, cpu_cond);
4297 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4298 break;
4299 case 0x13: /* load double word alternate */
4300 #ifndef TARGET_SPARC64
4301 if (IS_IMM)
4302 goto illegal_insn;
4303 if (!supervisor(dc))
4304 goto priv_insn;
4305 #endif
4306 if (rd & 1)
4307 goto illegal_insn;
4308 save_state(dc, cpu_cond);
4309 gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4310 gen_movl_TN_reg(rd + 1, cpu_tmp0);
4311 break;
4312 case 0x19: /* load signed byte alternate */
4313 #ifndef TARGET_SPARC64
4314 if (IS_IMM)
4315 goto illegal_insn;
4316 if (!supervisor(dc))
4317 goto priv_insn;
4318 #endif
4319 save_state(dc, cpu_cond);
4320 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4321 break;
4322 case 0x1a: /* load signed halfword alternate */
4323 #ifndef TARGET_SPARC64
4324 if (IS_IMM)
4325 goto illegal_insn;
4326 if (!supervisor(dc))
4327 goto priv_insn;
4328 #endif
4329 save_state(dc, cpu_cond);
4330 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4331 break;
4332 case 0x1d: /* ldstuba -- XXX: should be atomically */
4333 #ifndef TARGET_SPARC64
4334 if (IS_IMM)
4335 goto illegal_insn;
4336 if (!supervisor(dc))
4337 goto priv_insn;
4338 #endif
4339 save_state(dc, cpu_cond);
4340 gen_ldstub_asi(cpu_val, cpu_addr, insn);
4341 break;
4342 case 0x1f: /* swap reg with alt. memory. Also
4343 atomically */
4344 CHECK_IU_FEATURE(dc, SWAP);
4345 #ifndef TARGET_SPARC64
4346 if (IS_IMM)
4347 goto illegal_insn;
4348 if (!supervisor(dc))
4349 goto priv_insn;
4350 #endif
4351 save_state(dc, cpu_cond);
4352 gen_movl_reg_TN(rd, cpu_val);
4353 gen_swap_asi(cpu_val, cpu_addr, insn);
4354 break;
4355
4356 #ifndef TARGET_SPARC64
4357 case 0x30: /* ldc */
4358 case 0x31: /* ldcsr */
4359 case 0x33: /* lddc */
4360 goto ncp_insn;
4361 #endif
4362 #endif
4363 #ifdef TARGET_SPARC64
4364 case 0x08: /* V9 ldsw */
4365 ABI32_MASK(cpu_addr);
4366 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4367 break;
4368 case 0x0b: /* V9 ldx */
4369 ABI32_MASK(cpu_addr);
4370 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4371 break;
4372 case 0x18: /* V9 ldswa */
4373 save_state(dc, cpu_cond);
4374 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4375 break;
4376 case 0x1b: /* V9 ldxa */
4377 save_state(dc, cpu_cond);
4378 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4379 break;
4380 case 0x2d: /* V9 prefetch, no effect */
4381 goto skip_move;
4382 case 0x30: /* V9 ldfa */
4383 save_state(dc, cpu_cond);
4384 gen_ldf_asi(cpu_addr, insn, 4, rd);
4385 goto skip_move;
4386 case 0x33: /* V9 lddfa */
4387 save_state(dc, cpu_cond);
4388 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4389 goto skip_move;
4390 case 0x3d: /* V9 prefetcha, no effect */
4391 goto skip_move;
4392 case 0x32: /* V9 ldqfa */
4393 CHECK_FPU_FEATURE(dc, FLOAT128);
4394 save_state(dc, cpu_cond);
4395 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4396 goto skip_move;
4397 #endif
4398 default:
4399 goto illegal_insn;
4400 }
4401 gen_movl_TN_reg(rd, cpu_val);
4402 #ifdef TARGET_SPARC64
4403 skip_move: ;
4404 #endif
4405 } else if (xop >= 0x20 && xop < 0x24) {
4406 if (gen_trap_ifnofpu(dc, cpu_cond))
4407 goto jmp_insn;
4408 save_state(dc, cpu_cond);
4409 switch (xop) {
4410 case 0x20: /* load fpreg */
4411 ABI32_MASK(cpu_addr);
4412 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4413 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4414 offsetof(CPUState, fpr[rd]));
4415 break;
4416 case 0x21: /* load fsr */
4417 ABI32_MASK(cpu_addr);
4418 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4419 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4420 offsetof(CPUState, ft0));
4421 tcg_gen_helper_0_0(helper_ldfsr);
4422 break;
4423 case 0x22: /* load quad fpreg */
4424 {
4425 TCGv r_const;
4426
4427 CHECK_FPU_FEATURE(dc, FLOAT128);
4428 r_const = tcg_const_i32(dc->mem_idx);
4429 tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4430 tcg_temp_free(r_const);
4431 gen_op_store_QT0_fpr(QFPREG(rd));
4432 }
4433 break;
4434 case 0x23: /* load double fpreg */
4435 {
4436 TCGv r_const;
4437
4438 r_const = tcg_const_i32(dc->mem_idx);
4439 tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4440 tcg_temp_free(r_const);
4441 gen_op_store_DT0_fpr(DFPREG(rd));
4442 }
4443 break;
4444 default:
4445 goto illegal_insn;
4446 }
4447 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4448 xop == 0xe || xop == 0x1e) {
4449 gen_movl_reg_TN(rd, cpu_val);
4450 switch (xop) {
4451 case 0x4: /* store word */
4452 ABI32_MASK(cpu_addr);
4453 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4454 break;
4455 case 0x5: /* store byte */
4456 ABI32_MASK(cpu_addr);
4457 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4458 break;
4459 case 0x6: /* store halfword */
4460 ABI32_MASK(cpu_addr);
4461 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4462 break;
4463 case 0x7: /* store double word */
4464 if (rd & 1)
4465 goto illegal_insn;
4466 else {
4467 TCGv r_low, r_const;
4468
4469 save_state(dc, cpu_cond);
4470 ABI32_MASK(cpu_addr);
4471 r_const = tcg_const_i32(7);
4472 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4473 r_const); // XXX remove
4474 tcg_temp_free(r_const);
4475 r_low = tcg_temp_new(TCG_TYPE_TL);
4476 gen_movl_reg_TN(rd + 1, r_low);
4477 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4478 r_low);
4479 tcg_temp_free(r_low);
4480 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4481 }
4482 break;
4483 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4484 case 0x14: /* store word alternate */
4485 #ifndef TARGET_SPARC64
4486 if (IS_IMM)
4487 goto illegal_insn;
4488 if (!supervisor(dc))
4489 goto priv_insn;
4490 #endif
4491 save_state(dc, cpu_cond);
4492 gen_st_asi(cpu_val, cpu_addr, insn, 4);
4493 break;
4494 case 0x15: /* store byte alternate */
4495 #ifndef TARGET_SPARC64
4496 if (IS_IMM)
4497 goto illegal_insn;
4498 if (!supervisor(dc))
4499 goto priv_insn;
4500 #endif
4501 save_state(dc, cpu_cond);
4502 gen_st_asi(cpu_val, cpu_addr, insn, 1);
4503 break;
4504 case 0x16: /* store halfword alternate */
4505 #ifndef TARGET_SPARC64
4506 if (IS_IMM)
4507 goto illegal_insn;
4508 if (!supervisor(dc))
4509 goto priv_insn;
4510 #endif
4511 save_state(dc, cpu_cond);
4512 gen_st_asi(cpu_val, cpu_addr, insn, 2);
4513 break;
4514 case 0x17: /* store double word alternate */
4515 #ifndef TARGET_SPARC64
4516 if (IS_IMM)
4517 goto illegal_insn;
4518 if (!supervisor(dc))
4519 goto priv_insn;
4520 #endif
4521 if (rd & 1)
4522 goto illegal_insn;
4523 else {
4524 save_state(dc, cpu_cond);
4525 gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4526 }
4527 break;
4528 #endif
4529 #ifdef TARGET_SPARC64
4530 case 0x0e: /* V9 stx */
4531 ABI32_MASK(cpu_addr);
4532 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4533 break;
4534 case 0x1e: /* V9 stxa */
4535 save_state(dc, cpu_cond);
4536 gen_st_asi(cpu_val, cpu_addr, insn, 8);
4537 break;
4538 #endif
4539 default:
4540 goto illegal_insn;
4541 }
4542 } else if (xop > 0x23 && xop < 0x28) {
4543 if (gen_trap_ifnofpu(dc, cpu_cond))
4544 goto jmp_insn;
4545 save_state(dc, cpu_cond);
4546 switch (xop) {
4547 case 0x24: /* store fpreg */
4548 ABI32_MASK(cpu_addr);
4549 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4550 offsetof(CPUState, fpr[rd]));
4551 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4552 break;
4553 case 0x25: /* stfsr, V9 stxfsr */
4554 ABI32_MASK(cpu_addr);
4555 tcg_gen_helper_0_0(helper_stfsr);
4556 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4557 offsetof(CPUState, ft0));
4558 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4559 break;
4560 case 0x26:
4561 #ifdef TARGET_SPARC64
4562 /* V9 stqf, store quad fpreg */
4563 {
4564 TCGv r_const;
4565
4566 CHECK_FPU_FEATURE(dc, FLOAT128);
4567 gen_op_load_fpr_QT0(QFPREG(rd));
4568 r_const = tcg_const_i32(dc->mem_idx);
4569 tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4570 tcg_temp_free(r_const);
4571 }
4572 break;
4573 #else /* !TARGET_SPARC64 */
4574 /* stdfq, store floating point queue */
4575 #if defined(CONFIG_USER_ONLY)
4576 goto illegal_insn;
4577 #else
4578 if (!supervisor(dc))
4579 goto priv_insn;
4580 if (gen_trap_ifnofpu(dc, cpu_cond))
4581 goto jmp_insn;
4582 goto nfq_insn;
4583 #endif
4584 #endif
4585 case 0x27: /* store double fpreg */
4586 {
4587 TCGv r_const;
4588
4589 gen_op_load_fpr_DT0(DFPREG(rd));
4590 r_const = tcg_const_i32(dc->mem_idx);
4591 tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4592 tcg_temp_free(r_const);
4593 }
4594 break;
4595 default:
4596 goto illegal_insn;
4597 }
4598 } else if (xop > 0x33 && xop < 0x3f) {
4599 save_state(dc, cpu_cond);
4600 switch (xop) {
4601 #ifdef TARGET_SPARC64
4602 case 0x34: /* V9 stfa */
4603 gen_op_load_fpr_FT0(rd);
4604 gen_stf_asi(cpu_addr, insn, 4, rd);
4605 break;
4606 case 0x36: /* V9 stqfa */
4607 {
4608 TCGv r_const;
4609
4610 CHECK_FPU_FEATURE(dc, FLOAT128);
4611 r_const = tcg_const_i32(7);
4612 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4613 r_const);
4614 tcg_temp_free(r_const);
4615 gen_op_load_fpr_QT0(QFPREG(rd));
4616 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4617 }
4618 break;
4619 case 0x37: /* V9 stdfa */
4620 gen_op_load_fpr_DT0(DFPREG(rd));
4621 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4622 break;
4623 case 0x3c: /* V9 casa */
4624 gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4625 gen_movl_TN_reg(rd, cpu_val);
4626 break;
4627 case 0x3e: /* V9 casxa */
4628 gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4629 gen_movl_TN_reg(rd, cpu_val);
4630 break;
4631 #else
4632 case 0x34: /* stc */
4633 case 0x35: /* stcsr */
4634 case 0x36: /* stdcq */
4635 case 0x37: /* stdc */
4636 goto ncp_insn;
4637 #endif
4638 default:
4639 goto illegal_insn;
4640 }
4641 }
4642 else
4643 goto illegal_insn;
4644 }
4645 break;
4646 }
4647 /* default case for non jump instructions */
4648 if (dc->npc == DYNAMIC_PC) {
4649 dc->pc = DYNAMIC_PC;
4650 gen_op_next_insn();
4651 } else if (dc->npc == JUMP_PC) {
4652 /* we can do a static jump */
4653 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4654 dc->is_br = 1;
4655 } else {
4656 dc->pc = dc->npc;
4657 dc->npc = dc->npc + 4;
4658 }
4659 jmp_insn:
4660 return;
4661 illegal_insn:
4662 {
4663 TCGv r_const;
4664
4665 save_state(dc, cpu_cond);
4666 r_const = tcg_const_i32(TT_ILL_INSN);
4667 tcg_gen_helper_0_1(raise_exception, r_const);
4668 tcg_temp_free(r_const);
4669 dc->is_br = 1;
4670 }
4671 return;
4672 unimp_flush:
4673 {
4674 TCGv r_const;
4675
4676 save_state(dc, cpu_cond);
4677 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4678 tcg_gen_helper_0_1(raise_exception, r_const);
4679 tcg_temp_free(r_const);
4680 dc->is_br = 1;
4681 }
4682 return;
4683 #if !defined(CONFIG_USER_ONLY)
4684 priv_insn:
4685 {
4686 TCGv r_const;
4687
4688 save_state(dc, cpu_cond);
4689 r_const = tcg_const_i32(TT_PRIV_INSN);
4690 tcg_gen_helper_0_1(raise_exception, r_const);
4691 tcg_temp_free(r_const);
4692 dc->is_br = 1;
4693 }
4694 return;
4695 #endif
4696 nfpu_insn:
4697 save_state(dc, cpu_cond);
4698 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4699 dc->is_br = 1;
4700 return;
4701 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4702 nfq_insn:
4703 save_state(dc, cpu_cond);
4704 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4705 dc->is_br = 1;
4706 return;
4707 #endif
4708 #ifndef TARGET_SPARC64
4709 ncp_insn:
4710 {
4711 TCGv r_const;
4712
4713 save_state(dc, cpu_cond);
4714 r_const = tcg_const_i32(TT_NCP_INSN);
4715 tcg_gen_helper_0_1(raise_exception, r_const);
4716 tcg_temp_free(r_const);
4717 dc->is_br = 1;
4718 }
4719 return;
4720 #endif
4721 }
4722
4723 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4724 int spc, CPUSPARCState *env)
4725 {
4726 target_ulong pc_start, last_pc;
4727 uint16_t *gen_opc_end;
4728 DisasContext dc1, *dc = &dc1;
4729 int j, lj = -1;
4730
4731 memset(dc, 0, sizeof(DisasContext));
4732 dc->tb = tb;
4733 pc_start = tb->pc;
4734 dc->pc = pc_start;
4735 last_pc = dc->pc;
4736 dc->npc = (target_ulong) tb->cs_base;
4737 dc->mem_idx = cpu_mmu_index(env);
4738 dc->features = env->features;
4739 if ((dc->features & CPU_FEATURE_FLOAT)) {
4740 dc->fpu_enabled = cpu_fpu_enabled(env);
4741 #if defined(CONFIG_USER_ONLY)
4742 dc->features |= CPU_FEATURE_FLOAT128;
4743 #endif
4744 } else
4745 dc->fpu_enabled = 0;
4746 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4747
4748 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4749 cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4750 cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4751
4752 do {
4753 if (env->nb_breakpoints > 0) {
4754 for(j = 0; j < env->nb_breakpoints; j++) {
4755 if (env->breakpoints[j] == dc->pc) {
4756 if (dc->pc != pc_start)
4757 save_state(dc, cpu_cond);
4758 tcg_gen_helper_0_0(helper_debug);
4759 tcg_gen_exit_tb(0);
4760 dc->is_br = 1;
4761 goto exit_gen_loop;
4762 }
4763 }
4764 }
4765 if (spc) {
4766 if (loglevel > 0)
4767 fprintf(logfile, "Search PC...\n");
4768 j = gen_opc_ptr - gen_opc_buf;
4769 if (lj < j) {
4770 lj++;
4771 while (lj < j)
4772 gen_opc_instr_start[lj++] = 0;
4773 gen_opc_pc[lj] = dc->pc;
4774 gen_opc_npc[lj] = dc->npc;
4775 gen_opc_instr_start[lj] = 1;
4776 }
4777 }
4778 last_pc = dc->pc;
4779 disas_sparc_insn(dc);
4780
4781 if (dc->is_br)
4782 break;
4783 /* if the next PC is different, we abort now */
4784 if (dc->pc != (last_pc + 4))
4785 break;
4786 /* if we reach a page boundary, we stop generation so that the
4787 PC of a TT_TFAULT exception is always in the right page */
4788 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4789 break;
4790 /* if single step mode, we generate only one instruction and
4791 generate an exception */
4792 if (env->singlestep_enabled) {
4793 tcg_gen_movi_tl(cpu_pc, dc->pc);
4794 tcg_gen_exit_tb(0);
4795 break;
4796 }
4797 } while ((gen_opc_ptr < gen_opc_end) &&
4798 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4799
4800 exit_gen_loop:
4801 tcg_temp_free(cpu_tmp64);
4802 tcg_temp_free(cpu_tmp32);
4803 tcg_temp_free(cpu_tmp0);
4804 if (!dc->is_br) {
4805 if (dc->pc != DYNAMIC_PC &&
4806 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4807 /* static PC and NPC: we can use direct chaining */
4808 gen_goto_tb(dc, 0, dc->pc, dc->npc);
4809 } else {
4810 if (dc->pc != DYNAMIC_PC)
4811 tcg_gen_movi_tl(cpu_pc, dc->pc);
4812 save_npc(dc, cpu_cond);
4813 tcg_gen_exit_tb(0);
4814 }
4815 }
4816 *gen_opc_ptr = INDEX_op_end;
4817 if (spc) {
4818 j = gen_opc_ptr - gen_opc_buf;
4819 lj++;
4820 while (lj <= j)
4821 gen_opc_instr_start[lj++] = 0;
4822 #if 0
4823 if (loglevel > 0) {
4824 page_dump(logfile);
4825 }
4826 #endif
4827 gen_opc_jump_pc[0] = dc->jump_pc[0];
4828 gen_opc_jump_pc[1] = dc->jump_pc[1];
4829 } else {
4830 tb->size = last_pc + 4 - pc_start;
4831 }
4832 #ifdef DEBUG_DISAS
4833 if (loglevel & CPU_LOG_TB_IN_ASM) {
4834 fprintf(logfile, "--------------\n");
4835 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4836 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4837 fprintf(logfile, "\n");
4838 }
4839 #endif
4840 return 0;
4841 }
4842
4843 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4844 {
4845 return gen_intermediate_code_internal(tb, 0, env);
4846 }
4847
4848 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4849 {
4850 return gen_intermediate_code_internal(tb, 1, env);
4851 }
4852
4853 void gen_intermediate_code_init(CPUSPARCState *env)
4854 {
4855 unsigned int i;
4856 static int inited;
4857 static const char * const gregnames[8] = {
4858 NULL, // g0 not used
4859 "g1",
4860 "g2",
4861 "g3",
4862 "g4",
4863 "g5",
4864 "g6",
4865 "g7",
4866 };
4867
4868 /* init various static tables */
4869 if (!inited) {
4870 inited = 1;
4871
4872 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4873 cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4874 offsetof(CPUState, regwptr),
4875 "regwptr");
4876 #ifdef TARGET_SPARC64
4877 cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4878 TCG_AREG0, offsetof(CPUState, xcc),
4879 "xcc");
4880 #endif
4881 /* XXX: T0 and T1 should be temporaries */
4882 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4883 TCG_AREG0, offsetof(CPUState, t0), "T0");
4884 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4885 TCG_AREG0, offsetof(CPUState, t1), "T1");
4886 cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4887 TCG_AREG0, offsetof(CPUState, cond),
4888 "cond");
4889 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4890 TCG_AREG0, offsetof(CPUState, cc_src),
4891 "cc_src");
4892 cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4893 offsetof(CPUState, cc_src2),
4894 "cc_src2");
4895 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4896 TCG_AREG0, offsetof(CPUState, cc_dst),
4897 "cc_dst");
4898 cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4899 TCG_AREG0, offsetof(CPUState, psr),
4900 "psr");
4901 cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4902 TCG_AREG0, offsetof(CPUState, fsr),
4903 "fsr");
4904 cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4905 TCG_AREG0, offsetof(CPUState, pc),
4906 "pc");
4907 cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4908 TCG_AREG0, offsetof(CPUState, npc),
4909 "npc");
4910 for (i = 1; i < 8; i++)
4911 cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4912 offsetof(CPUState, gregs[i]),
4913 gregnames[i]);
4914 /* register helpers */
4915
4916 #undef DEF_HELPER
4917 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4918 #include "helper.h"
4919 }
4920 }
4921
4922 void gen_pc_load(CPUState *env, TranslationBlock *tb,
4923 unsigned long searched_pc, int pc_pos, void *puc)
4924 {
4925 target_ulong npc;
4926 env->pc = gen_opc_pc[pc_pos];
4927 npc = gen_opc_npc[pc_pos];
4928 if (npc == 1) {
4929 /* dynamic NPC: already stored */
4930 } else if (npc == 2) {
4931 target_ulong t2 = (target_ulong)(unsigned long)puc;
4932 /* jump PC: use T2 and the jump targets of the translation */
4933 if (t2)
4934 env->npc = gen_opc_jump_pc[0];
4935 else
4936 env->npc = gen_opc_jump_pc[1];
4937 } else {
4938 env->npc = npc;
4939 }
4940 }
Patches shipped by Fedora