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Re-add missing declaration for pci_hypercall_init
[qemu-kvm/fedora.git] / hw / cirrus_vga.c
blobee7ec1c1ec1a055d36640664b739bff0f97d40ad
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #ifndef _WIN32
35 #include <sys/mman.h>
36 #endif
37
38 /*
39 * TODO:
40 * - destination write mask support not complete (bits 5..7)
41 * - optimize linear mappings
42 * - optimize bitblt functions
43 */
44
45 //#define DEBUG_CIRRUS
46 //#define DEBUG_BITBLT
47
48 /***************************************
49 *
50 * definitions
51 *
52 ***************************************/
53
54 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
55
56 // ID
57 #define CIRRUS_ID_CLGD5422 (0x23<<2)
58 #define CIRRUS_ID_CLGD5426 (0x24<<2)
59 #define CIRRUS_ID_CLGD5424 (0x25<<2)
60 #define CIRRUS_ID_CLGD5428 (0x26<<2)
61 #define CIRRUS_ID_CLGD5430 (0x28<<2)
62 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
63 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
64 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
65
66 // sequencer 0x07
67 #define CIRRUS_SR7_BPP_VGA 0x00
68 #define CIRRUS_SR7_BPP_SVGA 0x01
69 #define CIRRUS_SR7_BPP_MASK 0x0e
70 #define CIRRUS_SR7_BPP_8 0x00
71 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
72 #define CIRRUS_SR7_BPP_24 0x04
73 #define CIRRUS_SR7_BPP_16 0x06
74 #define CIRRUS_SR7_BPP_32 0x08
75 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
76
77 // sequencer 0x0f
78 #define CIRRUS_MEMSIZE_512k 0x08
79 #define CIRRUS_MEMSIZE_1M 0x10
80 #define CIRRUS_MEMSIZE_2M 0x18
81 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
82
83 // sequencer 0x12
84 #define CIRRUS_CURSOR_SHOW 0x01
85 #define CIRRUS_CURSOR_HIDDENPEL 0x02
86 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
87
88 // sequencer 0x17
89 #define CIRRUS_BUSTYPE_VLBFAST 0x10
90 #define CIRRUS_BUSTYPE_PCI 0x20
91 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
92 #define CIRRUS_BUSTYPE_ISA 0x38
93 #define CIRRUS_MMIO_ENABLE 0x04
94 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
95 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
96
97 // control 0x0b
98 #define CIRRUS_BANKING_DUAL 0x01
99 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
100
101 // control 0x30
102 #define CIRRUS_BLTMODE_BACKWARDS 0x01
103 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
104 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
105 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
106 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
107 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
108 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
109 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
110 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
111 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
112 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
113
114 // control 0x31
115 #define CIRRUS_BLT_BUSY 0x01
116 #define CIRRUS_BLT_START 0x02
117 #define CIRRUS_BLT_RESET 0x04
118 #define CIRRUS_BLT_FIFOUSED 0x10
119 #define CIRRUS_BLT_AUTOSTART 0x80
120
121 // control 0x32
122 #define CIRRUS_ROP_0 0x00
123 #define CIRRUS_ROP_SRC_AND_DST 0x05
124 #define CIRRUS_ROP_NOP 0x06
125 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
126 #define CIRRUS_ROP_NOTDST 0x0b
127 #define CIRRUS_ROP_SRC 0x0d
128 #define CIRRUS_ROP_1 0x0e
129 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
130 #define CIRRUS_ROP_SRC_XOR_DST 0x59
131 #define CIRRUS_ROP_SRC_OR_DST 0x6d
132 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
133 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
134 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
135 #define CIRRUS_ROP_NOTSRC 0xd0
136 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
137 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
138
139 #define CIRRUS_ROP_NOP_INDEX 2
140 #define CIRRUS_ROP_SRC_INDEX 5
141
142 // control 0x33
143 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
144 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
145 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
146
147 // memory-mapped IO
148 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
149 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
150 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
151 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
152 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
153 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
154 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
155 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
156 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
157 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
158 #define CIRRUS_MMIO_BLTROP 0x1a // byte
159 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
161 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
162 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
163 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
165 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
169 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
170 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
171 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
172 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
173 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
174 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
175 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
176 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
177
178 // PCI 0x00: vendor, 0x02: device
179 #define PCI_VENDOR_CIRRUS 0x1013
180 #define PCI_DEVICE_CLGD5462 0x00d0
181 #define PCI_DEVICE_CLGD5465 0x00d6
182
183 // PCI 0x04: command(word), 0x06(word): status
184 #define PCI_COMMAND_IOACCESS 0x0001
185 #define PCI_COMMAND_MEMACCESS 0x0002
186 #define PCI_COMMAND_BUSMASTER 0x0004
187 #define PCI_COMMAND_SPECIALCYCLE 0x0008
188 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
189 #define PCI_COMMAND_PALETTESNOOPING 0x0020
190 #define PCI_COMMAND_PARITYDETECTION 0x0040
191 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
192 #define PCI_COMMAND_SERR 0x0100
193 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
194 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
195 #define PCI_CLASS_BASE_DISPLAY 0x03
196 // PCI 0x08, 0x00ff0000
197 #define PCI_CLASS_SUB_VGA 0x00
198 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
199 #define PCI_CLASS_HEADERTYPE_00h 0x00
200 // 0x10-0x3f (headertype 00h)
201 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
202 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
203 #define PCI_MAP_MEM 0x0
204 #define PCI_MAP_IO 0x1
205 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
206 #define PCI_MAP_IO_ADDR_MASK (~0x3)
207 #define PCI_MAP_MEMFLAGS_32BIT 0x0
208 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
209 #define PCI_MAP_MEMFLAGS_64BIT 0x4
210 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
211 // PCI 0x28: cardbus CIS pointer
212 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
213 // PCI 0x30: expansion ROM base address
214 #define PCI_ROMBIOS_ENABLED 0x1
215 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
216 // PCI 0x38: reserved
217 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
218
219 #define CIRRUS_PNPMMIO_SIZE 0x1000
220
221
222 /* I/O and memory hook */
223 #define CIRRUS_HOOK_NOT_HANDLED 0
224 #define CIRRUS_HOOK_HANDLED 1
225
226 struct CirrusVGAState;
227 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
228 uint8_t * dst, const uint8_t * src,
229 int dstpitch, int srcpitch,
230 int bltwidth, int bltheight);
231 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
232 uint8_t *dst, int dst_pitch, int width, int height);
233
234 typedef struct CirrusVGAState {
235 VGA_STATE_COMMON
236
237 int cirrus_linear_io_addr;
238 int cirrus_linear_bitblt_io_addr;
239 int cirrus_mmio_io_addr;
240 #ifdef USE_KVM
241 unsigned long cirrus_lfb_addr;
242 unsigned long cirrus_lfb_end;
243 int aliases_enabled;
244 uint32_t aliased_bank_base[2];
245 uint32_t aliased_bank_limit[2];
246 #endif
247 uint32_t cirrus_addr_mask;
248 uint32_t linear_mmio_mask;
249 uint8_t cirrus_shadow_gr0;
250 uint8_t cirrus_shadow_gr1;
251 uint8_t cirrus_hidden_dac_lockindex;
252 uint8_t cirrus_hidden_dac_data;
253 uint32_t cirrus_bank_base[2];
254 uint32_t cirrus_bank_limit[2];
255 uint8_t cirrus_hidden_palette[48];
256 uint32_t hw_cursor_x;
257 uint32_t hw_cursor_y;
258 int cirrus_blt_pixelwidth;
259 int cirrus_blt_width;
260 int cirrus_blt_height;
261 int cirrus_blt_dstpitch;
262 int cirrus_blt_srcpitch;
263 uint32_t cirrus_blt_fgcol;
264 uint32_t cirrus_blt_bgcol;
265 uint32_t cirrus_blt_dstaddr;
266 uint32_t cirrus_blt_srcaddr;
267 uint8_t cirrus_blt_mode;
268 uint8_t cirrus_blt_modeext;
269 cirrus_bitblt_rop_t cirrus_rop;
270 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
271 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
272 uint8_t *cirrus_srcptr;
273 uint8_t *cirrus_srcptr_end;
274 uint32_t cirrus_srccounter;
275 /* hwcursor display state */
276 int last_hw_cursor_size;
277 int last_hw_cursor_x;
278 int last_hw_cursor_y;
279 int last_hw_cursor_y_start;
280 int last_hw_cursor_y_end;
281 int real_vram_size; /* XXX: suppress that */
282 CPUWriteMemoryFunc **cirrus_linear_write;
283 } CirrusVGAState;
284
285 typedef struct PCICirrusVGAState {
286 PCIDevice dev;
287 CirrusVGAState cirrus_vga;
288 } PCICirrusVGAState;
289
290 static uint8_t rop_to_index[256];
291
292 /***************************************
293 *
294 * prototypes.
295 *
296 ***************************************/
297
298
299 static void cirrus_bitblt_reset(CirrusVGAState *s);
300 static void cirrus_update_memory_access(CirrusVGAState *s);
301
302 /***************************************
303 *
304 * raster operations
305 *
306 ***************************************/
307
308 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
309 uint8_t *dst,const uint8_t *src,
310 int dstpitch,int srcpitch,
311 int bltwidth,int bltheight)
312 {
313 }
314
315 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
316 uint8_t *dst,
317 int dstpitch, int bltwidth,int bltheight)
318 {
319 }
320
321 #define ROP_NAME 0
322 #define ROP_OP(d, s) d = 0
323 #include "cirrus_vga_rop.h"
324
325 #define ROP_NAME src_and_dst
326 #define ROP_OP(d, s) d = (s) & (d)
327 #include "cirrus_vga_rop.h"
328
329 #define ROP_NAME src_and_notdst
330 #define ROP_OP(d, s) d = (s) & (~(d))
331 #include "cirrus_vga_rop.h"
332
333 #define ROP_NAME notdst
334 #define ROP_OP(d, s) d = ~(d)
335 #include "cirrus_vga_rop.h"
336
337 #define ROP_NAME src
338 #define ROP_OP(d, s) d = s
339 #include "cirrus_vga_rop.h"
340
341 #define ROP_NAME 1
342 #define ROP_OP(d, s) d = ~0
343 #include "cirrus_vga_rop.h"
344
345 #define ROP_NAME notsrc_and_dst
346 #define ROP_OP(d, s) d = (~(s)) & (d)
347 #include "cirrus_vga_rop.h"
348
349 #define ROP_NAME src_xor_dst
350 #define ROP_OP(d, s) d = (s) ^ (d)
351 #include "cirrus_vga_rop.h"
352
353 #define ROP_NAME src_or_dst
354 #define ROP_OP(d, s) d = (s) | (d)
355 #include "cirrus_vga_rop.h"
356
357 #define ROP_NAME notsrc_or_notdst
358 #define ROP_OP(d, s) d = (~(s)) | (~(d))
359 #include "cirrus_vga_rop.h"
360
361 #define ROP_NAME src_notxor_dst
362 #define ROP_OP(d, s) d = ~((s) ^ (d))
363 #include "cirrus_vga_rop.h"
364
365 #define ROP_NAME src_or_notdst
366 #define ROP_OP(d, s) d = (s) | (~(d))
367 #include "cirrus_vga_rop.h"
368
369 #define ROP_NAME notsrc
370 #define ROP_OP(d, s) d = (~(s))
371 #include "cirrus_vga_rop.h"
372
373 #define ROP_NAME notsrc_or_dst
374 #define ROP_OP(d, s) d = (~(s)) | (d)
375 #include "cirrus_vga_rop.h"
376
377 #define ROP_NAME notsrc_and_notdst
378 #define ROP_OP(d, s) d = (~(s)) & (~(d))
379 #include "cirrus_vga_rop.h"
380
381 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
382 cirrus_bitblt_rop_fwd_0,
383 cirrus_bitblt_rop_fwd_src_and_dst,
384 cirrus_bitblt_rop_nop,
385 cirrus_bitblt_rop_fwd_src_and_notdst,
386 cirrus_bitblt_rop_fwd_notdst,
387 cirrus_bitblt_rop_fwd_src,
388 cirrus_bitblt_rop_fwd_1,
389 cirrus_bitblt_rop_fwd_notsrc_and_dst,
390 cirrus_bitblt_rop_fwd_src_xor_dst,
391 cirrus_bitblt_rop_fwd_src_or_dst,
392 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
393 cirrus_bitblt_rop_fwd_src_notxor_dst,
394 cirrus_bitblt_rop_fwd_src_or_notdst,
395 cirrus_bitblt_rop_fwd_notsrc,
396 cirrus_bitblt_rop_fwd_notsrc_or_dst,
397 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
398 };
399
400 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
401 cirrus_bitblt_rop_bkwd_0,
402 cirrus_bitblt_rop_bkwd_src_and_dst,
403 cirrus_bitblt_rop_nop,
404 cirrus_bitblt_rop_bkwd_src_and_notdst,
405 cirrus_bitblt_rop_bkwd_notdst,
406 cirrus_bitblt_rop_bkwd_src,
407 cirrus_bitblt_rop_bkwd_1,
408 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
409 cirrus_bitblt_rop_bkwd_src_xor_dst,
410 cirrus_bitblt_rop_bkwd_src_or_dst,
411 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
412 cirrus_bitblt_rop_bkwd_src_notxor_dst,
413 cirrus_bitblt_rop_bkwd_src_or_notdst,
414 cirrus_bitblt_rop_bkwd_notsrc,
415 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
416 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
417 };
418
419 #define TRANSP_ROP(name) {\
420 name ## _8,\
421 name ## _16,\
422 }
423 #define TRANSP_NOP(func) {\
424 func,\
425 func,\
426 }
427
428 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
429 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
430 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
431 TRANSP_NOP(cirrus_bitblt_rop_nop),
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
433 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
435 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
445 };
446
447 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
448 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
449 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
450 TRANSP_NOP(cirrus_bitblt_rop_nop),
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
452 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
454 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
464 };
465
466 #define ROP2(name) {\
467 name ## _8,\
468 name ## _16,\
469 name ## _24,\
470 name ## _32,\
471 }
472
473 #define ROP_NOP2(func) {\
474 func,\
475 func,\
476 func,\
477 func,\
478 }
479
480 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
481 ROP2(cirrus_patternfill_0),
482 ROP2(cirrus_patternfill_src_and_dst),
483 ROP_NOP2(cirrus_bitblt_rop_nop),
484 ROP2(cirrus_patternfill_src_and_notdst),
485 ROP2(cirrus_patternfill_notdst),
486 ROP2(cirrus_patternfill_src),
487 ROP2(cirrus_patternfill_1),
488 ROP2(cirrus_patternfill_notsrc_and_dst),
489 ROP2(cirrus_patternfill_src_xor_dst),
490 ROP2(cirrus_patternfill_src_or_dst),
491 ROP2(cirrus_patternfill_notsrc_or_notdst),
492 ROP2(cirrus_patternfill_src_notxor_dst),
493 ROP2(cirrus_patternfill_src_or_notdst),
494 ROP2(cirrus_patternfill_notsrc),
495 ROP2(cirrus_patternfill_notsrc_or_dst),
496 ROP2(cirrus_patternfill_notsrc_and_notdst),
497 };
498
499 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
500 ROP2(cirrus_colorexpand_transp_0),
501 ROP2(cirrus_colorexpand_transp_src_and_dst),
502 ROP_NOP2(cirrus_bitblt_rop_nop),
503 ROP2(cirrus_colorexpand_transp_src_and_notdst),
504 ROP2(cirrus_colorexpand_transp_notdst),
505 ROP2(cirrus_colorexpand_transp_src),
506 ROP2(cirrus_colorexpand_transp_1),
507 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
508 ROP2(cirrus_colorexpand_transp_src_xor_dst),
509 ROP2(cirrus_colorexpand_transp_src_or_dst),
510 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
511 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
512 ROP2(cirrus_colorexpand_transp_src_or_notdst),
513 ROP2(cirrus_colorexpand_transp_notsrc),
514 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
515 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
516 };
517
518 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
519 ROP2(cirrus_colorexpand_0),
520 ROP2(cirrus_colorexpand_src_and_dst),
521 ROP_NOP2(cirrus_bitblt_rop_nop),
522 ROP2(cirrus_colorexpand_src_and_notdst),
523 ROP2(cirrus_colorexpand_notdst),
524 ROP2(cirrus_colorexpand_src),
525 ROP2(cirrus_colorexpand_1),
526 ROP2(cirrus_colorexpand_notsrc_and_dst),
527 ROP2(cirrus_colorexpand_src_xor_dst),
528 ROP2(cirrus_colorexpand_src_or_dst),
529 ROP2(cirrus_colorexpand_notsrc_or_notdst),
530 ROP2(cirrus_colorexpand_src_notxor_dst),
531 ROP2(cirrus_colorexpand_src_or_notdst),
532 ROP2(cirrus_colorexpand_notsrc),
533 ROP2(cirrus_colorexpand_notsrc_or_dst),
534 ROP2(cirrus_colorexpand_notsrc_and_notdst),
535 };
536
537 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
538 ROP2(cirrus_colorexpand_pattern_transp_0),
539 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
540 ROP_NOP2(cirrus_bitblt_rop_nop),
541 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
542 ROP2(cirrus_colorexpand_pattern_transp_notdst),
543 ROP2(cirrus_colorexpand_pattern_transp_src),
544 ROP2(cirrus_colorexpand_pattern_transp_1),
545 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
546 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
547 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
548 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
549 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
550 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
551 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
552 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
553 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
554 };
555
556 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
557 ROP2(cirrus_colorexpand_pattern_0),
558 ROP2(cirrus_colorexpand_pattern_src_and_dst),
559 ROP_NOP2(cirrus_bitblt_rop_nop),
560 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
561 ROP2(cirrus_colorexpand_pattern_notdst),
562 ROP2(cirrus_colorexpand_pattern_src),
563 ROP2(cirrus_colorexpand_pattern_1),
564 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
565 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
566 ROP2(cirrus_colorexpand_pattern_src_or_dst),
567 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
568 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
569 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
570 ROP2(cirrus_colorexpand_pattern_notsrc),
571 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
572 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
573 };
574
575 static const cirrus_fill_t cirrus_fill[16][4] = {
576 ROP2(cirrus_fill_0),
577 ROP2(cirrus_fill_src_and_dst),
578 ROP_NOP2(cirrus_bitblt_fill_nop),
579 ROP2(cirrus_fill_src_and_notdst),
580 ROP2(cirrus_fill_notdst),
581 ROP2(cirrus_fill_src),
582 ROP2(cirrus_fill_1),
583 ROP2(cirrus_fill_notsrc_and_dst),
584 ROP2(cirrus_fill_src_xor_dst),
585 ROP2(cirrus_fill_src_or_dst),
586 ROP2(cirrus_fill_notsrc_or_notdst),
587 ROP2(cirrus_fill_src_notxor_dst),
588 ROP2(cirrus_fill_src_or_notdst),
589 ROP2(cirrus_fill_notsrc),
590 ROP2(cirrus_fill_notsrc_or_dst),
591 ROP2(cirrus_fill_notsrc_and_notdst),
592 };
593
594 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
595 {
596 unsigned int color;
597 switch (s->cirrus_blt_pixelwidth) {
598 case 1:
599 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
600 break;
601 case 2:
602 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
603 s->cirrus_blt_fgcol = le16_to_cpu(color);
604 break;
605 case 3:
606 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
607 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
608 break;
609 default:
610 case 4:
611 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
612 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
613 s->cirrus_blt_fgcol = le32_to_cpu(color);
614 break;
615 }
616 }
617
618 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
619 {
620 unsigned int color;
621 switch (s->cirrus_blt_pixelwidth) {
622 case 1:
623 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
624 break;
625 case 2:
626 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
627 s->cirrus_blt_bgcol = le16_to_cpu(color);
628 break;
629 case 3:
630 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
631 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
632 break;
633 default:
634 case 4:
635 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
636 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
637 s->cirrus_blt_bgcol = le32_to_cpu(color);
638 break;
639 }
640 }
641
642 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
643 int off_pitch, int bytesperline,
644 int lines)
645 {
646 int y;
647 int off_cur;
648 int off_cur_end;
649
650 for (y = 0; y < lines; y++) {
651 off_cur = off_begin;
652 off_cur_end = off_cur + bytesperline;
653 off_cur &= TARGET_PAGE_MASK;
654 while (off_cur < off_cur_end) {
655 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
656 off_cur += TARGET_PAGE_SIZE;
657 }
658 off_begin += off_pitch;
659 }
660 }
661
662 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
663 const uint8_t * src)
664 {
665 uint8_t *dst;
666
667 dst = s->vram_ptr + s->cirrus_blt_dstaddr;
668 (*s->cirrus_rop) (s, dst, src,
669 s->cirrus_blt_dstpitch, 0,
670 s->cirrus_blt_width, s->cirrus_blt_height);
671 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
672 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
673 s->cirrus_blt_height);
674 return 1;
675 }
676
677 /* fill */
678
679 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
680 {
681 cirrus_fill_t rop_func;
682
683 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
684 rop_func(s, s->vram_ptr + s->cirrus_blt_dstaddr,
685 s->cirrus_blt_dstpitch,
686 s->cirrus_blt_width, s->cirrus_blt_height);
687 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
688 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
689 s->cirrus_blt_height);
690 cirrus_bitblt_reset(s);
691 return 1;
692 }
693
694 /***************************************
695 *
696 * bitblt (video-to-video)
697 *
698 ***************************************/
699
700 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
701 {
702 return cirrus_bitblt_common_patterncopy(s,
703 s->vram_ptr +
704 (s->cirrus_blt_srcaddr & ~7));
705 }
706
707 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
708 {
709 int sx, sy;
710 int dx, dy;
711 int width, height;
712 int depth;
713 int notify = 0;
714
715 depth = s->get_bpp((VGAState *)s) / 8;
716 s->get_resolution((VGAState *)s, &width, &height);
717
718 /* extra x, y */
719 sx = (src % (width * depth)) / depth;
720 sy = (src / (width * depth));
721 dx = (dst % (width *depth)) / depth;
722 dy = (dst / (width * depth));
723
724 /* normalize width */
725 w /= depth;
726
727 /* if we're doing a backward copy, we have to adjust
728 our x/y to be the upper left corner (instead of the lower
729 right corner) */
730 if (s->cirrus_blt_dstpitch < 0) {
731 sx -= (s->cirrus_blt_width / depth) - 1;
732 dx -= (s->cirrus_blt_width / depth) - 1;
733 sy -= s->cirrus_blt_height - 1;
734 dy -= s->cirrus_blt_height - 1;
735 }
736
737 /* are we in the visible portion of memory? */
738 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
739 (sx + w) <= width && (sy + h) <= height &&
740 (dx + w) <= width && (dy + h) <= height) {
741 notify = 1;
742 }
743
744 /* make to sure only copy if it's a plain copy ROP */
745 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
746 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
747 notify = 0;
748
749 /* we have to flush all pending changes so that the copy
750 is generated at the appropriate moment in time */
751 if (notify)
752 vga_hw_update();
753
754 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
755 s->vram_ptr + s->cirrus_blt_srcaddr,
756 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
757 s->cirrus_blt_width, s->cirrus_blt_height);
758
759 if (notify)
760 s->ds->dpy_copy(s->ds,
761 sx, sy, dx, dy,
762 s->cirrus_blt_width / depth,
763 s->cirrus_blt_height);
764
765 /* we don't have to notify the display that this portion has
766 changed since dpy_copy implies this */
767
768 if (!notify)
769 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
770 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
771 s->cirrus_blt_height);
772 }
773
774 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
775 {
776 if (s->ds->dpy_copy) {
777 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
778 s->cirrus_blt_srcaddr - s->start_addr,
779 s->cirrus_blt_width, s->cirrus_blt_height);
780 } else {
781 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
782 s->vram_ptr + s->cirrus_blt_srcaddr,
783 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
784 s->cirrus_blt_width, s->cirrus_blt_height);
785
786 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
787 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
788 s->cirrus_blt_height);
789 }
790
791 return 1;
792 }
793
794 /***************************************
795 *
796 * bitblt (cpu-to-video)
797 *
798 ***************************************/
799
800 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
801 {
802 int copy_count;
803 uint8_t *end_ptr;
804
805 if (s->cirrus_srccounter > 0) {
806 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
807 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
808 the_end:
809 s->cirrus_srccounter = 0;
810 cirrus_bitblt_reset(s);
811 } else {
812 /* at least one scan line */
813 do {
814 (*s->cirrus_rop)(s, s->vram_ptr + s->cirrus_blt_dstaddr,
815 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
816 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
817 s->cirrus_blt_width, 1);
818 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
819 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
820 if (s->cirrus_srccounter <= 0)
821 goto the_end;
822 /* more bytes than needed can be transfered because of
823 word alignment, so we keep them for the next line */
824 /* XXX: keep alignment to speed up transfer */
825 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
826 copy_count = s->cirrus_srcptr_end - end_ptr;
827 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
828 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
829 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
830 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
831 }
832 }
833 }
834
835 /***************************************
836 *
837 * bitblt wrapper
838 *
839 ***************************************/
840
841 static void cirrus_bitblt_reset(CirrusVGAState * s)
842 {
843 s->gr[0x31] &=
844 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
845 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
846 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
847 s->cirrus_srccounter = 0;
848 cirrus_update_memory_access(s);
849 }
850
851 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
852 {
853 int w;
854
855 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
856 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
857 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
858
859 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
860 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
861 s->cirrus_blt_srcpitch = 8;
862 } else {
863 /* XXX: check for 24 bpp */
864 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
865 }
866 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
867 } else {
868 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
869 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
870 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
871 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
872 else
873 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
874 } else {
875 /* always align input size to 32 bits */
876 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
877 }
878 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
879 }
880 s->cirrus_srcptr = s->cirrus_bltbuf;
881 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
882 cirrus_update_memory_access(s);
883 return 1;
884 }
885
886 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
887 {
888 /* XXX */
889 #ifdef DEBUG_BITBLT
890 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
891 #endif
892 return 0;
893 }
894
895 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
896 {
897 int ret;
898
899 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
900 ret = cirrus_bitblt_videotovideo_patterncopy(s);
901 } else {
902 ret = cirrus_bitblt_videotovideo_copy(s);
903 }
904 if (ret)
905 cirrus_bitblt_reset(s);
906 return ret;
907 }
908
909 static void cirrus_bitblt_start(CirrusVGAState * s)
910 {
911 uint8_t blt_rop;
912
913 s->gr[0x31] |= CIRRUS_BLT_BUSY;
914
915 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
916 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
917 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
918 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
919 s->cirrus_blt_dstaddr =
920 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
921 s->cirrus_blt_srcaddr =
922 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
923 s->cirrus_blt_mode = s->gr[0x30];
924 s->cirrus_blt_modeext = s->gr[0x33];
925 blt_rop = s->gr[0x32];
926
927 #ifdef DEBUG_BITBLT
928 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
929 blt_rop,
930 s->cirrus_blt_mode,
931 s->cirrus_blt_modeext,
932 s->cirrus_blt_width,
933 s->cirrus_blt_height,
934 s->cirrus_blt_dstpitch,
935 s->cirrus_blt_srcpitch,
936 s->cirrus_blt_dstaddr,
937 s->cirrus_blt_srcaddr,
938 s->gr[0x2f]);
939 #endif
940
941 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
942 case CIRRUS_BLTMODE_PIXELWIDTH8:
943 s->cirrus_blt_pixelwidth = 1;
944 break;
945 case CIRRUS_BLTMODE_PIXELWIDTH16:
946 s->cirrus_blt_pixelwidth = 2;
947 break;
948 case CIRRUS_BLTMODE_PIXELWIDTH24:
949 s->cirrus_blt_pixelwidth = 3;
950 break;
951 case CIRRUS_BLTMODE_PIXELWIDTH32:
952 s->cirrus_blt_pixelwidth = 4;
953 break;
954 default:
955 #ifdef DEBUG_BITBLT
956 printf("cirrus: bitblt - pixel width is unknown\n");
957 #endif
958 goto bitblt_ignore;
959 }
960 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
961
962 if ((s->
963 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
964 CIRRUS_BLTMODE_MEMSYSDEST))
965 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
966 #ifdef DEBUG_BITBLT
967 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
968 #endif
969 goto bitblt_ignore;
970 }
971
972 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
973 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
974 CIRRUS_BLTMODE_TRANSPARENTCOMP |
975 CIRRUS_BLTMODE_PATTERNCOPY |
976 CIRRUS_BLTMODE_COLOREXPAND)) ==
977 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
978 cirrus_bitblt_fgcol(s);
979 cirrus_bitblt_solidfill(s, blt_rop);
980 } else {
981 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
982 CIRRUS_BLTMODE_PATTERNCOPY)) ==
983 CIRRUS_BLTMODE_COLOREXPAND) {
984
985 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
986 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
987 cirrus_bitblt_bgcol(s);
988 else
989 cirrus_bitblt_fgcol(s);
990 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
991 } else {
992 cirrus_bitblt_fgcol(s);
993 cirrus_bitblt_bgcol(s);
994 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
995 }
996 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
997 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
998 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
999 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1000 cirrus_bitblt_bgcol(s);
1001 else
1002 cirrus_bitblt_fgcol(s);
1003 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1004 } else {
1005 cirrus_bitblt_fgcol(s);
1006 cirrus_bitblt_bgcol(s);
1007 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1008 }
1009 } else {
1010 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1011 }
1012 } else {
1013 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1014 if (s->cirrus_blt_pixelwidth > 2) {
1015 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1016 goto bitblt_ignore;
1017 }
1018 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1019 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1020 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1021 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1022 } else {
1023 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1024 }
1025 } else {
1026 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1027 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1028 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1029 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1030 } else {
1031 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1032 }
1033 }
1034 }
1035 // setup bitblt engine.
1036 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1037 if (!cirrus_bitblt_cputovideo(s))
1038 goto bitblt_ignore;
1039 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1040 if (!cirrus_bitblt_videotocpu(s))
1041 goto bitblt_ignore;
1042 } else {
1043 if (!cirrus_bitblt_videotovideo(s))
1044 goto bitblt_ignore;
1045 }
1046 }
1047 return;
1048 bitblt_ignore:;
1049 cirrus_bitblt_reset(s);
1050 }
1051
1052 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1053 {
1054 unsigned old_value;
1055
1056 old_value = s->gr[0x31];
1057 s->gr[0x31] = reg_value;
1058
1059 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1060 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1061 cirrus_bitblt_reset(s);
1062 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1063 ((reg_value & CIRRUS_BLT_START) != 0)) {
1064 cirrus_bitblt_start(s);
1065 }
1066 }
1067
1068
1069 /***************************************
1070 *
1071 * basic parameters
1072 *
1073 ***************************************/
1074
1075 static void cirrus_get_offsets(VGAState *s1,
1076 uint32_t *pline_offset,
1077 uint32_t *pstart_addr,
1078 uint32_t *pline_compare)
1079 {
1080 CirrusVGAState * s = (CirrusVGAState *)s1;
1081 uint32_t start_addr, line_offset, line_compare;
1082
1083 line_offset = s->cr[0x13]
1084 | ((s->cr[0x1b] & 0x10) << 4);
1085 line_offset <<= 3;
1086 *pline_offset = line_offset;
1087
1088 start_addr = (s->cr[0x0c] << 8)
1089 | s->cr[0x0d]
1090 | ((s->cr[0x1b] & 0x01) << 16)
1091 | ((s->cr[0x1b] & 0x0c) << 15)
1092 | ((s->cr[0x1d] & 0x80) << 12);
1093 *pstart_addr = start_addr;
1094
1095 line_compare = s->cr[0x18] |
1096 ((s->cr[0x07] & 0x10) << 4) |
1097 ((s->cr[0x09] & 0x40) << 3);
1098 *pline_compare = line_compare;
1099 }
1100
1101 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1102 {
1103 uint32_t ret = 16;
1104
1105 switch (s->cirrus_hidden_dac_data & 0xf) {
1106 case 0:
1107 ret = 15;
1108 break; /* Sierra HiColor */
1109 case 1:
1110 ret = 16;
1111 break; /* XGA HiColor */
1112 default:
1113 #ifdef DEBUG_CIRRUS
1114 printf("cirrus: invalid DAC value %x in 16bpp\n",
1115 (s->cirrus_hidden_dac_data & 0xf));
1116 #endif
1117 ret = 15; /* XXX */
1118 break;
1119 }
1120 return ret;
1121 }
1122
1123 static int cirrus_get_bpp(VGAState *s1)
1124 {
1125 CirrusVGAState * s = (CirrusVGAState *)s1;
1126 uint32_t ret = 8;
1127
1128 if ((s->sr[0x07] & 0x01) != 0) {
1129 /* Cirrus SVGA */
1130 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1131 case CIRRUS_SR7_BPP_8:
1132 ret = 8;
1133 break;
1134 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1135 ret = cirrus_get_bpp16_depth(s);
1136 break;
1137 case CIRRUS_SR7_BPP_24:
1138 ret = 24;
1139 break;
1140 case CIRRUS_SR7_BPP_16:
1141 ret = cirrus_get_bpp16_depth(s);
1142 break;
1143 case CIRRUS_SR7_BPP_32:
1144 ret = 32;
1145 break;
1146 default:
1147 #ifdef DEBUG_CIRRUS
1148 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1149 #endif
1150 ret = 8;
1151 break;
1152 }
1153 } else {
1154 /* VGA */
1155 ret = 0;
1156 }
1157
1158 return ret;
1159 }
1160
1161 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1162 {
1163 int width, height;
1164
1165 width = (s->cr[0x01] + 1) * 8;
1166 height = s->cr[0x12] |
1167 ((s->cr[0x07] & 0x02) << 7) |
1168 ((s->cr[0x07] & 0x40) << 3);
1169 height = (height + 1);
1170 /* interlace support */
1171 if (s->cr[0x1a] & 0x01)
1172 height = height * 2;
1173 *pwidth = width;
1174 *pheight = height;
1175 }
1176
1177 /***************************************
1178 *
1179 * bank memory
1180 *
1181 ***************************************/
1182
1183 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1184 {
1185 unsigned offset;
1186 unsigned limit;
1187
1188 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1189 offset = s->gr[0x09 + bank_index];
1190 else /* single bank */
1191 offset = s->gr[0x09];
1192
1193 if ((s->gr[0x0b] & 0x20) != 0)
1194 offset <<= 14;
1195 else
1196 offset <<= 12;
1197
1198 if (s->real_vram_size <= offset)
1199 limit = 0;
1200 else
1201 limit = s->real_vram_size - offset;
1202
1203 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1204 if (limit > 0x8000) {
1205 offset += 0x8000;
1206 limit -= 0x8000;
1207 } else {
1208 limit = 0;
1209 }
1210 }
1211
1212 if (limit > 0) {
1213 s->cirrus_bank_base[bank_index] = offset;
1214 s->cirrus_bank_limit[bank_index] = limit;
1215 } else {
1216 s->cirrus_bank_base[bank_index] = 0;
1217 s->cirrus_bank_limit[bank_index] = 0;
1218 }
1219 }
1220
1221 /***************************************
1222 *
1223 * I/O access between 0x3c4-0x3c5
1224 *
1225 ***************************************/
1226
1227 static int
1228 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1229 {
1230 switch (reg_index) {
1231 case 0x00: // Standard VGA
1232 case 0x01: // Standard VGA
1233 case 0x02: // Standard VGA
1234 case 0x03: // Standard VGA
1235 case 0x04: // Standard VGA
1236 return CIRRUS_HOOK_NOT_HANDLED;
1237 case 0x06: // Unlock Cirrus extensions
1238 *reg_value = s->sr[reg_index];
1239 break;
1240 case 0x10:
1241 case 0x30:
1242 case 0x50:
1243 case 0x70: // Graphics Cursor X
1244 case 0x90:
1245 case 0xb0:
1246 case 0xd0:
1247 case 0xf0: // Graphics Cursor X
1248 *reg_value = s->sr[0x10];
1249 break;
1250 case 0x11:
1251 case 0x31:
1252 case 0x51:
1253 case 0x71: // Graphics Cursor Y
1254 case 0x91:
1255 case 0xb1:
1256 case 0xd1:
1257 case 0xf1: // Graphics Cursor Y
1258 *reg_value = s->sr[0x11];
1259 break;
1260 case 0x05: // ???
1261 case 0x07: // Extended Sequencer Mode
1262 case 0x08: // EEPROM Control
1263 case 0x09: // Scratch Register 0
1264 case 0x0a: // Scratch Register 1
1265 case 0x0b: // VCLK 0
1266 case 0x0c: // VCLK 1
1267 case 0x0d: // VCLK 2
1268 case 0x0e: // VCLK 3
1269 case 0x0f: // DRAM Control
1270 case 0x12: // Graphics Cursor Attribute
1271 case 0x13: // Graphics Cursor Pattern Address
1272 case 0x14: // Scratch Register 2
1273 case 0x15: // Scratch Register 3
1274 case 0x16: // Performance Tuning Register
1275 case 0x17: // Configuration Readback and Extended Control
1276 case 0x18: // Signature Generator Control
1277 case 0x19: // Signal Generator Result
1278 case 0x1a: // Signal Generator Result
1279 case 0x1b: // VCLK 0 Denominator & Post
1280 case 0x1c: // VCLK 1 Denominator & Post
1281 case 0x1d: // VCLK 2 Denominator & Post
1282 case 0x1e: // VCLK 3 Denominator & Post
1283 case 0x1f: // BIOS Write Enable and MCLK select
1284 #ifdef DEBUG_CIRRUS
1285 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1286 #endif
1287 *reg_value = s->sr[reg_index];
1288 break;
1289 default:
1290 #ifdef DEBUG_CIRRUS
1291 printf("cirrus: inport sr_index %02x\n", reg_index);
1292 #endif
1293 *reg_value = 0xff;
1294 break;
1295 }
1296
1297 return CIRRUS_HOOK_HANDLED;
1298 }
1299
1300 static int
1301 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1302 {
1303 switch (reg_index) {
1304 case 0x00: // Standard VGA
1305 case 0x01: // Standard VGA
1306 case 0x02: // Standard VGA
1307 case 0x03: // Standard VGA
1308 case 0x04: // Standard VGA
1309 return CIRRUS_HOOK_NOT_HANDLED;
1310 case 0x06: // Unlock Cirrus extensions
1311 reg_value &= 0x17;
1312 if (reg_value == 0x12) {
1313 s->sr[reg_index] = 0x12;
1314 } else {
1315 s->sr[reg_index] = 0x0f;
1316 }
1317 break;
1318 case 0x10:
1319 case 0x30:
1320 case 0x50:
1321 case 0x70: // Graphics Cursor X
1322 case 0x90:
1323 case 0xb0:
1324 case 0xd0:
1325 case 0xf0: // Graphics Cursor X
1326 s->sr[0x10] = reg_value;
1327 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1328 break;
1329 case 0x11:
1330 case 0x31:
1331 case 0x51:
1332 case 0x71: // Graphics Cursor Y
1333 case 0x91:
1334 case 0xb1:
1335 case 0xd1:
1336 case 0xf1: // Graphics Cursor Y
1337 s->sr[0x11] = reg_value;
1338 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1339 break;
1340 case 0x07: // Extended Sequencer Mode
1341 case 0x08: // EEPROM Control
1342 case 0x09: // Scratch Register 0
1343 case 0x0a: // Scratch Register 1
1344 case 0x0b: // VCLK 0
1345 case 0x0c: // VCLK 1
1346 case 0x0d: // VCLK 2
1347 case 0x0e: // VCLK 3
1348 case 0x0f: // DRAM Control
1349 case 0x12: // Graphics Cursor Attribute
1350 case 0x13: // Graphics Cursor Pattern Address
1351 case 0x14: // Scratch Register 2
1352 case 0x15: // Scratch Register 3
1353 case 0x16: // Performance Tuning Register
1354 case 0x18: // Signature Generator Control
1355 case 0x19: // Signature Generator Result
1356 case 0x1a: // Signature Generator Result
1357 case 0x1b: // VCLK 0 Denominator & Post
1358 case 0x1c: // VCLK 1 Denominator & Post
1359 case 0x1d: // VCLK 2 Denominator & Post
1360 case 0x1e: // VCLK 3 Denominator & Post
1361 case 0x1f: // BIOS Write Enable and MCLK select
1362 s->sr[reg_index] = reg_value;
1363 #ifdef DEBUG_CIRRUS
1364 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1365 reg_index, reg_value);
1366 #endif
1367 if (reg_index == 0x07)
1368 cirrus_update_memory_access(s);
1369 break;
1370 case 0x17: // Configuration Readback and Extended Control
1371 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1372 cirrus_update_memory_access(s);
1373 break;
1374 default:
1375 #ifdef DEBUG_CIRRUS
1376 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1377 reg_value);
1378 #endif
1379 break;
1380 }
1381
1382 return CIRRUS_HOOK_HANDLED;
1383 }
1384
1385 /***************************************
1386 *
1387 * I/O access at 0x3c6
1388 *
1389 ***************************************/
1390
1391 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1392 {
1393 *reg_value = 0xff;
1394 if (++s->cirrus_hidden_dac_lockindex == 5) {
1395 *reg_value = s->cirrus_hidden_dac_data;
1396 s->cirrus_hidden_dac_lockindex = 0;
1397 }
1398 }
1399
1400 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1401 {
1402 if (s->cirrus_hidden_dac_lockindex == 4) {
1403 s->cirrus_hidden_dac_data = reg_value;
1404 #if defined(DEBUG_CIRRUS)
1405 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1406 #endif
1407 }
1408 s->cirrus_hidden_dac_lockindex = 0;
1409 }
1410
1411 /***************************************
1412 *
1413 * I/O access at 0x3c9
1414 *
1415 ***************************************/
1416
1417 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1418 {
1419 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1420 return CIRRUS_HOOK_NOT_HANDLED;
1421 *reg_value =
1422 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1423 s->dac_sub_index];
1424 if (++s->dac_sub_index == 3) {
1425 s->dac_sub_index = 0;
1426 s->dac_read_index++;
1427 }
1428 return CIRRUS_HOOK_HANDLED;
1429 }
1430
1431 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1432 {
1433 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1434 return CIRRUS_HOOK_NOT_HANDLED;
1435 s->dac_cache[s->dac_sub_index] = reg_value;
1436 if (++s->dac_sub_index == 3) {
1437 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1438 s->dac_cache, 3);
1439 /* XXX update cursor */
1440 s->dac_sub_index = 0;
1441 s->dac_write_index++;
1442 }
1443 return CIRRUS_HOOK_HANDLED;
1444 }
1445
1446 /***************************************
1447 *
1448 * I/O access between 0x3ce-0x3cf
1449 *
1450 ***************************************/
1451
1452 static int
1453 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1454 {
1455 switch (reg_index) {
1456 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1457 *reg_value = s->cirrus_shadow_gr0;
1458 return CIRRUS_HOOK_HANDLED;
1459 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1460 *reg_value = s->cirrus_shadow_gr1;
1461 return CIRRUS_HOOK_HANDLED;
1462 case 0x02: // Standard VGA
1463 case 0x03: // Standard VGA
1464 case 0x04: // Standard VGA
1465 case 0x06: // Standard VGA
1466 case 0x07: // Standard VGA
1467 case 0x08: // Standard VGA
1468 return CIRRUS_HOOK_NOT_HANDLED;
1469 case 0x05: // Standard VGA, Cirrus extended mode
1470 default:
1471 break;
1472 }
1473
1474 if (reg_index < 0x3a) {
1475 *reg_value = s->gr[reg_index];
1476 } else {
1477 #ifdef DEBUG_CIRRUS
1478 printf("cirrus: inport gr_index %02x\n", reg_index);
1479 #endif
1480 *reg_value = 0xff;
1481 }
1482
1483 return CIRRUS_HOOK_HANDLED;
1484 }
1485
1486 static int
1487 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1488 {
1489 #if defined(DEBUG_BITBLT) && 0
1490 printf("gr%02x: %02x\n", reg_index, reg_value);
1491 #endif
1492 switch (reg_index) {
1493 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1494 s->cirrus_shadow_gr0 = reg_value;
1495 return CIRRUS_HOOK_NOT_HANDLED;
1496 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1497 s->cirrus_shadow_gr1 = reg_value;
1498 return CIRRUS_HOOK_NOT_HANDLED;
1499 case 0x02: // Standard VGA
1500 case 0x03: // Standard VGA
1501 case 0x04: // Standard VGA
1502 case 0x06: // Standard VGA
1503 case 0x07: // Standard VGA
1504 case 0x08: // Standard VGA
1505 return CIRRUS_HOOK_NOT_HANDLED;
1506 case 0x05: // Standard VGA, Cirrus extended mode
1507 s->gr[reg_index] = reg_value & 0x7f;
1508 cirrus_update_memory_access(s);
1509 break;
1510 case 0x09: // bank offset #0
1511 case 0x0A: // bank offset #1
1512 s->gr[reg_index] = reg_value;
1513 cirrus_update_bank_ptr(s, 0);
1514 cirrus_update_bank_ptr(s, 1);
1515 cirrus_update_memory_access(s);
1516 break;
1517 case 0x0B:
1518 s->gr[reg_index] = reg_value;
1519 cirrus_update_bank_ptr(s, 0);
1520 cirrus_update_bank_ptr(s, 1);
1521 cirrus_update_memory_access(s);
1522 break;
1523 case 0x10: // BGCOLOR 0x0000ff00
1524 case 0x11: // FGCOLOR 0x0000ff00
1525 case 0x12: // BGCOLOR 0x00ff0000
1526 case 0x13: // FGCOLOR 0x00ff0000
1527 case 0x14: // BGCOLOR 0xff000000
1528 case 0x15: // FGCOLOR 0xff000000
1529 case 0x20: // BLT WIDTH 0x0000ff
1530 case 0x22: // BLT HEIGHT 0x0000ff
1531 case 0x24: // BLT DEST PITCH 0x0000ff
1532 case 0x26: // BLT SRC PITCH 0x0000ff
1533 case 0x28: // BLT DEST ADDR 0x0000ff
1534 case 0x29: // BLT DEST ADDR 0x00ff00
1535 case 0x2c: // BLT SRC ADDR 0x0000ff
1536 case 0x2d: // BLT SRC ADDR 0x00ff00
1537 case 0x2f: // BLT WRITEMASK
1538 case 0x30: // BLT MODE
1539 case 0x32: // RASTER OP
1540 case 0x33: // BLT MODEEXT
1541 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1542 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1543 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1544 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1545 s->gr[reg_index] = reg_value;
1546 break;
1547 case 0x21: // BLT WIDTH 0x001f00
1548 case 0x23: // BLT HEIGHT 0x001f00
1549 case 0x25: // BLT DEST PITCH 0x001f00
1550 case 0x27: // BLT SRC PITCH 0x001f00
1551 s->gr[reg_index] = reg_value & 0x1f;
1552 break;
1553 case 0x2a: // BLT DEST ADDR 0x3f0000
1554 s->gr[reg_index] = reg_value & 0x3f;
1555 /* if auto start mode, starts bit blt now */
1556 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1557 cirrus_bitblt_start(s);
1558 }
1559 break;
1560 case 0x2e: // BLT SRC ADDR 0x3f0000
1561 s->gr[reg_index] = reg_value & 0x3f;
1562 break;
1563 case 0x31: // BLT STATUS/START
1564 cirrus_write_bitblt(s, reg_value);
1565 break;
1566 default:
1567 #ifdef DEBUG_CIRRUS
1568 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1569 reg_value);
1570 #endif
1571 break;
1572 }
1573
1574 return CIRRUS_HOOK_HANDLED;
1575 }
1576
1577 /***************************************
1578 *
1579 * I/O access between 0x3d4-0x3d5
1580 *
1581 ***************************************/
1582
1583 static int
1584 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1585 {
1586 switch (reg_index) {
1587 case 0x00: // Standard VGA
1588 case 0x01: // Standard VGA
1589 case 0x02: // Standard VGA
1590 case 0x03: // Standard VGA
1591 case 0x04: // Standard VGA
1592 case 0x05: // Standard VGA
1593 case 0x06: // Standard VGA
1594 case 0x07: // Standard VGA
1595 case 0x08: // Standard VGA
1596 case 0x09: // Standard VGA
1597 case 0x0a: // Standard VGA
1598 case 0x0b: // Standard VGA
1599 case 0x0c: // Standard VGA
1600 case 0x0d: // Standard VGA
1601 case 0x0e: // Standard VGA
1602 case 0x0f: // Standard VGA
1603 case 0x10: // Standard VGA
1604 case 0x11: // Standard VGA
1605 case 0x12: // Standard VGA
1606 case 0x13: // Standard VGA
1607 case 0x14: // Standard VGA
1608 case 0x15: // Standard VGA
1609 case 0x16: // Standard VGA
1610 case 0x17: // Standard VGA
1611 case 0x18: // Standard VGA
1612 return CIRRUS_HOOK_NOT_HANDLED;
1613 case 0x19: // Interlace End
1614 case 0x1a: // Miscellaneous Control
1615 case 0x1b: // Extended Display Control
1616 case 0x1c: // Sync Adjust and Genlock
1617 case 0x1d: // Overlay Extended Control
1618 case 0x22: // Graphics Data Latches Readback (R)
1619 case 0x24: // Attribute Controller Toggle Readback (R)
1620 case 0x25: // Part Status
1621 case 0x27: // Part ID (R)
1622 *reg_value = s->cr[reg_index];
1623 break;
1624 case 0x26: // Attribute Controller Index Readback (R)
1625 *reg_value = s->ar_index & 0x3f;
1626 break;
1627 default:
1628 #ifdef DEBUG_CIRRUS
1629 printf("cirrus: inport cr_index %02x\n", reg_index);
1630 *reg_value = 0xff;
1631 #endif
1632 break;
1633 }
1634
1635 return CIRRUS_HOOK_HANDLED;
1636 }
1637
1638 static int
1639 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1640 {
1641 switch (reg_index) {
1642 case 0x00: // Standard VGA
1643 case 0x01: // Standard VGA
1644 case 0x02: // Standard VGA
1645 case 0x03: // Standard VGA
1646 case 0x04: // Standard VGA
1647 case 0x05: // Standard VGA
1648 case 0x06: // Standard VGA
1649 case 0x07: // Standard VGA
1650 case 0x08: // Standard VGA
1651 case 0x09: // Standard VGA
1652 case 0x0a: // Standard VGA
1653 case 0x0b: // Standard VGA
1654 case 0x0c: // Standard VGA
1655 case 0x0d: // Standard VGA
1656 case 0x0e: // Standard VGA
1657 case 0x0f: // Standard VGA
1658 case 0x10: // Standard VGA
1659 case 0x11: // Standard VGA
1660 case 0x12: // Standard VGA
1661 case 0x13: // Standard VGA
1662 case 0x14: // Standard VGA
1663 case 0x15: // Standard VGA
1664 case 0x16: // Standard VGA
1665 case 0x17: // Standard VGA
1666 case 0x18: // Standard VGA
1667 return CIRRUS_HOOK_NOT_HANDLED;
1668 case 0x19: // Interlace End
1669 case 0x1a: // Miscellaneous Control
1670 case 0x1b: // Extended Display Control
1671 case 0x1c: // Sync Adjust and Genlock
1672 case 0x1d: // Overlay Extended Control
1673 s->cr[reg_index] = reg_value;
1674 #ifdef DEBUG_CIRRUS
1675 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1676 reg_index, reg_value);
1677 #endif
1678 break;
1679 case 0x22: // Graphics Data Latches Readback (R)
1680 case 0x24: // Attribute Controller Toggle Readback (R)
1681 case 0x26: // Attribute Controller Index Readback (R)
1682 case 0x27: // Part ID (R)
1683 break;
1684 case 0x25: // Part Status
1685 default:
1686 #ifdef DEBUG_CIRRUS
1687 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1688 reg_value);
1689 #endif
1690 break;
1691 }
1692
1693 return CIRRUS_HOOK_HANDLED;
1694 }
1695
1696 /***************************************
1697 *
1698 * memory-mapped I/O (bitblt)
1699 *
1700 ***************************************/
1701
1702 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1703 {
1704 int value = 0xff;
1705
1706 switch (address) {
1707 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1708 cirrus_hook_read_gr(s, 0x00, &value);
1709 break;
1710 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1711 cirrus_hook_read_gr(s, 0x10, &value);
1712 break;
1713 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1714 cirrus_hook_read_gr(s, 0x12, &value);
1715 break;
1716 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1717 cirrus_hook_read_gr(s, 0x14, &value);
1718 break;
1719 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1720 cirrus_hook_read_gr(s, 0x01, &value);
1721 break;
1722 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1723 cirrus_hook_read_gr(s, 0x11, &value);
1724 break;
1725 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1726 cirrus_hook_read_gr(s, 0x13, &value);
1727 break;
1728 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1729 cirrus_hook_read_gr(s, 0x15, &value);
1730 break;
1731 case (CIRRUS_MMIO_BLTWIDTH + 0):
1732 cirrus_hook_read_gr(s, 0x20, &value);
1733 break;
1734 case (CIRRUS_MMIO_BLTWIDTH + 1):
1735 cirrus_hook_read_gr(s, 0x21, &value);
1736 break;
1737 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1738 cirrus_hook_read_gr(s, 0x22, &value);
1739 break;
1740 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1741 cirrus_hook_read_gr(s, 0x23, &value);
1742 break;
1743 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1744 cirrus_hook_read_gr(s, 0x24, &value);
1745 break;
1746 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1747 cirrus_hook_read_gr(s, 0x25, &value);
1748 break;
1749 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1750 cirrus_hook_read_gr(s, 0x26, &value);
1751 break;
1752 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1753 cirrus_hook_read_gr(s, 0x27, &value);
1754 break;
1755 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1756 cirrus_hook_read_gr(s, 0x28, &value);
1757 break;
1758 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1759 cirrus_hook_read_gr(s, 0x29, &value);
1760 break;
1761 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1762 cirrus_hook_read_gr(s, 0x2a, &value);
1763 break;
1764 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1765 cirrus_hook_read_gr(s, 0x2c, &value);
1766 break;
1767 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1768 cirrus_hook_read_gr(s, 0x2d, &value);
1769 break;
1770 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1771 cirrus_hook_read_gr(s, 0x2e, &value);
1772 break;
1773 case CIRRUS_MMIO_BLTWRITEMASK:
1774 cirrus_hook_read_gr(s, 0x2f, &value);
1775 break;
1776 case CIRRUS_MMIO_BLTMODE:
1777 cirrus_hook_read_gr(s, 0x30, &value);
1778 break;
1779 case CIRRUS_MMIO_BLTROP:
1780 cirrus_hook_read_gr(s, 0x32, &value);
1781 break;
1782 case CIRRUS_MMIO_BLTMODEEXT:
1783 cirrus_hook_read_gr(s, 0x33, &value);
1784 break;
1785 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1786 cirrus_hook_read_gr(s, 0x34, &value);
1787 break;
1788 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1789 cirrus_hook_read_gr(s, 0x35, &value);
1790 break;
1791 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1792 cirrus_hook_read_gr(s, 0x38, &value);
1793 break;
1794 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1795 cirrus_hook_read_gr(s, 0x39, &value);
1796 break;
1797 case CIRRUS_MMIO_BLTSTATUS:
1798 cirrus_hook_read_gr(s, 0x31, &value);
1799 break;
1800 default:
1801 #ifdef DEBUG_CIRRUS
1802 printf("cirrus: mmio read - address 0x%04x\n", address);
1803 #endif
1804 break;
1805 }
1806
1807 return (uint8_t) value;
1808 }
1809
1810 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1811 uint8_t value)
1812 {
1813 switch (address) {
1814 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1815 cirrus_hook_write_gr(s, 0x00, value);
1816 break;
1817 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1818 cirrus_hook_write_gr(s, 0x10, value);
1819 break;
1820 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1821 cirrus_hook_write_gr(s, 0x12, value);
1822 break;
1823 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1824 cirrus_hook_write_gr(s, 0x14, value);
1825 break;
1826 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1827 cirrus_hook_write_gr(s, 0x01, value);
1828 break;
1829 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1830 cirrus_hook_write_gr(s, 0x11, value);
1831 break;
1832 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1833 cirrus_hook_write_gr(s, 0x13, value);
1834 break;
1835 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1836 cirrus_hook_write_gr(s, 0x15, value);
1837 break;
1838 case (CIRRUS_MMIO_BLTWIDTH + 0):
1839 cirrus_hook_write_gr(s, 0x20, value);
1840 break;
1841 case (CIRRUS_MMIO_BLTWIDTH + 1):
1842 cirrus_hook_write_gr(s, 0x21, value);
1843 break;
1844 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1845 cirrus_hook_write_gr(s, 0x22, value);
1846 break;
1847 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1848 cirrus_hook_write_gr(s, 0x23, value);
1849 break;
1850 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1851 cirrus_hook_write_gr(s, 0x24, value);
1852 break;
1853 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1854 cirrus_hook_write_gr(s, 0x25, value);
1855 break;
1856 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1857 cirrus_hook_write_gr(s, 0x26, value);
1858 break;
1859 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1860 cirrus_hook_write_gr(s, 0x27, value);
1861 break;
1862 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1863 cirrus_hook_write_gr(s, 0x28, value);
1864 break;
1865 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1866 cirrus_hook_write_gr(s, 0x29, value);
1867 break;
1868 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1869 cirrus_hook_write_gr(s, 0x2a, value);
1870 break;
1871 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1872 /* ignored */
1873 break;
1874 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1875 cirrus_hook_write_gr(s, 0x2c, value);
1876 break;
1877 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1878 cirrus_hook_write_gr(s, 0x2d, value);
1879 break;
1880 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1881 cirrus_hook_write_gr(s, 0x2e, value);
1882 break;
1883 case CIRRUS_MMIO_BLTWRITEMASK:
1884 cirrus_hook_write_gr(s, 0x2f, value);
1885 break;
1886 case CIRRUS_MMIO_BLTMODE:
1887 cirrus_hook_write_gr(s, 0x30, value);
1888 break;
1889 case CIRRUS_MMIO_BLTROP:
1890 cirrus_hook_write_gr(s, 0x32, value);
1891 break;
1892 case CIRRUS_MMIO_BLTMODEEXT:
1893 cirrus_hook_write_gr(s, 0x33, value);
1894 break;
1895 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1896 cirrus_hook_write_gr(s, 0x34, value);
1897 break;
1898 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1899 cirrus_hook_write_gr(s, 0x35, value);
1900 break;
1901 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1902 cirrus_hook_write_gr(s, 0x38, value);
1903 break;
1904 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1905 cirrus_hook_write_gr(s, 0x39, value);
1906 break;
1907 case CIRRUS_MMIO_BLTSTATUS:
1908 cirrus_hook_write_gr(s, 0x31, value);
1909 break;
1910 default:
1911 #ifdef DEBUG_CIRRUS
1912 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1913 address, value);
1914 #endif
1915 break;
1916 }
1917 }
1918
1919 /***************************************
1920 *
1921 * write mode 4/5
1922 *
1923 * assume TARGET_PAGE_SIZE >= 16
1924 *
1925 ***************************************/
1926
1927 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1928 unsigned mode,
1929 unsigned offset,
1930 uint32_t mem_value)
1931 {
1932 int x;
1933 unsigned val = mem_value;
1934 uint8_t *dst;
1935
1936 dst = s->vram_ptr + offset;
1937 for (x = 0; x < 8; x++) {
1938 if (val & 0x80) {
1939 *dst = s->cirrus_shadow_gr1;
1940 } else if (mode == 5) {
1941 *dst = s->cirrus_shadow_gr0;
1942 }
1943 val <<= 1;
1944 dst++;
1945 }
1946 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1947 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1948 }
1949
1950 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1951 unsigned mode,
1952 unsigned offset,
1953 uint32_t mem_value)
1954 {
1955 int x;
1956 unsigned val = mem_value;
1957 uint8_t *dst;
1958
1959 dst = s->vram_ptr + offset;
1960 for (x = 0; x < 8; x++) {
1961 if (val & 0x80) {
1962 *dst = s->cirrus_shadow_gr1;
1963 *(dst + 1) = s->gr[0x11];
1964 } else if (mode == 5) {
1965 *dst = s->cirrus_shadow_gr0;
1966 *(dst + 1) = s->gr[0x10];
1967 }
1968 val <<= 1;
1969 dst += 2;
1970 }
1971 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1972 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1973 }
1974
1975 /***************************************
1976 *
1977 * memory access between 0xa0000-0xbffff
1978 *
1979 ***************************************/
1980
1981 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1982 {
1983 CirrusVGAState *s = opaque;
1984 unsigned bank_index;
1985 unsigned bank_offset;
1986 uint32_t val;
1987
1988 if ((s->sr[0x07] & 0x01) == 0) {
1989 return vga_mem_readb(s, addr);
1990 }
1991
1992 addr &= 0x1ffff;
1993
1994 if (addr < 0x10000) {
1995 /* XXX handle bitblt */
1996 /* video memory */
1997 bank_index = addr >> 15;
1998 bank_offset = addr & 0x7fff;
1999 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2000 bank_offset += s->cirrus_bank_base[bank_index];
2001 if ((s->gr[0x0B] & 0x14) == 0x14) {
2002 bank_offset <<= 4;
2003 } else if (s->gr[0x0B] & 0x02) {
2004 bank_offset <<= 3;
2005 }
2006 bank_offset &= s->cirrus_addr_mask;
2007 val = *(s->vram_ptr + bank_offset);
2008 } else
2009 val = 0xff;
2010 } else if (addr >= 0x18000 && addr < 0x18100) {
2011 /* memory-mapped I/O */
2012 val = 0xff;
2013 if ((s->sr[0x17] & 0x44) == 0x04) {
2014 val = cirrus_mmio_blt_read(s, addr & 0xff);
2015 }
2016 } else {
2017 val = 0xff;
2018 #ifdef DEBUG_CIRRUS
2019 printf("cirrus: mem_readb %06x\n", addr);
2020 #endif
2021 }
2022 return val;
2023 }
2024
2025 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2026 {
2027 uint32_t v;
2028 #ifdef TARGET_WORDS_BIGENDIAN
2029 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2030 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2031 #else
2032 v = cirrus_vga_mem_readb(opaque, addr);
2033 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2034 #endif
2035 return v;
2036 }
2037
2038 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2039 {
2040 uint32_t v;
2041 #ifdef TARGET_WORDS_BIGENDIAN
2042 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2043 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2044 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2045 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2046 #else
2047 v = cirrus_vga_mem_readb(opaque, addr);
2048 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2049 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2050 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2051 #endif
2052 return v;
2053 }
2054
2055 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2056 uint32_t mem_value)
2057 {
2058 CirrusVGAState *s = opaque;
2059 unsigned bank_index;
2060 unsigned bank_offset;
2061 unsigned mode;
2062
2063 if ((s->sr[0x07] & 0x01) == 0) {
2064 vga_mem_writeb(s, addr, mem_value);
2065 return;
2066 }
2067
2068 addr &= 0x1ffff;
2069
2070 if (addr < 0x10000) {
2071 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2072 /* bitblt */
2073 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2074 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2075 cirrus_bitblt_cputovideo_next(s);
2076 }
2077 } else {
2078 /* video memory */
2079 bank_index = addr >> 15;
2080 bank_offset = addr & 0x7fff;
2081 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2082 bank_offset += s->cirrus_bank_base[bank_index];
2083 if ((s->gr[0x0B] & 0x14) == 0x14) {
2084 bank_offset <<= 4;
2085 } else if (s->gr[0x0B] & 0x02) {
2086 bank_offset <<= 3;
2087 }
2088 bank_offset &= s->cirrus_addr_mask;
2089 mode = s->gr[0x05] & 0x7;
2090 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2091 *(s->vram_ptr + bank_offset) = mem_value;
2092 cpu_physical_memory_set_dirty(s->vram_offset +
2093 bank_offset);
2094 } else {
2095 if ((s->gr[0x0B] & 0x14) != 0x14) {
2096 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2097 bank_offset,
2098 mem_value);
2099 } else {
2100 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2101 bank_offset,
2102 mem_value);
2103 }
2104 }
2105 }
2106 }
2107 } else if (addr >= 0x18000 && addr < 0x18100) {
2108 /* memory-mapped I/O */
2109 if ((s->sr[0x17] & 0x44) == 0x04) {
2110 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2111 }
2112 } else {
2113 #ifdef DEBUG_CIRRUS
2114 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2115 #endif
2116 }
2117 }
2118
2119 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2120 {
2121 #ifdef TARGET_WORDS_BIGENDIAN
2122 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2123 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2124 #else
2125 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2126 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2127 #endif
2128 }
2129
2130 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2131 {
2132 #ifdef TARGET_WORDS_BIGENDIAN
2133 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2134 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2135 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2136 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2137 #else
2138 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2139 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2140 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2141 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2142 #endif
2143 }
2144
2145 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2146 cirrus_vga_mem_readb,
2147 cirrus_vga_mem_readw,
2148 cirrus_vga_mem_readl,
2149 };
2150
2151 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2152 cirrus_vga_mem_writeb,
2153 cirrus_vga_mem_writew,
2154 cirrus_vga_mem_writel,
2155 };
2156
2157 /***************************************
2158 *
2159 * hardware cursor
2160 *
2161 ***************************************/
2162
2163 static inline void invalidate_cursor1(CirrusVGAState *s)
2164 {
2165 if (s->last_hw_cursor_size) {
2166 vga_invalidate_scanlines((VGAState *)s,
2167 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2168 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2169 }
2170 }
2171
2172 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2173 {
2174 const uint8_t *src;
2175 uint32_t content;
2176 int y, y_min, y_max;
2177
2178 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2179 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2180 src += (s->sr[0x13] & 0x3c) * 256;
2181 y_min = 64;
2182 y_max = -1;
2183 for(y = 0; y < 64; y++) {
2184 content = ((uint32_t *)src)[0] |
2185 ((uint32_t *)src)[1] |
2186 ((uint32_t *)src)[2] |
2187 ((uint32_t *)src)[3];
2188 if (content) {
2189 if (y < y_min)
2190 y_min = y;
2191 if (y > y_max)
2192 y_max = y;
2193 }
2194 src += 16;
2195 }
2196 } else {
2197 src += (s->sr[0x13] & 0x3f) * 256;
2198 y_min = 32;
2199 y_max = -1;
2200 for(y = 0; y < 32; y++) {
2201 content = ((uint32_t *)src)[0] |
2202 ((uint32_t *)(src + 128))[0];
2203 if (content) {
2204 if (y < y_min)
2205 y_min = y;
2206 if (y > y_max)
2207 y_max = y;
2208 }
2209 src += 4;
2210 }
2211 }
2212 if (y_min > y_max) {
2213 s->last_hw_cursor_y_start = 0;
2214 s->last_hw_cursor_y_end = 0;
2215 } else {
2216 s->last_hw_cursor_y_start = y_min;
2217 s->last_hw_cursor_y_end = y_max + 1;
2218 }
2219 }
2220
2221 /* NOTE: we do not currently handle the cursor bitmap change, so we
2222 update the cursor only if it moves. */
2223 static void cirrus_cursor_invalidate(VGAState *s1)
2224 {
2225 CirrusVGAState *s = (CirrusVGAState *)s1;
2226 int size;
2227
2228 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2229 size = 0;
2230 } else {
2231 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2232 size = 64;
2233 else
2234 size = 32;
2235 }
2236 /* invalidate last cursor and new cursor if any change */
2237 if (s->last_hw_cursor_size != size ||
2238 s->last_hw_cursor_x != s->hw_cursor_x ||
2239 s->last_hw_cursor_y != s->hw_cursor_y) {
2240
2241 invalidate_cursor1(s);
2242
2243 s->last_hw_cursor_size = size;
2244 s->last_hw_cursor_x = s->hw_cursor_x;
2245 s->last_hw_cursor_y = s->hw_cursor_y;
2246 /* compute the real cursor min and max y */
2247 cirrus_cursor_compute_yrange(s);
2248 invalidate_cursor1(s);
2249 }
2250 }
2251
2252 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2253 {
2254 CirrusVGAState *s = (CirrusVGAState *)s1;
2255 int w, h, bpp, x1, x2, poffset;
2256 unsigned int color0, color1;
2257 const uint8_t *palette, *src;
2258 uint32_t content;
2259
2260 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2261 return;
2262 /* fast test to see if the cursor intersects with the scan line */
2263 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2264 h = 64;
2265 } else {
2266 h = 32;
2267 }
2268 if (scr_y < s->hw_cursor_y ||
2269 scr_y >= (s->hw_cursor_y + h))
2270 return;
2271
2272 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2273 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2274 src += (s->sr[0x13] & 0x3c) * 256;
2275 src += (scr_y - s->hw_cursor_y) * 16;
2276 poffset = 8;
2277 content = ((uint32_t *)src)[0] |
2278 ((uint32_t *)src)[1] |
2279 ((uint32_t *)src)[2] |
2280 ((uint32_t *)src)[3];
2281 } else {
2282 src += (s->sr[0x13] & 0x3f) * 256;
2283 src += (scr_y - s->hw_cursor_y) * 4;
2284 poffset = 128;
2285 content = ((uint32_t *)src)[0] |
2286 ((uint32_t *)(src + 128))[0];
2287 }
2288 /* if nothing to draw, no need to continue */
2289 if (!content)
2290 return;
2291 w = h;
2292
2293 x1 = s->hw_cursor_x;
2294 if (x1 >= s->last_scr_width)
2295 return;
2296 x2 = s->hw_cursor_x + w;
2297 if (x2 > s->last_scr_width)
2298 x2 = s->last_scr_width;
2299 w = x2 - x1;
2300 palette = s->cirrus_hidden_palette;
2301 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2302 c6_to_8(palette[0x0 * 3 + 1]),
2303 c6_to_8(palette[0x0 * 3 + 2]));
2304 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2305 c6_to_8(palette[0xf * 3 + 1]),
2306 c6_to_8(palette[0xf * 3 + 2]));
2307 bpp = ((s->ds->depth + 7) >> 3);
2308 d1 += x1 * bpp;
2309 switch(s->ds->depth) {
2310 default:
2311 break;
2312 case 8:
2313 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2314 break;
2315 case 15:
2316 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2317 break;
2318 case 16:
2319 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2320 break;
2321 case 32:
2322 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2323 break;
2324 }
2325 }
2326
2327 /***************************************
2328 *
2329 * LFB memory access
2330 *
2331 ***************************************/
2332
2333 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2334 {
2335 CirrusVGAState *s = (CirrusVGAState *) opaque;
2336 uint32_t ret;
2337
2338 addr &= s->cirrus_addr_mask;
2339
2340 if (((s->sr[0x17] & 0x44) == 0x44) &&
2341 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2342 /* memory-mapped I/O */
2343 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2344 } else if (0) {
2345 /* XXX handle bitblt */
2346 ret = 0xff;
2347 } else {
2348 /* video memory */
2349 if ((s->gr[0x0B] & 0x14) == 0x14) {
2350 addr <<= 4;
2351 } else if (s->gr[0x0B] & 0x02) {
2352 addr <<= 3;
2353 }
2354 addr &= s->cirrus_addr_mask;
2355 ret = *(s->vram_ptr + addr);
2356 }
2357
2358 return ret;
2359 }
2360
2361 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2362 {
2363 uint32_t v;
2364 #ifdef TARGET_WORDS_BIGENDIAN
2365 v = cirrus_linear_readb(opaque, addr) << 8;
2366 v |= cirrus_linear_readb(opaque, addr + 1);
2367 #else
2368 v = cirrus_linear_readb(opaque, addr);
2369 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2370 #endif
2371 return v;
2372 }
2373
2374 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2375 {
2376 uint32_t v;
2377 #ifdef TARGET_WORDS_BIGENDIAN
2378 v = cirrus_linear_readb(opaque, addr) << 24;
2379 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2380 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2381 v |= cirrus_linear_readb(opaque, addr + 3);
2382 #else
2383 v = cirrus_linear_readb(opaque, addr);
2384 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2385 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2386 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2387 #endif
2388 return v;
2389 }
2390
2391 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2392 uint32_t val)
2393 {
2394 CirrusVGAState *s = (CirrusVGAState *) opaque;
2395 unsigned mode;
2396
2397 addr &= s->cirrus_addr_mask;
2398
2399 if (((s->sr[0x17] & 0x44) == 0x44) &&
2400 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2401 /* memory-mapped I/O */
2402 cirrus_mmio_blt_write(s, addr & 0xff, val);
2403 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2404 /* bitblt */
2405 *s->cirrus_srcptr++ = (uint8_t) val;
2406 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2407 cirrus_bitblt_cputovideo_next(s);
2408 }
2409 } else {
2410 /* video memory */
2411 if ((s->gr[0x0B] & 0x14) == 0x14) {
2412 addr <<= 4;
2413 } else if (s->gr[0x0B] & 0x02) {
2414 addr <<= 3;
2415 }
2416 addr &= s->cirrus_addr_mask;
2417
2418 mode = s->gr[0x05] & 0x7;
2419 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2420 *(s->vram_ptr + addr) = (uint8_t) val;
2421 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2422 } else {
2423 if ((s->gr[0x0B] & 0x14) != 0x14) {
2424 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2425 } else {
2426 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2427 }
2428 }
2429 }
2430 }
2431
2432 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2433 uint32_t val)
2434 {
2435 #ifdef TARGET_WORDS_BIGENDIAN
2436 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2437 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2438 #else
2439 cirrus_linear_writeb(opaque, addr, val & 0xff);
2440 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2441 #endif
2442 }
2443
2444 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2445 uint32_t val)
2446 {
2447 #ifdef TARGET_WORDS_BIGENDIAN
2448 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2449 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2450 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2451 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2452 #else
2453 cirrus_linear_writeb(opaque, addr, val & 0xff);
2454 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2455 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2456 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2457 #endif
2458 }
2459
2460
2461 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2462 cirrus_linear_readb,
2463 cirrus_linear_readw,
2464 cirrus_linear_readl,
2465 };
2466
2467 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2468 cirrus_linear_writeb,
2469 cirrus_linear_writew,
2470 cirrus_linear_writel,
2471 };
2472
2473 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2474 uint32_t val)
2475 {
2476 CirrusVGAState *s = (CirrusVGAState *) opaque;
2477
2478 addr &= s->cirrus_addr_mask;
2479 *(s->vram_ptr + addr) = val;
2480 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2481 }
2482
2483 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2484 uint32_t val)
2485 {
2486 CirrusVGAState *s = (CirrusVGAState *) opaque;
2487
2488 addr &= s->cirrus_addr_mask;
2489 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2490 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2491 }
2492
2493 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2494 uint32_t val)
2495 {
2496 CirrusVGAState *s = (CirrusVGAState *) opaque;
2497
2498 addr &= s->cirrus_addr_mask;
2499 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2500 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2501 }
2502
2503 /***************************************
2504 *
2505 * system to screen memory access
2506 *
2507 ***************************************/
2508
2509
2510 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2511 {
2512 uint32_t ret;
2513
2514 /* XXX handle bitblt */
2515 ret = 0xff;
2516 return ret;
2517 }
2518
2519 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2520 {
2521 uint32_t v;
2522 #ifdef TARGET_WORDS_BIGENDIAN
2523 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2524 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2525 #else
2526 v = cirrus_linear_bitblt_readb(opaque, addr);
2527 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2528 #endif
2529 return v;
2530 }
2531
2532 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2533 {
2534 uint32_t v;
2535 #ifdef TARGET_WORDS_BIGENDIAN
2536 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2537 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2538 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2539 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2540 #else
2541 v = cirrus_linear_bitblt_readb(opaque, addr);
2542 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2543 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2544 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2545 #endif
2546 return v;
2547 }
2548
2549 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2550 uint32_t val)
2551 {
2552 CirrusVGAState *s = (CirrusVGAState *) opaque;
2553
2554 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2555 /* bitblt */
2556 *s->cirrus_srcptr++ = (uint8_t) val;
2557 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2558 cirrus_bitblt_cputovideo_next(s);
2559 }
2560 }
2561 }
2562
2563 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2564 uint32_t val)
2565 {
2566 #ifdef TARGET_WORDS_BIGENDIAN
2567 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2568 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2569 #else
2570 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2571 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2572 #endif
2573 }
2574
2575 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2576 uint32_t val)
2577 {
2578 #ifdef TARGET_WORDS_BIGENDIAN
2579 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2580 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2581 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2582 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2583 #else
2584 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2585 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2586 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2587 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2588 #endif
2589 }
2590
2591
2592 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2593 cirrus_linear_bitblt_readb,
2594 cirrus_linear_bitblt_readw,
2595 cirrus_linear_bitblt_readl,
2596 };
2597
2598 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2599 cirrus_linear_bitblt_writeb,
2600 cirrus_linear_bitblt_writew,
2601 cirrus_linear_bitblt_writel,
2602 };
2603
2604 #ifdef USE_KVM
2605
2606 #include "qemu-kvm.h"
2607
2608 extern kvm_context_t kvm_context;
2609
2610 void *set_vram_mapping(unsigned long begin, unsigned long end)
2611 {
2612 void *vram_pointer = NULL;
2613
2614 /* align begin and end address */
2615 begin = begin & TARGET_PAGE_MASK;
2616 end = begin + VGA_RAM_SIZE;
2617 end = (end + TARGET_PAGE_SIZE -1 ) & TARGET_PAGE_MASK;
2618
2619 vram_pointer = kvm_create_phys_mem(kvm_context, begin, end - begin,
2620 1, 1);
2621
2622 if (vram_pointer == NULL) {
2623 printf("set_vram_mapping: cannot allocate memory: %m\n");
2624 return NULL;
2625 }
2626
2627 memset(vram_pointer, 0, end - begin);
2628
2629 return vram_pointer;
2630 }
2631
2632 int unset_vram_mapping(unsigned long begin, unsigned long end)
2633 {
2634 /* align begin and end address */
2635 end = begin + VGA_RAM_SIZE;
2636 begin = begin & TARGET_PAGE_MASK;
2637 end = (end + TARGET_PAGE_SIZE -1 ) & TARGET_PAGE_MASK;
2638
2639 kvm_destroy_phys_mem(kvm_context, begin, end - begin);
2640
2641 return 0;
2642 }
2643 #ifdef CONFIG_X86
2644 static void kvm_update_vga_alias(CirrusVGAState *s, int ok, int bank,
2645 unsigned long phys_addr)
2646 {
2647 unsigned limit, base;
2648
2649 if (!ok && !s->aliases_enabled)
2650 return;
2651 limit = s->cirrus_bank_limit[bank];
2652 if (limit > 0x8000)
2653 limit = 0x8000;
2654 base = s->cirrus_lfb_addr + s->cirrus_bank_base[bank];
2655 if (ok) {
2656 if (!s->aliases_enabled
2657 || base != s->aliased_bank_base[bank]
2658 || limit != s->aliased_bank_limit[bank]) {
2659 kvm_create_memory_alias(kvm_context, phys_addr,
2660 0xa0000 + bank * 0x8000,
2661 limit, base);
2662 s->aliased_bank_base[bank] = base;
2663 s->aliased_bank_limit[bank] = limit;
2664 }
2665 } else {
2666 kvm_destroy_memory_alias(kvm_context, phys_addr);
2667 }
2668 }
2669
2670 static void kvm_update_vga_aliases(CirrusVGAState *s, int ok)
2671 {
2672 if (kvm_allowed) {
2673 kvm_update_vga_alias(s, ok, 0, 0xc0000);
2674 kvm_update_vga_alias(s, ok, 1, s->map_addr);
2675 }
2676 s->aliases_enabled = ok;
2677 }
2678 #endif
2679 #endif
2680
2681 /* Compute the memory access functions */
2682 static void cirrus_update_memory_access(CirrusVGAState *s)
2683 {
2684 unsigned mode;
2685 #if defined(USE_KVM) && defined(CONFIG_X86)
2686 int want_vga_alias = 0;
2687 #endif
2688
2689 if ((s->sr[0x17] & 0x44) == 0x44) {
2690 goto generic_io;
2691 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2692 goto generic_io;
2693 } else {
2694 if ((s->gr[0x0B] & 0x14) == 0x14) {
2695 goto generic_io;
2696 } else if (s->gr[0x0B] & 0x02) {
2697 goto generic_io;
2698 }
2699
2700 mode = s->gr[0x05] & 0x7;
2701 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2702 #ifdef USE_KVM
2703 if (kvm_allowed && s->cirrus_lfb_addr && s->cirrus_lfb_end &&
2704 !s->map_addr) {
2705 void *vram_pointer, *old_vram;
2706
2707 vram_pointer = set_vram_mapping(s->cirrus_lfb_addr,
2708 s->cirrus_lfb_end);
2709 if (!vram_pointer)
2710 fprintf(stderr, "NULL vram_pointer\n");
2711 else {
2712 old_vram = vga_update_vram((VGAState *)s, vram_pointer,
2713 VGA_RAM_SIZE);
2714 qemu_free(old_vram);
2715 }
2716 s->map_addr = s->cirrus_lfb_addr;
2717 s->map_end = s->cirrus_lfb_end;
2718 }
2719 #ifdef CONFIG_X86
2720 if (kvm_allowed
2721 && !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2722 && !((s->sr[0x07] & 0x01) == 0)
2723 && !((s->gr[0x0B] & 0x14) == 0x14)
2724 && !(s->gr[0x0B] & 0x02))
2725 want_vga_alias = 1;
2726 #endif
2727 #endif
2728 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2729 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2730 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2731 } else {
2732 generic_io:
2733 #ifdef USE_KVM
2734 if (kvm_allowed && s->cirrus_lfb_addr && s->cirrus_lfb_end &&
2735 s->map_addr) {
2736 int error;
2737 void *old_vram = NULL;
2738
2739 error = unset_vram_mapping(s->cirrus_lfb_addr,
2740 s->cirrus_lfb_end);
2741 if (!error)
2742 old_vram = vga_update_vram((VGAState *)s, NULL,
2743 VGA_RAM_SIZE);
2744 if (old_vram)
2745 munmap(old_vram, s->map_end - s->map_addr);
2746 s->map_addr = s->map_end = 0;
2747 }
2748 #endif
2749 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2750 s->cirrus_linear_write[1] = cirrus_linear_writew;
2751 s->cirrus_linear_write[2] = cirrus_linear_writel;
2752 }
2753 }
2754 #if defined(USE_KVM) && defined(CONFIG_X86)
2755 kvm_update_vga_aliases(s, want_vga_alias);
2756 #endif
2757
2758 }
2759
2760
2761 /* I/O ports */
2762
2763 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2764 {
2765 CirrusVGAState *s = opaque;
2766 int val, index;
2767
2768 /* check port range access depending on color/monochrome mode */
2769 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2770 || (addr >= 0x3d0 && addr <= 0x3df
2771 && !(s->msr & MSR_COLOR_EMULATION))) {
2772 val = 0xff;
2773 } else {
2774 switch (addr) {
2775 case 0x3c0:
2776 if (s->ar_flip_flop == 0) {
2777 val = s->ar_index;
2778 } else {
2779 val = 0;
2780 }
2781 break;
2782 case 0x3c1:
2783 index = s->ar_index & 0x1f;
2784 if (index < 21)
2785 val = s->ar[index];
2786 else
2787 val = 0;
2788 break;
2789 case 0x3c2:
2790 val = s->st00;
2791 break;
2792 case 0x3c4:
2793 val = s->sr_index;
2794 break;
2795 case 0x3c5:
2796 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2797 break;
2798 val = s->sr[s->sr_index];
2799 #ifdef DEBUG_VGA_REG
2800 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2801 #endif
2802 break;
2803 case 0x3c6:
2804 cirrus_read_hidden_dac(s, &val);
2805 break;
2806 case 0x3c7:
2807 val = s->dac_state;
2808 break;
2809 case 0x3c8:
2810 val = s->dac_write_index;
2811 s->cirrus_hidden_dac_lockindex = 0;
2812 break;
2813 case 0x3c9:
2814 if (cirrus_hook_read_palette(s, &val))
2815 break;
2816 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2817 if (++s->dac_sub_index == 3) {
2818 s->dac_sub_index = 0;
2819 s->dac_read_index++;
2820 }
2821 break;
2822 case 0x3ca:
2823 val = s->fcr;
2824 break;
2825 case 0x3cc:
2826 val = s->msr;
2827 break;
2828 case 0x3ce:
2829 val = s->gr_index;
2830 break;
2831 case 0x3cf:
2832 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2833 break;
2834 val = s->gr[s->gr_index];
2835 #ifdef DEBUG_VGA_REG
2836 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2837 #endif
2838 break;
2839 case 0x3b4:
2840 case 0x3d4:
2841 val = s->cr_index;
2842 break;
2843 case 0x3b5:
2844 case 0x3d5:
2845 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2846 break;
2847 val = s->cr[s->cr_index];
2848 #ifdef DEBUG_VGA_REG
2849 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2850 #endif
2851 break;
2852 case 0x3ba:
2853 case 0x3da:
2854 /* just toggle to fool polling */
2855 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
2856 val = s->st01;
2857 s->ar_flip_flop = 0;
2858 break;
2859 default:
2860 val = 0x00;
2861 break;
2862 }
2863 }
2864 #if defined(DEBUG_VGA)
2865 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2866 #endif
2867 return val;
2868 }
2869
2870 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2871 {
2872 CirrusVGAState *s = opaque;
2873 int index;
2874
2875 /* check port range access depending on color/monochrome mode */
2876 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2877 || (addr >= 0x3d0 && addr <= 0x3df
2878 && !(s->msr & MSR_COLOR_EMULATION)))
2879 return;
2880
2881 #ifdef DEBUG_VGA
2882 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2883 #endif
2884
2885 switch (addr) {
2886 case 0x3c0:
2887 if (s->ar_flip_flop == 0) {
2888 val &= 0x3f;
2889 s->ar_index = val;
2890 } else {
2891 index = s->ar_index & 0x1f;
2892 switch (index) {
2893 case 0x00 ... 0x0f:
2894 s->ar[index] = val & 0x3f;
2895 break;
2896 case 0x10:
2897 s->ar[index] = val & ~0x10;
2898 break;
2899 case 0x11:
2900 s->ar[index] = val;
2901 break;
2902 case 0x12:
2903 s->ar[index] = val & ~0xc0;
2904 break;
2905 case 0x13:
2906 s->ar[index] = val & ~0xf0;
2907 break;
2908 case 0x14:
2909 s->ar[index] = val & ~0xf0;
2910 break;
2911 default:
2912 break;
2913 }
2914 }
2915 s->ar_flip_flop ^= 1;
2916 break;
2917 case 0x3c2:
2918 s->msr = val & ~0x10;
2919 break;
2920 case 0x3c4:
2921 s->sr_index = val;
2922 break;
2923 case 0x3c5:
2924 if (cirrus_hook_write_sr(s, s->sr_index, val))
2925 break;
2926 #ifdef DEBUG_VGA_REG
2927 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2928 #endif
2929 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2930 break;
2931 case 0x3c6:
2932 cirrus_write_hidden_dac(s, val);
2933 break;
2934 case 0x3c7:
2935 s->dac_read_index = val;
2936 s->dac_sub_index = 0;
2937 s->dac_state = 3;
2938 break;
2939 case 0x3c8:
2940 s->dac_write_index = val;
2941 s->dac_sub_index = 0;
2942 s->dac_state = 0;
2943 break;
2944 case 0x3c9:
2945 if (cirrus_hook_write_palette(s, val))
2946 break;
2947 s->dac_cache[s->dac_sub_index] = val;
2948 if (++s->dac_sub_index == 3) {
2949 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2950 s->dac_sub_index = 0;
2951 s->dac_write_index++;
2952 }
2953 break;
2954 case 0x3ce:
2955 s->gr_index = val;
2956 break;
2957 case 0x3cf:
2958 if (cirrus_hook_write_gr(s, s->gr_index, val))
2959 break;
2960 #ifdef DEBUG_VGA_REG
2961 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2962 #endif
2963 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2964 break;
2965 case 0x3b4:
2966 case 0x3d4:
2967 s->cr_index = val;
2968 break;
2969 case 0x3b5:
2970 case 0x3d5:
2971 if (cirrus_hook_write_cr(s, s->cr_index, val))
2972 break;
2973 #ifdef DEBUG_VGA_REG
2974 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2975 #endif
2976 /* handle CR0-7 protection */
2977 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2978 /* can always write bit 4 of CR7 */
2979 if (s->cr_index == 7)
2980 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2981 return;
2982 }
2983 switch (s->cr_index) {
2984 case 0x01: /* horizontal display end */
2985 case 0x07:
2986 case 0x09:
2987 case 0x0c:
2988 case 0x0d:
2989 case 0x12: /* vertical display end */
2990 s->cr[s->cr_index] = val;
2991 break;
2992
2993 default:
2994 s->cr[s->cr_index] = val;
2995 break;
2996 }
2997 break;
2998 case 0x3ba:
2999 case 0x3da:
3000 s->fcr = val & 0x10;
3001 break;
3002 }
3003 }
3004
3005 /***************************************
3006 *
3007 * memory-mapped I/O access
3008 *
3009 ***************************************/
3010
3011 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
3012 {
3013 CirrusVGAState *s = (CirrusVGAState *) opaque;
3014
3015 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3016
3017 if (addr >= 0x100) {
3018 return cirrus_mmio_blt_read(s, addr - 0x100);
3019 } else {
3020 return vga_ioport_read(s, addr + 0x3c0);
3021 }
3022 }
3023
3024 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
3025 {
3026 uint32_t v;
3027 #ifdef TARGET_WORDS_BIGENDIAN
3028 v = cirrus_mmio_readb(opaque, addr) << 8;
3029 v |= cirrus_mmio_readb(opaque, addr + 1);
3030 #else
3031 v = cirrus_mmio_readb(opaque, addr);
3032 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3033 #endif
3034 return v;
3035 }
3036
3037 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
3038 {
3039 uint32_t v;
3040 #ifdef TARGET_WORDS_BIGENDIAN
3041 v = cirrus_mmio_readb(opaque, addr) << 24;
3042 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3043 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3044 v |= cirrus_mmio_readb(opaque, addr + 3);
3045 #else
3046 v = cirrus_mmio_readb(opaque, addr);
3047 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3048 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3049 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3050 #endif
3051 return v;
3052 }
3053
3054 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3055 uint32_t val)
3056 {
3057 CirrusVGAState *s = (CirrusVGAState *) opaque;
3058
3059 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3060
3061 if (addr >= 0x100) {
3062 cirrus_mmio_blt_write(s, addr - 0x100, val);
3063 } else {
3064 vga_ioport_write(s, addr + 0x3c0, val);
3065 }
3066 }
3067
3068 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3069 uint32_t val)
3070 {
3071 #ifdef TARGET_WORDS_BIGENDIAN
3072 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3073 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3074 #else
3075 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3076 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3077 #endif
3078 }
3079
3080 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3081 uint32_t val)
3082 {
3083 #ifdef TARGET_WORDS_BIGENDIAN
3084 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3085 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3086 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3087 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3088 #else
3089 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3090 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3091 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3092 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3093 #endif
3094 }
3095
3096
3097 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3098 cirrus_mmio_readb,
3099 cirrus_mmio_readw,
3100 cirrus_mmio_readl,
3101 };
3102
3103 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3104 cirrus_mmio_writeb,
3105 cirrus_mmio_writew,
3106 cirrus_mmio_writel,
3107 };
3108
3109 /* load/save state */
3110
3111 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3112 {
3113 CirrusVGAState *s = opaque;
3114
3115 if (s->pci_dev)
3116 pci_device_save(s->pci_dev, f);
3117
3118 qemu_put_be32s(f, &s->latch);
3119 qemu_put_8s(f, &s->sr_index);
3120 qemu_put_buffer(f, s->sr, 256);
3121 qemu_put_8s(f, &s->gr_index);
3122 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3123 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3124 qemu_put_buffer(f, s->gr + 2, 254);
3125 qemu_put_8s(f, &s->ar_index);
3126 qemu_put_buffer(f, s->ar, 21);
3127 qemu_put_be32(f, s->ar_flip_flop);
3128 qemu_put_8s(f, &s->cr_index);
3129 qemu_put_buffer(f, s->cr, 256);
3130 qemu_put_8s(f, &s->msr);
3131 qemu_put_8s(f, &s->fcr);
3132 qemu_put_8s(f, &s->st00);
3133 qemu_put_8s(f, &s->st01);
3134
3135 qemu_put_8s(f, &s->dac_state);
3136 qemu_put_8s(f, &s->dac_sub_index);
3137 qemu_put_8s(f, &s->dac_read_index);
3138 qemu_put_8s(f, &s->dac_write_index);
3139 qemu_put_buffer(f, s->dac_cache, 3);
3140 qemu_put_buffer(f, s->palette, 768);
3141
3142 qemu_put_be32(f, s->bank_offset);
3143
3144 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3145 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3146
3147 qemu_put_be32s(f, &s->hw_cursor_x);
3148 qemu_put_be32s(f, &s->hw_cursor_y);
3149 /* XXX: we do not save the bitblt state - we assume we do not save
3150 the state when the blitter is active */
3151
3152 #ifdef USE_KVM
3153 if (kvm_allowed) { /* XXX: KVM images ought to be loadable in QEMU */
3154 qemu_put_be32s(f, &s->real_vram_size);
3155 qemu_put_buffer(f, s->vram_ptr, s->real_vram_size);
3156 }
3157 #endif
3158 }
3159
3160 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3161 {
3162 CirrusVGAState *s = opaque;
3163 int ret;
3164
3165 if (version_id > 2)
3166 return -EINVAL;
3167
3168 if (s->pci_dev && version_id >= 2) {
3169 ret = pci_device_load(s->pci_dev, f);
3170 if (ret < 0)
3171 return ret;
3172 }
3173
3174 qemu_get_be32s(f, &s->latch);
3175 qemu_get_8s(f, &s->sr_index);
3176 qemu_get_buffer(f, s->sr, 256);
3177 qemu_get_8s(f, &s->gr_index);
3178 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3179 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3180 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3181 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3182 qemu_get_buffer(f, s->gr + 2, 254);
3183 qemu_get_8s(f, &s->ar_index);
3184 qemu_get_buffer(f, s->ar, 21);
3185 s->ar_flip_flop=qemu_get_be32(f);
3186 qemu_get_8s(f, &s->cr_index);
3187 qemu_get_buffer(f, s->cr, 256);
3188 qemu_get_8s(f, &s->msr);
3189 qemu_get_8s(f, &s->fcr);
3190 qemu_get_8s(f, &s->st00);
3191 qemu_get_8s(f, &s->st01);
3192
3193 qemu_get_8s(f, &s->dac_state);
3194 qemu_get_8s(f, &s->dac_sub_index);
3195 qemu_get_8s(f, &s->dac_read_index);
3196 qemu_get_8s(f, &s->dac_write_index);
3197 qemu_get_buffer(f, s->dac_cache, 3);
3198 qemu_get_buffer(f, s->palette, 768);
3199
3200 s->bank_offset=qemu_get_be32(f);
3201
3202 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3203 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3204
3205 qemu_get_be32s(f, &s->hw_cursor_x);
3206 qemu_get_be32s(f, &s->hw_cursor_y);
3207
3208 #ifdef USE_KVM
3209 if (kvm_allowed) {
3210 int real_vram_size;
3211 qemu_get_be32s(f, &real_vram_size);
3212 if (real_vram_size != s->real_vram_size) {
3213 if (real_vram_size > s->real_vram_size)
3214 real_vram_size = s->real_vram_size;
3215 printf("%s: REAL_VRAM_SIZE MISMATCH !!!!!! SAVED=%d CURRENT=%d",
3216 __FUNCTION__, real_vram_size, s->real_vram_size);
3217 }
3218 qemu_get_buffer(f, s->vram_ptr, real_vram_size);
3219 cirrus_update_memory_access(s);
3220 }
3221 #endif
3222
3223
3224 /* force refresh */
3225 s->graphic_mode = -1;
3226 cirrus_update_bank_ptr(s, 0);
3227 cirrus_update_bank_ptr(s, 1);
3228 return 0;
3229 }
3230
3231 /***************************************
3232 *
3233 * initialize
3234 *
3235 ***************************************/
3236
3237 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3238 {
3239 int vga_io_memory, i;
3240 static int inited;
3241
3242 if (!inited) {
3243 inited = 1;
3244 for(i = 0;i < 256; i++)
3245 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3246 rop_to_index[CIRRUS_ROP_0] = 0;
3247 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3248 rop_to_index[CIRRUS_ROP_NOP] = 2;
3249 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3250 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3251 rop_to_index[CIRRUS_ROP_SRC] = 5;
3252 rop_to_index[CIRRUS_ROP_1] = 6;
3253 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3254 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3255 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3256 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3257 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3258 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3259 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3260 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3261 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3262 }
3263
3264 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3265
3266 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3267 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3268 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3269 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3270
3271 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3272
3273 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3274 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3275 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3276 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3277
3278 vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3279 cirrus_vga_mem_write, s);
3280 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3281 vga_io_memory);
3282
3283 s->sr[0x06] = 0x0f;
3284 if (device_id == CIRRUS_ID_CLGD5446) {
3285 /* 4MB 64 bit memory config, always PCI */
3286 s->sr[0x1F] = 0x2d; // MemClock
3287 s->gr[0x18] = 0x0f; // fastest memory configuration
3288 #if 1
3289 s->sr[0x0f] = 0x98;
3290 s->sr[0x17] = 0x20;
3291 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3292 s->real_vram_size = 4096 * 1024;
3293 #else
3294 s->sr[0x0f] = 0x18;
3295 s->sr[0x17] = 0x20;
3296 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3297 s->real_vram_size = 2048 * 1024;
3298 #endif
3299 } else {
3300 s->sr[0x1F] = 0x22; // MemClock
3301 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3302 if (is_pci)
3303 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3304 else
3305 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3306 s->real_vram_size = 2048 * 1024;
3307 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3308 }
3309 s->cr[0x27] = device_id;
3310
3311 /* Win2K seems to assume that the pattern buffer is at 0xff
3312 initially ! */
3313 memset(s->vram_ptr, 0xff, s->real_vram_size);
3314
3315 s->cirrus_hidden_dac_lockindex = 5;
3316 s->cirrus_hidden_dac_data = 0;
3317
3318 /* I/O handler for LFB */
3319 s->cirrus_linear_io_addr =
3320 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3321 s);
3322 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3323
3324 /* I/O handler for LFB */
3325 s->cirrus_linear_bitblt_io_addr =
3326 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3327 s);
3328
3329 /* I/O handler for memory-mapped I/O */
3330 s->cirrus_mmio_io_addr =
3331 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3332
3333 /* XXX: s->vram_size must be a power of two */
3334 s->cirrus_addr_mask = s->real_vram_size - 1;
3335 s->linear_mmio_mask = s->real_vram_size - 256;
3336
3337 s->get_bpp = cirrus_get_bpp;
3338 s->get_offsets = cirrus_get_offsets;
3339 s->get_resolution = cirrus_get_resolution;
3340 s->cursor_invalidate = cirrus_cursor_invalidate;
3341 s->cursor_draw_line = cirrus_cursor_draw_line;
3342
3343 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3344 }
3345
3346 /***************************************
3347 *
3348 * ISA bus support
3349 *
3350 ***************************************/
3351
3352 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3353 unsigned long vga_ram_offset, int vga_ram_size)
3354 {
3355 CirrusVGAState *s;
3356
3357 s = qemu_mallocz(sizeof(CirrusVGAState));
3358
3359 vga_common_init((VGAState *)s,
3360 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3361 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3362 /* XXX ISA-LFB support */
3363 }
3364
3365 /***************************************
3366 *
3367 * PCI bus support
3368 *
3369 ***************************************/
3370
3371 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3372 uint32_t addr, uint32_t size, int type)
3373 {
3374 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3375
3376 /* XXX: add byte swapping apertures */
3377 cpu_register_physical_memory(addr, s->vram_size,
3378 s->cirrus_linear_io_addr);
3379 #ifdef USE_KVM
3380 if (kvm_allowed) {
3381 s->cirrus_lfb_addr = addr;
3382 s->cirrus_lfb_end = addr + VGA_RAM_SIZE;
3383
3384 if (s->map_addr && (s->cirrus_lfb_addr != s->map_addr) &&
3385 (s->cirrus_lfb_end != s->map_end))
3386 printf("cirrus vga map change while on lfb mode\n");
3387 }
3388 #endif
3389
3390 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3391 s->cirrus_linear_bitblt_io_addr);
3392 }
3393
3394 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3395 uint32_t addr, uint32_t size, int type)
3396 {
3397 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3398
3399 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3400 s->cirrus_mmio_io_addr);
3401 }
3402
3403 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3404 unsigned long vga_ram_offset, int vga_ram_size)
3405 {
3406 PCICirrusVGAState *d;
3407 uint8_t *pci_conf;
3408 CirrusVGAState *s;
3409 int device_id;
3410
3411 device_id = CIRRUS_ID_CLGD5446;
3412
3413 /* setup PCI configuration registers */
3414 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3415 sizeof(PCICirrusVGAState),
3416 -1, NULL, NULL);
3417 pci_conf = d->dev.config;
3418 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3419 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3420 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3421 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3422 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3423 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3424 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3425 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3426
3427 /* setup VGA */
3428 s = &d->cirrus_vga;
3429 vga_common_init((VGAState *)s,
3430 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3431 cirrus_init_common(s, device_id, 1);
3432
3433 graphic_console_init(s->ds, s->update, s->invalidate, s->screen_dump, s);
3434
3435 s->pci_dev = (PCIDevice *)d;
3436
3437 /* setup memory space */
3438 /* memory #0 LFB */
3439 /* memory #1 memory-mapped I/O */
3440 /* XXX: s->vram_size must be a power of two */
3441 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3442 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3443 if (device_id == CIRRUS_ID_CLGD5446) {
3444 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3445 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3446 }
3447 /* XXX: ROM BIOS */
3448 }
Patches shipped by Fedora