3 /* PC-style peripherals (also used by other machines). */
7 SerialState
*serial_init(int base
, qemu_irq irq
, int baudbase
,
9 SerialState
*serial_mm_init (target_phys_addr_t base
, int it_shift
,
10 qemu_irq irq
, int baudbase
,
11 CharDriverState
*chr
, int ioregister
);
12 uint32_t serial_mm_readb (void *opaque
, target_phys_addr_t addr
);
13 void serial_mm_writeb (void *opaque
, target_phys_addr_t addr
, uint32_t value
);
14 uint32_t serial_mm_readw (void *opaque
, target_phys_addr_t addr
);
15 void serial_mm_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
);
16 uint32_t serial_mm_readl (void *opaque
, target_phys_addr_t addr
);
17 void serial_mm_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
);
21 typedef struct ParallelState ParallelState
;
22 ParallelState
*parallel_init(int base
, qemu_irq irq
, CharDriverState
*chr
);
23 ParallelState
*parallel_mm_init(target_phys_addr_t base
, int it_shift
, qemu_irq irq
, CharDriverState
*chr
);
27 typedef struct PicState2 PicState2
;
28 extern PicState2
*isa_pic
;
29 void pic_set_irq(int irq
, int level
);
30 void pic_set_irq_new(void *opaque
, int irq
, int level
);
31 qemu_irq
*i8259_init(qemu_irq parent_irq
);
32 void pic_set_alt_irq_func(PicState2
*s
, SetIRQFunc
*alt_irq_func
,
33 void *alt_irq_opaque
);
34 int pic_read_irq(PicState2
*s
);
35 void pic_update_irq(PicState2
*s
);
36 uint32_t pic_intack_read(PicState2
*s
);
41 typedef struct IOAPICState IOAPICState
;
43 int apic_init(CPUState
*env
);
44 int apic_accept_pic_intr(CPUState
*env
);
45 void apic_deliver_pic_intr(CPUState
*env
, int level
);
46 int apic_get_interrupt(CPUState
*env
);
47 IOAPICState
*ioapic_init(void);
48 void ioapic_set_irq(void *opaque
, int vector
, int level
);
49 void apic_reset_irq_delivered(void);
50 int apic_get_irq_delivered(void);
54 #define PIT_FREQ 1193182
56 typedef struct PITState PITState
;
58 PITState
*pit_init(int base
, qemu_irq irq
);
59 void pit_set_gate(PITState
*pit
, int channel
, int val
);
60 int pit_get_gate(PITState
*pit
, int channel
);
61 int pit_get_initial_count(PITState
*pit
, int channel
);
62 int pit_get_mode(PITState
*pit
, int channel
);
63 int pit_get_out(PITState
*pit
, int channel
, int64_t current_time
);
67 PITState
*kvm_pit_init(int base
, qemu_irq irq
);
69 void hpet_pit_disable(void);
70 void hpet_pit_enable(void);
73 void vmport_init(void);
74 void vmport_register(unsigned char command
, IOPortReadFunc
*func
, void *opaque
);
77 void *vmmouse_init(void *m
);
81 void i8042_init(qemu_irq kbd_irq
, qemu_irq mouse_irq
, uint32_t io_base
);
82 void i8042_mm_init(qemu_irq kbd_irq
, qemu_irq mouse_irq
,
83 target_phys_addr_t base
, ram_addr_t size
,
84 target_phys_addr_t mask
);
88 typedef struct RTCState RTCState
;
90 RTCState
*rtc_init(int base
, qemu_irq irq
, int base_year
);
91 RTCState
*rtc_mm_init(target_phys_addr_t base
, int it_shift
, qemu_irq irq
,
93 void rtc_set_memory(RTCState
*s
, int addr
, int val
);
94 void rtc_set_date(RTCState
*s
, const struct tm
*tm
);
95 void cmos_set_s3_resume(void);
98 extern int fd_bootchk
;
100 void ioport_set_a20(int enable
);
101 int ioport_get_a20(void);
102 CPUState
*pc_new_cpu(int cpu
, const char *cpu_model
, int pci_enabled
);
105 extern int acpi_enabled
;
106 i2c_bus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
108 void piix4_smbus_register_device(SMBusDevice
*dev
, uint8_t addr
);
109 void acpi_bios_init(void);
115 void pcspk_init(PITState
*);
116 int pcspk_audio_init(AudioState
*, qemu_irq
*pic
);
119 /* config space register for IRQ routing */
120 #define PIIX_CONFIG_IRQ_ROUTE 0x60
122 PCIBus
*i440fx_init(PCIDevice
**pi440fx_state
, qemu_irq
*pic
);
123 void i440fx_set_smm(PCIDevice
*d
, int val
);
124 int piix3_init(PCIBus
*bus
, int devfn
);
125 void i440fx_init_memory_mappings(PCIDevice
*d
);
127 extern PCIDevice
*piix4_dev
;
128 int piix4_init(PCIBus
*bus
, int devfn
);
130 int piix_get_irq(int pin
);
132 int ipf_map_irq(PCIDevice
*pci_dev
, int irq_num
);
135 enum vga_retrace_method
{
140 extern enum vga_retrace_method vga_retrace_method
;
143 #define VGA_RAM_SIZE (16 * 1024 * 1024)
145 #define VGA_RAM_SIZE (17 * 1024 * 1024)
148 int isa_vga_init(uint8_t *vga_ram_base
,
149 unsigned long vga_ram_offset
, int vga_ram_size
);
150 int pci_vga_init(PCIBus
*bus
, uint8_t *vga_ram_base
,
151 unsigned long vga_ram_offset
, int vga_ram_size
,
152 unsigned long vga_bios_offset
, int vga_bios_size
);
153 int isa_vga_mm_init(uint8_t *vga_ram_base
,
154 unsigned long vga_ram_offset
, int vga_ram_size
,
155 target_phys_addr_t vram_base
, target_phys_addr_t ctrl_base
,
159 void pci_cirrus_vga_init(PCIBus
*bus
, uint8_t *vga_ram_base
,
160 ram_addr_t vga_ram_offset
, int vga_ram_size
);
161 void isa_cirrus_vga_init(uint8_t *vga_ram_base
,
162 ram_addr_t vga_ram_offset
, int vga_ram_size
);
165 void isa_ide_init(int iobase
, int iobase2
, qemu_irq irq
,
166 BlockDriverState
*hd0
, BlockDriverState
*hd1
);
167 void pci_cmd646_ide_init(PCIBus
*bus
, BlockDriverState
**hd_table
,
168 int secondary_ide_enabled
);
169 void pci_piix3_ide_init(PCIBus
*bus
, BlockDriverState
**hd_table
, int devfn
,
171 void pci_piix4_ide_init(PCIBus
*bus
, BlockDriverState
**hd_table
, int devfn
,
176 void isa_ne2000_init(int base
, qemu_irq irq
, NICInfo
*nd
);
180 void extboot_init(BlockDriverState
*bs
, int cmd
);