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Merge branch 'qemu-cvs'
[qemu-kvm/fedora.git] / hw / e1000.c
blobfe155d428c8b6509895f0cf94f3e99fb824f3b53
1 /*
2 * QEMU e1000 emulation
3 *
4 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
5 * Copyright (c) 2008 Qumranet
6 * Based on work done by:
7 * Copyright (c) 2007 Dan Aloni
8 * Copyright (c) 2004 Antony T Curtis
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
23 */
24
25
26 #include "hw.h"
27 #include "pci.h"
28 #include "net.h"
29 #include "qemu-kvm.h"
30
31 #include "e1000_hw.h"
32
33 #define DEBUG
34
35 #ifdef DEBUG
36 enum {
37 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
38 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
39 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
40 DEBUG_RXFILTER, DEBUG_NOTYET,
41 };
42 #define DBGBIT(x) (1<<DEBUG_##x)
43 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
44
45 #define DBGOUT(what, fmt, params...) do { \
46 if (debugflags & DBGBIT(what)) \
47 fprintf(stderr, "e1000: " fmt, ##params); \
48 } while (0)
49 #else
50 #define DBGOUT(what, fmt, params...) do {} while (0)
51 #endif
52
53 #define IOPORT_SIZE 0x40
54 #define PNPMMIO_SIZE 0x20000
55
56 /*
57 * HW models:
58 * E1000_DEV_ID_82540EM works with Windows and Linux
59 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
60 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
61 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
62 * Others never tested
63 */
64 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
65
66 /*
67 * May need to specify additional MAC-to-PHY entries --
68 * Intel's Windows driver refuses to initialize unless they match
69 */
70 enum {
71 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
72 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
73 /* default to E1000_DEV_ID_82540EM */ 0xc20
74 };
75
76 typedef struct E1000State_st {
77 PCIDevice dev;
78 VLANClientState *vc;
79 NICInfo *nd;
80 int mmio_index;
81
82 uint32_t mac_reg[0x8000];
83 uint16_t phy_reg[0x20];
84 uint16_t eeprom_data[64];
85
86 uint32_t rxbuf_size;
87 uint32_t rxbuf_min_shift;
88 int check_rxov;
89 struct e1000_tx {
90 unsigned char header[256];
91 unsigned char vlan_header[4];
92 unsigned char vlan[4];
93 unsigned char data[0x10000];
94 uint16_t size;
95 unsigned char sum_needed;
96 unsigned char vlan_needed;
97 uint8_t ipcss;
98 uint8_t ipcso;
99 uint16_t ipcse;
100 uint8_t tucss;
101 uint8_t tucso;
102 uint16_t tucse;
103 uint8_t hdr_len;
104 uint16_t mss;
105 uint32_t paylen;
106 uint16_t tso_frames;
107 char tse;
108 int8_t ip;
109 int8_t tcp;
110 char cptse; // current packet tse bit
111 } tx;
112
113 struct {
114 uint32_t val_in; // shifted in from guest driver
115 uint16_t bitnum_in;
116 uint16_t bitnum_out;
117 uint16_t reading;
118 uint32_t old_eecd;
119 } eecd_state;
120 } E1000State;
121
122 #define defreg(x) x = (E1000_##x>>2)
123 enum {
124 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
125 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
126 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
127 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
128 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
129 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
130 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
131 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
132 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
133 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
134 defreg(VET),
135 };
136
137 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
138 static const char phy_regcap[0x20] = {
139 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
140 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
141 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
142 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
143 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
144 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
145 };
146
147 static void
148 ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr,
149 uint32_t size, int type)
150 {
151 DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
152 }
153
154 static void
155 set_interrupt_cause(E1000State *s, int index, uint32_t val)
156 {
157 if (val)
158 val |= E1000_ICR_INT_ASSERTED;
159 s->mac_reg[ICR] = val;
160 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
161 }
162
163 static void
164 set_ics(E1000State *s, int index, uint32_t val)
165 {
166 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
167 s->mac_reg[IMS]);
168 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
169 }
170
171 static int
172 rxbufsize(uint32_t v)
173 {
174 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
175 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
176 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
177 switch (v) {
178 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
179 return 16384;
180 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
181 return 8192;
182 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
183 return 4096;
184 case E1000_RCTL_SZ_1024:
185 return 1024;
186 case E1000_RCTL_SZ_512:
187 return 512;
188 case E1000_RCTL_SZ_256:
189 return 256;
190 }
191 return 2048;
192 }
193
194 static void
195 set_rx_control(E1000State *s, int index, uint32_t val)
196 {
197 s->mac_reg[RCTL] = val;
198 s->rxbuf_size = rxbufsize(val);
199 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
200 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
201 s->mac_reg[RCTL]);
202 }
203
204 static void
205 set_mdic(E1000State *s, int index, uint32_t val)
206 {
207 uint32_t data = val & E1000_MDIC_DATA_MASK;
208 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
209
210 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
211 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
212 else if (val & E1000_MDIC_OP_READ) {
213 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
214 if (!(phy_regcap[addr] & PHY_R)) {
215 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
216 val |= E1000_MDIC_ERROR;
217 } else
218 val = (val ^ data) | s->phy_reg[addr];
219 } else if (val & E1000_MDIC_OP_WRITE) {
220 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
221 if (!(phy_regcap[addr] & PHY_W)) {
222 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
223 val |= E1000_MDIC_ERROR;
224 } else
225 s->phy_reg[addr] = data;
226 }
227 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
228 set_ics(s, 0, E1000_ICR_MDAC);
229 }
230
231 static uint32_t
232 get_eecd(E1000State *s, int index)
233 {
234 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
235
236 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
237 s->eecd_state.bitnum_out, s->eecd_state.reading);
238 if (!s->eecd_state.reading ||
239 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
240 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
241 ret |= E1000_EECD_DO;
242 return ret;
243 }
244
245 static void
246 set_eecd(E1000State *s, int index, uint32_t val)
247 {
248 uint32_t oldval = s->eecd_state.old_eecd;
249
250 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
251 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
252 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
253 return;
254 if (!(E1000_EECD_SK & val)) { // falling edge
255 s->eecd_state.bitnum_out++;
256 return;
257 }
258 if (!(val & E1000_EECD_CS)) { // rising, no CS (EEPROM reset)
259 memset(&s->eecd_state, 0, sizeof s->eecd_state);
260 return;
261 }
262 s->eecd_state.val_in <<= 1;
263 if (val & E1000_EECD_DI)
264 s->eecd_state.val_in |= 1;
265 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
266 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
267 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
268 EEPROM_READ_OPCODE_MICROWIRE);
269 }
270 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
271 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
272 s->eecd_state.reading);
273 }
274
275 static uint32_t
276 flash_eerd_read(E1000State *s, int x)
277 {
278 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
279
280 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
281 return 0;
282 return (s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
283 E1000_EEPROM_RW_REG_DONE | r;
284 }
285
286 static void
287 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
288 {
289 uint32_t sum;
290
291 if (cse && cse < n)
292 n = cse + 1;
293 if (sloc < n-1) {
294 sum = net_checksum_add(n-css, data+css);
295 cpu_to_be16wu((uint16_t *)(data + sloc),
296 net_checksum_finish(sum));
297 }
298 }
299
300 static inline int
301 vlan_enabled(E1000State *s)
302 {
303 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
304 }
305
306 static inline int
307 vlan_rx_filter_enabled(E1000State *s)
308 {
309 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
310 }
311
312 static inline int
313 is_vlan_packet(E1000State *s, const uint8_t *buf)
314 {
315 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
316 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
317 }
318
319 static inline int
320 is_vlan_txd(uint32_t txd_lower)
321 {
322 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
323 }
324
325 static void
326 xmit_seg(E1000State *s)
327 {
328 uint16_t len, *sp;
329 unsigned int frames = s->tx.tso_frames, css, sofar, n;
330 struct e1000_tx *tp = &s->tx;
331
332 if (tp->tse && tp->cptse) {
333 css = tp->ipcss;
334 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
335 frames, tp->size, css);
336 if (tp->ip) { // IPv4
337 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
338 tp->size - css);
339 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
340 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
341 } else // IPv6
342 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
343 tp->size - css);
344 css = tp->tucss;
345 len = tp->size - css;
346 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
347 if (tp->tcp) {
348 sofar = frames * tp->mss;
349 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
350 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
351 if (tp->paylen - sofar > tp->mss)
352 tp->data[css + 13] &= ~9; // PSH, FIN
353 } else // UDP
354 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
355 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
356 // add pseudo-header length before checksum calculation
357 sp = (uint16_t *)(tp->data + tp->tucso);
358 cpu_to_be16wu(sp, be16_to_cpup(sp) + len);
359 }
360 tp->tso_frames++;
361 }
362
363 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
364 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
365 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
366 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
367 if (tp->vlan_needed) {
368 memmove(tp->vlan, tp->data, 12);
369 memcpy(tp->data + 8, tp->vlan_header, 4);
370 qemu_send_packet(s->vc, tp->vlan, tp->size + 4);
371 } else
372 qemu_send_packet(s->vc, tp->data, tp->size);
373 s->mac_reg[TPT]++;
374 s->mac_reg[GPTC]++;
375 n = s->mac_reg[TOTL];
376 if ((s->mac_reg[TOTL] += s->tx.size) < n)
377 s->mac_reg[TOTH]++;
378 }
379
380 static void
381 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
382 {
383 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
384 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
385 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
386 unsigned int msh = 0xfffff, hdr = 0;
387 uint64_t addr;
388 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
389 struct e1000_tx *tp = &s->tx;
390
391 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
392 op = le32_to_cpu(xp->cmd_and_length);
393 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
394 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
395 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
396 tp->tucss = xp->upper_setup.tcp_fields.tucss;
397 tp->tucso = xp->upper_setup.tcp_fields.tucso;
398 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
399 tp->paylen = op & 0xfffff;
400 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
401 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
402 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
403 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
404 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
405 tp->tso_frames = 0;
406 if (tp->tucso == 0) { // this is probably wrong
407 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
408 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
409 }
410 return;
411 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
412 // data descriptor
413 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
414 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
415 } else
416 // legacy descriptor
417 tp->cptse = 0;
418
419 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
420 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
421 tp->vlan_needed = 1;
422 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
423 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
424 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
425 le16_to_cpu(dp->upper.fields.special));
426 }
427
428 addr = le64_to_cpu(dp->buffer_addr);
429 if (tp->tse && tp->cptse) {
430 hdr = tp->hdr_len;
431 msh = hdr + tp->mss;
432 do {
433 bytes = split_size;
434 if (tp->size + bytes > msh)
435 bytes = msh - tp->size;
436 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
437 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
438 memmove(tp->header, tp->data, hdr);
439 tp->size = sz;
440 addr += bytes;
441 if (sz == msh) {
442 xmit_seg(s);
443 memmove(tp->data, tp->header, hdr);
444 tp->size = hdr;
445 }
446 } while (split_size -= bytes);
447 } else if (!tp->tse && tp->cptse) {
448 // context descriptor TSE is not set, while data descriptor TSE is set
449 DBGOUT(TXERR, "TCP segmentaion Error\n");
450 } else {
451 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
452 tp->size += split_size;
453 }
454
455 if (!(txd_lower & E1000_TXD_CMD_EOP))
456 return;
457 if (!(tp->tse && tp->cptse && tp->size < hdr))
458 xmit_seg(s);
459 tp->tso_frames = 0;
460 tp->sum_needed = 0;
461 tp->vlan_needed = 0;
462 tp->size = 0;
463 tp->cptse = 0;
464 }
465
466 static uint32_t
467 txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
468 {
469 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
470
471 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
472 return 0;
473 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
474 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
475 dp->upper.data = cpu_to_le32(txd_upper);
476 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
477 (void *)&dp->upper, sizeof(dp->upper));
478 return E1000_ICR_TXDW;
479 }
480
481 static void
482 start_xmit(E1000State *s)
483 {
484 target_phys_addr_t base;
485 struct e1000_tx_desc desc;
486 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
487
488 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
489 DBGOUT(TX, "tx disabled\n");
490 return;
491 }
492
493 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
494 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
495 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
496 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
497
498 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
499 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
500 desc.upper.data);
501
502 process_tx_desc(s, &desc);
503 cause |= txdesc_writeback(base, &desc);
504
505 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
506 s->mac_reg[TDH] = 0;
507 /*
508 * the following could happen only if guest sw assigns
509 * bogus values to TDT/TDLEN.
510 * there's nothing too intelligent we could do about this.
511 */
512 if (s->mac_reg[TDH] == tdh_start) {
513 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
514 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
515 break;
516 }
517 }
518 set_ics(s, 0, cause);
519 }
520
521 static int
522 receive_filter(E1000State *s, const uint8_t *buf, int size)
523 {
524 static uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
525 static int mta_shift[] = {4, 3, 2, 0};
526 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
527
528 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
529 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
530 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
531 ((vid >> 5) & 0x7f));
532 if ((vfta & (1 << (vid & 0x1f))) == 0)
533 return 0;
534 }
535
536 if (rctl & E1000_RCTL_UPE) // promiscuous
537 return 1;
538
539 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
540 return 1;
541
542 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
543 return 1;
544
545 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
546 if (!(rp[1] & E1000_RAH_AV))
547 continue;
548 ra[0] = cpu_to_le32(rp[0]);
549 ra[1] = cpu_to_le32(rp[1]);
550 if (!memcmp(buf, (uint8_t *)ra, 6)) {
551 DBGOUT(RXFILTER,
552 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
553 (int)(rp - s->mac_reg - RA)/2,
554 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
555 return 1;
556 }
557 }
558 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
559 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
560
561 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
562 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
563 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
564 return 1;
565 DBGOUT(RXFILTER,
566 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
567 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
568 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
569 s->mac_reg[MTA + (f >> 5)]);
570
571 return 0;
572 }
573
574 static void
575 e1000_set_link_status(VLANClientState *vc)
576 {
577 E1000State *s = vc->opaque;
578 uint32_t old_status = s->mac_reg[STATUS];
579
580 if (vc->link_down)
581 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
582 else
583 s->mac_reg[STATUS] |= E1000_STATUS_LU;
584
585 if (s->mac_reg[STATUS] != old_status)
586 set_ics(s, 0, E1000_ICR_LSC);
587 }
588
589 static int
590 e1000_can_receive(void *opaque)
591 {
592 E1000State *s = opaque;
593
594 return (s->mac_reg[RCTL] & E1000_RCTL_EN);
595 }
596
597 static void
598 e1000_receive(void *opaque, const uint8_t *buf, int size)
599 {
600 E1000State *s = opaque;
601 struct e1000_rx_desc desc;
602 target_phys_addr_t base;
603 unsigned int n, rdt;
604 uint32_t rdh_start;
605 uint16_t vlan_special = 0;
606 uint8_t vlan_status = 0, vlan_offset = 0;
607
608 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
609 return;
610
611 if (size > s->rxbuf_size) {
612 DBGOUT(RX, "packet too large for buffers (%d > %d)\n", size,
613 s->rxbuf_size);
614 return;
615 }
616
617 if (!receive_filter(s, buf, size))
618 return;
619
620 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
621 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
622 memmove((void *)(buf + 4), buf, 12);
623 vlan_status = E1000_RXD_STAT_VP;
624 vlan_offset = 4;
625 size -= 4;
626 }
627
628 rdh_start = s->mac_reg[RDH];
629 size += 4; // for the header
630 do {
631 if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) {
632 set_ics(s, 0, E1000_ICS_RXO);
633 return;
634 }
635 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
636 sizeof(desc) * s->mac_reg[RDH];
637 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
638 desc.special = vlan_special;
639 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
640 if (desc.buffer_addr) {
641 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
642 (void *)(buf + vlan_offset), size);
643 desc.length = cpu_to_le16(size);
644 desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM;
645 } else // as per intel docs; skip descriptors with null buf addr
646 DBGOUT(RX, "Null RX descriptor!!\n");
647 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
648
649 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
650 s->mac_reg[RDH] = 0;
651 s->check_rxov = 1;
652 /* see comment in start_xmit; same here */
653 if (s->mac_reg[RDH] == rdh_start) {
654 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
655 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
656 set_ics(s, 0, E1000_ICS_RXO);
657 return;
658 }
659 } while (desc.buffer_addr == 0);
660
661 s->mac_reg[GPRC]++;
662 s->mac_reg[TPR]++;
663 n = s->mac_reg[TORL];
664 if ((s->mac_reg[TORL] += size) < n)
665 s->mac_reg[TORH]++;
666
667 n = E1000_ICS_RXT0;
668 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
669 rdt += s->mac_reg[RDLEN] / sizeof(desc);
670 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) << s->rxbuf_min_shift >=
671 s->mac_reg[RDLEN])
672 n |= E1000_ICS_RXDMT0;
673
674 set_ics(s, 0, n);
675 }
676
677 static uint32_t
678 mac_readreg(E1000State *s, int index)
679 {
680 return s->mac_reg[index];
681 }
682
683 static uint32_t
684 mac_icr_read(E1000State *s, int index)
685 {
686 uint32_t ret = s->mac_reg[ICR];
687
688 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
689 set_interrupt_cause(s, 0, 0);
690 return ret;
691 }
692
693 static uint32_t
694 mac_read_clr4(E1000State *s, int index)
695 {
696 uint32_t ret = s->mac_reg[index];
697
698 s->mac_reg[index] = 0;
699 return ret;
700 }
701
702 static uint32_t
703 mac_read_clr8(E1000State *s, int index)
704 {
705 uint32_t ret = s->mac_reg[index];
706
707 s->mac_reg[index] = 0;
708 s->mac_reg[index-1] = 0;
709 return ret;
710 }
711
712 static void
713 mac_writereg(E1000State *s, int index, uint32_t val)
714 {
715 s->mac_reg[index] = val;
716 }
717
718 static void
719 set_rdt(E1000State *s, int index, uint32_t val)
720 {
721 s->check_rxov = 0;
722 s->mac_reg[index] = val & 0xffff;
723 }
724
725 static void
726 set_16bit(E1000State *s, int index, uint32_t val)
727 {
728 s->mac_reg[index] = val & 0xffff;
729 }
730
731 static void
732 set_dlen(E1000State *s, int index, uint32_t val)
733 {
734 s->mac_reg[index] = val & 0xfff80;
735 }
736
737 static void
738 set_tctl(E1000State *s, int index, uint32_t val)
739 {
740 s->mac_reg[index] = val;
741 s->mac_reg[TDT] &= 0xffff;
742 start_xmit(s);
743 }
744
745 static void
746 set_icr(E1000State *s, int index, uint32_t val)
747 {
748 DBGOUT(INTERRUPT, "set_icr %x\n", val);
749 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
750 }
751
752 static void
753 set_imc(E1000State *s, int index, uint32_t val)
754 {
755 s->mac_reg[IMS] &= ~val;
756 set_ics(s, 0, 0);
757 }
758
759 static void
760 set_ims(E1000State *s, int index, uint32_t val)
761 {
762 s->mac_reg[IMS] |= val;
763 set_ics(s, 0, 0);
764 }
765
766 #define getreg(x) [x] = mac_readreg
767 static uint32_t (*macreg_readops[])(E1000State *, int) = {
768 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
769 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
770 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
771 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
772 getreg(RDH), getreg(RDT), getreg(VET),
773
774 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
775 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
776 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
777 [CRCERRS ... MPC] = &mac_readreg,
778 [RA ... RA+31] = &mac_readreg,
779 [MTA ... MTA+127] = &mac_readreg,
780 [VFTA ... VFTA+127] = &mac_readreg,
781 };
782 enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
783
784 #define putreg(x) [x] = mac_writereg
785 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
786 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
787 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
788 putreg(RDBAL), putreg(LEDCTL), putreg(CTRL), putreg(VET),
789 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
790 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
791 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
792 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
793 [EECD] = set_eecd, [RCTL] = set_rx_control,
794 [RA ... RA+31] = &mac_writereg,
795 [MTA ... MTA+127] = &mac_writereg,
796 [VFTA ... VFTA+127] = &mac_writereg,
797 };
798 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
799
800 static void
801 e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
802 {
803 E1000State *s = opaque;
804 unsigned int index = (addr & 0x1ffff) >> 2;
805
806 #ifdef TARGET_WORDS_BIGENDIAN
807 val = bswap32(val);
808 #endif
809 if (index < NWRITEOPS && macreg_writeops[index])
810 macreg_writeops[index](s, index, val);
811 else if (index < NREADOPS && macreg_readops[index])
812 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
813 else
814 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
815 index<<2, val);
816 }
817
818 static void
819 e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
820 {
821 // emulate hw without byte enables: no RMW
822 e1000_mmio_writel(opaque, addr & ~3,
823 (val & 0xffff) << (8*(addr & 3)));
824 }
825
826 static void
827 e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
828 {
829 // emulate hw without byte enables: no RMW
830 e1000_mmio_writel(opaque, addr & ~3,
831 (val & 0xff) << (8*(addr & 3)));
832 }
833
834 static uint32_t
835 e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
836 {
837 E1000State *s = opaque;
838 unsigned int index = (addr & 0x1ffff) >> 2;
839
840 if (index < NREADOPS && macreg_readops[index])
841 {
842 uint32_t val = macreg_readops[index](s, index);
843 #ifdef TARGET_WORDS_BIGENDIAN
844 val = bswap32(val);
845 #endif
846 return val;
847 }
848 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
849 return 0;
850 }
851
852 static uint32_t
853 e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
854 {
855 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
856 (8 * (addr & 3))) & 0xff;
857 }
858
859 static uint32_t
860 e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
861 {
862 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
863 (8 * (addr & 3))) & 0xffff;
864 }
865
866 static const int mac_regtosave[] = {
867 CTRL, EECD, EERD, GPRC, GPTC, ICR, ICS, IMC, IMS,
868 LEDCTL, MANC, MDIC, MPC, PBA, RCTL, RDBAH, RDBAL, RDH,
869 RDLEN, RDT, STATUS, SWSM, TCTL, TDBAH, TDBAL, TDH, TDLEN,
870 TDT, TORH, TORL, TOTH, TOTL, TPR, TPT, TXDCTL, WUFC,
871 VET,
872 };
873 enum { MAC_NSAVE = ARRAY_SIZE(mac_regtosave) };
874
875 static const struct {
876 int size;
877 int array0;
878 } mac_regarraystosave[] = { {32, RA}, {128, MTA}, {128, VFTA} };
879 enum { MAC_NARRAYS = ARRAY_SIZE(mac_regarraystosave) };
880
881 static void
882 nic_save(QEMUFile *f, void *opaque)
883 {
884 E1000State *s = (E1000State *)opaque;
885 int i, j;
886
887 pci_device_save(&s->dev, f);
888 qemu_put_be32(f, 0);
889 qemu_put_be32s(f, &s->rxbuf_size);
890 qemu_put_be32s(f, &s->rxbuf_min_shift);
891 qemu_put_be32s(f, &s->eecd_state.val_in);
892 qemu_put_be16s(f, &s->eecd_state.bitnum_in);
893 qemu_put_be16s(f, &s->eecd_state.bitnum_out);
894 qemu_put_be16s(f, &s->eecd_state.reading);
895 qemu_put_be32s(f, &s->eecd_state.old_eecd);
896 qemu_put_8s(f, &s->tx.ipcss);
897 qemu_put_8s(f, &s->tx.ipcso);
898 qemu_put_be16s(f, &s->tx.ipcse);
899 qemu_put_8s(f, &s->tx.tucss);
900 qemu_put_8s(f, &s->tx.tucso);
901 qemu_put_be16s(f, &s->tx.tucse);
902 qemu_put_be32s(f, &s->tx.paylen);
903 qemu_put_8s(f, &s->tx.hdr_len);
904 qemu_put_be16s(f, &s->tx.mss);
905 qemu_put_be16s(f, &s->tx.size);
906 qemu_put_be16s(f, &s->tx.tso_frames);
907 qemu_put_8s(f, &s->tx.sum_needed);
908 qemu_put_s8s(f, &s->tx.ip);
909 qemu_put_s8s(f, &s->tx.tcp);
910 qemu_put_buffer(f, s->tx.header, sizeof s->tx.header);
911 qemu_put_buffer(f, s->tx.data, sizeof s->tx.data);
912 for (i = 0; i < 64; i++)
913 qemu_put_be16s(f, s->eeprom_data + i);
914 for (i = 0; i < 0x20; i++)
915 qemu_put_be16s(f, s->phy_reg + i);
916 for (i = 0; i < MAC_NSAVE; i++)
917 qemu_put_be32s(f, s->mac_reg + mac_regtosave[i]);
918 for (i = 0; i < MAC_NARRAYS; i++)
919 for (j = 0; j < mac_regarraystosave[i].size; j++)
920 qemu_put_be32s(f,
921 s->mac_reg + mac_regarraystosave[i].array0 + j);
922 }
923
924 static int
925 nic_load(QEMUFile *f, void *opaque, int version_id)
926 {
927 E1000State *s = (E1000State *)opaque;
928 int i, j, ret;
929
930 if ((ret = pci_device_load(&s->dev, f)) < 0)
931 return ret;
932 if (version_id == 1)
933 qemu_get_sbe32s(f, &i); /* once some unused instance id */
934 qemu_get_be32(f); /* Ignored. Was mmio_base. */
935 qemu_get_be32s(f, &s->rxbuf_size);
936 qemu_get_be32s(f, &s->rxbuf_min_shift);
937 qemu_get_be32s(f, &s->eecd_state.val_in);
938 qemu_get_be16s(f, &s->eecd_state.bitnum_in);
939 qemu_get_be16s(f, &s->eecd_state.bitnum_out);
940 qemu_get_be16s(f, &s->eecd_state.reading);
941 qemu_get_be32s(f, &s->eecd_state.old_eecd);
942 qemu_get_8s(f, &s->tx.ipcss);
943 qemu_get_8s(f, &s->tx.ipcso);
944 qemu_get_be16s(f, &s->tx.ipcse);
945 qemu_get_8s(f, &s->tx.tucss);
946 qemu_get_8s(f, &s->tx.tucso);
947 qemu_get_be16s(f, &s->tx.tucse);
948 qemu_get_be32s(f, &s->tx.paylen);
949 qemu_get_8s(f, &s->tx.hdr_len);
950 qemu_get_be16s(f, &s->tx.mss);
951 qemu_get_be16s(f, &s->tx.size);
952 qemu_get_be16s(f, &s->tx.tso_frames);
953 qemu_get_8s(f, &s->tx.sum_needed);
954 qemu_get_s8s(f, &s->tx.ip);
955 qemu_get_s8s(f, &s->tx.tcp);
956 qemu_get_buffer(f, s->tx.header, sizeof s->tx.header);
957 qemu_get_buffer(f, s->tx.data, sizeof s->tx.data);
958 for (i = 0; i < 64; i++)
959 qemu_get_be16s(f, s->eeprom_data + i);
960 for (i = 0; i < 0x20; i++)
961 qemu_get_be16s(f, s->phy_reg + i);
962 for (i = 0; i < MAC_NSAVE; i++)
963 qemu_get_be32s(f, s->mac_reg + mac_regtosave[i]);
964 for (i = 0; i < MAC_NARRAYS; i++)
965 for (j = 0; j < mac_regarraystosave[i].size; j++)
966 qemu_get_be32s(f,
967 s->mac_reg + mac_regarraystosave[i].array0 + j);
968 return 0;
969 }
970
971 static const uint16_t e1000_eeprom_template[64] = {
972 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
973 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
974 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
975 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
976 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
977 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
978 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
979 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
980 };
981
982 static const uint16_t phy_reg_init[] = {
983 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
984 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
985 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
986 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
987 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
988 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
989 };
990
991 static const uint32_t mac_reg_init[] = {
992 [PBA] = 0x00100030,
993 [LEDCTL] = 0x602,
994 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
995 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
996 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
997 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
998 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
999 E1000_STATUS_LU,
1000 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1001 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1002 E1000_MANC_RMCP_EN,
1003 };
1004
1005 /* PCI interface */
1006
1007 static CPUWriteMemoryFunc *e1000_mmio_write[] = {
1008 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
1009 };
1010
1011 static CPUReadMemoryFunc *e1000_mmio_read[] = {
1012 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
1013 };
1014
1015 static void
1016 e1000_mmio_map(PCIDevice *pci_dev, int region_num,
1017 uint32_t addr, uint32_t size, int type)
1018 {
1019 E1000State *d = (E1000State *)pci_dev;
1020 int i;
1021 const uint32_t excluded_regs[] = {
1022 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1023 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1024 };
1025
1026
1027 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
1028
1029 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
1030 qemu_register_coalesced_mmio(addr, excluded_regs[0]);
1031
1032 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1033 qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4,
1034 excluded_regs[i + 1] -
1035 excluded_regs[i] - 4);
1036 }
1037
1038 static int
1039 pci_e1000_uninit(PCIDevice *dev)
1040 {
1041 E1000State *d = (E1000State *) dev;
1042
1043 cpu_unregister_io_memory(d->mmio_index);
1044
1045 return 0;
1046 }
1047
1048 PCIDevice *
1049 pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn)
1050 {
1051 E1000State *d;
1052 uint8_t *pci_conf;
1053 uint16_t checksum = 0;
1054 static const char info_str[] = "e1000";
1055 int i;
1056
1057 d = (E1000State *)pci_register_device(bus, "e1000",
1058 sizeof(E1000State), devfn, NULL, NULL);
1059
1060 if (!d)
1061 return NULL;
1062
1063 pci_conf = d->dev.config;
1064 memset(pci_conf, 0, 256);
1065
1066 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1067 pci_config_set_device_id(pci_conf, E1000_DEVID);
1068 *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407);
1069 *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010);
1070 pci_conf[0x08] = 0x03;
1071 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
1072 pci_conf[0x0c] = 0x10;
1073
1074 pci_conf[0x3d] = 1; // interrupt pin 0
1075
1076 d->mmio_index = cpu_register_io_memory(0, e1000_mmio_read,
1077 e1000_mmio_write, d);
1078
1079 pci_register_io_region((PCIDevice *)d, 0, PNPMMIO_SIZE,
1080 PCI_ADDRESS_SPACE_MEM, e1000_mmio_map);
1081
1082 pci_register_io_region((PCIDevice *)d, 1, IOPORT_SIZE,
1083 PCI_ADDRESS_SPACE_IO, ioport_map);
1084
1085 d->nd = nd;
1086 memmove(d->eeprom_data, e1000_eeprom_template,
1087 sizeof e1000_eeprom_template);
1088 for (i = 0; i < 3; i++)
1089 d->eeprom_data[i] = (nd->macaddr[2*i+1]<<8) | nd->macaddr[2*i];
1090 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1091 checksum += d->eeprom_data[i];
1092 checksum = (uint16_t) EEPROM_SUM - checksum;
1093 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1094
1095 memset(d->phy_reg, 0, sizeof d->phy_reg);
1096 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1097 memset(d->mac_reg, 0, sizeof d->mac_reg);
1098 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1099 d->rxbuf_min_shift = 1;
1100 memset(&d->tx, 0, sizeof d->tx);
1101
1102 d->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
1103 e1000_receive, e1000_can_receive, d);
1104 d->vc->link_status_changed = e1000_set_link_status;
1105
1106 qemu_format_nic_info_str(d->vc, d->nd->macaddr);
1107
1108 register_savevm(info_str, -1, 2, nic_save, nic_load, d);
1109 d->dev.unregister = pci_e1000_uninit;
1110
1111 return (PCIDevice *)d;
1112 }
Patches shipped by Fedora