hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "nvram.h"
  29 #include "pc.h"
  30 #include "sysemu.h"
  31 #include "net.h"
  32 #include "isa.h"
  33 #include "pci.h"
  34 #include "boards.h"
  35 #include "fw_cfg.h"
  36
  37 #define MAX_IDE_BUS 2
  38 #define VGA_BIOS_SIZE 65536
  39 #define CFG_ADDR 0xf0000510
  40
  41 /* temporary frame buffer OSI calls for the video.x driver. The right
  42    solution is to modify the driver to use VGA PCI I/Os */
  43 /* XXX: to be removed. This is no way related to emulation */
  44 static int vga_osi_call (CPUState *env)
  45 {
  46     static int vga_vbl_enabled;
  47     int linesize;
  48
  49     //    printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
  50
  51     /* same handler as PearPC, coming from the original MOL video
  52        driver. */
  53     switch(env->gpr[5]) {
  54     case 4:
  55         break;
  56     case 28: /* set_vmode */
  57         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  58             env->gpr[3] = 1;
  59         else
  60             env->gpr[3] = 0;
  61         break;
  62     case 29: /* get_vmode_info */
  63         if (env->gpr[6] != 0) {
  64             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  65                 env->gpr[3] = 1;
  66                 break;
  67             }
  68         }
  69         env->gpr[3] = 0;
  70         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  71         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  72         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  73         env->gpr[7] = 85 << 16; /* refresh rate */
  74         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  75         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  76         linesize = (linesize + 3) & ~3;
  77         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  78         break;
  79     case 31: /* set_video power */
  80         env->gpr[3] = 0;
  81         break;
  82     case 39: /* video_ctrl */
  83         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  84             vga_vbl_enabled = env->gpr[6];
  85         env->gpr[3] = 0;
  86         break;
  87     case 47:
  88         break;
  89     case 59: /* set_color */
  90         /* R6 = index, R7 = RGB */
  91         env->gpr[3] = 0;
  92         break;
  93     case 64: /* get color */
  94         /* R6 = index */
  95         env->gpr[3] = 0;
  96         break;
  97     case 116: /* set hwcursor */
  98         /* R6 = x, R7 = y, R8 = visible, R9 = data */
  99         break;
 100     default:
 101         fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
 102                 ppc_dump_gpr(env, 5));
 103         break;
 104     }
 105
 106     return 1; /* osi_call handled */
 107 }
 108
 109 static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
 110                                const char *boot_device, DisplayState *ds,
 111                                const char *kernel_filename,
 112                                const char *kernel_cmdline,
 113                                const char *initrd_filename,
 114                                const char *cpu_model)
 115 {
 116     CPUState *env = NULL, *envs[MAX_CPUS];
 117     char buf[1024];
 118     qemu_irq *pic, **heathrow_irqs;
 119     nvram_t nvram;
 120     m48t59_t *m48t59;
 121     int linux_boot, i;
 122     ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
 123     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 124     PCIBus *pci_bus;
 125     MacIONVRAMState *nvr;
 126     int vga_bios_size, bios_size;
 127     qemu_irq *dummy_irq;
 128     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 129     int ide_mem_index[2];
 130     int ppc_boot_device;
 131     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 132     int index;
 133     void *fw_cfg;
 134
 135     linux_boot = (kernel_filename != NULL);
 136
 137     /* init CPUs */
 138     if (cpu_model == NULL)
 139         cpu_model = "G3";
 140     for (i = 0; i < smp_cpus; i++) {
 141         env = cpu_init(cpu_model);
 142         if (!env) {
 143             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 144             exit(1);
 145         }
 146         /* Set time-base frequency to 100 Mhz */
 147         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 148         env->osi_call = vga_osi_call;
 149         qemu_register_reset(&cpu_ppc_reset, env);
 150         envs[i] = env;
 151     }
 152     if (env->nip < 0xFFF80000) {
 153         /* Special test for PowerPC 601:
 154          * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
 155          * But the NVRAM is located at 0xFFF04000...
 156          */
 157         cpu_abort(env, "G3 Beige Mac hardware can not handle 1 MB BIOS\n");
 158     }
 159
 160     /* allocate RAM */
 161     ram_offset = qemu_ram_alloc(ram_size);
 162     cpu_register_physical_memory(0, ram_size, ram_offset);
 163
 164     /* allocate VGA RAM */
 165     vga_ram_offset = qemu_ram_alloc(vga_ram_size);
 166
 167     /* allocate and load BIOS */
 168     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 169     if (bios_name == NULL)
 170         bios_name = PROM_FILENAME;
 171     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 172     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 173
 174     /* Load OpenBIOS (ELF) */
 175     bios_size = load_elf(buf, 0, NULL, NULL, NULL);
 176     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 177         cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
 178         exit(1);
 179     }
 180
 181     /* allocate and load VGA BIOS */
 182     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 183     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 184     vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
 185     if (vga_bios_size < 0) {
 186         /* if no bios is present, we can still work */
 187         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
 188         vga_bios_size = 0;
 189     } else {
 190         /* set a specific header (XXX: find real Apple format for NDRV
 191            drivers) */
 192         phys_ram_base[vga_bios_offset] = 'N';
 193         phys_ram_base[vga_bios_offset + 1] = 'D';
 194         phys_ram_base[vga_bios_offset + 2] = 'R';
 195         phys_ram_base[vga_bios_offset + 3] = 'V';
 196         cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
 197                      vga_bios_size);
 198         vga_bios_size += 8;
 199     }
 200
 201     if (linux_boot) {
 202         kernel_base = KERNEL_LOAD_ADDR;
 203         /* now we can load the kernel */
 204         kernel_size = load_elf(kernel_filename, kernel_base - 0xc0000000ULL,
 205                                NULL, NULL, NULL);
 206         if (kernel_size < 0)
 207             kernel_size = load_aout(kernel_filename, kernel_base,
 208                                     ram_size - kernel_base);
 209         if (kernel_size < 0)
 210             kernel_size = load_image_targphys(kernel_filename,
 211                                               kernel_base,
 212                                               ram_size - kernel_base);
 213         if (kernel_size < 0) {
 214             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 215                       kernel_filename);
 216             exit(1);
 217         }
 218         /* load initrd */
 219         if (initrd_filename) {
 220             initrd_base = INITRD_LOAD_ADDR;
 221             initrd_size = load_image(initrd_filename,
 222                                      phys_ram_base + initrd_base);
 223             if (initrd_size < 0) {
 224                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 225                           initrd_filename);
 226                 exit(1);
 227             }
 228         } else {
 229             initrd_base = 0;
 230             initrd_size = 0;
 231         }
 232         ppc_boot_device = 'm';
 233     } else {
 234         kernel_base = 0;
 235         kernel_size = 0;
 236         initrd_base = 0;
 237         initrd_size = 0;
 238         ppc_boot_device = '\0';
 239         for (i = 0; boot_device[i] != '\0'; i++) {
 240             /* TOFIX: for now, the second IDE channel is not properly
 241              *        used by OHW. The Mac floppy disk are not emulated.
 242              *        For now, OHW cannot boot from the network.
 243              */
 244 #if 0
 245             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 246                 ppc_boot_device = boot_device[i];
 247                 break;
 248             }
 249 #else
 250             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 251                 ppc_boot_device = boot_device[i];
 252                 break;
 253             }
 254 #endif
 255         }
 256         if (ppc_boot_device == '\0') {
 257             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 258             exit(1);
 259         }
 260     }
 261
 262     isa_mem_base = 0x80000000;
 263
 264     /* Register 2 MB of ISA IO space */
 265     isa_mmio_init(0xfe000000, 0x00200000);
 266
 267     /* XXX: we register only 1 output pin for heathrow PIC */
 268     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 269     heathrow_irqs[0] =
 270         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 271     /* Connect the heathrow PIC outputs to the 6xx bus */
 272     for (i = 0; i < smp_cpus; i++) {
 273         switch (PPC_INPUT(env)) {
 274         case PPC_FLAGS_INPUT_6xx:
 275             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 276             heathrow_irqs[i][0] =
 277                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 278             break;
 279         default:
 280             cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
 281             exit(1);
 282         }
 283     }
 284
 285     /* init basic PC hardware */
 286     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 287         cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
 288         exit(1);
 289     }
 290     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 291     pci_bus = pci_grackle_init(0xfec00000, pic);
 292     pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset,
 293                  vga_ram_offset, vga_ram_size,
 294                  vga_bios_offset, vga_bios_size);
 295
 296     /* XXX: suppress that */
 297     dummy_irq = i8259_init(NULL);
 298
 299     /* XXX: use Mac Serial port */
 300     serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);
 301
 302     for(i = 0; i < nb_nics; i++) {
 303         if (!nd_table[i].model)
 304             nd_table[i].model = "ne2k_pci";
 305         pci_nic_init(pci_bus, &nd_table[i], -1);
 306     }
 307
 308     /* First IDE channel is a CMD646 on the PCI bus */
 309
 310     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 311         fprintf(stderr, "qemu: too many IDE bus\n");
 312         exit(1);
 313     }
 314     index = drive_get_index(IF_IDE, 0, 0);
 315     if (index == -1)
 316         hd[0] = NULL;
 317     else
 318         hd[0] =  drives_table[index].bdrv;
 319     index = drive_get_index(IF_IDE, 0, 1);
 320     if (index == -1)
 321         hd[1] = NULL;
 322     else
 323         hd[1] =  drives_table[index].bdrv;
 324     hd[3] = hd[2] = NULL;
 325     pci_cmd646_ide_init(pci_bus, hd, 0);
 326
 327     /* Second IDE channel is a MAC IDE on the MacIO bus */
 328     index = drive_get_index(IF_IDE, 1, 0);
 329     if (index == -1)
 330         hd[0] = NULL;
 331     else
 332         hd[0] =  drives_table[index].bdrv;
 333     index = drive_get_index(IF_IDE, 1, 1);
 334     if (index == -1)
 335         hd[1] = NULL;
 336     else
 337         hd[1] =  drives_table[index].bdrv;
 338     ide_mem_index[0] = -1;
 339     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]);
 340
 341     /* cuda also initialize ADB */
 342     cuda_init(&cuda_mem_index, pic[0x12]);
 343
 344     adb_kbd_init(&adb_bus);
 345     adb_mouse_init(&adb_bus);
 346
 347     nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
 348     pmac_format_nvram_partition(nvr, 0x2000);
 349
 350     dbdma_init(&dbdma_mem_index);
 351
 352     macio_init(pci_bus, 0x0010, 1, pic_mem_index, dbdma_mem_index,
 353                cuda_mem_index, nvr, 2, ide_mem_index);
 354
 355     if (usb_enabled) {
 356         usb_ohci_init_pci(pci_bus, 3, -1);
 357     }
 358
 359     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 360         graphic_depth = 15;
 361
 362     m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
 363     nvram.opaque = m48t59;
 364     nvram.read_fn = &m48t59_read;
 365     nvram.write_fn = &m48t59_write;
 366     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
 367                          ppc_boot_device, kernel_base, kernel_size,
 368                          kernel_cmdline,
 369                          initrd_base, initrd_size,
 370                          /* XXX: need an option to load a NVRAM image */
 371                          0,
 372                          graphic_width, graphic_height, graphic_depth);
 373     /* No PCI init: the BIOS will do it */
 374
 375     /* Special port to get debug messages from Open-Firmware */
 376     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 377
 378     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 379     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 380     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 381     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 382 }
 383
 384 QEMUMachine heathrow_machine = {
 385     .name = "g3beige",
 386     .desc = "Heathrow based PowerMAC",
 387     .init = ppc_heathrow_init,
 388     .ram_require = BIOS_SIZE + VGA_BIOS_SIZE + VGA_RAM_SIZE,
 389     .max_cpus = MAX_CPUS,
 390 };