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Export qemu_system_reset() for qemu-kvm.c
[qemu-kvm/fedora.git] / qemu-kvm.c
blob43048c3748754eec47abbc92bcdd432214a0de40
1
2 #include "config.h"
3 #include "config-host.h"
4
5 #ifdef USE_KVM
6 #define KVM_ALLOWED_DEFAULT 1
7 #else
8 #define KVM_ALLOWED_DEFAULT 0
9 #endif
10
11 int kvm_allowed = KVM_ALLOWED_DEFAULT;
12
13 #ifdef USE_KVM
14
15 #include <string.h>
16 #include "vl.h"
17
18 #include "qemu-kvm.h"
19 #include <kvmctl.h>
20 #include <pthread.h>
21
22 #define MSR_IA32_TSC 0x10
23
24 extern void perror(const char *s);
25
26 kvm_context_t kvm_context;
27 static struct kvm_msr_list *kvm_msr_list;
28 static int kvm_has_msr_star;
29
30 extern int smp_cpus;
31
32 pthread_mutex_t qemu_mutex = PTHREAD_MUTEX_INITIALIZER;
33 static __thread CPUState *vcpu_env;
34
35 static sigset_t io_sigset, io_negsigset;
36
37 static int wait_hack;
38
39 #define SIG_IPI (SIGRTMIN+4)
40
41 struct vcpu_info {
42 int sipi_needed;
43 int init;
44 pthread_t thread;
45 int signalled;
46 } vcpu_info[4];
47
48 static void sig_ipi_handler(int n)
49 {
50 }
51
52 void kvm_update_interrupt_request(CPUState *env)
53 {
54 if (env && env != vcpu_env) {
55 if (vcpu_info[env->cpu_index].signalled)
56 return;
57 vcpu_info[env->cpu_index].signalled = 1;
58 if (vcpu_info[env->cpu_index].thread)
59 pthread_kill(vcpu_info[env->cpu_index].thread, SIG_IPI);
60 }
61 }
62
63 void kvm_update_after_sipi(CPUState *env)
64 {
65 vcpu_info[env->cpu_index].sipi_needed = 1;
66 kvm_update_interrupt_request(env);
67
68 /*
69 * the qemu bios waits using a busy loop that's much too short for
70 * kvm. add a wait after the first sipi.
71 */
72 {
73 static int first_sipi = 1;
74
75 if (first_sipi) {
76 wait_hack = 1;
77 first_sipi = 0;
78 }
79 }
80 }
81
82 void kvm_apic_init(CPUState *env)
83 {
84 vcpu_info[env->cpu_index].init = 1;
85 kvm_update_interrupt_request(env);
86 }
87
88 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
89 uint64_t data)
90 {
91 entry->index = index;
92 entry->data = data;
93 }
94
95 /* returns 0 on success, non-0 on failure */
96 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
97 {
98 switch (entry->index) {
99 case MSR_IA32_SYSENTER_CS:
100 env->sysenter_cs = entry->data;
101 break;
102 case MSR_IA32_SYSENTER_ESP:
103 env->sysenter_esp = entry->data;
104 break;
105 case MSR_IA32_SYSENTER_EIP:
106 env->sysenter_eip = entry->data;
107 break;
108 case MSR_STAR:
109 env->star = entry->data;
110 break;
111 #ifdef TARGET_X86_64
112 case MSR_CSTAR:
113 env->cstar = entry->data;
114 break;
115 case MSR_KERNELGSBASE:
116 env->kernelgsbase = entry->data;
117 break;
118 case MSR_FMASK:
119 env->fmask = entry->data;
120 break;
121 case MSR_LSTAR:
122 env->lstar = entry->data;
123 break;
124 #endif
125 case MSR_IA32_TSC:
126 env->tsc = entry->data;
127 break;
128 default:
129 printf("Warning unknown msr index 0x%x\n", entry->index);
130 return 1;
131 }
132 return 0;
133 }
134
135 #ifdef TARGET_X86_64
136 #define MSR_COUNT 9
137 #else
138 #define MSR_COUNT 5
139 #endif
140
141 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
142 {
143 lhs->selector = rhs->selector;
144 lhs->base = rhs->base;
145 lhs->limit = rhs->limit;
146 lhs->type = 3;
147 lhs->present = 1;
148 lhs->dpl = 3;
149 lhs->db = 0;
150 lhs->s = 1;
151 lhs->l = 0;
152 lhs->g = 0;
153 lhs->avl = 0;
154 lhs->unusable = 0;
155 }
156
157 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
158 {
159 unsigned flags = rhs->flags;
160 lhs->selector = rhs->selector;
161 lhs->base = rhs->base;
162 lhs->limit = rhs->limit;
163 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
164 lhs->present = (flags & DESC_P_MASK) != 0;
165 lhs->dpl = rhs->selector & 3;
166 lhs->db = (flags >> DESC_B_SHIFT) & 1;
167 lhs->s = (flags & DESC_S_MASK) != 0;
168 lhs->l = (flags >> DESC_L_SHIFT) & 1;
169 lhs->g = (flags & DESC_G_MASK) != 0;
170 lhs->avl = (flags & DESC_AVL_MASK) != 0;
171 lhs->unusable = 0;
172 }
173
174 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
175 {
176 lhs->selector = rhs->selector;
177 lhs->base = rhs->base;
178 lhs->limit = rhs->limit;
179 lhs->flags =
180 (rhs->type << DESC_TYPE_SHIFT)
181 | (rhs->present * DESC_P_MASK)
182 | (rhs->dpl << DESC_DPL_SHIFT)
183 | (rhs->db << DESC_B_SHIFT)
184 | (rhs->s * DESC_S_MASK)
185 | (rhs->l << DESC_L_SHIFT)
186 | (rhs->g * DESC_G_MASK)
187 | (rhs->avl * DESC_AVL_MASK);
188 }
189
190 /* the reset values of qemu are not compatible to SVM
191 * this function is used to fix the segment descriptor values */
192 static void fix_realmode_dataseg(struct kvm_segment *seg)
193 {
194 seg->type = 0x02;
195 seg->present = 1;
196 seg->s = 1;
197 }
198
199 static void load_regs(CPUState *env)
200 {
201 struct kvm_regs regs;
202 struct kvm_fpu fpu;
203 struct kvm_sregs sregs;
204 struct kvm_msr_entry msrs[MSR_COUNT];
205 int rc, n, i;
206
207 regs.rax = env->regs[R_EAX];
208 regs.rbx = env->regs[R_EBX];
209 regs.rcx = env->regs[R_ECX];
210 regs.rdx = env->regs[R_EDX];
211 regs.rsi = env->regs[R_ESI];
212 regs.rdi = env->regs[R_EDI];
213 regs.rsp = env->regs[R_ESP];
214 regs.rbp = env->regs[R_EBP];
215 #ifdef TARGET_X86_64
216 regs.r8 = env->regs[8];
217 regs.r9 = env->regs[9];
218 regs.r10 = env->regs[10];
219 regs.r11 = env->regs[11];
220 regs.r12 = env->regs[12];
221 regs.r13 = env->regs[13];
222 regs.r14 = env->regs[14];
223 regs.r15 = env->regs[15];
224 #endif
225
226 regs.rflags = env->eflags;
227 regs.rip = env->eip;
228
229 kvm_set_regs(kvm_context, env->cpu_index, &regs);
230
231 memset(&fpu, 0, sizeof fpu);
232 fpu.fsw = env->fpus & ~(7 << 11);
233 fpu.fsw |= (env->fpstt & 7) << 11;
234 fpu.fcw = env->fpuc;
235 for (i = 0; i < 8; ++i)
236 fpu.ftwx |= (!env->fptags[i]) << i;
237 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
238 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
239 fpu.mxcsr = env->mxcsr;
240 kvm_set_fpu(kvm_context, env->cpu_index, &fpu);
241
242 memcpy(sregs.interrupt_bitmap, env->kvm_interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
243
244 if ((env->eflags & VM_MASK)) {
245 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
246 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
247 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
248 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
249 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
250 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
251 } else {
252 set_seg(&sregs.cs, &env->segs[R_CS]);
253 set_seg(&sregs.ds, &env->segs[R_DS]);
254 set_seg(&sregs.es, &env->segs[R_ES]);
255 set_seg(&sregs.fs, &env->segs[R_FS]);
256 set_seg(&sregs.gs, &env->segs[R_GS]);
257 set_seg(&sregs.ss, &env->segs[R_SS]);
258
259 if (env->cr[0] & CR0_PE_MASK) {
260 /* force ss cpl to cs cpl */
261 sregs.ss.selector = (sregs.ss.selector & ~3) |
262 (sregs.cs.selector & 3);
263 sregs.ss.dpl = sregs.ss.selector & 3;
264 }
265
266 if (!(env->cr[0] & CR0_PG_MASK)) {
267 fix_realmode_dataseg(&sregs.cs);
268 fix_realmode_dataseg(&sregs.ds);
269 fix_realmode_dataseg(&sregs.es);
270 fix_realmode_dataseg(&sregs.fs);
271 fix_realmode_dataseg(&sregs.gs);
272 fix_realmode_dataseg(&sregs.ss);
273 }
274 }
275
276 set_seg(&sregs.tr, &env->tr);
277 set_seg(&sregs.ldt, &env->ldt);
278
279 sregs.idt.limit = env->idt.limit;
280 sregs.idt.base = env->idt.base;
281 sregs.gdt.limit = env->gdt.limit;
282 sregs.gdt.base = env->gdt.base;
283
284 sregs.cr0 = env->cr[0];
285 sregs.cr2 = env->cr[2];
286 sregs.cr3 = env->cr[3];
287 sregs.cr4 = env->cr[4];
288
289 sregs.apic_base = cpu_get_apic_base(env);
290 sregs.efer = env->efer;
291 sregs.cr8 = cpu_get_apic_tpr(env);
292
293 kvm_set_sregs(kvm_context, env->cpu_index, &sregs);
294
295 /* msrs */
296 n = 0;
297 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
298 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
299 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
300 if (kvm_has_msr_star)
301 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
302 set_msr_entry(&msrs[n++], MSR_IA32_TSC, env->tsc);
303 #ifdef TARGET_X86_64
304 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
305 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
306 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
307 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
308 #endif
309
310 rc = kvm_set_msrs(kvm_context, env->cpu_index, msrs, n);
311 if (rc == -1)
312 perror("kvm_set_msrs FAILED");
313 }
314
315
316 static void save_regs(CPUState *env)
317 {
318 struct kvm_regs regs;
319 struct kvm_fpu fpu;
320 struct kvm_sregs sregs;
321 struct kvm_msr_entry msrs[MSR_COUNT];
322 uint32_t hflags;
323 uint32_t i, n, rc;
324
325 kvm_get_regs(kvm_context, env->cpu_index, &regs);
326
327 env->regs[R_EAX] = regs.rax;
328 env->regs[R_EBX] = regs.rbx;
329 env->regs[R_ECX] = regs.rcx;
330 env->regs[R_EDX] = regs.rdx;
331 env->regs[R_ESI] = regs.rsi;
332 env->regs[R_EDI] = regs.rdi;
333 env->regs[R_ESP] = regs.rsp;
334 env->regs[R_EBP] = regs.rbp;
335 #ifdef TARGET_X86_64
336 env->regs[8] = regs.r8;
337 env->regs[9] = regs.r9;
338 env->regs[10] = regs.r10;
339 env->regs[11] = regs.r11;
340 env->regs[12] = regs.r12;
341 env->regs[13] = regs.r13;
342 env->regs[14] = regs.r14;
343 env->regs[15] = regs.r15;
344 #endif
345
346 env->eflags = regs.rflags;
347 env->eip = regs.rip;
348
349 kvm_get_fpu(kvm_context, env->cpu_index, &fpu);
350 env->fpstt = (fpu.fsw >> 11) & 7;
351 env->fpus = fpu.fsw;
352 env->fpuc = fpu.fcw;
353 for (i = 0; i < 8; ++i)
354 env->fptags[i] = !((fpu.ftwx >> i) & 1);
355 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
356 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
357 env->mxcsr = fpu.mxcsr;
358
359 kvm_get_sregs(kvm_context, env->cpu_index, &sregs);
360
361 memcpy(env->kvm_interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->kvm_interrupt_bitmap));
362
363 get_seg(&env->segs[R_CS], &sregs.cs);
364 get_seg(&env->segs[R_DS], &sregs.ds);
365 get_seg(&env->segs[R_ES], &sregs.es);
366 get_seg(&env->segs[R_FS], &sregs.fs);
367 get_seg(&env->segs[R_GS], &sregs.gs);
368 get_seg(&env->segs[R_SS], &sregs.ss);
369
370 get_seg(&env->tr, &sregs.tr);
371 get_seg(&env->ldt, &sregs.ldt);
372
373 env->idt.limit = sregs.idt.limit;
374 env->idt.base = sregs.idt.base;
375 env->gdt.limit = sregs.gdt.limit;
376 env->gdt.base = sregs.gdt.base;
377
378 env->cr[0] = sregs.cr0;
379 env->cr[2] = sregs.cr2;
380 env->cr[3] = sregs.cr3;
381 env->cr[4] = sregs.cr4;
382
383 cpu_set_apic_base(env, sregs.apic_base);
384
385 env->efer = sregs.efer;
386 //cpu_set_apic_tpr(env, sregs.cr8);
387
388 #define HFLAG_COPY_MASK ~( \
389 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
390 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
391 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
392 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
393
394
395
396 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
397 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
398 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
399 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
400 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
401 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
402 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
403
404 if (env->efer & MSR_EFER_LMA) {
405 hflags |= HF_LMA_MASK;
406 }
407
408 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
409 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
410 } else {
411 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
412 (DESC_B_SHIFT - HF_CS32_SHIFT);
413 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
414 (DESC_B_SHIFT - HF_SS32_SHIFT);
415 if (!(env->cr[0] & CR0_PE_MASK) ||
416 (env->eflags & VM_MASK) ||
417 !(hflags & HF_CS32_MASK)) {
418 hflags |= HF_ADDSEG_MASK;
419 } else {
420 hflags |= ((env->segs[R_DS].base |
421 env->segs[R_ES].base |
422 env->segs[R_SS].base) != 0) <<
423 HF_ADDSEG_SHIFT;
424 }
425 }
426 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
427 env->cc_src = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
428 env->df = 1 - (2 * ((env->eflags >> 10) & 1));
429 env->cc_op = CC_OP_EFLAGS;
430 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
431
432 /* msrs */
433 n = 0;
434 msrs[n++].index = MSR_IA32_SYSENTER_CS;
435 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
436 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
437 if (kvm_has_msr_star)
438 msrs[n++].index = MSR_STAR;
439 msrs[n++].index = MSR_IA32_TSC;
440 #ifdef TARGET_X86_64
441 msrs[n++].index = MSR_CSTAR;
442 msrs[n++].index = MSR_KERNELGSBASE;
443 msrs[n++].index = MSR_FMASK;
444 msrs[n++].index = MSR_LSTAR;
445 #endif
446 rc = kvm_get_msrs(kvm_context, env->cpu_index, msrs, n);
447 if (rc == -1) {
448 perror("kvm_get_msrs FAILED");
449 }
450 else {
451 n = rc; /* actual number of MSRs */
452 for (i=0 ; i<n; i++) {
453 if (get_msr_entry(&msrs[i], env))
454 return;
455 }
456 }
457 }
458
459 #include <signal.h>
460
461
462 static int try_push_interrupts(void *opaque)
463 {
464 CPUState *env = cpu_single_env;
465 int r, irq;
466
467 if (env->ready_for_interrupt_injection &&
468 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
469 (env->eflags & IF_MASK)) {
470 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
471 irq = cpu_get_pic_interrupt(env);
472 if (irq >= 0) {
473 r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
474 if (r < 0)
475 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
476 }
477 }
478
479 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
480 }
481
482 static void post_kvm_run(void *opaque, int vcpu)
483 {
484 CPUState *env = vcpu_env;
485
486 pthread_mutex_lock(&qemu_mutex);
487 cpu_single_env = env;
488 env->eflags = kvm_get_interrupt_flag(kvm_context, vcpu)
489 ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
490 env->ready_for_interrupt_injection
491 = kvm_is_ready_for_interrupt_injection(kvm_context, vcpu);
492 //cpu_set_apic_tpr(env, kvm_run->cr8);
493 cpu_set_apic_base(env, kvm_get_apic_base(kvm_context, vcpu));
494 }
495
496 static int pre_kvm_run(void *opaque, int vcpu)
497 {
498 CPUState *env = cpu_single_env;
499
500 if (env->cpu_index == 0 && wait_hack) {
501 int i;
502
503 wait_hack = 0;
504
505 pthread_mutex_unlock(&qemu_mutex);
506 for (i = 0; i < 10; ++i)
507 usleep(1000);
508 pthread_mutex_lock(&qemu_mutex);
509 }
510
511 kvm_set_cr8(kvm_context, vcpu, cpu_get_apic_tpr(env));
512 if (env->interrupt_request & CPU_INTERRUPT_EXIT)
513 return 1;
514 pthread_mutex_unlock(&qemu_mutex);
515 return 0;
516 }
517
518 void kvm_load_registers(CPUState *env)
519 {
520 if (kvm_allowed)
521 load_regs(env);
522 }
523
524 void kvm_save_registers(CPUState *env)
525 {
526 if (kvm_allowed)
527 save_regs(env);
528 }
529
530 int kvm_cpu_exec(CPUState *env)
531 {
532 int r;
533
534 r = kvm_run(kvm_context, env->cpu_index);
535 if (r < 0) {
536 printf("kvm_run returned %d\n", r);
537 exit(1);
538 }
539
540 return 0;
541 }
542
543 extern int vm_running;
544
545 static int has_work(CPUState *env)
546 {
547 if (!vm_running)
548 return 0;
549 if (!(env->hflags & HF_HALTED_MASK))
550 return 1;
551 if (env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT))
552 return 1;
553 return 0;
554 }
555
556 static int kvm_eat_signal(CPUState *env, int timeout)
557 {
558 struct timespec ts;
559 int r, e, ret = 0;
560 siginfo_t siginfo;
561 struct sigaction sa;
562
563 ts.tv_sec = timeout / 1000;
564 ts.tv_nsec = (timeout % 1000) * 1000000;
565 r = sigtimedwait(&io_sigset, &siginfo, &ts);
566 if (r == -1 && (errno == EAGAIN || errno == EINTR) && !timeout)
567 return 0;
568 e = errno;
569 pthread_mutex_lock(&qemu_mutex);
570 cpu_single_env = vcpu_env;
571 if (r == -1 && !(errno == EAGAIN || errno == EINTR)) {
572 printf("sigtimedwait: %s\n", strerror(e));
573 exit(1);
574 }
575 if (r != -1) {
576 sigaction(siginfo.si_signo, NULL, &sa);
577 sa.sa_handler(siginfo.si_signo);
578 ret = 1;
579 }
580 pthread_mutex_unlock(&qemu_mutex);
581
582 return ret;
583 }
584
585
586 static int kvm_eat_signals(CPUState *env, int timeout)
587 {
588 int r = 0;
589
590 while (kvm_eat_signal(env, 0))
591 r = 1;
592 if (!r && timeout) {
593 r = kvm_eat_signal(env, timeout);
594 if (r)
595 while (kvm_eat_signal(env, 0))
596 ;
597 }
598 /*
599 * we call select() even if no signal was received, to account for
600 * for which there is no signal handler installed.
601 */
602 pthread_mutex_lock(&qemu_mutex);
603 cpu_single_env = vcpu_env;
604 main_loop_wait(0);
605 pthread_mutex_unlock(&qemu_mutex);
606 }
607
608 static void kvm_main_loop_wait(CPUState *env, int timeout)
609 {
610 if (vcpu_info[env->cpu_index].signalled && timeout)
611 goto shortcut;
612 pthread_mutex_unlock(&qemu_mutex);
613 if (env->cpu_index == 0)
614 kvm_eat_signals(env, timeout);
615 else
616 if (timeout) {
617 sigset_t set;
618 int n;
619
620 sigemptyset(&set);
621 sigaddset(&set, SIG_IPI);
622 sigwait(&set, &n);
623 }
624 pthread_mutex_lock(&qemu_mutex);
625 cpu_single_env = env;
626 shortcut:
627 vcpu_info[env->cpu_index].signalled = 0;
628 }
629
630 static void update_regs_for_sipi(CPUState *env)
631 {
632 SegmentCache cs = env->segs[R_CS];
633
634 save_regs(env);
635 env->segs[R_CS] = cs;
636 env->eip = 0;
637 load_regs(env);
638 vcpu_info[env->cpu_index].sipi_needed = 0;
639 vcpu_info[env->cpu_index].init = 0;
640 }
641
642 static void update_regs_for_init(CPUState *env)
643 {
644 cpu_reset(env);
645 load_regs(env);
646 }
647
648 static void setup_kernel_sigmask(CPUState *env)
649 {
650 sigset_t set;
651
652 sigprocmask(SIG_BLOCK, NULL, &set);
653 sigdelset(&set, SIG_IPI);
654 if (env->cpu_index == 0)
655 sigandset(&set, &set, &io_negsigset);
656
657 kvm_set_signal_mask(kvm_context, env->cpu_index, &set);
658 }
659
660 static int kvm_main_loop_cpu(CPUState *env)
661 {
662 setup_kernel_sigmask(env);
663 pthread_mutex_lock(&qemu_mutex);
664 cpu_single_env = env;
665 while (1) {
666 while (!has_work(env))
667 kvm_main_loop_wait(env, 10);
668 if (env->interrupt_request & CPU_INTERRUPT_HARD)
669 env->hflags &= ~HF_HALTED_MASK;
670 if (vcpu_info[env->cpu_index].sipi_needed)
671 update_regs_for_sipi(env);
672 if (vcpu_info[env->cpu_index].init)
673 update_regs_for_init(env);
674 if (!(env->hflags & HF_HALTED_MASK) && !vcpu_info[env->cpu_index].init)
675 kvm_cpu_exec(env);
676 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
677 kvm_main_loop_wait(env, 0);
678 if (qemu_shutdown_requested())
679 break;
680 else if (qemu_powerdown_requested())
681 qemu_system_powerdown();
682 else if (qemu_reset_requested()) {
683 env->interrupt_request = 0;
684 qemu_system_reset();
685 load_regs(env);
686 }
687 }
688 pthread_mutex_unlock(&qemu_mutex);
689 return 0;
690 }
691
692 static void *ap_main_loop(void *_env)
693 {
694 CPUState *env = _env;
695 sigset_t signals;
696
697 vcpu_env = env;
698 sigfillset(&signals);
699 //sigdelset(&signals, SIG_IPI);
700 sigprocmask(SIG_BLOCK, &signals, NULL);
701 kvm_create_vcpu(kvm_context, env->cpu_index);
702 kvm_qemu_init_env(env);
703 kvm_main_loop_cpu(env);
704 return NULL;
705 }
706
707 static void kvm_add_signal(int signum)
708 {
709 sigaddset(&io_sigset, signum);
710 sigdelset(&io_negsigset, signum);
711 sigprocmask(SIG_BLOCK, &io_sigset, NULL);
712 }
713
714 int kvm_main_loop(void)
715 {
716 CPUState *env = first_cpu->next_cpu;
717 int i;
718
719 sigemptyset(&io_sigset);
720 sigfillset(&io_negsigset);
721 kvm_add_signal(SIGIO);
722 kvm_add_signal(SIGALRM);
723 kvm_add_signal(SIGUSR2);
724 kvm_add_signal(SIG_IPI);
725
726 vcpu_env = first_cpu;
727 signal(SIG_IPI, sig_ipi_handler);
728 for (i = 1; i < smp_cpus; ++i) {
729 pthread_create(&vcpu_info[i].thread, NULL, ap_main_loop, env);
730 env = env->next_cpu;
731 }
732 vcpu_info[0].thread = pthread_self();
733 return kvm_main_loop_cpu(first_cpu);
734 }
735
736 static int kvm_debug(void *opaque, int vcpu)
737 {
738 CPUState *env = cpu_single_env;
739
740 env->exception_index = EXCP_DEBUG;
741 return 1;
742 }
743
744 static int kvm_inb(void *opaque, uint16_t addr, uint8_t *data)
745 {
746 *data = cpu_inb(0, addr);
747 return 0;
748 }
749
750 static int kvm_inw(void *opaque, uint16_t addr, uint16_t *data)
751 {
752 *data = cpu_inw(0, addr);
753 return 0;
754 }
755
756 static int kvm_inl(void *opaque, uint16_t addr, uint32_t *data)
757 {
758 *data = cpu_inl(0, addr);
759 return 0;
760 }
761
762 #define PM_IO_BASE 0xb000
763
764 static int kvm_outb(void *opaque, uint16_t addr, uint8_t data)
765 {
766 if (addr == 0xb2) {
767 switch (data) {
768 case 0: {
769 cpu_outb(0, 0xb3, 0);
770 break;
771 }
772 case 0xf0: {
773 unsigned x;
774
775 /* enable acpi */
776 x = cpu_inw(0, PM_IO_BASE + 4);
777 x &= ~1;
778 cpu_outw(0, PM_IO_BASE + 4, x);
779 break;
780 }
781 case 0xf1: {
782 unsigned x;
783
784 /* enable acpi */
785 x = cpu_inw(0, PM_IO_BASE + 4);
786 x |= 1;
787 cpu_outw(0, PM_IO_BASE + 4, x);
788 break;
789 }
790 default:
791 break;
792 }
793 return 0;
794 }
795 cpu_outb(0, addr, data);
796 return 0;
797 }
798
799 static int kvm_outw(void *opaque, uint16_t addr, uint16_t data)
800 {
801 cpu_outw(0, addr, data);
802 return 0;
803 }
804
805 static int kvm_outl(void *opaque, uint16_t addr, uint32_t data)
806 {
807 cpu_outl(0, addr, data);
808 return 0;
809 }
810
811 static int kvm_readb(void *opaque, uint64_t addr, uint8_t *data)
812 {
813 *data = ldub_phys(addr);
814 return 0;
815 }
816
817 static int kvm_readw(void *opaque, uint64_t addr, uint16_t *data)
818 {
819 *data = lduw_phys(addr);
820 return 0;
821 }
822
823 static int kvm_readl(void *opaque, uint64_t addr, uint32_t *data)
824 {
825 *data = ldl_phys(addr);
826 return 0;
827 }
828
829 static int kvm_readq(void *opaque, uint64_t addr, uint64_t *data)
830 {
831 *data = ldq_phys(addr);
832 return 0;
833 }
834
835 static int kvm_writeb(void *opaque, uint64_t addr, uint8_t data)
836 {
837 stb_phys(addr, data);
838 return 0;
839 }
840
841 static int kvm_writew(void *opaque, uint64_t addr, uint16_t data)
842 {
843 stw_phys(addr, data);
844 return 0;
845 }
846
847 static int kvm_writel(void *opaque, uint64_t addr, uint32_t data)
848 {
849 stl_phys(addr, data);
850 return 0;
851 }
852
853 static int kvm_writeq(void *opaque, uint64_t addr, uint64_t data)
854 {
855 stq_phys(addr, data);
856 return 0;
857 }
858
859 static int kvm_io_window(void *opaque)
860 {
861 return 1;
862 }
863
864
865 static int kvm_halt(void *opaque, int vcpu)
866 {
867 CPUState *env = cpu_single_env;
868
869 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
870 (env->eflags & IF_MASK))) {
871 env->hflags |= HF_HALTED_MASK;
872 env->exception_index = EXCP_HLT;
873 }
874
875 return 1;
876 }
877
878 static int kvm_shutdown(void *opaque, int vcpu)
879 {
880 qemu_system_reset_request();
881 return 1;
882 }
883
884 static struct kvm_callbacks qemu_kvm_ops = {
885 .debug = kvm_debug,
886 .inb = kvm_inb,
887 .inw = kvm_inw,
888 .inl = kvm_inl,
889 .outb = kvm_outb,
890 .outw = kvm_outw,
891 .outl = kvm_outl,
892 .readb = kvm_readb,
893 .readw = kvm_readw,
894 .readl = kvm_readl,
895 .readq = kvm_readq,
896 .writeb = kvm_writeb,
897 .writew = kvm_writew,
898 .writel = kvm_writel,
899 .writeq = kvm_writeq,
900 .halt = kvm_halt,
901 .shutdown = kvm_shutdown,
902 .io_window = kvm_io_window,
903 .try_push_interrupts = try_push_interrupts,
904 .post_kvm_run = post_kvm_run,
905 .pre_kvm_run = pre_kvm_run,
906 };
907
908 int kvm_qemu_init()
909 {
910 /* Try to initialize kvm */
911 kvm_context = kvm_init(&qemu_kvm_ops, cpu_single_env);
912 if (!kvm_context) {
913 return -1;
914 }
915
916 return 0;
917 }
918
919 int kvm_qemu_create_context(void)
920 {
921 int i;
922
923 if (kvm_create(kvm_context, phys_ram_size, (void**)&phys_ram_base) < 0) {
924 kvm_qemu_destroy();
925 return -1;
926 }
927 kvm_msr_list = kvm_get_msr_list(kvm_context);
928 if (!kvm_msr_list) {
929 kvm_qemu_destroy();
930 return -1;
931 }
932 for (i = 0; i < kvm_msr_list->nmsrs; ++i)
933 if (kvm_msr_list->indices[i] == MSR_STAR)
934 kvm_has_msr_star = 1;
935 return 0;
936 }
937
938 void kvm_qemu_destroy(void)
939 {
940 kvm_finalize(kvm_context);
941 }
942
943 static void host_cpuid(uint32_t function, uint32_t *eax, uint32_t *ebx,
944 uint32_t *ecx, uint32_t *edx)
945 {
946 uint32_t vec[4];
947
948 vec[0] = function;
949 asm volatile (
950 #ifdef __x86_64__
951 "sub $128, %%rsp \n\t" /* skip red zone */
952 "push %0; push %%rsi \n\t"
953 "push %%rax; push %%rbx; push %%rcx; push %%rdx \n\t"
954 "mov 8*5(%%rsp), %%rsi \n\t"
955 "mov (%%rsi), %%eax \n\t"
956 "cpuid \n\t"
957 "mov %%eax, (%%rsi) \n\t"
958 "mov %%ebx, 4(%%rsi) \n\t"
959 "mov %%ecx, 8(%%rsi) \n\t"
960 "mov %%edx, 12(%%rsi) \n\t"
961 "pop %%rdx; pop %%rcx; pop %%rbx; pop %%rax \n\t"
962 "pop %%rsi; pop %0 \n\t"
963 "add $128, %%rsp"
964 #else
965 "push %0; push %%esi \n\t"
966 "push %%eax; push %%ebx; push %%ecx; push %%edx \n\t"
967 "mov 4*5(%%esp), %%esi \n\t"
968 "mov (%%esi), %%eax \n\t"
969 "cpuid \n\t"
970 "mov %%eax, (%%esi) \n\t"
971 "mov %%ebx, 4(%%esi) \n\t"
972 "mov %%ecx, 8(%%esi) \n\t"
973 "mov %%edx, 12(%%esi) \n\t"
974 "pop %%edx; pop %%ecx; pop %%ebx; pop %%eax \n\t"
975 "pop %%esi; pop %0 \n\t"
976 #endif
977 : : "rm"(vec) : "memory");
978 if (eax)
979 *eax = vec[0];
980 if (ebx)
981 *ebx = vec[1];
982 if (ecx)
983 *ecx = vec[2];
984 if (edx)
985 *edx = vec[3];
986 }
987
988 static void do_cpuid_ent(struct kvm_cpuid_entry *e, uint32_t function,
989 CPUState *env)
990 {
991 env->regs[R_EAX] = function;
992 qemu_kvm_cpuid_on_env(env);
993 e->function = function;
994 e->eax = env->regs[R_EAX];
995 e->ebx = env->regs[R_EBX];
996 e->ecx = env->regs[R_ECX];
997 e->edx = env->regs[R_EDX];
998 if (function == 0x80000001) {
999 uint32_t h_eax, h_edx;
1000
1001 host_cpuid(function, &h_eax, NULL, NULL, &h_edx);
1002
1003 // long mode
1004 if ((h_edx & 0x20000000) == 0)
1005 e->edx &= ~0x20000000u;
1006 // syscall
1007 if ((h_edx & 0x00000800) == 0)
1008 e->edx &= ~0x00000800u;
1009 // nx
1010 if ((h_edx & 0x00100000) == 0)
1011 e->edx &= ~0x00100000u;
1012 }
1013 // sysenter isn't supported on compatibility mode on AMD. and syscall
1014 // isn't supported in compatibility mode on Intel. so advertise the
1015 // actuall cpu, and say goodbye to migration between different vendors
1016 // is you use compatibility mode.
1017 if (function == 0) {
1018 uint32_t bcd[3];
1019
1020 host_cpuid(0, NULL, &bcd[0], &bcd[1], &bcd[2]);
1021 e->ebx = bcd[0];
1022 e->ecx = bcd[1];
1023 e->edx = bcd[2];
1024 }
1025 }
1026
1027 int kvm_qemu_init_env(CPUState *cenv)
1028 {
1029 struct kvm_cpuid_entry cpuid_ent[100];
1030 int cpuid_nent = 0;
1031 CPUState copy;
1032 uint32_t i, limit;
1033
1034 copy = *cenv;
1035
1036 copy.regs[R_EAX] = 0;
1037 qemu_kvm_cpuid_on_env(&copy);
1038 limit = copy.regs[R_EAX];
1039
1040 for (i = 0; i <= limit; ++i)
1041 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, &copy);
1042
1043 copy.regs[R_EAX] = 0x80000000;
1044 qemu_kvm_cpuid_on_env(&copy);
1045 limit = copy.regs[R_EAX];
1046
1047 for (i = 0x80000000; i <= limit; ++i)
1048 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, &copy);
1049
1050 kvm_setup_cpuid(kvm_context, cenv->cpu_index, cpuid_nent, cpuid_ent);
1051
1052 return 0;
1053 }
1054
1055 int kvm_update_debugger(CPUState *env)
1056 {
1057 struct kvm_debug_guest dbg;
1058 int i;
1059
1060 dbg.enabled = 0;
1061 if (env->nb_breakpoints || env->singlestep_enabled) {
1062 dbg.enabled = 1;
1063 for (i = 0; i < 4 && i < env->nb_breakpoints; ++i) {
1064 dbg.breakpoints[i].enabled = 1;
1065 dbg.breakpoints[i].address = env->breakpoints[i];
1066 }
1067 dbg.singlestep = env->singlestep_enabled;
1068 }
1069 return kvm_guest_debug(kvm_context, env->cpu_index, &dbg);
1070 }
1071
1072
1073 /*
1074 * dirty pages logging
1075 */
1076 /* FIXME: use unsigned long pointer instead of unsigned char */
1077 unsigned char *kvm_dirty_bitmap = NULL;
1078 int kvm_physical_memory_set_dirty_tracking(int enable)
1079 {
1080 int r = 0;
1081
1082 if (!kvm_allowed)
1083 return 0;
1084
1085 if (enable) {
1086 if (!kvm_dirty_bitmap) {
1087 unsigned bitmap_size = BITMAP_SIZE(phys_ram_size);
1088 kvm_dirty_bitmap = qemu_malloc(bitmap_size);
1089 if (kvm_dirty_bitmap == NULL) {
1090 perror("Failed to allocate dirty pages bitmap");
1091 r=-1;
1092 }
1093 else {
1094 r = kvm_dirty_pages_log_enable_all(kvm_context);
1095 }
1096 }
1097 }
1098 else {
1099 if (kvm_dirty_bitmap) {
1100 r = kvm_dirty_pages_log_reset(kvm_context);
1101 qemu_free(kvm_dirty_bitmap);
1102 kvm_dirty_bitmap = NULL;
1103 }
1104 }
1105 return r;
1106 }
1107
1108 /* get kvm's dirty pages bitmap and update qemu's */
1109 int kvm_get_dirty_pages_log_slot(int slot,
1110 unsigned char *bitmap,
1111 unsigned int offset,
1112 unsigned int len)
1113 {
1114 int r;
1115 unsigned int i, j, n=0;
1116 unsigned char c;
1117 unsigned page_number, addr, addr1;
1118
1119 memset(bitmap, 0, len);
1120 r = kvm_get_dirty_pages(kvm_context, slot, bitmap);
1121 if (r)
1122 return r;
1123
1124 /*
1125 * bitmap-traveling is faster than memory-traveling (for addr...)
1126 * especially when most of the memory is not dirty.
1127 */
1128 for (i=0; i<len; i++) {
1129 c = bitmap[i];
1130 while (c>0) {
1131 j = ffsl(c) - 1;
1132 c &= ~(1u<<j);
1133 page_number = i * 8 + j;
1134 addr1 = page_number * TARGET_PAGE_SIZE;
1135 addr = offset + addr1;
1136 cpu_physical_memory_set_dirty(addr);
1137 n++;
1138 }
1139 }
1140 return 0;
1141 }
1142
1143 /*
1144 * get kvm's dirty pages bitmap and update qemu's
1145 * we only care about physical ram, which resides in slots 0 and 3
1146 */
1147 int kvm_update_dirty_pages_log(void)
1148 {
1149 int r = 0, len;
1150
1151 len = BITMAP_SIZE(0xa0000);
1152 r = kvm_get_dirty_pages_log_slot(3, kvm_dirty_bitmap, 0 , len);
1153 len = BITMAP_SIZE(phys_ram_size - 0xc0000);
1154 r = r || kvm_get_dirty_pages_log_slot(0, kvm_dirty_bitmap, 0xc0000, len);
1155 return r;
1156 }
1157
1158 int kvm_get_phys_ram_page_bitmap(unsigned char *bitmap)
1159 {
1160 int r=0, len, offset;
1161
1162 len = BITMAP_SIZE(phys_ram_size);
1163 memset(bitmap, 0, len);
1164
1165 r = kvm_get_mem_map(kvm_context, 3, bitmap);
1166 if (r)
1167 goto out;
1168
1169 offset = BITMAP_SIZE(0xc0000);
1170 r = kvm_get_mem_map(kvm_context, 0, bitmap + offset);
1171
1172 out:
1173 return r;
1174 }
1175 #endif
Patches shipped by Fedora